Back contact battery preparation method adopting laser-induced crystallization process and battery

Abstract

The invention belongs to the technical field of back contact cells, and particularly relates to a back contact cell preparation method adopting a laser-induced crystallization process and a cell, and the method comprises the steps: S1082, carrying out the laser engraving of at least a part of a second doped amorphous silicon layer in a second semiconductor opening region through the laser-induced crystallization process, crystallizing the second doped amorphous silicon layer corresponding to the laser engraving area to form a second doped microcrystalline silicon layer; the conditions of the laser-induced crystallization process are as follows: the laser spot energy density is less than 190mJ / cm < 2 >, and the spot overlapping rate is greater than or equal to 50%. According to the invention, the requirement on the thickness of amorphous silicon and the requirement on the consistency of a film layer are greatly reduced; meanwhile, the requirements on a laser and a light path are reduced, and the preparation process is simplified, so that large-scale mass production is facilitated; and meanwhile, good battery efficiency is considered, and the amorphous silicon productivity is improved.

Description

Technical Field

[0001] This invention belongs to the field of back contact battery technology, specifically relating to a method for preparing a back contact battery using laser-induced crystallization technology and the battery itself. Background Technology

[0002] Currently, the relatively low-cost manufacturing process for back-contact batteries is generally as follows:

[0003] S101 provides a double-sided polished silicon substrate;

[0004] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate;

[0005] S103. Perform a first etching on the back side obtained in S102 to form a second semiconductor opening region;

[0006] S104. Perform texturing and cleaning to simultaneously form a texturing surface on the front side of the silicon substrate and the second semiconductor opening area; then remove part or all of the mask layer outside the second semiconductor opening area on the back side of the silicon substrate.

[0007] S105. A passivation layer and an antireflection layer are formed on the light-receiving surface of a silicon substrate;

[0008] S106. After routine RCA cleaning, the interface cleanliness of the second semiconductor opening area on the back side of the silicon substrate meets the requirements for depositing the second semiconductor layer.

[0009] S107. A second semiconductor layer is deposited by CVD on the back side obtained in S106. The second semiconductor layer includes an intrinsic silicon layer and a second doped amorphous silicon layer. The thickness of the second doped amorphous silicon layer is generally greater than 30 nm.

[0010] S108. Laser irradiation-induced crystallization of the second semiconductor layer is performed in the second semiconductor opening region on the back side of the silicon substrate, with a laser energy density greater than 200 mJ / cm². 2 The laser spot overlap rate is low (generally less than 20%), and the laser pulse width is generally a nanosecond laser; and a second etching is performed on the second semiconductor layer on the first semiconductor region to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region;

[0011] S109. Deposit a conductive film layer on the back side;

[0012] S110. A third etching is performed on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0013] S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0014] However, the existing manufacturing process for back contact batteries has the following shortcomings:

[0015] ① Currently, the energy density of laser-induced crystallization is very high, which causes great damage to amorphous silicon. The current approach is to significantly increase the thickness of amorphous silicon (generally greater than 30nm) to reduce laser damage, thereby significantly reducing the production capacity of CVD-deposited amorphous silicon in S107.

[0016] ② The high-energy-density laser-induced crystallization process has a narrow window and requires a high degree of consistency in the film layer;

[0017] ③ Because a very high laser energy density is required, the requirements for the laser and the optical path are particularly high. Under the condition of a fixed spot size, the higher the laser energy density, the higher the corresponding laser pulse energy requirement.

[0018] It should be noted that this part of the present invention only provides background technology related to the present invention, and does not necessarily constitute prior art or known technology. Summary of the Invention

[0019] The purpose of this invention is to overcome the shortcomings of existing back-contact battery fabrication processes, which require thick amorphous silicon layers, cannot balance laser damage and amorphous silicon production capacity, and have high requirements for film consistency, laser, and optical path. This invention provides a back-contact battery fabrication method and battery using a laser-induced crystallization process. This invention significantly reduces the requirements for amorphous silicon thickness and film consistency; it also reduces the requirements for laser and optical path, simplifies the fabrication process, and is more conducive to large-scale mass production; while simultaneously achieving good battery efficiency and improving amorphous silicon production capacity.

[0020] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a back contact battery using a laser-induced crystallization process, comprising the following steps:

[0021] S100: A first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals. The back side of the corresponding part of the second semiconductor opening region is a textured surface.

[0022] S107. Deposit a second semiconductor layer on the back side. The second semiconductor layer includes an intrinsic silicon layer and a second doped amorphous silicon layer deposited sequentially. The thickness of the second doped amorphous silicon layer is 6-20 nm.

[0023] S108, proceed with S1081 and S1082:

[0024] S1081. A second etching opening is made on the second semiconductor layer above the vertical stack of the first semiconductor layer on the back side to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0025] S1082. A laser-induced crystallization process is used to laser-etch at least a portion of the second-doped amorphous silicon layer within the second semiconductor opening region, causing the corresponding portion of the second-doped amorphous silicon layer in the laser-etched region to crystallize and form a second-doped microcrystalline silicon layer; the conditions for the laser-induced crystallization process include: laser spot energy density < 190 mJ / cm². 2 The overlap rate of light spots is ≥50%.

[0026] In some preferred embodiments of the present invention, 1 mJ / cm 2 ≤Laser spot energy density<190mJ / cm 2 And / or, 99.9% ≥ spot overlap rate ≥ 50%.

[0027] In some preferred embodiments of the present invention, the conditions for the laser-induced crystallization process further include: the laser pulse width is less than 100 ns and the laser wavelength is between 325 nm and 1064 nm.

[0028] In some preferred embodiments of the present invention, the laser-induced crystallization process satisfies the following trend: the lower the laser spot energy density, the higher the spot overlap rate.

[0029] In some preferred embodiments of the present invention, the width of the second doped microcrystalline silicon layer in S108 is 20%-98% of the total width of the second doped amorphous silicon layer in S107.

[0030] In some preferred embodiments of the present invention, the thickness of the intrinsic silicon layer is 5-15 nm, and the effective doping concentration of the second doped microcrystalline silicon layer is 2e18 cm⁻¹. -3 -3e20cm -3 .

[0031] Preferably, the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer deposited sequentially.

[0032] In some preferred embodiments of the present invention, S100, a first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals, wherein the back side of the corresponding portion of the second semiconductor opening region is a textured surface; the specific process includes:

[0033] S101 provides a double-sided polished silicon substrate;

[0034] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate;

[0035] S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region;

[0036] S104. Texturing and cleaning: A texturing surface is formed on the front side of the silicon substrate and the second semiconductor opening area, and then the mask layer is completely removed or a portion of the mask layer is retained.

[0037] S105. A passivation layer and an anti-reflection layer are formed on the front side of the silicon substrate after texturing and cleaning in S104.

[0038] S106. Then, the interface cleansing is performed to ensure that the cleanliness of the second semiconductor opening region meets the requirements for depositing the second semiconductor layer.

[0039] In some preferred embodiments of the present invention, the method for preparing a back contact battery further includes:

[0040] S109. Deposit a conductive film layer on the back side obtained in S108;

[0041] S110. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0042] S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0043] In a second aspect, the present invention provides a back contact battery, which is prepared by the back contact battery preparation method using laser-induced crystallization process described in the first aspect.

[0044] Beneficial effects:

[0045] This invention, through the aforementioned technical solution, particularly for the structure where the second semiconductor layer comprises a sequentially deposited intrinsic silicon layer and a second doped amorphous silicon layer, employs a specific laser-induced crystallization process with suitable low energy density and suitable high overlap rate to replace the existing crystallization method using high energy density and low spot overlap rate. This process crystallizes a portion of the second doped amorphous silicon layer to form a second doped microcrystalline silicon layer. This achieves crystallization while reducing the thickness of the amorphous silicon film, without damaging the passivation effect of the amorphous silicon film or reducing the transmission resistance in the thickness direction of the amorphous silicon, thereby achieving good battery efficiency. Simultaneously, it significantly reduces the thickness requirement for amorphous silicon; the thickness of the doped amorphous silicon layer in this invention can be in the lower range of 6-20 nm, increasing amorphous silicon production capacity. Furthermore, the low-energy-density laser-induced crystallization process has a wider window, significantly reducing the requirements for the uniformity of the amorphous silicon film. It also reduces the requirements for the laser, thus facilitating large-scale mass production. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a schematic diagram of the structure of a silicon substrate after double-sided texturing in a specific embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of a structure in which a first semiconductor layer and a mask layer are formed on the back side of a silicon substrate in a specific embodiment of the present invention.

[0049] Figure 3 This is a schematic diagram of a structure in which a second semiconductor opening region is formed by etching on the back side of a silicon substrate in a specific embodiment of the present invention.

[0050] Figure 4 This is a schematic diagram of the structure after the texturing and cleaning process and the removal of the mask layer in a specific embodiment of the present invention.

[0051] Figure 5 This is a schematic diagram of a structure in a specific embodiment of the present invention, showing the formation of a passivation layer and an antireflection layer on the front side.

[0052] Figure 6 This is a schematic diagram of a structure in which a second semiconductor layer is formed on the back side in a specific embodiment of the present invention.

[0053] Figure 7 This is a schematic diagram of a structure in a specific embodiment of the present invention, showing the formation of a first semiconductor opening region by etching an opening in the second semiconductor layer on the back side, thereby forming a P-type microcrystalline silicon.

[0054] Figure 7-1 This is a schematic diagram of the structure with different laser spot overlap rates according to the present invention.

[0055] Figure 7-2 The image shown is a pyramid-shaped SEM image (magnified 100,000 times) of the P-type doped amorphous silicon layer in Embodiment 2 of the present invention without laser characterization.

[0056] Figure 7-3 The image shown is a SEM image of the pyramid after laser characterization of the P-type doped amorphous silicon layer in Embodiment 2 of the present invention (magnified 100,000 times).

[0057] Figure 8 This is a schematic diagram of a structure in which a transparent conductive film layer is formed on the back side in a specific embodiment of the present invention.

[0058] Figure 9This is a schematic diagram of the structure formed by etching the transparent conductive film layer on the back to create an isolation groove in a specific embodiment of the present invention.

[0059] Figure 10 This is a schematic diagram of a structure in which a metal electrode is formed on the back side in a specific embodiment of the present invention.

[0060] Explanation of reference numerals in the attached figures

[0061] 1. Silicon substrate, 2. Tunneling oxide layer, 3. N-type doped polycrystalline silicon layer, 4. Mask layer, 5. Passivation layer, 6. Antireflection layer, 7. Intrinsic amorphous silicon layer, 81. P-type doped amorphous silicon layer, 82. P-type microcrystalline silicon, 9. Transparent conductive film layer, 10. Metal electrode. Detailed Implementation

[0062] In this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0063] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0064] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of the ranges, the endpoint values ​​of the ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. The terms "optional" and "optional" mean that they may or may not be included (or may or may not be present).

[0065] In this invention, the area closer to the silicon substrate is considered the inside, and the area farther from the silicon substrate is considered the outside.

[0066] In a first aspect, the present invention provides a method for preparing a back contact battery using a laser-induced crystallization process, comprising the following steps:

[0067] S100: A first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals. The back side of the corresponding part of the second semiconductor opening region is a textured surface.

[0068] S107. Deposit a second semiconductor layer on the back side, the second semiconductor layer comprising an intrinsic silicon layer and a second doped amorphous silicon layer deposited sequentially.

[0069] S108, proceed with S1081 and S1082:

[0070] S1081. A second etching opening is made on the second semiconductor layer above the vertical stack of the first semiconductor layer on the back side to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region.

[0071] S1082: Using a laser-induced crystallization process, at least a portion of the second doped amorphous silicon layer within the second semiconductor opening region is laser-etched, causing the corresponding portion of the second doped amorphous silicon layer in the laser-etched region to crystallize and form a second doped microcrystalline silicon layer. In S108, the order of S1081 and S1082 is not required; S1081 can be performed first, followed by S1082, or vice versa.

[0072] Preferably, the thickness of the second doped amorphous silicon layer in this invention is 6-20 nm, for example, it can be 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, or 20 nm, or any range between two such values. The fabrication method of this invention does not require a thick second doped amorphous silicon layer; a thinner second doped amorphous silicon layer can avoid laser damage and achieve high battery efficiency.

[0073] Preferably, the conditions for the laser-induced crystallization process include: laser spot energy density ≤ 190 mJ / cm². 2 The beam overlap rate is ≥50%. This invention uses a low energy density, high beam overlap rate instead of a high energy density, low beam overlap rate crystallization method, which significantly reduces the requirements for the thickness and consistency of amorphous silicon, and also reduces the requirements for the laser, thus making it more conducive to large-scale mass production.

[0074] In some preferred embodiments of the present invention, 1 mJ / cm 2 Laser spot energy density ≤190mJ / cm 2 The laser spot energy density can be, for example, 1 mJ / cm². 2 2mJ / cm 2 3mJ / cm 2 4mJ / cm 2 5mJ / cm2 6mJ / cm 2 7mJ / cm 2 8mJ / cm 2 9mJ / cm 2 10mJ / cm 2 12mJ / cm 2 15mJ / cm 2 17mJ / cm 2 20mJ / cm 2 25mJ / cm 2 30mJ / cm 2 40mJ / cm 2 50mJ / cm 2 60mJ / cm 2 70mJ / cm 2 80mJ / cm 2 90mJ / cm 2 100mJ / cm 2 120mJ / cm 2 140mJ / cm 2 150mJ / cm 2 160mJ / cm 2 170mJ / cm 2 180mJ / cm 2 Or 190mJ / cm 2 And the range between any two point values.

[0075] Preferably, in this invention, the spot overlap rate is 99.9% ≥ 50%. The spot overlap rate can be, for example, 50%, 55%, 60%, 66%, 70%, 75%, 80%, 85%, 90%, 95%, 99.0%, or 99.9%, or a range between any two point values, such as... Figure 7-1 As shown.

[0076] In some preferred embodiments of the present invention, the conditions for the laser-induced crystallization process further include: the laser pulse width is less than 100 ns and the laser wavelength is between 325 nm and 1064 nm.

[0077] In some preferred embodiments of the present invention, the laser-induced crystallization process satisfies the following condition: the lower the laser spot energy density, the higher the spot overlap rate. This preferred embodiment of the present invention is more conducive to further reducing the thickness of the amorphous silicon film. Specifically, the lower the laser spot energy density, the higher the spot overlap rate; for example, when the spot energy density is 20 mJ / cm², the overlap rate tends to be higher. 2 At that time, the beam overlap rate was 95%; at a beam energy density of 10 mJ / cm², the beam overlap rate was 95%. 2At that time, the beam overlap rate was 97.5%; at a beam energy density of 5 mJ / cm², the beam overlap rate was 97.5%. 2 At that time, the light spot overlap rate was 99%.

[0078] In some preferred embodiments of the present invention, the width of the second doped microcrystalline silicon layer in S108 is 20%-98% of the total width of the second doped amorphous silicon layer in S107, specifically, it can be 20%, 30%, 40%, 50%, 55%, 60%, 66%, 70%, 75%, 80%, 85%, 90%, 95%, 97%, or 98%, or any range between any two values. This preferred embodiment of the present invention is more conducive to improving battery efficiency.

[0079] In some preferred embodiments of the present invention, the thickness of the intrinsic silicon layer is 5-15 nm. The intrinsic silicon layer is preferably an intrinsic amorphous silicon layer.

[0080] Preferably, in this invention, the effective doping concentration of the second doped microcrystalline silicon layer is 2e18cm. -3 -3e20cm -3 .

[0081] Preferably, the first semiconductor layer comprises a tunneling oxide layer and a first doped polycrystalline silicon layer deposited sequentially. This invention employs a combined passivation structure, which is more conducive to improving battery efficiency.

[0082] In some preferred embodiments of the present invention, in the first semiconductor layer, the thickness of the tunneling oxide layer is 1-2 nm, and the thickness of the first doped polysilicon layer is 30-250 nm with an effective doping concentration greater than 5e18 cm⁻¹. -3 .

[0083] In this invention, it is understood that one of the first doped polycrystalline silicon layer and the second doped amorphous silicon layer (or the second doped microcrystalline silicon layer) is N-type and the other is P-type.

[0084] In some preferred embodiments of the present invention, S100, a first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals, wherein the back side of the corresponding portion of the second semiconductor opening region is a textured surface; the specific process includes:

[0085] S101 provides a double-sided polished silicon substrate;

[0086] S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate;

[0087] S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region;

[0088] S104. Texturing and cleaning: A texturing surface is formed on the front side of the silicon substrate and the second semiconductor opening area, and then the mask layer is completely removed or a portion of the mask layer is retained.

[0089] S105. A passivation layer and an anti-reflection layer are formed on the front side of the silicon substrate after texturing and cleaning in S104.

[0090] S106. Then, the interface cleansing is performed to ensure that the cleanliness of the second semiconductor opening region meets the requirements for depositing the second semiconductor layer.

[0091] In this invention, the passivation layer and antireflection layer can be constructed with reference to existing technologies. Preferably, the passivation layer is at least one of an amorphous silicon passivation layer, a silicon oxide passivation layer, and an aluminum oxide passivation layer. More preferably, the passivation layer is a combination of silicon oxide and aluminum oxide, wherein the thickness of the silicon oxide is 0.5-2 nm and the thickness of the aluminum oxide is 3-10 nm.

[0092] For example, the antireflection layer can be at least one of silicon nitride, aluminum oxide, and silicon oxide. Preferably, the antireflection layer is a combination of silicon nitride and silicon oxide, wherein the thickness of silicon nitride is 50-100 nm and the thickness of silicon oxide is 70-150 nm.

[0093] In step S106, cleaning can be performed using conventional solutions in the art (such as conventional RCA cleaning), for example, standard cleaning solution No. 1 (SC1), standard cleaning solution No. 2 (SC2), or HF solution, etc. The mass concentration of the HF solution is 0.1%-10%. Standard cleaning solution No. 1 is a mixture of NH4OH / H2O2 / H2O (ammonia / hydrogen peroxide / water) in a 1:1:5 ratio, and standard cleaning solution No. 2 is a mixture of HCl / H2O2 / H2O (hydrochloric acid / hydrogen peroxide / water) in a 1:1:6 ratio. Preferably, the cleaning conditions include: a treatment temperature of 20℃-30℃ and a cleaning time of 50-900s.

[0094] In some preferred embodiments of the present invention, the method for preparing a back contact battery further includes:

[0095] S109. Deposit a conductive film layer on the back side obtained in S108;

[0096] S110. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench.

[0097] S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0098] In a second aspect, the present invention provides a back contact battery, which is prepared by the back contact battery preparation method using laser-induced crystallization process described in the first aspect.

[0099] The embodiments of the present invention described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0100] Example 1

[0101] A back-contact battery is prepared by the following method:

[0102] S101, such as Figure 1 As shown, a double-sided polished silicon substrate 1 is provided;

[0103] S102, such as Figure 2 As shown, a first semiconductor layer and a mask layer 4 (specifically, a phosphorosilicate glass layer naturally formed during the first semiconductor layer formation process, with a thickness of 35 nm) are sequentially formed on the back side of the silicon substrate 1. The first semiconductor layer includes a tunneling oxide layer 2 with a thickness of 1.5 nm and an N-type doped polycrystalline silicon layer 3 (with a thickness of 120 nm and an effective doping concentration of 4e19cm). -3 );

[0104] S103, such as Figure 3 As shown, a first etching is performed on the back side obtained in S102 to form a second semiconductor opening region;

[0105] S104, such as Figure 4 As shown, texturing and cleaning are performed to form a texturing surface on the front side of the silicon substrate 1 and the second semiconductor opening area simultaneously. The width of the second semiconductor opening area is W1. Then, all mask layers 4 outside the second semiconductor opening area on the back side of the silicon substrate 1 are removed.

[0106] S105, such as Figure 5 As shown, a passivation layer 5 (specifically, the passivation layer is a combination of silicon oxide and aluminum oxide, with the silicon oxide having a thickness of 0.5 nm and the aluminum oxide having a thickness of 7 nm) and an antireflection layer 6 (specifically, a stack of silicon nitride with a thickness of 50 nm and silicon oxynitride with a thickness of 70 nm, with a total thickness of 120 nm) are formed on the light-receiving surface of the silicon substrate 1.

[0107] S106. After routine RCA cleaning (using standard cleaning solution No. 1 (SC1, i.e., NH4OH / H2O2 / H2O (ammonia / hydrogen peroxide / water) mixed in a ratio of 1:1:5)), the interface cleanliness of the second semiconductor opening area on the back side of the silicon substrate 1 meets the requirements for depositing the second semiconductor layer.

[0108] S107, such as Figure 6 As shown, a second semiconductor layer is deposited on the back side obtained in S106 using PECVD. The second semiconductor layer includes an intrinsic amorphous silicon layer 7 with a thickness of 8 nm and a P-type doped amorphous silicon layer 81. The P-type doped amorphous silicon layer 81 has a thickness of 10 nm and an effective doping concentration of 3e19 cm⁻¹.-3 ;

[0109] S108, such as Figure 7 As shown, a second etching is performed on the second semiconductor layer above the vertically stacked first semiconductor layer on the back side of the silicon substrate 1 to form a first semiconductor opening region with an opening width of W2, spaced apart from the second semiconductor opening region. Then, a laser-induced crystallization process is used to laser-etch the P-type doped amorphous silicon layer 81 in the second semiconductor opening region, causing partial crystallization of the P-type doped amorphous silicon layer 81 in the laser-etched area to form P-type microcrystalline silicon 82. The laser-induced crystallization process uses a laser with a pulse width of 80 ns, a wavelength of 532 nm, and a spot energy density of 20 mJ / cm². 2 The beam overlap rate is 95% (equivalent to the laser irradiating the same area 20 times). The width of the second doped microcrystalline silicon layer in S108 is 80% of the total width of the second doped amorphous silicon layer in S107.

[0110] S109, such as Figure 8 As shown, a transparent conductive film layer 9 (specifically ITO) is deposited on the back side obtained in S108.

[0111] S110, such as Figure 9 As shown, a third etching is performed on a portion of the transparent conductive film layer 9 located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench with an opening width of W3.

[0112] S111, such as Figure 10 As shown, metal electrodes 10 are formed on the outer surfaces of the corresponding transparent conductive film layers 9 in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0113] Example 2

[0114] The process was carried out in accordance with Example 1, except that the S108 laser marking process was different. The laser pulse width was 20 ps, ​​and the spot overlap rate was 99.9% (equivalent to the same area being continuously irradiated by the laser 1000 times). The SEM image of the pyramid without laser marking is shown below. Figure 7-2 As shown, the surface of the pyramid's top is smooth. The SEM image of the pyramid after laser marking is shown below. Figure 7-3 As shown in the image, there are obvious traces of laser treatment on the top of the pyramid.

[0115] Example 3

[0116] The process was carried out in accordance with Example 1, except that the laser marking process of S108 was different. The pulse width of its laser was 20ns and the spot overlap rate was 98% (equivalent to the laser continuously irradiating the same area 50 times).

[0117] Example 4

[0118] The procedure was carried out in accordance with Example 3, except that the overlap rate of the laser spots engraved by the S108 laser was 99% (equivalent to the laser continuously irradiating the same area 100 times).

[0119] Example 5

[0120] The procedure was carried out in accordance with Example 1, except that the S108 laser marking process was different, and the spot energy density was 10 mJ / cm². 2 The laser spot overlap rate was 97.5% (equivalent to the laser continuously irradiating the same area 40 times).

[0121] Example 6

[0122] The procedure was carried out in accordance with Example 1, except that the S108 laser marking process was different, and the spot energy density was 5 mJ / cm². 2 The laser spot overlap rate is 99% (equivalent to the laser continuously irradiating the same area 100 times).

[0123] Example 7

[0124] The procedure is carried out with reference to Example 1, except that the area laser-etched in S108 makes the width of the second doped microcrystalline silicon layer 50% of the total width of the second doped amorphous silicon layer in S107.

[0125] Comparative Example 1

[0126] The procedure was carried out in accordance with Example 1, except that the S108 laser marking process was different, specifically employing high energy density and low spot overlap. The laser pulse width was 20 ns, and the spot energy density was 400 mJ / cm². 2 The spot overlap rate is 0% (equivalent to the laser continuously irradiating the same area once, the number of irradiations = 1 / (1-spot overlap rate)).

[0127] Comparative Example 2

[0128] The same procedure was performed as in Comparative Example 1, except that the thickness of the second doped amorphous silicon layer in S107 was 40 nm.

[0129] Test case

[0130] The back contact batteries obtained from the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. The PECVD capacity and contact resistivity of each embodiment and comparative example were calculated using Embodiment 1 as a reference. The data for Embodiment 1 was normalized to a reference value of 1.0. Other examples were calculated based on Embodiment 1; for example, the contact resistivity of Comparative Example 1 / the contact resistivity of Embodiment 1 is 1.2.

[0131] Table 1

[0132] Performance indicators PECVD capacity Contact resistivity Fill factor FF (%) Battery efficiency (%) Example 1 1.0 1.0 87.0 27.50 Example 2 1.0 1.05 86.8 27.45 Example 3 1.0 1.1 86.6 27.43 Example 4 1.0 1.06 86.6 27.43 Example 5 1.0 1.02 86.9 27.41 Example 6 1.0 1.01 86.9 27.48 Example 7 1.0 1.12 86.4 27.38 Comparative Example 1 1.0 1.2 86.3 27.3 Comparative Example 2 0.7 1.4 86.6 27.35

[0133] The results above show that, compared with the comparative example, the embodiments of the present invention significantly reduce the requirements for the thickness and film consistency of amorphous silicon, thereby increasing the production capacity of amorphous silicon PECVD; at the same time, it also reduces the requirements for lasers, simplifies the preparation process, and is more conducive to large-scale mass production; and at the same time, it also achieves good cell efficiency.

[0134] Furthermore, as can be seen from Examples 1 and 2-6, the preferred scheme of the present invention is more conducive to improving CVD production capacity while also achieving higher battery efficiency.

[0135] The preferred embodiments of the present invention have been described in detail above; however, the present invention is not limited thereto. Within the scope of the inventive concept, various simple modifications can be made to the technical solutions of the present invention, including combining the various technical features in any other suitable manner. These simple modifications and combinations should also be considered as the content disclosed in the present invention and are all within the protection scope of the present invention.

Claims

1. A method for fabricating a back contact battery using laser-induced crystallization technology, characterized in that, Includes the following steps: S100: A first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals. The back side of the corresponding part of the second semiconductor opening region is a textured surface. S107. Deposit a second semiconductor layer on the back side. The second semiconductor layer includes an intrinsic silicon layer and a second doped amorphous silicon layer deposited sequentially. The thickness of the second doped amorphous silicon layer is 6-20 nm. S108, proceed with S1081 and S1082: S1081. A second etching opening is made on the second semiconductor layer above the vertical stack of the first semiconductor layer on the back side to form a first semiconductor opening region that is spaced apart from the second semiconductor opening region. S1082. Using a laser-induced crystallization process, at least a portion of the second doped amorphous silicon layer in the second semiconductor opening region is laser-etched, so that the corresponding portion of the second doped amorphous silicon layer in the laser-etched region crystallizes to form a second doped microcrystalline silicon layer. The conditions for the laser-induced crystallization process include: laser spot energy density < 190 mJ / cm². 2 The overlap rate of light spots is ≥50%.

2. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, 1mJ / cm 2 ≤Laser spot energy density<190mJ / cm 2 And / or, 99.99% ≥ spot overlap rate ≥ 50%.

3. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, The conditions for the laser-induced crystallization process also include: the laser pulse width is less than 100 ns and the laser wavelength is between 325 nm and 1064 nm.

4. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, The laser-induced crystallization process satisfies the following trend: the lower the laser spot energy density, the higher the spot overlap rate.

5. The method for preparing a back contact battery using laser-induced crystallization process according to any one of claims 1-4, characterized in that, The width of the second doped microcrystalline silicon layer in S108 is 20%-98% of the total width of the second doped amorphous silicon layer in S107.

6. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, The thickness of the intrinsic silicon layer is 5-15 nm, and the effective doping concentration of the second doped microcrystalline silicon layer is 2e18 cm⁻¹. -3 -3e20cm -3 .

7. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, The first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer deposited sequentially.

8. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, S100: A first semiconductor layer is disposed at intervals on the back side of a silicon substrate, and a second semiconductor opening region is formed at the intervals. The back side of the corresponding portion of the second semiconductor opening region is a textured surface. The specific process includes: S101 provides a double-sided polished silicon substrate; S102, A first semiconductor layer and a mask layer are sequentially formed on the back side of a silicon substrate; S103. A first etching opening is made on the back side obtained in S102 to form a second semiconductor opening region; S104. Texturing and cleaning: A texturing surface is formed on the front side of the silicon substrate and the second semiconductor opening area, and then the mask layer is completely removed or a portion of the mask layer is retained. S105. A passivation layer and an anti-reflection layer are formed on the front side of the silicon substrate after texturing and cleaning in S104. S106. Then, the interface cleansing is performed to ensure that the cleanliness of the second semiconductor opening region meets the requirements for depositing the second semiconductor layer.

9. The method for preparing a back contact battery using laser-induced crystallization process according to claim 1, characterized in that, The methods for preparing back contact batteries also include: S109. Deposit a conductive film layer on the back side obtained in S108; S110. A third etched opening is made on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an isolation trench. S111, metal electrodes are formed on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

10. A back-contact battery, characterized in that, It is prepared by the back contact cell preparation method using laser-induced crystallization process as described in any one of claims 1-9.

Images