Back contact battery and photovoltaic module

Abstract

The invention discloses a back contact cell and a photovoltaic module, relates to the technical field of photovoltaics, and aims to optimize the transmission path of current carriers and realize effective collection of the current carriers. The back contact cell includes a semiconductor substrate, and a first semiconductor layer and a second semiconductor layer disposed on a back surface of the semiconductor substrate. The first semiconductor layer and the semiconductor substrate are of the same doping type, and the first semiconductor layer comprises a plurality of semiconductor parts which are discretely arranged on the back face. The doping types of the second semiconductor layer and the semiconductor substrate are opposite. The second semiconductor layer surrounds the plurality of semiconductor portions. The plurality of semiconductor parts are a plurality of groups of semiconductor parts which are distributed at intervals along the first direction, and each group of semiconductor parts comprises a plurality of semiconductor parts which are distributed at intervals along the second direction and are collinear. In the back surface of the semiconductor substrate, a region between two semiconductor portions adjacent in the second direction is defined as a target region. The projections of at least two rows of adjacent target areas in the first direction are staggered in the first direction.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and more particularly to a back-contact battery and a photovoltaic module. Background Technology

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight shines on the semiconductor pn junction, forming new electron-hole pairs. Under the influence of the built-in electric field of the pn junction, photogenerated holes flow to the p-region, and photogenerated electrons flow to the n-region. When the circuit is connected, an electric current is generated. Solar cells where both the positive and negative electrodes are located on the back side of the cell are called back-contact cells. Compared to double-sided contact solar cells, the front side of a back-contact cell has no metal electrodes to block the light, resulting in higher light utilization on the light-facing side. Therefore, back-contact cells have higher short-circuit current and photoelectric conversion efficiency, making them one of the current technological directions for achieving high-efficiency crystalline silicon solar cells.

[0003] However, the conversion efficiency of existing back-contact batteries results in poor performance. Summary of the Invention

[0004] The purpose of this invention is to provide a back-contact battery and photovoltaic module for optimizing the carrier transport path, achieving effective carrier collection, and improving the working performance of the back-contact battery.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a back contact battery, comprising: a semiconductor substrate, and a first semiconductor layer and a second semiconductor layer disposed on the back side of the semiconductor substrate. The first semiconductor layer and the semiconductor substrate have the same doping type, and the first semiconductor layer includes a plurality of semiconductor portions discretely disposed on the back side. The second semiconductor layer and the semiconductor substrate have opposite doping types. The second semiconductor layer surrounds the plurality of semiconductor portions. The plurality of semiconductor portions are multiple groups of semiconductor portions spaced apart along a first direction, and each group of semiconductor portions includes a plurality of collinear semiconductor portions spaced apart along a second direction. The first direction is different from the second direction. In the back side of the semiconductor substrate, a region located between two adjacent semiconductor portions along the second direction is defined as a target region. At least two rows of target regions adjacent along the first direction are staggered in projection along the first direction.

[0006] In the back-contact battery provided by the present invention, the doping type of the first semiconductor layer is the same as that of the semiconductor substrate, that is, the back field region of the back-contact battery includes the first semiconductor layer. The doping type of the second semiconductor layer is opposite to that of the semiconductor substrate, that is, the emitter region of the back-contact battery includes the second semiconductor layer. Based on this, when the first semiconductor layer includes multiple semiconductor portions discretely disposed on the back side, and the second semiconductor layer surrounds the multiple semiconductor portions, it is advantageous to increase the area ratio of the second semiconductor layer on the back side of the semiconductor substrate, which is advantageous to increase the junction area of ​​the PN junction, thereby improving the carrier separation and collection efficiency and reducing the carrier recombination rate. Furthermore, reducing the area ratio of the first semiconductor layer on the back side also helps to reduce the edge length between the first and second semiconductor layers, which can reduce the impact of edge recombination on the battery conversion efficiency.

[0007] Furthermore, on the back side of the semiconductor substrate, the target region is located between two adjacent semiconductor sections along the second direction, and a second semiconductor layer is disposed on this region. Based on this, when the back contact battery is in operation, charge carriers generated in the target region with the same conductivity type as the first semiconductor layer need to be transported to the adjacent semiconductor section and collected therefrom. Therefore, when the projections of at least two rows of target regions adjacent along the first direction are staggered, the target region has two adjacent semiconductor sections not only along the second direction but also along the first direction. Compared to when the projections of at least two rows of target regions adjacent along the first direction overlap (in which case the charge carriers generated in the target region with the same conductivity type as the first semiconductor layer cannot be transported to the adjacent semiconductor section along the first direction and need to travel a longer path to be collected), in this invention, the charge carriers generated in the target region with the same conductivity type as the first semiconductor layer can be collected by the semiconductor section within a shorter transport distance, optimizing the carrier transport path, achieving effective carrier collection, reducing the carrier recombination rate, and improving the operating performance of the back contact battery.

[0008] As one possible implementation, at least two rows of target regions along the first direction have overlapping projections in the first direction, and at least one set of semiconductor portions is included between the two overlapping rows of target regions. With this configuration, the projections of different rows of target regions in the first direction on the back side of the semiconductor substrate can be regularly distributed, which simplifies the patterning process during the fabrication of the first and second semiconductor layers. Furthermore, while ensuring that the projections of multiple adjacent rows of target regions along the first direction are staggered, allowing for the effective collection of carriers with the same conductivity type as the first semiconductor layer within the target region, the length of the semiconductor portion can be reduced and / or the target region can have a certain length. This increases the junction area of ​​the PN junction, thereby improving carrier separation and collection efficiency. Simultaneously, it also helps to reduce the edge length between the first and second semiconductor layers, reducing the impact of edge recombination on battery conversion efficiency.

[0009] As one possible implementation, along the second direction, the ratio of the length of at least one target region to the length of the semiconductor portion is greater than or equal to 3% and less than or equal to 40%; and / or, the length of at least one target region along the second direction is greater than or equal to the width of the semiconductor portion along the first direction; and / or, along the second direction, the length of at least one target region is greater than or equal to 50 μm and less than or equal to 5000 μm; and / or, along the second direction, the length of at least one semiconductor portion is greater than or equal to 150 μm and less than or equal to 15000 μm.

[0010] With the above technical solution, it is understood that the target region is the area on the back side of the semiconductor substrate located between two adjacent semiconductor portions along the second direction, and a second semiconductor layer is disposed on this region. It is evident that the length of the target region also affects the coverage area of ​​the second semiconductor layer disposed on it on the back side. Therefore, when the ratio of the length of at least one target region to the length of the semiconductor portion is within the aforementioned range, it prevents the target region from being too short and / or the semiconductor portion from being too long due to an excessively small ratio. This helps ensure that the second semiconductor layer has a larger area ratio on the back side of the semiconductor substrate, increasing the junction area of ​​the PN junction, thereby improving carrier separation and collection efficiency. Simultaneously, it also helps reduce the edge length between the first and second semiconductor layers, reducing the impact of edge recombination on battery conversion efficiency. Furthermore, it prevents the target region from being too long and / or the semiconductor portion from being too short due to an excessively large ratio, helping to ensure that the first semiconductor layer has good carrier collection capability and reducing the carrier recombination rate.

[0011] As for the application principle of the beneficial effect that at least one target region has a length in the second direction that is greater than or equal to the width of the semiconductor portion in the first direction, or that the length of at least one target region in the second direction is greater than or equal to 50 μm and less than or equal to 5000 μm, or that the length of at least one semiconductor portion in the second direction is greater than or equal to 150 μm and less than or equal to 15000 μm, the application principle of the beneficial effect that the ratio of the length of at least one target region to the length of the semiconductor portion is greater than or equal to 3% and less than or equal to 40% as described above can be referred to, and will not be repeated here.

[0012] As one possible implementation, the projection of two adjacent rows of target regions along the first direction is staggered by a distance of less than or equal to 8000 μm. This setting prevents the target region from being too short and / or the semiconductor portion from being too long due to excessive spacing. It helps ensure that the second semiconductor layer has a large area ratio on the back side of the semiconductor substrate, increasing the junction area of ​​the PN junction and thus improving the separation and collection efficiency of charge carriers. At the same time, it also helps to reduce the edge length between the first and second semiconductor layers, which can reduce the impact of edge recombination on the battery conversion efficiency.

[0013] As one possible implementation, the back contact battery further includes: a plurality of first current collectors, a plurality of first interconnect structures, and a first insulating isolation structure. The plurality of first current collectors extend along a second direction and are spaced apart along a first direction. The plurality of first interconnect structures extend along the first direction and are spaced apart along the second direction. Each first current collector is electrically connected to a first interconnect structure. The first insulating isolation structure is disposed between the first current collectors and a second semiconductor layer, and / or, the first insulating isolation structure is disposed at the intersection of the extension lines of the second semiconductor layer and the first interconnect structure along the first direction. The plurality of first current collectors correspond one-to-one with a plurality of sets of semiconductor portions, and each first current collector is electrically connected to a corresponding set of semiconductor portions. At least one first interconnect structure is offset from the projection of the target region in the first direction.

[0014] With the above technical solution, it is understood that multiple first collector electrodes correspond one-to-one with multiple sets of semiconductor sections, and each first collector electrode is electrically connected to the corresponding set of semiconductor sections. In this case, charge carriers within the semiconductor sections can be collected through the first collector electrodes. The interconnecting element used to connect two adjacent back-contact batteries in series is electrically connected to the first interconnecting structure. In this case, charge carriers can be discharged through the first interconnecting structure electrically connected to the first collector electrodes. When multiple first interconnecting structures are spaced apart along the second direction, the interconnecting element used to connect two adjacent back-contact batteries in series also extends along the first direction. Based on this, when at least one first interconnecting structure is offset from the projection of the target area in the first direction, it is advantageous that the interconnecting element can be placed on more rows of semiconductor sections when extending along the first direction. This helps reduce the number and / or area of ​​the first insulating isolation structure, prevents battery warping, improves battery yield, and reduces the risk of leakage.

[0015] As one possible implementation, at least one semiconductor portion is disposed between two adjacent first interconnect structures along the second direction. This arrangement prevents the spacing between two adjacent first interconnect structures along the second direction from being too small and / or the length of the semiconductor portion from being too large. It also prevents an excessive number of first interconnect structures spaced apart along the second direction, which would lead to excessive material consumption and a large light-shielding area of ​​the first interconnect structures. This helps reduce the manufacturing cost of the back contact battery and improves the bifaciality of the back contact battery. Secondly, it helps control the length of the semiconductor portion, ensuring that the second semiconductor layer has a large area ratio on the back side of the semiconductor substrate, increasing the junction area of ​​the PN junction, and thus improving the separation and collection efficiency of charge carriers. Simultaneously, it also helps reduce the edge length between the first and second semiconductor layers, reducing the impact of edge recombination on battery conversion efficiency.

[0016] As one possible implementation, the portion of at least one first collector electrode located on at least one semiconductor portion is irregularly shaped, including a sun-shaped, field-shaped, rice-shaped, or Feng-shaped form; and / or, the width of the portion of at least one first collector electrode located on at least one semiconductor portion is greater than the width of the portion located on the target area. This configuration effectively increases the contact area between the first collector electrode and at least one semiconductor portion while reducing the area ratio of the first semiconductor layer on the back side, thereby reducing the contact resistance between them.

[0017] As one possible implementation, on the back side of the semiconductor substrate, the area where the first semiconductor layer is disposed is designated as the first region, and the remaining area is designated as the second region. The surface height of the second region is less than that of the first region. This configuration, with its smaller surface height, indicates that during the fabrication of the back contact battery, in addition to patterning the entire first semiconductor layer, selective etching is performed on the portion of the semiconductor substrate corresponding to the second region. This reduces or even prevents residual first semiconductor material in the second region, lowering the risk of leakage and improving the carrier collection efficiency of the second semiconductor layer. Furthermore, the height difference between the first and second regions can at least partially offset the first semiconductor layer in the first region and the second semiconductor layer in the second region along the thickness direction of the semiconductor substrate, further reducing the risk of leakage between them.

[0018] As one possible implementation, the first insulating isolation structure is disposed on a portion of the second semiconductor layer corresponding to the second region.

[0019] With the above technical solution, the surface height of the second region is smaller compared to the first region. The first insulating isolation structure separates the first collector electrode from the second semiconductor layer, and also separates the interconnect (or the interconnect and the first bus electrode) from the second semiconductor layer. Since the second semiconductor layer surrounds the outer periphery of the semiconductor portion, when the first collector electrode extends along the second direction, it is not only disposed on the semiconductor portion with a larger surface height but also passes through the second semiconductor layer with a smaller surface height in its extension direction. Similarly, for the interconnect (or the interconnect and the first bus electrode), it is not only disposed on the semiconductor portion with a larger surface height but also passes through the second semiconductor layer with a smaller surface height in its extension direction. Therefore, when the first insulating isolation structure is disposed on the portion of the second semiconductor layer corresponding to the second region, the first collector electrode and the interconnect (or the interconnect and the first bus electrode) disposed on the second semiconductor layer can be raised by additionally providing the first insulating isolation structure. This results in a smaller height difference between different portions of the first collector electrode and the interconnect (or the interconnect and the first bus electrode) along their respective extension directions, leading to higher flatness, improved contact performance, and also helps prevent detachment and improve bonding stability.

[0020] As one possible implementation, the surface of the second region is velvety, and a side surface for connection is provided between the first and second regions. The side surface includes a first side surface and a second side surface. The first side surface is located at the edges of the first region extending along a first direction and a second direction; the second side surface is located at the four corners where every two adjacent edges of the first region intersect. At least a portion of the first side surface has ridge-like protrusions; and / or, at least one corner of the second side surface has a sheet-like protrusion.

[0021] When the above technical solution is adopted, if the surface of the second region is textured, at least a portion of the first side surface used to connect the first and second regions has a ridge-like protrusion structure. This increases the undulation of the side surface, increases the contact area between the second semiconductor layer and the side surface, facilitates carrier collection, increases the passivation contact area, and reduces the carrier recombination rate. Simultaneously, it also improves the light-trapping effect of the side surface and enhances the bifaciality of the back-contact battery. Furthermore, at least four corners of the first region have greater undulation than the straight sections of the side surface due to the presence of corners. Therefore, at least one corner of the second side surface has a flatter, sheet-like protrusion structure compared to the ridge-like protrusion structure. This effectively reduces the roughness at the corner, improves the coverage and passivation effect of the second semiconductor layer at the corner, and reduces the carrier recombination rate.

[0022] As one possible implementation, the second semiconductor layer further extends to cover the edge region of at least one semiconductor portion to form a stacked structure. The edge region is located at least at both ends of the semiconductor portion along a first direction. In the stacked structure, at least a portion of the first semiconductor layer and the second semiconductor layer are electrically connected. This configuration allows the first and second semiconductor layers to form a built-in diode structure with a low reverse breakdown voltage at the stacked structure, reducing the risk of hot spots on the back contact battery. Secondly, in the stacked structure, the second semiconductor layer extending to cover the edge region of at least one semiconductor portion along the first direction facilitates the staggering of the stacked structure from the first collector electrode, preventing excessive leakage current due to the first collector electrode overlapping the stacked structure, and ensuring high conversion efficiency of the back contact battery in the forward voltage region. Simultaneously, it eliminates the need for strict control of the size of the stacked structure and / or the printing accuracy of the first collector electrode to stagger its placement, improving the yield of the back contact battery.

[0023] As one possible implementation, the back-contact battery further includes: a plurality of second current collector electrodes and a plurality of second auxiliary electrodes disposed on the side of the second semiconductor layer opposite to the semiconductor substrate. The plurality of second current collector electrodes extend along a second direction and are spaced apart along a first direction. The second current collector electrodes are disposed between at least two adjacent sets of semiconductor portions along the first direction. The second auxiliary electrodes extend from the second current collector electrodes and extend to corresponding target regions. The plurality of second auxiliary electrodes on the same second current collector electrode extend along the first direction and are spaced apart along the second direction. The second current collector electrodes and the second auxiliary electrodes are arranged in a grid or herringbone pattern.

[0024] When the above technical solution is adopted, the presence of the second auxiliary electrode can improve the carrier collection efficiency in the target region and reduce the carrier recombination rate.

[0025] As one possible implementation, at least one target region is provided with a plurality of second auxiliary electrodes spaced apart along a second direction. This arrangement is beneficial for further improving the carrier collection efficiency in the target region and reducing the carrier recombination rate.

[0026] As one possible implementation, in at least one target region, the spacing between two adjacent second auxiliary electrodes along the second direction is greater than or equal to 10 μm and less than or equal to 3000 μm.

[0027] With the above technical solution, the spacing between two adjacent second auxiliary electrodes along the second direction is within the aforementioned range. This prevents excessive material consumption and excessive light-shielding area of ​​the second auxiliary electrodes due to an excessively small spacing on the same target area, which is beneficial for controlling the manufacturing cost of the back contact battery and improving its bifaciality. Furthermore, it prevents an excessively large spacing from resulting in too few second auxiliary electrodes on the target area, ensuring that charge carriers generated in different parts of the target area along the second direction can be collected and discharged in a timely manner through the second auxiliary electrodes, reducing the carrier recombination rate.

[0028] As one possible implementation, along the second direction, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one target region is greater than or equal to 10 μm and less than or equal to 3000 μm.

[0029] When the above technical solution is adopted, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one target region is within the aforementioned range. This prevents the distance between the second auxiliary electrode and the adjacent semiconductor portion with the opposite conductivity type from being too small due to the minimum distance being too small, reducing the risk of leakage and lowering the manufacturing difficulty of the second auxiliary electrode. Furthermore, it also prevents the number of second auxiliary electrodes on the target region from being too small due to the minimum distance being too large, ensuring that charge carriers generated in different parts of the target region along the second direction can be collected and discharged in a timely manner through the second auxiliary electrode, reducing the carrier recombination rate.

[0030] As one possible implementation, the back contact battery further includes: a plurality of second interconnect structures and a plurality of second insulating isolation structures. The plurality of second interconnect structures extend along a first direction and are spaced apart along a second direction. Each second interconnect structure is electrically connected to a second current collector electrode. The second insulating isolation structures are disposed at the intersection of the first semiconductor layer and the extension lines of the second interconnect structures along the first direction. Specifically, at least one second interconnect structure is offset from the projection of the target region in the first direction; or, the projection of at least one second interconnect structure in the first direction lies within the projection of at least one target region in the first direction.

[0031] When the above technical solution is adopted, if at least one second interconnect structure is staggered from the projection of the target area in the first direction, it is beneficial to make the spacing between different second interconnect structures and the adjacent first interconnect structure approximately the same, resulting in a relatively regular distribution of the second and first interconnect structures on the back side and reducing manufacturing difficulty. When the projection of at least one second interconnect structure in the first direction is located within the projection of at least one target area in the first direction, it is beneficial to allow the second interconnect structure to be placed on more rows of the second semiconductor layer as it extends along the first direction. This reduces the number and / or area of ​​the second insulating isolation structure, prevents battery warping, improves battery yield, and reduces leakage risk. Furthermore, there are two examples of the second interconnect structure's placement on the back side, allowing for the selection of a suitable solution based on different needs, thus improving the applicability of the back contact battery provided by this invention in different application scenarios.

[0032] In a second aspect, the present invention provides a photovoltaic module comprising: a plurality of cell strings and an encapsulation layer. The cell strings include a plurality of solar cells and a plurality of interconnecting elements. The interconnecting elements are used to connect the plurality of solar cells in series. The solar cells are back-contact cells as provided in the first aspect and various implementations thereof; the encapsulation layer covers the surface of the cell strings.

[0033] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 A longitudinal sectional view of the back contact battery provided in an embodiment of the present invention. Figure 1 ; Figure 2 This is a schematic diagram illustrating the distribution of different semiconductor portions in a back contact battery provided in an embodiment of the present invention. Figure 1 ; Figure 3 A schematic diagram illustrating the distribution of the semiconductor portion and the second semiconductor layer in the back contact battery provided in an embodiment of the present invention. Figure 1 ; Figure 4 This is a schematic diagram illustrating the distribution of the first and second current collector electrodes in a back-contact battery provided in an embodiment of the present invention. Figure 1 ; Figure 5 A schematic diagram illustrating the distribution of the first and second insulating isolation structures in a back contact battery provided in an embodiment of the present invention. Figure 1; Figure 6 A schematic diagram illustrating the distribution of the first and second insulating isolation structures in a back contact battery provided in an embodiment of the present invention. Figure 2 ; Figure 7 A longitudinal sectional view of the back contact battery provided in an embodiment of the present invention. Figure 2 ; Figure 8 This is a SEM image of the corner position in the first region of the back contact battery provided in an embodiment of the present invention; Figure 9 This is a schematic diagram illustrating the distribution of different semiconductor portions in a back contact battery provided in an embodiment of the present invention. Figure 2 ; Figure 10 This is a schematic diagram illustrating the distribution of the first and second current collector electrodes in a back-contact battery provided in an embodiment of the present invention. Figure 2 ; Figure 11 This is a schematic diagram showing the distribution of the first current collector electrode on the semiconductor section in a back contact battery provided in an embodiment of the present invention. Figure 1 ; Figure 12 This is a schematic diagram showing the distribution of the first current collector electrode on the semiconductor section in a back contact battery provided in an embodiment of the present invention. Figure 2 ; Figure 13 This is a schematic diagram showing the distribution of the first current collector electrode on the semiconductor section in a back contact battery provided in an embodiment of the present invention. Figure 3 ; Figure 14 This is a schematic diagram illustrating the distribution of the first and second current collector electrodes in a back-contact battery provided in an embodiment of the present invention. Figure 3 ; Figure 15 This is a schematic diagram illustrating the distribution of the first and second current collector electrodes in a back-contact battery provided in an embodiment of the present invention. Figure 4 .

[0035] Reference numerals: 11 is a semiconductor substrate, 12 is a first semiconductor layer, 13 is a second semiconductor layer, 14 is a semiconductor section, 15 is a target region, 16 is a first collector electrode, 17 is a first interconnect structure, 18 is a first insulating isolation structure, 19 is a first region, 20 is a second region, 21 is a ridge-shaped protrusion structure, 22 is a sheet-like protrusion structure, 23 is a second collector electrode, 24 is a second auxiliary electrode, 25 is a second interconnect structure, 26 is a second insulating isolation structure, 27 is a first interface passivation layer, and 28 is a second interface passivation layer. Detailed Implementation

[0036] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0037] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0038] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0039] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0040] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0041] In a first aspect, embodiments of the present invention provide a back-contact battery. For example... Figures 1 to 3As shown, the back contact battery includes: a semiconductor substrate 11, and a first semiconductor layer 12 and a second semiconductor layer 13 disposed on the back side of the semiconductor substrate 11. The first semiconductor layer 12 and the semiconductor substrate 11 have the same doping type, and the first semiconductor layer 12 includes a plurality of semiconductor portions 14 discretely disposed on the back side. The second semiconductor layer 13 and the semiconductor substrate 11 have opposite doping types. The second semiconductor layer 13 surrounds the plurality of semiconductor portions 14.

[0042] It should be noted that the term "surrounding" in the context of the second semiconductor layer surrounding multiple semiconductor portions is used in a broad sense. It can mean that each part of the second semiconductor layer surrounds multiple semiconductor portions; or it can mean that, along the thickness direction of the semiconductor substrate, although at least a portion of one of the first and second semiconductor layers is not only disposed on the semiconductor substrate but also extends and covers the other (forming a stacked structure), most of the area of ​​the second semiconductor layer along the direction parallel to the back surface of the semiconductor substrate does not form a stacked structure, and this majority of the area still presents a state of surrounding multiple semiconductor portions.

[0043] When the above technical solution is adopted, such as Figures 1 to 3 As shown, in the back-contact battery provided in this embodiment of the invention, the doping type of the first semiconductor layer 12 is the same as that of the semiconductor substrate 11, that is, the back field region of the back-contact battery includes the first semiconductor layer 12. The doping type of the second semiconductor layer 13 is opposite to that of the semiconductor substrate 11, that is, the emitter region of the back-contact battery includes the second semiconductor layer 13. Based on this, when the first semiconductor layer 12 includes a plurality of semiconductor portions 14 discretely disposed on the back side, and the second semiconductor layer 13 surrounds the plurality of semiconductor portions 14, it is beneficial to increase the area ratio of the second semiconductor layer 13 on the back side of the semiconductor substrate 11, which is beneficial to increase the junction area of ​​the PN junction, thereby improving the separation and collection efficiency of charge carriers and reducing the carrier recombination rate. Furthermore, reducing the area ratio of the first semiconductor layer 12 on the back side also helps to reduce the edge length between the first semiconductor layer 12 and the second semiconductor layer 13, which can reduce the impact of edge recombination on the battery conversion efficiency.

[0044] In practical applications, the embodiments of the present invention do not specifically limit the material and doping type of the semiconductor substrate. For example, the semiconductor substrate can be a silicon substrate; or, it can be a substrate made of any semiconductor material such as germanium-silicon substrate, germanium substrate, or gallium arsenide substrate. In terms of doping type, the semiconductor substrate can be a P-type substrate or an N-type substrate.

[0045] The specific structure and morphology of the electrode structure of a back contact battery can be set according to the type of back contact battery and actual needs.

[0046] For example, such as Figure 4 and Figure 5 As shown, the back-contact battery may include a plurality of first current collectors 16, a plurality of first interconnect structures 17, a plurality of second current collectors 23, and a plurality of second interconnect structures 25. The plurality of first current collectors 16 extend along a second direction and are spaced apart along a first direction. The first direction is different from the second direction. The plurality of first interconnect structures 17 extend along the first direction and are spaced apart along the second direction. The first current collectors 16 are electrically connected to a first semiconductor layer 12, and each first interconnect structure 17 is electrically connected to a first current collector 16. The plurality of second current collectors 23 extend along the second direction and are spaced apart along the first direction. The plurality of second interconnect structures 25 extend along the first direction and are spaced apart along the second direction. The second current collectors 23 are electrically connected to a second semiconductor layer 13, and each second interconnect structure 25 is electrically connected to a second current collector 23. The first current collectors 16 and second current collectors 23 may be alternately spaced along the first direction, and the first interconnect structures 17 and second interconnect structures 25 may be alternately spaced along the second direction.

[0047] In practical applications, such as Figure 4 and Figure 5As shown, the plurality of semiconductor portions 14 can be divided into multiple groups of semiconductor portions 14 spaced apart along a first direction, and each group of semiconductor portions 14 includes multiple collinear semiconductor portions 14 spaced apart along a second direction. The first direction is different from the second direction. In the above case, the plurality of first collector electrodes 16 can correspond one-to-one with the plurality of groups of semiconductor portions 14, and each first collector electrode 16 is electrically connected to the corresponding group of semiconductor portions 14. Furthermore, the back contact battery may also include a first insulating isolation structure 18 and a second insulating isolation structure 26. The first insulating isolation structure 18 is disposed between the first collector electrode 16 and the second semiconductor layer 13, and / or, the first insulating isolation structure 18 is disposed at the intersection of the extension line of the second semiconductor layer 13 and the first interconnect structure 17 along the first direction to prevent short circuit. The specific location of the first insulating isolation structure 18 can be determined based on the height difference between the surface of the region where the first semiconductor layer is disposed and the surface of the region where the second semiconductor layer is disposed on the back side of the semiconductor substrate, as well as the leakage prevention requirements. For example, in practical applications, if the requirements for preventing battery leakage are high, the first insulating isolation structure 18 can be disposed between the first current collector 16 and the second semiconductor layer 13. Simultaneously, the first insulating isolation structure 18 can also be disposed at the intersection of the extension line of the second semiconductor layer 13 and the first interconnect structure 17 along the first direction. As another example, in practical applications, if the requirements for preventing battery leakage are low, or if the surface of the area where the second semiconductor layer is disposed on the back of the semiconductor substrate is lower than the surface of the area where the second semiconductor layer is disposed with a large height difference (after the interconnect extends along the first direction, the portion of the interconnect located on the second region does not fall to connect with the second current collector and / or the second semiconductor layer due to a certain structural rigidity), then the first insulating isolation structure 18 can be disposed only between the first current collector 16 and the second semiconductor layer 13, or only at the intersection of the extension line of the second semiconductor layer 13 and the first interconnect structure 17 along the first direction, or the first insulating isolation structure 18 can be omitted.

[0048] As for the second collector electrode, such as Figure 4 and Figure 5 As shown, the second collector electrode 23 can be disposed between at least two adjacent sets of semiconductor sections 14 along the first direction.

[0049] like Figure 4 and Figure 5 As shown, at least one second collector electrode 23 can be a continuous collector electrode, and, as Figure 5As shown, the back contact battery also includes a second insulating isolation structure 26. The second insulating isolation structure 26 is at least disposed at the intersection of the extension lines of the first semiconductor layer 12 and the second interconnect structure 25 along the first direction. The second insulating isolation structure 26 is used to isolate the electrode structure electrically connected to the second semiconductor layer 13 from the first semiconductor layer 12 to prevent short circuits. With this configuration, the effective length of the second collector electrode 23 is larger, which can increase the effective carrier collection range of the second collector electrode 23 and reduce the carrier recombination rate.

[0050] Or, such as Figure 6 As shown, at least one second current collector electrode 23 can also be disconnected at the extension line of the first interconnect structure 17 along the first direction. For example, in a back-contact battery, when the first semiconductor layer 12 and the second semiconductor layer 13 are provided with a non-conductive film layer such as a surface passivation layer on the side away from the semiconductor substrate 11, the second current collector electrode 23 can be electrically insulated by the first interconnect structure 17, which has a discontinuity and is opposite to its own conductivity type, without the need for a second insulating isolation structure 26. This reduces the area of ​​the insulating isolation structure on the back side and reduces the material consumption of the insulating isolation structure. As another example, in a back-contact battery, when the first semiconductor layer 12 and the second semiconductor layer 13 are provided with a transparent conductive layer on the side away from the semiconductor substrate 11, a second insulating isolation structure 26 is still required at the discontinuity of the second current collector electrode 23. The second insulating isolation structure 26 can be an insulating material such as insulating adhesive placed between the first interconnect structure 17 and the transparent conductive layer to prevent short circuits. When the second current collector electrode 23 is disconnected at the extension line of the first interconnect structure 17 along the first direction, the risk of short circuits caused by the second current collector electrode 23 puncturing the insulating adhesive can also be reduced. In addition, the first interconnect structure 17 does not need to cross the second collector electrode 23, so that the different parts of the first interconnect structure 17 have a high degree of flatness, thereby improving the structural strength of the electrode and the connection reliability between the corresponding electrode and the semiconductor part 14.

[0051] In addition, the specific objects referred to by the first interconnection structure and the second interconnection structure mentioned above can be determined according to the type of back contact battery in the actual application scenario and the actual needs, and no specific limitation is made here.

[0052] For example, in the case of a "gridless back contact battery," the first interconnect structure and the second interconnect structure can be interconnect portions (e.g., welding portions) respectively disposed on the first current collector electrode and the second current collector electrode, or they can be portions of the first current collector electrode and the second current collector electrode used for electrical connection with the interconnect portion. Along the first direction, the size of the interconnect portion can be greater than or equal to the size of the first current collector electrode and the second current collector electrode. When the size of the interconnect portion is equal to the size of the first current collector electrode and the second current collector electrode, a non-welding process can be used to achieve the interconnection of the back contact battery, such as a coating process, where a carrier film with attached conductive interconnects is directly bonded to the surface of the back contact battery and pressed together to form an electrical interconnect.

[0053] For example, in the case of a "back contact battery with a main grid", the first interconnect structure and the second interconnect structure can be a first bus electrode and a second bus electrode, respectively; the first interconnect structure and the second interconnect structure can also be interconnect portions respectively disposed on the first bus electrode and the second bus electrode; the first interconnect structure can also include a first bus electrode and an interconnect portion disposed on the first bus electrode, and the second interconnect structure can also include a second bus electrode and an interconnect portion disposed on the second bus electrode.

[0054] The morphology of the first collector electrode, the second collector electrode, the first interconnect structure, and the second interconnect structure, as well as the specific directions referred to by the first and second directions, can be set according to actual needs and are not specifically limited here. It should be noted that the first and second directions can be any two adjacent directions that are parallel to the back side of the semiconductor substrate and are different from each other. Optionally, the first and second directions can be perpendicular.

[0055] Regarding the first semiconductor layer and the second semiconductor layer, in terms of area ratio, the area ratio of the first semiconductor layer and the second semiconductor layer on the back side of the semiconductor substrate can be set according to actual needs.

[0056] In terms of conductivity type, the doping types of the first and second semiconductor layers can be determined based on the doping type of the semiconductor substrate, as long as the first semiconductor layer and the semiconductor substrate have the same doping type, and the second semiconductor layer and the semiconductor substrate have opposite doping types. For example, when the semiconductor substrate is a P-type substrate, the first semiconductor layer is a P-type semiconductor layer, and the second semiconductor layer is an N-type semiconductor layer. As another example, when the semiconductor substrate is an N-type substrate, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

[0057] In terms of materials, the first semiconductor layer and / or the second semiconductor layer can be made of any semiconductor material such as silicon, germanium-silicon, germanium, or gallium arsenide. In terms of the arrangement of matter, the crystal phase of the first semiconductor layer and / or the second semiconductor layer can be amorphous, microcrystalline, nanocrystalline, single-crystal, or polycrystalline. The materials of the first semiconductor layer and the second semiconductor layer can be the same or different. For example, both the first and second semiconductor layers can be made of doped polycrystalline silicon. Another example is that both the first and second semiconductor layers can be made of at least one of doped amorphous silicon, doped nanocrystalline silicon, or doped microcrystalline silicon.

[0058] In terms of location, the first semiconductor layer can be directly disposed on the semiconductor substrate. Or, as... Figure 1 As shown, the back contact battery may further include a first interface passivation layer 27 located between the first semiconductor layer 12 and the semiconductor substrate 11. In this case, the first interface passivation layer 27 and the first semiconductor layer 12 can form a selective contact structure to achieve chemical passivation of the corresponding area on the back side of the semiconductor substrate 11 and selective collection of carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the back side and improving the photoelectric conversion efficiency of the back contact battery.

[0059] Specifically, the material of the first interface passivation layer can be determined based on the material of the first semiconductor layer and the type of selective contact structure formed by the first interface passivation layer and the first semiconductor layer in the actual application scenario; no specific limitation is made here. For example, when the first semiconductor layer is a doped polycrystalline silicon layer, the first interface passivation layer is a tunneling passivation layer; the material of the tunneling passivation layer can include materials such as silicon oxide, aluminum oxide, or titanium oxide. As another example, when the material of the first semiconductor layer can include at least one of doped amorphous silicon, doped nanocrystalline silicon, and doped microcrystalline silicon, the material of the first interface passivation layer can include at least one of intrinsic amorphous silicon, intrinsic nanocrystalline silicon, and intrinsic microcrystalline silicon.

[0060] As for the second semiconductor layer, it can be directly disposed on the semiconductor substrate. Or, as... Figure 1 As shown, the back contact cell may further include a second interface passivation layer 28 located at least between the second semiconductor layer 13 and the semiconductor substrate 11 to reduce the carrier recombination rate on the back side, thereby improving the photoelectric conversion efficiency of the back contact cell. The principle for selecting the material of the second interface passivation layer 28 can refer to the principle for selecting the material of the first interface passivation layer described above, and will not be repeated here.

[0061] Optionally, the first semiconductor layer may include a doped polycrystalline silicon layer, and the second semiconductor layer may include at least one of a doped amorphous silicon layer, a doped nanocrystalline silicon layer, and a doped microcrystalline silicon layer. The back contact battery also includes a first interface passivation layer located between the first semiconductor layer and the semiconductor substrate, and a second interface passivation layer located between the second semiconductor layer and the semiconductor substrate. The first interface passivation layer includes a tunneling passivation layer, and the second interface passivation layer includes at least one of an intrinsic amorphous silicon layer, an intrinsic nanocrystalline silicon layer, and an intrinsic microcrystalline silicon layer. In this case, the back contact battery may also include a transparent conductive layer. The transparent conductive layer is at least disposed on the side of the second semiconductor layer facing away from the semiconductor substrate (and may also be disposed on the side of the first semiconductor layer facing away from the semiconductor substrate). Furthermore, the transparent conductive layer is etched with insulating trenches using etching paste or laser processes. Figure 1 As shown, when the transparent conductive layer is disposed on the side of the first semiconductor layer 12 and the second semiconductor layer 13 facing away from the semiconductor substrate 11, the insulating trench can be arranged in a ring shape to isolate the portion of the transparent conductive layer directly electrically connected to the first semiconductor layer 12 and the portion of the transparent conductive layer directly electrically connected to the second semiconductor layer 13, preventing short circuits. Furthermore, in this case, the electrode structure of the back-contact battery can be a non-burn-through electrode (e.g., an electrode formed using copper paste, or an electrode formed using base metal pastes such as silver-coated copper, or an electrode formed using low-temperature silver paste). The non-burn-through paste can be cured at low temperatures to form the electrode, thereby preventing damage to the transparent conductive layer from high-temperature processes and affecting battery efficiency. Further, the non-burn-through electrode can be formed using base metal pastes such as low-temperature silver-coated copper paste, low-temperature copper paste, or low-temperature nickel paste, thereby reducing the electrode manufacturing cost. In addition, when using base metal pastes such as copper paste, the transparent conductive layer can also act as a barrier layer, preventing copper ions in the copper paste from diffusing into the battery, thereby improving the efficiency of the solar cell.

[0062] Optionally, both the first and second semiconductor layers include a doped polycrystalline silicon layer. The back contact cell further includes a first interface passivation layer located between the first semiconductor layer and the semiconductor substrate, and a second interface passivation layer located between the second semiconductor layer and the semiconductor substrate. Both the first and second interface passivation layers include a tunneling passivation layer. In this case, the back contact cell may also include a surface passivation layer. The surface passivation layer is disposed on the side of the first semiconductor layer facing away from the semiconductor substrate and on the side of the second semiconductor layer facing away from the semiconductor substrate to reduce the carrier recombination rate and improve the conversion efficiency of the back contact cell. This cell structure is a back contact tunneling oxide passivated contact cell (TBC cell). The surface passivation layer is made of an insulating material and can be a single-layer structure or a multi-layer structure. Its material includes at least one or two of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. For a TBC cell, its surface passivation layer may include aluminum oxide and silicon nitride layers stacked facing away from the silicon substrate. Furthermore, in this case, during practical applications, the electrode structure of the back contact battery can be a non-burn-through electrode (e.g., an electrode made using copper paste, or an electrode made using base metal pastes such as silver-coated copper), further reducing the cost of electrode manufacturing. For example, silver paste can be dot-printed onto the semiconductor portion to first burn through the surface passivation layer on the semiconductor portion; then, the first current collector electrode made of copper paste can be printed. Alternatively, an opening can be etched into the surface passivation layer using a laser irradiation process to expose the semiconductor portion, and a barrier layer such as nickel can be formed in the opening area by electroplating or chemical plating, followed by the printing of the first current collector electrode made of copper paste. The barrier layer can effectively block base metals such as copper, preventing copper diffusion.

[0063] In terms of distribution, the distribution of the first semiconductor layer and the second semiconductor layer on the back side of the semiconductor substrate can be set according to the materials of the two layers and actual needs.

[0064] For example, such as Figure 7 As shown, the first semiconductor layer 12 and the second semiconductor layer 13 can be spaced apart along a direction parallel to the back surface. On the back surface of the semiconductor substrate 11, the region between the first semiconductor layer 12 and the second semiconductor layer 13 is an isolation region.

[0065] Or, such as Figure 1As shown, at least a portion of the second semiconductor layer 13 can also extend to cover a portion of the first semiconductor layer 12, thereby reducing the etching amount of the patterning process of the second semiconductor layer 13 and improving etching yield. Furthermore, in this case, in the stacked structure formed by stacking the first semiconductor layer 12 and the second semiconductor layer 13 along the thickness direction of the semiconductor substrate 11, whether the first semiconductor layer 12 and the second semiconductor layer 13 are electrically connected can be determined according to actual needs. For example, in the stacked structure, an insulating layer (such as a silicon oxide layer, a silicon nitride layer, or an aluminum oxide layer) can be provided between the second semiconductor layer 13 and the first semiconductor layer 12 to isolate them, reduce leakage current, and improve the conversion efficiency of the back contact battery in the forward voltage region; alternatively, in the stacked structure, the first semiconductor layer 12 and the second semiconductor layer 13 can also be electrically connected. In this case, at the stacked structure, the first semiconductor layer 12 and the second semiconductor layer 13 can form a built-in diode structure with a low reverse breakdown voltage to reduce the hot spot risk of the back contact battery and improve the burn-out resistance of the back contact battery.

[0066] For example: Figure 1 As shown, the region on the back side of the semiconductor substrate 11 where the first semiconductor layer 12 is disposed is defined as the first region 19, and the remaining region is defined as the second region 20. In this case, the second semiconductor layer 13 is not only disposed on the second region 20, but also extends to cover the edge region of at least one semiconductor portion 14 to form a stacked structure. Furthermore, a transparent conductive layer is disposed on the side of the second semiconductor layer 13 facing away from the semiconductor substrate 11. This transparent conductive layer is not only located on the second region 20, but also extends to cover at least a portion of the stacked structure. The portion of the stacked structure covered by the transparent conductive layer extending from the second region 20 can form a reverse leakage region, reducing the risk of hot spots in the battery.

[0067] The position where the second semiconductor layer extends and covers at least one semiconductor part can be set according to the distribution of the electrode structure electrically connected to the first semiconductor layer and actual needs.

[0068] For example: Figure 1 As shown, the second semiconductor layer 13 further extends and covers the edge region of at least one semiconductor portion 14 along the first direction to form a stacked structure. In other words, the edge region of at least one semiconductor portion 14 covered by the second semiconductor layer 13 is disposed at both ends of the semiconductor portion 14 along the first direction. Furthermore, in the stacked structure, at least a portion of the first semiconductor layer 12 and the second semiconductor layer 13 are electrically connected (e.g., ...). Figure 1As shown, a transparent conductive layer is also disposed on the side of the second semiconductor layer 13 facing away from the semiconductor substrate 11. This transparent conductive layer is not only located on the second region 20, but also extends at least along the first direction and covers at least part of the stacked structure. This arrangement helps to stagger the stacked structure (or the stacked structure and the transparent conductive layer) from the first current collector 16 extending along the first direction, preventing excessive leakage current caused by the first current collector 16 overlapping the stacked structure. This helps to ensure that the back contact battery has a high conversion efficiency in the forward voltage region. At the same time, it eliminates the need to strictly control the size of the stacked structure and / or the printing accuracy of the first current collector 16 in order to stagger the first current collector 16 from the stacked structure, thereby improving the yield of the back contact battery.

[0069] Alternatively, the second semiconductor layer may not only be disposed on the second region, but also extend to cover the edge region of at least one semiconductor portion along the second direction, to form a stacked structure. In this case, the first collector electrode can be isolated from the second semiconductor layer in its own extending direction by the first insulating isolation structure, preventing excessive leakage current.

[0070] Alternatively, the second semiconductor layer may not only be disposed on the second region, but also extend and cover the edge regions of at least one semiconductor portion along the first and second directions to form a stacked structure. In this case, the first collector electrode can be isolated from the second semiconductor layer in its own extending direction by the first insulating isolation structure to prevent excessive leakage current.

[0071] In practical applications, such as Figure 1 As shown, the leakage current range can be controlled by adjusting the coverage area of ​​the transparent conductive layer disposed on the second semiconductor layer 13. For example, the second semiconductor layer 13 may also extend to cover at least one edge region of the semiconductor portion 14 along the first and second directions, but the transparent conductive layer disposed on the second semiconductor layer 13 may extend only from the second region to cover the second semiconductor layer 13 located at both ends of the semiconductor portion 14 along the first direction, while the transparent conductive layer extending from the second region 20 is not disposed on the second semiconductor layer 13 located at both ends of the semiconductor portion 14 along the first direction.

[0072] Optional, such as Figure 7 As shown, when both the first semiconductor layer 12 and the second semiconductor layer 13 are doped with polysilicon, the first semiconductor layer 12 and the second semiconductor layer 13 can be distributed at intervals along a direction parallel to the back surface.

[0073] Optional, such as Figure 1As shown, when the first semiconductor layer 12 includes a doped polycrystalline silicon layer and the second semiconductor layer 13 includes at least one of a doped amorphous silicon layer, a doped nanocrystalline silicon layer, and a doped microcrystalline silicon layer, the first semiconductor layer 12 is disposed on a first region 19 on the back side of the semiconductor substrate 11, and the second semiconductor layer 13 is disposed on a second region 20 on the back side of the semiconductor substrate 11, and also extends to cover at least the edge region along the second direction in at least one semiconductor portion 14.

[0074] In terms of height, the area on the back side of the semiconductor substrate where the first semiconductor layer is disposed is defined as the first region, and the remaining area is defined as the second region. The surface height of the first region and the second region can be set according to the distribution and manufacturing sequence of the first and second semiconductor layers on the back side of the semiconductor substrate, as well as actual requirements.

[0075] For example, such as Figure 1 As shown, the surface height of the second region 20 can be less than the surface height of the first region 19. In this case, the second region 20 is more recessed into the semiconductor substrate 11 relative to the first region 19. This configuration, with its smaller surface height, indicates that during the fabrication of the back contact battery, in the process of patterning the entire first semiconductor layer 12, the portion of the semiconductor substrate 11 corresponding to the second region 20 is selectively etched. This reduces or even prevents the presence of residual first semiconductor material in the second region 20, lowering the risk of leakage and improving the carrier collection efficiency of the second semiconductor layer 13. Furthermore, the height difference between the first region 19 and the second region 20 can at least partially offset the first semiconductor layer 12 located in the first region 19 and the second semiconductor layer 13 located in the second region 20 along the thickness direction of the semiconductor substrate 11, reducing the risk of leakage between them.

[0076] Of course, the surface height of the second region can also be the same as that of the first region.

[0077] Furthermore, when the second semiconductor layer is not only disposed on the second region but also extends to cover a portion of the first semiconductor layer, the surface heights of different portions of the second region can be approximately the same.

[0078] Or, such as Figure 7As shown, when at least a portion of the first semiconductor layer 12 and at least a portion of the second semiconductor layer 13 are spaced apart along a direction parallel to the back surface of the semiconductor substrate 11, the region on the back surface of the semiconductor substrate 11 located between the first semiconductor layer 12 and the second semiconductor layer 13 is an isolation region. In the second region 20, the region other than the isolation region is defined as a third region. Along the direction from the front to the back surface of the semiconductor substrate 11, the surface height of the third region may be less than the surface height of the first region 19, and the surface height of the isolation region may be less than or equal to the surface height of the third region.

[0079] For example, such as Figure 1 and Figure 5 As shown, when the surface height of the second region 20 is less than the surface height of the first region 19, the first insulating isolation structure 18 can be disposed on the portion of the second semiconductor layer 13 corresponding to the second region 20. In this case, the surface height of the second region 20 is smaller than that of the first region 19. The first insulating isolation structure 18 is used to isolate the first collector electrode 16 from the second semiconductor layer 13, and to isolate the interconnect (or the interconnect and the first bus electrode) from the second semiconductor layer 13. Since the second semiconductor layer 13 surrounds the outer periphery of the semiconductor portion 14, when the first collector electrode 16 extends along the second direction, it is disposed not only on the semiconductor portion 14 with a larger surface height but also passes through the second semiconductor layer 13 with a smaller surface height in its extension direction. Similarly, for the interconnect (or the interconnect and the first bus electrode), it is disposed not only on the semiconductor portion 14 with a larger surface height but also passes through the second semiconductor layer 13 with a smaller surface height in its extension direction. Based on this, when the first insulating isolation structure 18 is disposed on the portion of the second semiconductor layer 13 corresponding to the second region 20, the first collector electrode 16 and the interconnect (or the interconnect and the first bus electrode) disposed on the second semiconductor layer 13 can be raised by additionally setting the first insulating isolation structure 18, so that the height difference between different portions of the first collector electrode 16 and the interconnect (or the interconnect and the first bus electrode) along their respective extension directions is small, the flatness is high, the contact performance is improved, and it is also beneficial to prevent detachment and improve the bonding stability.

[0080] Of course, in addition to being disposed on the portion of the second semiconductor layer corresponding to the second region, the first insulating isolation structure can also extend to the edge portion of the semiconductor portion. Under the premise of ensuring that short circuits can be prevented, the precision requirements for printing the first insulating isolation structure can be reduced, and the manufacturing difficulty can be reduced.

[0081] In practical applications, the surfaces of the first and / or second regions on the back side of the semiconductor substrate can be planar to improve the deposition quality and passivation effect of the first or second semiconductor layer formed on it. Alternatively, as... Figure 1 and Figure 8 As shown, the surface of the first region 19 can be flat, and the surface of the second region 20 can be textured. This arrangement helps to increase the contact area between the second semiconductor layer 13 and the corresponding conductive material, thereby reducing the contact resistance.

[0082] Additionally, for example, when the surface of the second region is velvety, a side surface for connection is provided between the first and second regions. The surface topography of this side surface, and the degree of inclination of the side surface relative to the surface of the first region, can be set according to actual needs.

[0083] For example, the side between the first region and the second region can also be a plane; or, a velvet structure can be provided on the side.

[0084] The side between the first region and the second region is defined as a first side and a second side. The first side is located at the edges of the first region extending along a first direction and along a second direction; the second side is located at the four corners where every two adjacent edges of the first region intersect.

[0085] For example, such as Figure 8 As shown, at least a portion of the first side surface may have a ridge-shaped protrusion structure 21. Compared to a flat surface, this ridge-shaped protrusion structure 21 increases the undulation of the side surface, increases the contact area between the second semiconductor layer 13 and the side surface, facilitates carrier collection, and increases the passivation contact area, reducing the carrier recombination rate. Simultaneously, it also improves the light-trapping effect of the side surface, thus increasing the bifaciality of the back-contact battery. Furthermore, compared to a textured structure, the ridge-shaped protrusion structure 21 has lower roughness, which helps prevent an excessively large specific surface area on the side surface, improving the deposition quality and coating effect of the second semiconductor layer 13 on the side surface.

[0086] For example, such as Figure 8As shown, at least one corner of the second side surface can have a sheet-like protrusion structure 22. This configuration is understandable because the at least four corner positions of the first region 19 have greater undulations than the straight sections of the side surface due to the presence of corners. Therefore, having a sheet-like protrusion structure 22 at at least one corner, which is flatter than the ridge-like protrusion structure 21, can effectively reduce the roughness at the corner position, improve the coverage and passivation effect of the second semiconductor layer 13 at the corner position, and reduce the carrier recombination rate. The sheet-like protrusion structure 22 refers to a protrusion structure whose width and length are greater than its height in its three-dimensional dimensions (the height direction of the sheet-like protrusion structure 22 refers to the direction perpendicular to its side surface), so as to make itself relatively flat and reduce its roughness. The shape of the sheet-like protrusion structure 22 can be set according to actual needs. For example, the sheet-like protrusion structure 22 can be triangular or polygonal.

[0087] Alternatively, the second side at at least one corner may also be provided with a ridge-like protrusion structure.

[0088] Furthermore, in the first semiconductor layer, the semiconductor portion can be square, rectangular, rhomboid, circular, elliptical, or a polygon with a side length of 5 or more. Different semiconductor portions can have the same or different shapes. As for the distribution of multiple semiconductor portions on the back side, it can be set according to the structure and morphology of the first collector electrode and the first interconnect structure, as well as actual needs, and is not specifically limited here.

[0089] Secondly, in the first semiconductor layer, the number of semiconductor portions included in different groups of semiconductor portions can be the same or different. Along the second direction, the lengths of different semiconductor portions within the same group of semiconductor portions can be the same or different. The lengths of two semiconductor portions belonging to different groups of semiconductor portions can be the same or different. As for the specific length and width of the semiconductor portions, they can be determined based on the area ratio of the first semiconductor layer and the second semiconductor layer on the back side in the actual application scenario.

[0090] For example, along the second direction, the length of at least one semiconductor portion can be greater than or equal to 150 μm and less than or equal to 15000 μm. For instance, the length of at least one semiconductor portion can be 150 μm, 180 μm, 200 μm, 240 μm, 280 μm, 300 μm, 500 μm, 1000 μm, 1500 μm, 2000 μm, 5000 μm, 10000 μm, or 15000 μm, etc.

[0091] For example, such as Figure 2 and Figure 3As shown, on the back side of the semiconductor substrate 11, the region between two adjacent semiconductor portions 14 along the second direction is defined as the target region 15. The projections of at least two rows of target regions 15 adjacent along the first direction can be staggered. With this arrangement, it can be understood that on the back side of the semiconductor substrate 11, the target region 15 is the region between two adjacent semiconductor portions 14 along the second direction, on which a second semiconductor layer 13 is disposed. Based on this, when the back contact battery is in operation, charge carriers of the same conductivity type as the first semiconductor layer 12 generated at the target region 15 need to be transported to the adjacent semiconductor portion 14 and collected thereon. Based on this, when the projections of at least two adjacent rows of target regions 15 along the first direction are staggered, the target region 15 not only has two adjacent semiconductor sections 14 along the second direction, but also has two adjacent semiconductor sections 14 along the first direction. Compared with the projections of at least two adjacent rows of target regions 15 along the first direction overlapping (where the charge carriers generated at the target region 15 with the same conductivity type as the first semiconductor layer 12 cannot be transmitted to the adjacent semiconductor section 14 along the first direction and need to be transmitted to a longer path to be collected), in this embodiment of the invention, the charge carriers generated at the target region 15 with the same conductivity type as the first semiconductor layer 12 can be collected by the semiconductor section 14 in a shorter transmission distance, optimizing the carrier transmission path, realizing effective collection of charge carriers, reducing the carrier recombination rate, and improving the working performance of the back contact battery.

[0092] In practical applications, such as Figure 2 and Figure 3 As shown, there may be two adjacent rows of target areas 15 whose projections are staggered along the first direction; or there may be multiple adjacent rows of target areas 15 whose projections are staggered along the first direction, such as... Figure 9 As shown, the projections of the three adjacent target areas 15 along the first direction are staggered in the first direction.

[0093] Wherein, when there are multiple rows of target areas adjacent to each other along the first direction whose projections are staggered in the first direction, any two rows of the adjacent multiple rows of target areas whose projections are staggered in the first direction can have their projections staggered in the first direction.

[0094] Alternatively, two rows of target areas that are not adjacent along the first direction may have projections that at least partially overlap in the first direction. In this case, among the adjacent rows of target areas whose projections are staggered in the first direction, the specific rows of non-adjacent target areas whose projections at least partially overlap in the first direction can be determined based on the length of the target area and the semiconductor section, as well as actual requirements.

[0095] For example, at least two rows of target regions along the first direction have overlapping projections in the first direction, and at least one set of semiconductor portions is included between the two overlapping rows of target regions. With this configuration, the projections of different rows of target regions in the first direction on the back side of the semiconductor substrate can be regularly distributed, which simplifies the patterning process during the fabrication of the first and second semiconductor layers. Furthermore, while ensuring that the projections of multiple adjacent rows of target regions along the first direction are staggered, allowing carriers with the same conductivity type as the first semiconductor layer within the target region to be effectively collected, the length of the semiconductor portion can be reduced and / or the target region can have a certain length. This increases the junction area of ​​the PN junction, thereby improving carrier separation and collection efficiency. Simultaneously, it also helps to reduce the edge length between the first and second semiconductor layers, reducing the impact of edge recombination on battery conversion efficiency.

[0096] It should be noted that you can first select a target area, then determine another target area that overlaps with the projection of the target area in the first direction and has the smallest spacing in the first direction, and then determine the number of semiconductor groups between the two target areas.

[0097] Furthermore, it is understandable that the length of the target region, the distance between the projections of two adjacent rows of target regions in the first direction, and the length of the semiconductor section all affect how many adjacent rows of target regions are projected and staggered in the first direction on the back side of the semiconductor substrate, thereby affecting the collection of charge carriers by the first and second semiconductor layers. Therefore, the length of the target region and the distance between the projections of two adjacent rows of target regions in the first direction can be determined based on the requirements for the charge carrier collection efficiency of the first and second semiconductor layers in the actual application scenario, as well as the size of the semiconductor substrate.

[0098] For example, along the second direction, the ratio of the length of at least one target region to the length of the semiconductor portion can be greater than or equal to 3% and less than or equal to 40%. For instance, the ratio of the length of at least one target region to the length of the semiconductor portion can be 3%, 5%, 8%, 10%, 15%, 20%, 25%, 30%, 35%, or 40%, etc. With this configuration, it can be understood that the target region is a region on the back side of the semiconductor substrate located between two adjacent semiconductor portions along the second direction, and a second semiconductor layer is disposed on this region. It is evident that the length of the target region also affects the coverage area of ​​the second semiconductor layer disposed on it on the back side. Based on this, when the ratio of the length of at least one target region to the length of the semiconductor portion is within the aforementioned range, it can prevent the target region from being too short and / or the semiconductor portion from being too long due to an excessively small ratio. This helps ensure that the second semiconductor layer has a larger area ratio on the back side of the semiconductor substrate, increasing the junction area of ​​the PN junction, thereby improving the separation and collection efficiency of charge carriers. Simultaneously, it also helps to reduce the edge length between the first and second semiconductor layers, which can reduce the impact of edge recombination on the battery conversion efficiency. In addition, it can prevent the target region from being too long and / or the semiconductor section from being too short due to an excessively large ratio, which helps to ensure that the first semiconductor layer has good carrier collection capability and reduce carrier recombination rate.

[0099] For example, the length of at least one target region along the second direction may be greater than or equal to the width of the semiconductor portion along the first direction. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect described above where the ratio of the length of at least one target region to the length of the semiconductor portion is greater than or equal to 3% and less than or equal to 40%, which will not be repeated here.

[0100] For example, along the second direction, the length of at least one target region can be greater than or equal to 50 μm and less than or equal to 5000 μm. For instance, the length of at least one target region can be 50 μm, 80 μm, 100 μm, 200 μm, 300 μm, 500 μm, 800 μm, 1000 μm, 2000 μm, 3000 μm, 4000 μm, or 5000 μm, etc. The application principle of the beneficial effect in this case can be referred to the application principle of the beneficial effect described above where the ratio of the length of at least one target region to the length of the semiconductor portion is greater than or equal to 3% and less than or equal to 40%, which will not be repeated here.

[0101] For example, the distance between the projections of two adjacent rows of target regions along the first direction can be less than or equal to 8000 μm. For instance, the distance between the projections of two adjacent rows of target regions along the first direction can be 0, 2 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 30 μm, 50 μm, 60 μm, 80 μm, 100 μm, 500 μm, 1000 μm, 5000 μm, or 8000 μm, etc. This setting prevents the target region from being too short and / or the semiconductor portion from being too long due to excessive spacing. It helps ensure that the second semiconductor layer has a large area ratio on the back side of the semiconductor substrate, increasing the junction area of ​​the PN junction, thereby improving carrier separation and collection efficiency. Simultaneously, it also helps reduce the edge length between the first and second semiconductor layers, reducing the impact of edge recombination on battery conversion efficiency.

[0102] In addition, in practical applications, the distribution of the first interconnect structure and the second interconnect structure on the back side of the semiconductor substrate can be set according to actual needs.

[0103] For example, such as Figure 4 As shown, at least one first interconnect structure 17 can be offset from the projection of the target region 15 in the first direction. With this arrangement, it can be understood that multiple first collector electrodes 16 correspond one-to-one with multiple sets of semiconductor sections 14, and each first collector electrode 16 is electrically connected to the corresponding set of semiconductor sections 14. In this case, charge carriers within the semiconductor section 14 can be collected through the first collector electrodes 16. The interconnects used to connect two adjacent back-contact batteries in series are electrically connected to the first interconnect structure 17, allowing charge carriers to be discharged through the first interconnect structure 17 electrically connected to the first collector electrodes 16. When multiple first interconnect structures 17 are spaced apart along the second direction, the interconnects used to connect two adjacent back-contact batteries in series also extend along the first direction. Based on this, when at least one first interconnect structure 17 is offset from the projection of the target region 15 in the first direction, it is advantageous that the interconnects can be placed on more rows of semiconductor sections 14 when extending along the first direction, which helps reduce the number and / or area of ​​the first insulating isolation structures 18, prevents battery warping, improves battery yield, and reduces the risk of leakage.

[0104] Alternatively, at least one first interconnect structure may at least partially overlap with the projection of at least one target region in the first direction. This arrangement reduces the precision requirements for manufacturing the first interconnect structure; simultaneously, it facilitates shortening the length of the semiconductor portion, increasing the PN junction area, and improving carrier separation and collection.

[0105] As for the second interconnect structure, such as Figure 4As shown, at least one second interconnect structure 25 can be offset from the projection of the target area 15 in the first direction. This arrangement helps to ensure that the spacing between different second interconnect structures 25 and their adjacent first interconnect structures 17 is approximately the same, resulting in a relatively regular distribution of the second interconnect structures 25 and the first interconnect structures 17 on the back side, thus reducing manufacturing difficulty.

[0106] Or, such as Figure 10 As shown, the projection of at least one second interconnect structure 25 in the first direction lies within the projection of at least one target region 15 in the first direction. This arrangement, where the projection of at least one second interconnect structure 25 in the first direction lies within the projection of at least one target region 15 in the first direction, facilitates the placement of the second interconnect structure 25 on more rows of the second semiconductor layer 13 as it extends along the first direction. This reduces the number and / or area of ​​the second insulating isolation structure 26, prevents battery warping, improves battery yield, and reduces the risk of leakage.

[0107] Furthermore, there are at least two instances of the arrangement of the first interconnection structure and the second interconnection structure on the back side, and a suitable solution can be selected according to different needs, thereby improving the applicability of the back contact battery provided by the embodiments of the present invention in different application scenarios.

[0108] The spacing between two adjacent first interconnect structures or two adjacent second interconnect structures along the second direction, as well as the spacing between the first interconnect structure and the second interconnect structure along the second direction, can be determined based on the distribution of different target regions, the length of the semiconductor section, and the requirements for carrier collection efficiency.

[0109] For example, such as Figure 4 As shown, at least one semiconductor portion 14 can be disposed between two adjacent first interconnect structures 17 along the second direction. This arrangement can prevent the spacing between two adjacent first interconnect structures 17 along the second direction from being too small and / or the length of the semiconductor portion 14 from being too large. It can also prevent the number of first interconnect structures 17 spaced apart along the second direction from being too large, which would lead to excessive material consumption and a large light-shielding area of ​​the first interconnect structure 17. This is beneficial for reducing the manufacturing cost of the back contact battery and improving the bifaciality of the back contact battery. Secondly, it is beneficial for controlling the length of the semiconductor portion 14, which helps to ensure that the second semiconductor layer 13 has a large area ratio on the back side of the semiconductor substrate 11, increasing the junction area of ​​the PN junction, and thus improving the separation and collection efficiency of charge carriers. At the same time, it is also beneficial for reducing the edge length between the first semiconductor layer 12 and the second semiconductor layer 13, which can reduce the impact of edge recombination on the battery conversion efficiency.

[0110] As for the morphology of the first collector electrode, such as Figure 4As shown, the portion of the first collector electrode 16 located on at least one semiconductor portion 14 may be arranged in a strip shape. Optionally, the width of the first collector electrode 16 on at least one semiconductor portion 14 may be greater than the width of the portion of itself located on the target region 15.

[0111] Alternatively, as Figures 11 to 13 shown, the portion of the first collector electrode 16 located on at least one semiconductor portion 14 may also be in a special shape (which means that in the same first collector electrode 16, the shape of a certain region is different from the shapes of the remaining regions). For example, as Figures 11 to 13 shown, the special shape may include a shape like a Chinese character 'ri' (日), a Chinese character 'tian' (田), a Chinese character'mi' (米), or a Chinese character 'feng' (丰), etc.; by setting it like this, while reducing the area ratio of the first semiconductor layer 12 on the back surface, the contact area between the first collector electrode 16 and at least one semiconductor portion 14 can be effectively increased, and the contact resistance between the two can be reduced. As for the specific morphology of the patterned setting, it can be determined according to the requirements for the contact area between the first collector electrode 16 and the first semiconductor layer 12 in the actual application scenario, and no specific limitation is made here.

[0112] As for the electrode structure electrically connected to the second semiconductor layer, as Figure 4 shown, it may only include the second collector electrode 23 and the second interconnection structure 25.

[0113] Alternatively, as Figure 14 shown, the back-contact battery may further include: a plurality of second auxiliary electrodes 24 provided on the side of the second semiconductor layer 13 facing away from the semiconductor substrate 11. The second auxiliary electrodes 24 extend from the second collector electrode 23 and extend to the corresponding target region 15. The plurality of second auxiliary electrodes 24 on the same second collector electrode 23 extend along the first direction and are spaced apart along the second direction. The second collector electrode 23 and the second auxiliary electrodes 24 are arranged in a grid shape or a fishbone shape. In this case, the presence of the second auxiliary electrodes 24 can improve the carrier collection efficiency at the target region 15 and reduce the carrier recombination rate.

[0114] It should be noted that the second auxiliary electrodes are based on the existence of the second collector electrode. The carriers collected by the second auxiliary electrodes are conducted to the second collector electrode and are led out to the second interconnection structure 25 by the second collector electrode. Additionally, as Figure 15 shown, along the first direction, when the second auxiliary electrodes 24 electrically connected to two adjacent second collector electrodes 23 are continuously arranged in the target region 15, the electrode formed by the second collector electrode 23 and the second auxiliary electrodes 24 presents a grid shape; at this time, the second auxiliary electrodes 24 can be isolated from the first collector electrode 16 through the first insulating isolation structure 18.

[0115] As Figure 14As shown, along the first direction, when the second auxiliary electrode 24, which is electrically connected to the two adjacent second collector electrodes 23, is disconnected in the target area 15, the electrode formed by the second collector electrode 23 and the second auxiliary electrode 24 presents a fishbone shape.

[0116] In actual manufacturing, the second current collector electrode and the second auxiliary electrode can be manufactured simultaneously, in which case they are integrally formed with no obvious boundary. Alternatively, the second current collector electrode and the second auxiliary electrode can be formed separately in different operational steps.

[0117] The length of the second auxiliary electrode extending along the first direction relative to the second collector electrode, the number of second auxiliary electrodes distributed in the same target area, and the spacing between the second auxiliary electrode and the adjacent semiconductor part along the second direction can be determined according to the requirements of carrier collection efficiency, light shielding effect and consumables of the second auxiliary electrode, and leakage prevention in the actual application scenario.

[0118] For example, at least one second auxiliary electrode may be provided on at least one target area.

[0119] Or, such as Figure 14 As shown, at least one target region 15 may be provided with a plurality of second auxiliary electrodes 24 spaced apart along the second direction. This arrangement is beneficial to further improve the carrier collection efficiency at the target region 15 and reduce the carrier recombination rate.

[0120] For example, in at least one target area, the spacing between two adjacent second auxiliary electrodes along the second direction can be greater than or equal to 10 μm and less than or equal to 3000 μm. For instance, the spacing between two adjacent second auxiliary electrodes along the second direction can be 10 μm, 15 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 500 μm, 1000 μm, 1500 μm, 2000 μm, or 3000 μm, etc. This arrangement, with the spacing between two adjacent second auxiliary electrodes along the second direction within the aforementioned range, prevents excessive material consumption and excessive light-shielding area of ​​the second auxiliary electrodes due to excessively small spacing on the same target area. This helps control the manufacturing cost of the back contact battery and improves the bifaciality of the back contact battery. In addition, it can also prevent the number of second auxiliary electrodes on the target area from being too small due to excessive spacing, and ensure that the carriers generated in different parts of the target area along the second direction can be collected and discharged in time through the second auxiliary electrodes, thereby reducing the carrier recombination rate.

[0121] For example, along the second direction, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one target region can be greater than or equal to 10 μm and less than or equal to 3000 μm. For instance, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one target region can be 10 μm, 15 μm, 20 μm, 30 μm, 40 μm, 50 μm, 100 μm, 500 μm, 1000 μm, 1500 μm, 2000 μm, or 3000 μm, etc. With this configuration, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one target region is within the aforementioned range. This prevents the distance between the second auxiliary electrode and the adjacent semiconductor portion with the opposite conductivity type from being too small due to the minimum distance being too small, reducing the risk of leakage and lowering the manufacturing difficulty of the second auxiliary electrode. Furthermore, it also prevents the number of second auxiliary electrodes on the target region from being too small due to the minimum distance being too large, ensuring that charge carriers generated in different parts of the target region along the second direction can be collected and discharged in a timely manner through the second auxiliary electrode, reducing the charge carrier recombination rate.

[0122] Secondly, embodiments of the present invention provide a photovoltaic module comprising: a plurality of cell strings and an encapsulation layer. The cell strings include a plurality of solar cells and a plurality of interconnecting elements. The interconnecting elements are used to connect the plurality of solar cells in series. The solar cells are back-contact cells as provided in the first aspect and its various implementations; the encapsulation layer covers the surface of the cell strings.

[0123] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0124] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0125] The embodiments of the present invention have been described above. However, these embodiments are merely for clarity and are not intended to limit the scope of the invention. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A back-contact battery, characterized in that, include: A semiconductor substrate, and a first semiconductor layer and a second semiconductor layer disposed on the back side of the semiconductor substrate; The first semiconductor layer and the semiconductor substrate have the same doping type, and the first semiconductor layer includes a plurality of semiconductor portions discretely disposed on the back side; The second semiconductor layer and the semiconductor substrate have opposite doping types; The second semiconductor layer surrounds the plurality of said semiconductor portions; The plurality of semiconductor portions are multiple groups of semiconductor portions spaced apart along a first direction, and each group of semiconductor portions includes multiple semiconductor portions spaced apart and collinear along a second direction; the first direction is different from the second direction; On the back side of the semiconductor substrate, the region between two adjacent semiconductor portions along the second direction is defined as a target region; at least two rows of target regions adjacent along the first direction are staggered in the projection of the target regions in the first direction.

2. The back contact battery according to claim 1, characterized in that, The projections of at least two rows of the target regions along the first direction overlap in the first direction, and at least one set of semiconductor portions is included between the two overlapping rows of the target regions.

3. The back contact battery according to claim 1, characterized in that, Along the second direction, the ratio of the length of at least one target region to the length of the semiconductor portion is greater than or equal to 3% and less than or equal to 40%. And / or, at least one of the target regions has a length along the second direction that is greater than or equal to the width of the semiconductor portion along the first direction; And / or, along the second direction, the length of at least one of the target regions is greater than or equal to 50 μm and less than or equal to 5000 μm; And / or, along the second direction, the length of at least one of the semiconductor portions is greater than or equal to 150 μm and less than or equal to 15000 μm.

4. The back contact battery according to claim 1, characterized in that, The projections of two adjacent rows of the target area along the first direction are staggered by a distance of less than or equal to 8000 μm.

5. The back contact battery according to claim 1, characterized in that, The back contact battery further includes: a plurality of first current collector electrodes, a plurality of first interconnect structures, and a first insulating isolation structure; the plurality of first current collector electrodes extend along the second direction and are spaced apart along the first direction; the plurality of first interconnect structures extend along the first direction and are spaced apart along the second direction; each first current collector electrode is electrically connected to the first interconnect structure; the first insulating isolation structure is disposed between the first current collector electrode and the second semiconductor layer, and or, the first insulating isolation structure is disposed at the intersection of the extension line of the second semiconductor layer and the first interconnect structure along the first direction; Each of the first collector electrodes corresponds one-to-one with a plurality of the semiconductor portions, and each of the first collector electrodes is electrically connected to the corresponding group of the semiconductor portions; At least one of the first interconnect structures is offset from the projection of the target area in the first direction.

6. The back contact battery according to claim 5, characterized in that, Along the second direction, at least one of the semiconductor portions is disposed between two adjacent first interconnect structures.

7. The back contact battery according to claim 5, characterized in that, At least one portion of the first collector electrode located on at least one of the semiconductor portions is irregularly shaped, including the shape of a sun character, a field character, a rice character, or a fertile character; And / or, the width of at least one portion of the first collector electrode located on at least one of the semiconductor portions is greater than the width of the portion located on the target region.

8. The back contact battery according to claim 1 or 5, characterized in that, On the back side of the semiconductor substrate, the area where the first semiconductor layer is disposed is a first region, and the remaining area is a second region; the surface height of the second region is less than the surface height of the first region.

9. The back contact battery according to claim 8, characterized in that, The first insulating isolation structure is disposed on the portion of the second semiconductor layer corresponding to the second region.

10. The back contact battery according to claim 8, characterized in that, The surface of the second region is velvety, and a side surface for connection is provided between the first region and the second region; The side includes a first side and a second side; the first side is located at the edge of the first region extending along the first direction and along the second direction; the second side is located at the four corners where every two adjacent edge lines of the first region intersect. At least a portion of the first side surface has a ridge-like protrusion structure; And / or, the second side surface located at at least one corner has a sheet-like protrusion structure.

11. The back contact battery according to claim 1, characterized in that, The second semiconductor layer further extends to cover at least one edge region of the semiconductor portion to form a stacked structure; the edge region is disposed at least at both ends of the semiconductor portion along the first direction; In the stacked structure, at least a portion of the first semiconductor layer is electrically connected to the second semiconductor layer.

12. The back contact battery according to claim 1, characterized in that, The back contact battery further includes: a plurality of second current collector electrodes and a plurality of second auxiliary electrodes disposed on the side of the second semiconductor layer opposite to the semiconductor substrate; A plurality of second collector electrodes extend along the second direction and are spaced apart along the first direction; the second collector electrodes are disposed between at least two groups of semiconductor portions adjacent to each other along the first direction; The second auxiliary electrode extends from the second current collector electrode and extends to the corresponding target area; multiple second auxiliary electrodes on the same second current collector electrode extend along the first direction and are spaced apart along the second direction; the second current collector electrode and the second auxiliary electrodes are arranged in a grid or fishbone pattern.

13. The back contact battery according to claim 12, characterized in that, At least one of the target areas is provided with a plurality of second auxiliary electrodes spaced apart along the second direction.

14. The back contact battery according to claim 13, characterized in that, In at least one of the target regions, the spacing between two adjacent second auxiliary electrodes along the second direction is greater than or equal to 10 μm and less than or equal to 3000 μm; And / or, along the second direction, the minimum distance between the second auxiliary electrode and the adjacent semiconductor portion on at least one of the target regions is greater than or equal to 10 μm and less than or equal to 3000 μm.

15. The back contact battery according to claim 12, characterized in that, The back contact battery also includes: multiple second interconnect structures and multiple second insulating isolation structures; A plurality of second interconnect structures extend along the first direction and are spaced apart along the second direction; each second interconnect structure is electrically connected to the second collector electrode; the second insulating isolation structure is disposed at the intersection of the first semiconductor layer and the extension line of the second interconnect structure along the first direction; In this configuration, at least one of the second interconnection structures is offset from the projection of the target area in the first direction; Alternatively, the projection of at least one of the second interconnect structures in the first direction lies within the projection of at least one of the target areas in the first direction.

16. A photovoltaic module, characterized in that, include: Multiple battery strings, each battery string comprising multiple solar cells and multiple interconnecting elements, the interconnecting elements being used to connect the multiple solar cells in series; wherein the solar cells are back-contact batteries as described in any one of claims 1 to 15; And an encapsulation layer that covers the surface of the battery string.

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