Semiconductor inner lead bonding quality detection method

Abstract

The invention discloses a semiconductor inner lead bonding quality detection method, relates to the technical field of semiconductor packaging testing, and is used for detecting the inner lead bonding quality of a semiconductor packaging device with a PN junction. According to the method, a forward bias test loop is built, constant direct current forward bias voltage of 1.8-2.2 V is applied to a PN junction of a semiconductor device to be tested, loop conduction current is limited within the range of 1mA-2mA through a current-limiting resistor, a forward conduction voltage drop value of the PN junction is independently collected in a stable state of continuously applying bias, and the forward conduction voltage drop value is compared with a preset threshold value to judge the bonding quality. According to the invention, the non-destructive detection of the bonding quality of the lead in the semiconductor is realized, the pulse large current impact is avoided, the distinguishing degree of good products and defective products is extremely high, the misjudgment risk is avoided, the existing mass production test equipment is compatible, the application range is wide, and the mass production full detection of semiconductor devices can be realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and testing technology, and in particular to a method for detecting the quality of internal lead bonding in semiconductors. Background Technology

[0002] In the semiconductor packaging manufacturing process, internal wire bonding is the core process for achieving electrical connections between the chip and the external pins of the package. The bonding quality directly determines the electrical performance, reliability, and lifespan of the semiconductor device. As semiconductor devices develop towards higher integration, more pins, higher power, and higher value, extremely high requirements are placed on the robustness and stability of internal wire bonding.

[0003] In actual mass production, factors such as fluctuations in bonding process parameters, pad contamination, and lead deformation inevitably lead to defects such as poor bonding, poor contact, and open circuits. If these defects cannot be effectively intercepted during the packaging and testing stage, they can cause device failure or even safety accidents when they reach downstream applications. This is especially true for automotive-grade, military-grade, and industrial-grade high-reliability semiconductor devices, where the interception of bonding defects is of paramount importance.

[0004] Currently, the industry's testing methods for the quality of internal lead bonding mainly suffer from the following shortcomings: 1. Multimeter diode test: This method uses low voltage and low current testing, and the test signal has poor anti-interference ability. It cannot effectively identify medium contact resistance changes caused by poor bonding. The test values ​​of good and bad products are extremely different, and the resolution is extremely low. It can only detect serious defects of complete open circuit, and cannot identify potential poor bonding risks. In addition, the manual testing efficiency is extremely low and cannot meet the full inspection requirements of mass production.

[0005] 2. Traditional semiconductor testing equipment VF test: This method tests the forward voltage drop of the PN junction by injecting a large pulse current of hundreds of milliamps. The large current impact can cause the metal contact surface at the poor solder joint to fuse instantly, causing the contact resistance to disappear temporarily, resulting in serious misjudgment and classifying defective products as good products. At the same time, the dynamic response of the pulse test will introduce test interference, further reducing the test accuracy. In addition, the large current impact will cause irreversible thermal damage to the bonding points, destroying the original bonding state, making it impossible to achieve non-destructive testing and only suitable for sampling testing.

[0006] 3. Mechanical destructive testing: including bond pull test and shear test. This method is a destructive test and can only be used for process verification and sampling inspection. It cannot achieve full inspection in mass production and cannot reflect the actual bonding state of the device after packaging.

[0007] 4. Imaging inspection: including X-ray inspection and ultrasonic inspection, can only identify macroscopic defects such as deformation and breakage of inner leads, and cannot detect abnormal contact resistance of bonding interfaces. The recognition rate of micro-defects such as cold solder joints is extremely low, and the risk of missed detection is high.

[0008] Therefore, developing a non-destructive, highly accurate, highly sensitive, mass-production compatible, and widely applicable method for inspecting the quality of semiconductor internal lead bonding has become a pressing technical problem to be solved in this field. Summary of the Invention

[0009] In view of the shortcomings of the prior art, the purpose of this invention is to provide a semiconductor internal lead bonding quality inspection method to solve the problems of high false judgment rate, destructive testing, inability to identify cold solder joint defects, poor compatibility, and inability to meet the full inspection requirements of mass production in the prior art.

[0010] A method for inspecting the quality of internal lead bonding in semiconductors is disclosed, used to inspect the quality of internal lead bonding in a semiconductor packaged device with a PN junction, wherein the internal lead connects the semiconductor chip pads and the package pins. The inspection method includes the following steps: S1. Set up a forward bias test circuit: Connect the PN junction of the semiconductor device under test in series with a DC regulated power supply and a current-limiting resistor to form a forward bias test circuit. S2. Apply constant DC bias: Apply a constant DC forward bias voltage to the test circuit through the DC regulated power supply to make the PN junction of the semiconductor device under test in a stable forward conduction state, and at the same time limit the conduction current of the test circuit to the range of 1mA-2mA through the current limiting resistor. S3. Independently acquire voltage drop data: Under the condition of continuous application of constant DC forward bias voltage, independently acquire the forward conduction voltage drop value across the PN junction of the semiconductor device under test; S4. Bonding quality judgment: The collected forward conduction voltage drop value is compared with the preset good product threshold range, and the bonding quality of the inner lead is judged based on the comparison result.

[0011] Furthermore, in step S2, the applied constant DC forward bias voltage is 1.8V-2.2V.

[0012] Furthermore, in step S1, the resistance of the current-limiting resistor is 600Ω-750Ω, and the resistance error is controlled within ±1%.

[0013] Furthermore, in step S3, a high-precision voltage acquisition device is connected in parallel across the PN junction of the semiconductor device under test to acquire the voltage drop value. The acquisition process does not change the bias state and conduction current of the test circuit.

[0014] Furthermore, in step S4, the preset good product threshold range is 0.6V-0.7V; when the measured value is in the range of 0.6V-0.7V, it is determined that the internal lead bonding is good; when the measured value is greater than 0.7V, it is determined that the internal lead bonding is poor; when the measured value is greater than 1.5V, it is determined that the internal lead bonding is severely poorly soldered or open.

[0015] The detection principle of this invention is as follows: For silicon-based semiconductor devices, the inherent forward voltage drop of the PN junction is approximately 0.6V. When the internal lead bonding is good, the contact resistance at the bonding interface is extremely small, only in the milliohm range. Under mA-level test current, the voltage drop caused by the contact resistance is negligible. Therefore, the measured forward voltage drop of the PN junction is 0.6V-0.7V, which is basically consistent with the inherent voltage drop.

[0016] When the internal lead bonding is poor, the bonding interface will generate a large ohmic contact resistance. According to Ohm's law U=IR, under constant test current, the contact resistance will generate an additional voltage drop. This voltage drop is superimposed on the inherent voltage drop of the PN junction, which significantly increases the measured forward conduction voltage drop. When the bonding point is completely open, the measured voltage drop is close to the applied bias voltage, and it is in an open circuit state.

[0017] This invention avoids dynamic interference from pulse testing by using a constant DC bias, avoids the impact and fusion effect of large current on bonding points by using a small mA-level current, and accurately captures the voltage drop caused by changes in bonding contact resistance, thereby achieving high sensitivity and high accuracy detection of bonding defects.

[0018] The beneficial effects of this invention are: 1. This invention strictly limits the conduction current of the test circuit to the range of 1mA-2mA, without large current pulse impact, and will not cause thermal or mechanical damage to the bonding interface. The bonding strength does not decrease before and after the test, and does not change the original bonding state of the device. It can realize full inspection in mass production and breaks through the limitation of existing destructive testing that can only sample.

[0019] 2. This invention uses constant DC bias testing, which avoids the problem of temporary disappearance of contact resistance in poor solder joints caused by traditional pulse high current testing. The test value difference between good and defective products can reach more than 1.2V, which is much higher than the 0.14V of existing multimeter testing and the 0.333V of traditional machine testing. The distinction between good and defective products is extremely high, with no risk of missed or misjudged products.

[0020] 3. This invention can accurately capture minute changes in contact resistance caused by poor bonding, and can not only detect serious defects such as complete open circuit, but also effectively identify potential failure defects such as weak bonding and poor contact, thus greatly improving the factory reliability of the device.

[0021] 4. This invention does not require the development of dedicated test fixtures and test equipment. It can be directly built on existing semiconductor FT test fixtures. The test process can be directly integrated into the automated test program of existing FT test machines. No additional hardware investment is required, the modification cost is extremely low, and it is easy to promote and apply in the industry.

[0022] 5. This invention is applicable to all silicon-based semiconductor packaged devices with PN junction structures, including but not limited to diodes, transistors, MOSFETs, IGBTs, and integrated circuit chips. Furthermore, this invention can complete testing under normal temperature and pressure conditions, requiring no special testing environment. It also exhibits excellent testing results for high-frequency, high-voltage, and high-temperature special semiconductor devices, without requiring significant adjustments based on device type. Attached Figure Description

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram illustrating the testing principle of the semiconductor internal lead bonding quality detection method in Example 1. Figure 2 This is a SEM image of the semiconductor device with good bonding in Example 2 after unpacking; Figure 3 This is a SEM image of the semiconductor device of the defective bonded product in Example 2 after unpacking; The attached figures are labeled as follows: Vs: DC regulated power supply; R: Current-limiting resistor; P: Semiconductor device under test (with built-in PN junction structure); U: High-precision digital multimeter. Detailed Implementation

[0024] This invention provides a method for detecting the quality of semiconductor internal lead bonding. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.

[0025] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0026] In all embodiments of the present invention, the semiconductor device under test is a silicon-based semiconductor packaged device, and its internal leads are connected by copper wire bonding process to connect the chip pads and the exposed pins of the package. The test environment is normal temperature and pressure (25°C, 1 standard atmosphere).

[0027] Example 1 This embodiment provides a method for detecting the quality of semiconductor internal lead bonding, such as... Figure 1 As shown, Vs is a DC regulated power supply used to provide a constant DC forward bias voltage to the test circuit; R is a current-limiting resistor used to limit the conduction current of the test circuit, with the resistance error controlled within ±1%; P is the semiconductor device under test, which contains a PN junction structure, with internal leads connecting the semiconductor chip pads to the package pins; U is a high-precision digital multimeter used to acquire the forward voltage drop of the PN junction. The object under test is a silicon-based rectifier diode packaged device, and the specific testing steps are as follows: S1. Set up a forward bias test circuit: Connect the anode of the diode under test to the positive terminal of the DC regulated power supply through the test fixture, and connect the cathode to the negative terminal of the DC regulated power supply. Connect a 680Ω high-precision metal film resistor (resistance error ±1%) in series between the positive terminal of the DC regulated power supply and the anode of the diode under test to form a forward bias test circuit. S2. Apply constant DC bias: Apply a constant 2V DC forward bias voltage to the test circuit through a DC regulated power supply to ensure that the PN junction of the diode under test is in a stable forward conduction state. According to Kirchhoff's voltage law, the circuit conduction current formula is: I=(Vcc-Vpn) / R, where I is the conduction current of the test circuit, Vcc is the constant DC forward bias voltage applied by the DC regulated power supply, Vpn is the measured forward conduction voltage drop of the PN junction of the semiconductor device under test, and R is the resistance value of the current-limiting resistor connected in series in the test circuit.

[0028] Substituting the parameters into the formula, we can calculate: I = (2V - 0.6V) / 680Ω ≈ 2mA, which is within the design range of 1mA-2mA; S3. Independently acquire voltage drop data: Under the stable state of continuous application of 2V constant DC bias, use the voltage acquisition range of a 6.5-digit high-precision digital multimeter, connect it in parallel across the anode and cathode of the diode under test, and independently acquire the forward conduction voltage drop value of the PN junction. The acquisition process does not change the bias state and conduction current of the test circuit. S4. Bonding quality judgment: The preset forward conduction voltage drop threshold range for good PN junctions is 0.6V-0.7V; when the measured value is in the range of 0.6V-0.7V, it is judged as good internal lead bonding; when the measured value is greater than 0.7V, it is judged as poor internal lead bonding; when the measured value is greater than 1.5V, it is judged as severe internal lead bonding with poor solder joint or open circuit.

[0029] Example 2 This embodiment is a test effectiveness comparison and verification experiment to verify the detection accuracy advantage of the method of the present invention compared with the prior art.

[0030] Experimental sample preparation: Select silicon-based rectifier diodes from the same batch, including 3 good products with good bonding and 3 poorly bonded samples (including poor soldering, poor contact, and half-open circuit defects) produced through process control, for a total of 6 test samples.

[0031] Test methods: Six test samples were tested in parallel using the diode setting of a multimeter (existing technology), the VF test method of a traditional semiconductor testing machine, and the method described in Embodiment 1 of this invention. The test data were recorded, and the test results are shown in Table 1 below: Table 1

[0032] Analysis of experimental results: Multimeter test: The test value difference between good and defective products is only 0.14V, and the test values ​​overlap significantly, making it impossible to effectively distinguish between good and defective products, and the test is completely invalid; Traditional testing equipment: the range between good and defective products is only 0.314V. The test values ​​of defective products 1 and 6 are close to those of good products, which poses a very high risk of misjudgment. The method of this invention achieves a range of 1.289V between good and defective products, with all good product test values ​​falling within the 0.6V-0.7V range and all defective product test values ​​exceeding 1.5V. This method exhibits extremely high discrimination, eliminates any risk of misjudgment or missed judgment, and demonstrates a detection effectiveness far superior to existing technologies.

[0033] Simultaneously, the tested samples were subjected to open-pack SEM analysis, and the results are as follows: Figure 2 and Figure 3 As shown, the bonding interface of the samples judged as good is complete, and the copper wire and the pad are firmly bonded; the bonding interface of the samples judged as defective has obvious defects such as poor soldering and insufficient contact area, which is completely consistent with the test results of the present invention, thus verifying the accuracy of the method of the present invention.

[0034] Example 3 This embodiment is a theoretical verification and optimization of the test parameters, verifying the rationality of the 2V bias voltage and 680Ω current-limiting resistor selected in this invention.

[0035] 1. Optimization and verification of forward bias voltage: Using forward bias voltages of 1.5V, 2V, and 2.5V respectively, and with corresponding current-limiting resistors to control the current at 2mA, tests were conducted on good and defective products from the same batch. The test results are as follows: 1.5V bias voltage: The loop current is easily affected by environmental interference, and the test value fluctuates by ±0.1V, resulting in poor test stability and reduced differentiation between good and defective products; 2V bias voltage: The test value fluctuates less than ±0.01V, the test stability is excellent, and the distinction between good and defective products is the highest. 2.5V bias voltage: The loop current increases, the PN junction heats up significantly, the on-state voltage drop drifts, and the bond pull value decreases by about 5% after continuous testing, posing a slight risk of damage.

[0036] Therefore, the present invention preferably uses a forward bias voltage of 2V to balance test stability, discriminative power and non-destructive testing.

[0037] 2. Optimization and verification of the current-limiting resistor: Based on a 2V bias voltage, current-limiting resistors of 600Ω, 680Ω, and 750Ω were used for testing, and the test results are as follows: 600Ω current-limiting resistor: The loop current is about 2.3mA. It has strong anti-interference ability, but there is a slight risk of overheating at the bonding point after continuous testing. 680Ω current-limiting resistor: The loop current is about 2mA, which is in the optimal range of 1mA-2mA, achieving the best balance between test stability, anti-interference ability and non-destructive testing. 750Ω current-limiting resistor: The loop current is about 1.87mA, with no risk of damage, but the test interference resistance is slightly reduced.

[0038] Therefore, the present invention preferably uses a 680Ω current-limiting resistor, which is closest to the theoretically calculated value of 700Ω, conforms to the industrial standard resistor series, and achieves the optimal balance of test performance.

[0039] Example 4 This embodiment is a non-destructive verification experiment to verify that the method of the present invention does not damage the bonding points. Ten poorly bonded diode samples were selected and divided into two groups of five: Experimental group: Using the method of Example 1 of this invention, each sample was tested 1000 times continuously. Bonding tensile force was tested before and after the test, and the change in bond strength was recorded. Control group: The traditional testing machine was used to test each sample 10 times continuously with a 500mA pulse high current. Bond pull force was tested before and after the test, and the change in bond strength was recorded.

[0040] The test results are as follows: Experimental group: The average change rate of bonding tensile force before and after the test was less than 1%, with no statistical difference. The SEM morphology of the bonding interface showed no change, proving that the method of the present invention will not cause any damage to the bonding points and fully meets the requirements of non-destructive testing. Control group: The average bond pull force decreased by 32% before and after the test. Two samples showed fusion at the poorly soldered bond points, and the bond state was irreversibly changed, proving that the traditional high current test method can cause serious damage to the bond points.

[0041] Example 5 This embodiment verifies the applicability of the method of the present invention to different types of semiconductor devices.

[0042] 1. The tested object is an NPN silicon-based transistor. For its emitter-base PN junction structure, the test circuit was constructed using the method described in Example 1: The transistor base was connected to the positive terminal of a DC regulated power supply via a test fixture, and the emitter was connected to the negative terminal of the DC regulated power supply. A 680Ω high-precision metal film resistor (resistance error ±1%) was connected in series between the positive terminal of the DC regulated power supply and the transistor base. A constant 2V DC forward bias voltage was applied to ensure the emitter junction was in a stable forward conducting state. The forward conduction voltage drop between the emitter and base was independently measured to determine the bonding quality of the leads within the base and emitter. Similarly, for the collector-base PN junction structure, the bonding quality of the leads within the collector could be tested. The test results showed that the forward voltage drop of the emitter junction of a good transistor was 0.66V, while the voltage drop of a poorly bonded device was 1.64V, demonstrating significant differentiation. The test results were completely consistent with the unpacking verification.

[0043] 2. The device under test was an N-channel MOSFET. For the body diode (PN junction structure) between its source and drain, a test circuit was built using the method described in Example 1. A 2V forward bias was applied, and the forward voltage drop of the body diode was measured to determine the bonding quality of the inner leads of the source and drain. The test results showed that the forward voltage drop of the body diode of a good MOSFET was 0.68V, while that of a poorly bonded device was 1.72V, demonstrating significant differentiation. The test results were completely consistent with the unpacking verification.

[0044] 3. The device under test is a high-voltage IGBT (rated voltage 1200V). Using the method in Example 1, a 2V forward bias is applied to the PN junction between its collector and emitter. No high-voltage testing environment is required, and the internal lead bonding quality can be tested at room temperature. Test results show that the forward voltage drop of a good IGBT is 0.69V, while the voltage drop of a poorly bonded device is 1.85V. This effectively identifies bonding defects and avoids the safety risks of high-voltage testing.

[0045] 4. The object under test is an integrated circuit chip (with multiple built-in PN junction structures). The method of this invention is used to test the PN junction structure between the power supply pin and the ground pin of the chip. The specific testing method is as follows: For each pin to be tested of the integrated circuit chip, locate the PN junction structure of the semiconductor element connected to the internal pad of the chip corresponding to the pin. Take the pin corresponding to the anode of the PN junction as the test anode and the pin corresponding to the cathode as the test cathode, and build a forward bias test circuit: connect the test anode to the positive terminal of the DC regulated power supply through the test fixture, and connect the test cathode to the negative terminal of the DC regulated power supply. Connect a 680Ω high-precision current-limiting resistor in series between the positive terminal and the test anode, and apply a constant DC forward bias voltage of 2V to make the corresponding PN junction in a stable forward conduction state. Independently collect the forward conduction voltage drop across the PN junction and compare it with the preset good product threshold of 0.6V-0.7V to determine the bonding quality of the internal lead of the pin to be tested.

[0046] By performing a pin-by-pin traversal test as described above, a complete inspection of the internal lead bonding quality of all pins of an integrated circuit chip can be completed. In this embodiment, the power supply pins, input / output pins, and ground pins of an 8-pin MCU chip are inspected pin-by-pin. The forward voltage drop of the PN junction corresponding to good pins is in the range of 0.62V-0.69V, while the measured voltage drop of poorly bonded pins is greater than 1.5V. This method can accurately identify defects such as single-pin cold solder joints and multi-pin cold solder joints, and the inspection results are completely consistent with the SEM morphology analysis after unpacking.

[0047] Example 6 This embodiment verifies the integrated application of the method of the present invention in the FT test of semiconductor mass production. The test circuit of the present invention is directly built on the general fixture of existing semiconductor FT test. The semiconductor device under test is fed into the test station through the test tube, and the probe of the test fixture contacts the package pin of the device to form a stable electrical connection. The DC regulated power supply and current limiting resistor of the test circuit are integrated into the test board of the FT test machine, and the high-precision voltage acquisition module adopts the high-precision test channel of the machine.

[0048] The test process of this invention is written as a standardized test subroutine and integrated into the automated test program of the FT test machine. It is executed synchronously with the conventional electrical performance tests of the device, without the need for additional test stations or test durations. The automated execution steps of the test process are as follows: 1. The automated program controls the test fixture probes to press down and form reliable contact with the pins of the device under test. According to the preset pin definitions, the test channels are automatically switched to build the forward bias test circuit of the corresponding PN junction. 2. The machine applies a constant DC forward bias voltage of 2V to the test circuit through the test board. The circuit conduction current is limited to the range of 1mA-2mA through a 680Ω current limiting resistor. After the circuit state is stable, the forward voltage drop across the PN junction is independently acquired through a high-precision voltage acquisition channel. 3. The automated program of the machine will automatically compare the measured voltage drop value with the preset 0.6V-0.7V good product threshold range and output the bonding quality judgment result; for the devices judged to be defective, the machine will automatically perform sorting and rejection to achieve full inspection in mass production.

[0049] In this embodiment, mass production full inspection is carried out on 100,000 silicon-based rectifier diodes in the same batch. The testing efficiency can reach 10,000 per hour, which is consistent with the efficiency of conventional FT testing. The bonding defect interception rate is 100%, with no false or missed detections. Moreover, the bonding strength of the devices does not decrease after testing, which fully meets the requirements of full inspection in semiconductor mass production.

[0050] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention, and these equivalent modifications or substitutions are all included within the scope defined by the claims of the present invention.

Claims

1. A method for detecting the quality of semiconductor internal lead bonding, characterized in that, The method for detecting the quality of internal lead bonding in a semiconductor packaged device with a PN junction, wherein the internal leads connect the semiconductor chip pads to the package pins, includes the following steps: S1. Set up a forward bias test circuit: Connect the PN junction of the semiconductor device under test in series with a DC regulated power supply and a current-limiting resistor to form a forward bias test circuit. S2. Apply constant DC bias: Apply a constant DC forward bias voltage to the test circuit through the DC regulated power supply to make the PN junction of the semiconductor device under test in a stable forward conduction state, and at the same time limit the conduction current of the test circuit to the range of 1mA-2mA through the current limiting resistor. S3. Independently acquire voltage drop data: Under the condition of continuous application of constant DC forward bias voltage, independently acquire the forward conduction voltage drop value across the PN junction of the semiconductor device under test; S4. Bonding quality judgment: The collected forward conduction voltage drop value is compared with the preset good product threshold range, and the bonding quality of the inner lead is judged based on the comparison result.

2. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, In step S2, the applied constant DC forward bias voltage is 1.8V-2.2V.

3. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, In step S1, the resistance of the current-limiting resistor is 600Ω-750Ω, and the resistance error is controlled within ±1%.

4. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, In step S3, a high-precision voltage acquisition device is connected in parallel across the PN junction of the semiconductor device under test to acquire the voltage drop value. The acquisition process does not change the bias state and conduction current of the test circuit.

5. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, In step S4, the preset good product threshold range is 0.6V-0.7V; when the measured value is in the range of 0.6V-0.7V, it is determined that the internal lead bonding is good; when the measured value is greater than 0.7V, it is determined that the internal lead bonding is poor; when the measured value is greater than 1.5V, it is determined that the internal lead bonding is severely poorly soldered or open.

6. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, The detection method is a non-destructive test, with no pulsed high current impact throughout the test, and the bonding strength of the internal leads of the semiconductor device under test does not decrease before and after the test.

7. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, The semiconductor device under test includes any one of the following semiconductor packaged devices with a PN junction structure: silicon-based diodes, transistors, MOSFETs, IGBTs, and integrated circuit chips.

8. The semiconductor internal lead bonding quality inspection method according to claim 1, characterized in that, The test circuit is built on a semiconductor FT test fixture, and the test process is integrated into the automated test program of the FT test machine.

Images