Semiconductor package

Abstract

The invention discloses a semiconductor package, comprising: a substrate; a die mounted on the substrate; and a molding compound disposed on the substrate and surrounding the die, where the molding compound includes a top surface and a first upper surface lower than the top surface, where the die is exposed from the molding compound, and the first upper surface of the molding compound is flush with the top surface of the die. Therefore, when the thermal interface material is arranged on the top surface of the crystal grain in the subsequent process, the installed thermal interface material can be accurately positioned, and the thermal interface material is surrounded by the molding compound after being installed, so that the installed thermal interface material is more stable, and unexpected conditions such as displacement are not easy to occur.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor packaging. Background Technology

[0002] To ensure the continued miniaturization and versatility of electronic products and communication equipment, the industry desires semiconductor packages that are small in size, support multi-pin connections, operate at high speeds, and possess high functionality. This puts pressure on semiconductor packaging manufacturers to develop fan-out semiconductor packages. However, electronic components inevitably generate heat during operation. Therefore, how to dissipate heat from electronic components has become an important task for the industry.

[0003] Therefore, a new type of semiconductor packaging is needed. Summary of the Invention

[0004] In view of this, the present invention provides a novel semiconductor package that implements heat dissipation in a better manner and further improves heat dissipation efficiency.

[0005] This invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The molding compound includes a top surface and a first upper surface below the top surface. The die is exposed from the molding compound. The first upper surface of the molding compound is flush with the top surface of the die.

[0006] Furthermore, the top surface and the first upper surface of the molding compound do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain. This allows for smooth and stable installation of the thermal interface material in subsequent processes. The installed thermal interface material is firmly positioned and in close contact with the grain and the heat sink, thereby improving heat dissipation efficiency.

[0007] Furthermore, the distance between the first upper surface and the top surface of the molding compound is between 40 μm and 300 μm. This allows for easier control of the thickness of the thermal interface material after installation, making it easier to make the thermal interface material thinner and improve heat dissipation efficiency.

[0008] Furthermore, the molding compound further includes: a first side surface that contacts the side surface of the grain; and a second side surface connected to the top surface of the molding compound, wherein the distance between the first side surface and the second side surface is between 40 μm and 300 μm. This allows for easier control of the thickness of the thermal interface material after installation, making it easier to make the thermal interface material thinner and improving heat dissipation efficiency.

[0009] Furthermore, the first angle between the top surface and the second side surface of the molding compound is a right angle or an obtuse angle. This can be set according to different needs or process requirements, thereby improving design flexibility and adaptability.

[0010] Furthermore, the molding compound further includes a second upper surface that is higher than the top surface of the grain and lower than the top surface of the molding compound. This allows for the formation of different cavities to accommodate or shape the desired thermal interface material, meeting various requirements.

[0011] Furthermore, the second upper surface of the molding compound is parallel to the top surface of the molding compound.

[0012] Furthermore, the molding compound further includes a third side surface that connects the first upper surface and the second upper surface.

[0013] Furthermore, the second angle between the second upper surface and the third side surface of the molding compound is a right angle or an obtuse angle.

[0014] Furthermore, it includes: a heat sink disposed on the grain and the molding compound; and a thermal interface material disposed between the heat sink and the grain.

[0015] Furthermore, the thermal interface material is disposed in the cavity of the molding compound, the cavity being formed on the top surface of the grain and surrounded by the second side surface of the molding compound.

[0016] This invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The die is exposed from the molding compound. The molding compound includes a top surface and a sloped side surface. The top surface of the die is lower than the top surface of the molding compound. The sloped side surface connects the top surface of the die to the top surface of the molding compound.

[0017] Furthermore, the top surface and the inclined side surface of the molding compound do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain. This allows for smooth and stable installation of the thermal interface material in subsequent processes. The installed thermal interface material is firmly positioned and in close contact with the grain and the heat sink, thereby improving heat dissipation efficiency.

[0018] Furthermore, the inclined side surface has a height in a direction substantially perpendicular to the top surface of the grain and a width in a direction substantially perpendicular to the corresponding first side surface of the molding compound, and both the height and the width of the inclined side surface are between 40 μm and 300 μm. This allows for easier control of the thickness of the thermal interface material after installation, making it easier to make the thermal interface material thinner and improving heat dissipation efficiency.

[0019] Furthermore, the first angle between the top surface and the inclined side surface of the molding compound is between 98 degrees and 172 degrees. This forms the desired inclined side surface to meet the requirements of different thermal interface materials.

[0020] Furthermore, it includes: a heat sink disposed on the grain and the molding compound; and a thermal interface material disposed between the heat sink and the grain.

[0021] Furthermore, the thermal interface material is placed within a cavity of the molding compound, which is formed on the top surface of the grains and surrounded by the inclined side surfaces of the molding compound. Due to the stable accommodating cavity, the thickness of the thermal interface material is easier to control, allowing for a thinner material and further improving heat dissipation efficiency.

[0022] Furthermore, the present invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The die is exposed from the molding compound. The molding compound includes a top surface and an inner surface connected to the top surface of the molding compound. The top surface and the inner surface of the molding compound do not overlap with the top surface of the die in a direction substantially perpendicular to the top surface of the die.

[0023] Furthermore, the molding compound further includes a first upper surface that is lower than the top surface of the molding compound, the first upper surface being flush with the top surface of the grain, and the inner surface being connected between the top surface and the first upper surface.

[0024] Furthermore, the inner surface is an inclined side surface directly connected between the top surface of the grain and the top surface of the molding compound.

[0025] In the semiconductor package of the present invention, the molding compound includes a top surface and a first upper surface below the top surface, and the die is exposed within the molding compound, with the first upper surface of the molding compound flush with the top surface of the die. Therefore, when the thermal interface material is subsequently applied to the top surface of the die, the present invention allows for precise positioning of the installed thermal interface material. Furthermore, the installed thermal interface material is surrounded by the molding compound, resulting in greater stability and reducing the likelihood of displacement or other unexpected situations. In addition, due to the stable accommodating cavity, the thickness of the thermal interface material is easier to control, allowing for thinner designs and further improving heat dissipation efficiency. Attached Figure Description

[0026] Figure 1 , 2 3, 4, 5 and 6 are cross-sectional views of a semiconductor package according to some embodiments of the present invention. Detailed Implementation

[0027] The following description is intended to illustrate the general principles of the invention and should not be considered as a limiting description. The scope of the invention is best determined by referring to the appended claims.

[0028] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when a component or layer is referred to as being “located,” “connected to,” or “coupled to” another component or layer, it may be directly located, connected to, or coupled to that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another component or layer, there are no intermediate components or layers. The same numbers always refer to the same component. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all. The same numbers refer to the same component throughout the document. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0029] With the increasing use of semiconductor devices, meeting power requirements has become a priority. As device power increases, heat dissipation becomes a critical concern to prevent performance degradation caused by high temperatures. Traditional molded ball grid array (BGA) semiconductor packages are as follows: the exposed die and the top surface of the molding compound are flush, forming the top surface of the semiconductor package. In automotive applications, controlling the thickness of the thermal interface material (TIM) distributed between the exposed die and the heat sink above it is challenging. Therefore, further improvements to semiconductor packaging are needed to provide better reliability and thickness control to enhance heat dissipation efficiency.

[0030] Figure 1 This is a cross-sectional view of a semiconductor package 500A according to some embodiments of the present invention. In some embodiments, the semiconductor package 500A is part of a mobile phone, a personal digital assistant (PDA), a digital camera, and a server, etc. The semiconductor package 500A can be applied to (or disposed in) packages requiring high-power operation, such as flip chip ball grid array (FCBGA), planar grid array (LGA), fan-out package, three-dimensional (3D) integrated circuit (IC) package, etc. Figure 1 As shown, the semiconductor package 500A includes a substrate 200, a die 220, and a molding compound 240. In Figure 1 In the following figures, direction 10 is defined as a horizontal direction (generally parallel to the top surface 220T of the die 220 of the semiconductor package 500A), and direction 12 is defined as a vertical direction (generally perpendicular to the top surface 220T of the die 220 of the semiconductor package 500A).

[0031] The substrate 200 may be a single-layer or multi-layer structure. In some embodiments, the substrate 200 is, for example, a printed circuit board (PCB), an interposer, a package substrate, another semiconductor device, or a semiconductor package. In some embodiments, the substrate 200 may be made of a dielectric material (e.g., polypropylene (PP), epoxy resin, polyimide, or other suitable resin material) or a semiconductor material. The substrate 200 has a top surface 200T and a bottom surface 200B opposite to the top surface 200T. The substrate 200 is provided with a die 220 disposed on the top surface 200T. A plurality of conductive traces (not shown), conductive vias, and / or conductive pads (not shown) are disposed in the substrate 200. The conductive traces may be electrically connected to the corresponding conductive vias and conductive pads. The conductive pads and / or conductive traces are exposed in openings in a solder mask layer (not shown) disposed near the top surface 200T and the bottom surface 200B. In one embodiment, the conductive trace may include power supply trace segments, signal trace segments, or ground trace segments for input / output (I / O) connections of the die 220. Furthermore, conductive pads are disposed on the top surface 200T and bottom surface 200B of the substrate 200, connecting to different terminals of the conductive traces. The conductive pads on the top surface 200T of the substrate 200 are used for direct mounting of the die 220 thereon.

[0032] The semiconductor package 500A further includes a conductive structure 210 disposed on the bottom surface 200B of the substrate 200 away from the die 220, and in contact with a corresponding conductive pad (not shown) on the bottom surface 200B of the substrate 200. In some embodiments, the conductive structure 210 includes a conductive ball structure, such as a solder ball or a copper core solder ball; a conductive bump structure, such as a copper bump or a solder bump structure; or a conductive pillar structure, such as a copper pillar structure.

[0033] like Figure 1 As shown, the die 220 is flipped to be disposed on the substrate 200 through a bonding process, opposite to the conductive structure 210. The die 220 is mounted on the substrate 200 using the conductive structure 230. Furthermore, the die 220 is electrically connected to the conductive structure 210 through the substrate 200.

[0034] The die 220 has a top surface 220T and a bottom surface 220B. Conductive pads (not shown) of the die 220 are disposed near the bottom surface 220B to electrically connect to the circuitry (not shown) of the die 220. Therefore, the bottom surface 220B of the die 220 also serves as the active surface of the die 220. In some embodiments, the die 220 is manufactured using flip-chip technology. Furthermore, the die 220 is flipped to be disposed on the substrate 200, opposite the conductive structure 210. The bottom surface 220B of the die 220 (i.e., the active surface) may face the substrate 200.

[0035] In some embodiments, die 220 includes a system-on-chip (SoC) die (or system-level chip die), a logic device, a memory device, a radio frequency (RF) device, and so on, or any combination thereof. For example, die 220 may include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, an adio frequency front end (RFFE) die, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (I / O) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high-bandwidth memory (HBM), an application processor (AP) die, an application-specific integrated circuit (ASIC) die, and so on, or any combination thereof.

[0036] In some embodiments, the conductive structure 230 electrically connects the conductive pad (containing conductive traces) of the substrate 200 and the die 220. In some embodiments, the conductive structure 230 includes a conductive ball structure, such as a solder ball, or a conductive structure, such as a copper bump or solder bump structure. For example, the conductive structure 230 may be a controlled collapse chip connection (C4) structure. In some embodiments, each conductive structure 230 may include an under bump metallurgy (UBM) layer and a conductive ball structure disposed on the under bump metallurgy (UBM) layer.

[0037] like Figure 1 As shown, molding compound 240 is disposed on the top surface 200T of substrate 200 and laterally surrounds the grain 220 and conductive structure 230. More specifically, molding compound 240 fills the gap between substrate 200 and grain 220 and extends upward above the top surface 220T of grain 220. Molding compound 240 covers the bottom surface 220B of grain 220 and the top surface 200T of substrate 200. Molding compound 240 also contacts the bottom surface 220B of grain 220 and the top surface 200T of substrate 200. Molding compound 240 surrounds and completely covers the side surface 220S of grain 220. Molding compound 240 can contact the side surface 220S of grain 220. Furthermore, the edge (or sidewall) 240E of molding compound 240 is flush with the corresponding edge 200E of substrate 200.

[0038] Molding compound 240 forms a cavity 242 directly on the top surface 220T of grain 200. The entire top surface 220T of grain 220 is exposed from the cavity 242 of molding compound 240. The top surface 220T of grain 220 can provide additional heat dissipation channels, directly dissipating the heat of grain 220 to the external environment.

[0039] In another aspect, the molding compound 240 includes a top surface 240T and a first upper surface 240U1. The first upper surface 240U1 is lower than the top surface 240T of the molding compound 240 and flush with the top surface 220T of the grain 220. The first upper surface 240U1 may be adjacent to and surround the top surface 220T of the grain 220. The top surface 240T and the first upper surface 240U1 of the molding compound 240 do not overlap with the top surface 220T of the grain 200 in a direction 12 substantially perpendicular to the top surface 220T of the grain 220. This allows for smooth and stable installation of the thermal interface material in subsequent processes, resulting in a stable position of the installed thermal interface material and close contact with the grain and the heat sink, thereby improving heat dissipation efficiency. In direction 12, the first upper surface 240U1 is lower than the top surface 240T of the molding compound 240. In some embodiments, the distance (vertical distance) Y1 between the top surface 240T and the first upper surface 240U1 is between 40 μm and 300 μm in direction 12. When the distance Y1 is within this range, the thickness and uniformity of the thermal interface material (TIM) on the top surface 220T of the die 220 can be more easily controlled. This allows the TIM to be thinner, improving the heat dissipation performance of the semiconductor package 500A and preventing an unnecessary increase in the overall height.

[0040] like Figure 1 As shown, the molding compound 240 further includes opposing first side surfaces 240S1 and opposing second side surfaces 240S2 located inside opposing edges (or sidewalls) 240E of the molding compound 240. Therefore, the first side surfaces 240S1 and the second side surfaces 240S2 can also serve as the inner side surfaces 240S1 and 240S2 of the molding compound 240. Each first side surface 240S1 contacts a corresponding side surface 220S of the grain 220. Furthermore, each second side surface 240S2 is connected to the top surface 240T of the molding compound 240. In this embodiment, the first upper surface 240U1 is directly connected between the first side surfaces 240S1 and the second side surfaces 240S2. The first side surfaces 240S1 and the second side surfaces 240S2 are separated by a distance X1 in direction 10. In some embodiments, the distance X1 between the first side surfaces 240S1 and the second side surfaces 240S2 is between 40 μm and 300 μm. When the distance X1 is within this range, the molding compound 240 formed by the molding process can avoid covering the top surface 220T of the die 220, ensuring proper alignment between the mold and the die 220. This helps maintain good heat dissipation efficiency. Furthermore, keeping the distance X1 within this range prevents an unnecessary increase in the overall width of the semiconductor package 500A.

[0041] In some embodiments, the angle A1 between the top surface 240T and the second side surface 240S2 of the molding compound 240 is a right angle or an obtuse angle. This allows for customization based on different needs or process requirements, thereby improving design flexibility and adaptability. In this embodiment, the distance Y1 can also be used as the maximum depth of the cavity 242. When the angle A1 is a right angle, the depth of the cavity 242 can have a uniform value or a constant value (i.e., the distance Y1).

[0042] In some embodiments, molding compound 240 may be formed of a non-conductive material, such as an epoxy resin, resin, moldable polymer, or similar material. In some embodiments, molding compound 240 may be formed by a molding process including compression or injection. For example, molding compound 240 may be applied in a substantially liquid state and then cured by a chemical reaction, such as in an epoxy resin or resin. In other embodiments, molding compound 240 may be an ultraviolet (UV) or thermosetting polymer, applied as a gel or plastic solid capable of being set around grain 220, and then cured using a UV or thermosetting process. Molding compound 240 may be cured using a mold (not shown).

[0043] Figure 2 This is a cross-sectional view of a semiconductor package 500B according to some embodiments of the present invention. For the sake of brevity, it is... Figure 1 Components of the same or similar embodiments described previously will not be repeated here. Figure 1 and Figure 2 As shown, the difference between semiconductor package 500A and semiconductor package 500B includes at least that semiconductor package 500B further includes thermal interface material (TIM) 246 (or thermal interface material layer 246) and heat sink 250.

[0044] A heat sink 250 is disposed on the die 220 and the molding compound 240. The heat sink 250 can be disposed on the top surface 240T of the molding compound 240 by means of an adhesive (not shown). Furthermore, the molding compound 240 can extend laterally along direction 10 to cover the cavity 242. The heat sink 250 does not contact the first side surface 240S1, the second side surface 240S2, and the first upper surface 240U1 of the molding compound 240.

[0045] In some embodiments, the heat sink 250 may include at least one protruding portion 250P. The protruding portion 250P extends upward from its upper surface 250T. In some embodiments, the fin-shaped protruding portion 250P may increase the surface area of ​​the heat sink 250. Furthermore, the bottom surface 250B of the heat sink 250 may be planar. In other embodiments, the heat sink 250 may be plate-shaped with a uniform thickness. In some embodiments, the heat sink 250 may be made of metal or ceramic.

[0046] like Figure 2 As shown, TIM 246 is disposed between heat sink 250 and die 220. TIM 246 is disposed in cavity 242 of molding compound 240, which is formed on top surface 220T of die 220 and surrounded by second side surface 240S2 of molding compound 240. In some embodiments, top surface 220T of die 220, first upper surface 240U1 and second side surface 240S2 of molding compound 240 and bottom surface 250B of heat sink 250 can together form a closed space to accommodate TIM 246. In some embodiments, TIM 246 can substantially fill the closed space. Furthermore, TIM 246 is in contact with top surface 220T of die 220, first upper surface 240U1 and second side surface 240S2 of molding compound 240 and bottom surface 250B of heat sink 250. In some embodiments, TIM 246 is positioned within cavity 242 of molding compound 240. This design allows for precise control over the thickness of the TIM 246, minimizing it and improving heat dissipation efficiency. Furthermore, the cavity 242 helps prevent accidental movement or misalignment of the TIM 246, ensuring a stable and secure placement between the die 220 and the heatsink 250. Therefore, this configuration contributes to a robust semiconductor package structure and uniform, consistent, and efficient heat dissipation. In this embodiment, when a thermal interface material (or thermal interface material layer) is subsequently applied to the top surface of the die, the installed thermal interface material (or thermal interface material layer) can be precisely positioned and surrounded by a molding compound after installation, resulting in greater stability and reducing the likelihood of displacement or other unexpected situations. Moreover, due to the stable accommodating cavity, the thickness of the thermal interface material is easier to control, allowing for thinner thermal interface material (or thermal interface material layer) thicknesses, further improving heat dissipation efficiency.

[0047] In some embodiments, TIM 246 may comprise a metal or metal alloy, including Al, Cu, Ni, and Co. Additionally, TIM 246 may comprise diamond, aluminum nitride, boron nitride, or other materials with high thermal conductivity. In some embodiments, TIM 246 may be made of a non-metallic material, such as a polymer. This non-metallic TIM has a higher thermal conductivity than molding compound 240, thereby achieving faster heat dissipation.

[0048] Figure 3 This is a cross-sectional view of a semiconductor package 500C according to some embodiments of the present invention. For simplicity, it is... Figure 1 Components of the same or similar embodiments previously described will not be repeated here. Figure 3 As shown, the semiconductor package 500C includes a substrate 200, a die 220, and a molding compound 340. (As...) Figure 1 and Figure 3 As shown, the difference between semiconductor package 500A and semiconductor package 500C includes at least the fact that the molding compound 340 of semiconductor package 500C has a different profile than the cavity 242 of the molding compound 240 of semiconductor package 500A.

[0049] like Figure 3 As shown, molding compound 340 is disposed on the top surface 200T of substrate 200 and laterally surrounds the grain 220 and conductive structure 230. More specifically, molding compound 340 fills the gap between substrate 200 and grain 220 and extends upward above the top surface 220T of grain 220. Molding compound 340 covers the bottom surface 220B of grain 220 and the top surface 200T of substrate 200. Molding compound 340 also contacts the bottom surface 220B of grain 220 and the top surface 200T of substrate 200. Molding compound 340 surrounds and completely covers the side surface 220S of grain 220. Molding compound 340 can contact the side surface 220S of grain 220. Furthermore, the edge (or sidewall) 340E of molding compound 340 is flush with the corresponding edge 200E of substrate 200.

[0050] The cavity 342 of the molding compound 340 is formed directly on the top surface 220T of the grain 200. The entire top surface 220T of the grain 220 is exposed from the cavity 342 of the molding compound 340.

[0051] In another aspect, the molding compound 340 includes a top surface 340T, a first upper surface 340U1, and a second upper surface 340U2. The first upper surface 340U1 is lower than the top surface 340T of the molding compound 340 and flush with the top surface 220T of the grain 220. The first upper surface 340U1 is adjacent to and surrounds the top surface 220T of the grain 220. The second upper surface 340U2 is higher than the top surface 220T of the grain 220 and lower than the top surface 340T of the molding compound 340. In direction 12, the second upper surface 340U2 of the molding compound 340 may be parallel to the top surface 340T and / or the first upper surface 340U1 of the molding compound 340. The top surface 340T, the first upper surface 340U1, and the second upper surface 340U2 of the molding compound 340 do not overlap with the top surface 220T of the grain 200 in direction 12. This allows for the creation of different cavities to accommodate or form the desired shape of the thermal interface material, thus meeting diverse needs.

[0052] In direction 12, the first upper surface 340U1 is lower than the top surface 340T of the molding compound 340. The second upper surface 340U2 is lower than the top surface 340T of the molding compound 340. In some embodiments, the distance (vertical distance) Y2-1 between the first upper surface 340U1 and the top surface 340T of the molding compound 340 is between 40 μm and 300 μm in direction 12. When the distance Y2-1 is within this range, the thickness and uniformity of the thermal interface material (TIM) (or thermal interface material layer) on the top surface 220T of the die 220 can be more easily controlled. This allows for a thinner TIM, improves the heat dissipation performance of the semiconductor package 500C, and prevents an unnecessary increase in the overall height. In some embodiments, the distance (vertical distance) Y2-2 between the second upper surface 340U2 and the top surface 340T of the molding compound 340 is smaller than the distance Y2-1.

[0053] like Figure 3 As shown, the molding compound 340 further includes opposing first side surfaces 340S1, opposing second side surfaces 340S2, and opposing third side surfaces 340S3 located within opposing edges 340E of the molding compound 340. Therefore, the first side surfaces 340S1, 340S2, and 340S3 can also serve as inner side surfaces 340S1, 340S2, and 340S3 of the molding compound 340. Each first side surface 340S1 contacts a corresponding side surface 220S of the grain 220. Each second side surface 340S2 is directly connected between the top surface 340T and the second upper surface 340U2 of the molding compound 340. Furthermore, each third side surface 340S3 is directly connected between the first upper surface 340U1 and the second upper surface 340U2 of the molding compound 340.

[0054] In this embodiment, the first upper surface 340U1 is directly connected between the first side surface 340S1 and the third side surface 340S3. The second upper surface 340U2 is directly connected between the second side surface 340S2 and the third side surface 340S3. In direction 10, the distance between the first side surface 340S1 and the second side surface 340S2 is X2-1, and the distance between the first side surface 340S1 and the third side surface 340S3 is X2-2. In some embodiments, the distance X2-1 between the first side surface 340S1 and the second side surface 340S2 is between 40 μm and 300 μm. When the distance X2-1 is within this range, the molding compound 340 formed by the molding process can avoid covering the top surface 220T of the die 220, ensuring proper alignment between the mold and the die 220. This helps maintain good heat dissipation efficiency. Furthermore, keeping the distance X2-1 within this range prevents an unnecessary increase in the total width of the semiconductor package 500C. Furthermore, in some embodiments, the distance X2-2 between the first side surface 340S1 and the third side surface 340S3 is designed to be shorter than the distance X2-1. In some embodiments, the distance X2-2 between the first side surface 340S1 and the third side surface 340S3 is shorter than the distance X2-1.

[0055] In some embodiments, the angle A2-1 between the top surface 340T and the second side surface 340S2 of the molding compound 340 is a right angle or an obtuse angle. In some embodiments, distances Y2-1 and Y2-2 can also be used as the first and second depths of the cavity 342. Furthermore, distance Y2-1 can be used as the maximum depth of the cavity 342. When angle A2-1 is a right angle, the cavity 342 of the molding compound 340 can have two fixed depths (i.e., distances Y2-1 and Y2-2).

[0056] In some embodiments, the angle A2-2 between the second upper surface 340U2 and the third side surface 340S3 of the molding compound 340 is a right angle or an obtuse angle.

[0057] In some embodiments, the material of molding compound 340 may be the same as or similar to the material of molding compound 240. Molding compounds 240 and 340 may be manufactured using the same or similar processes.

[0058] Figure 4 This is a cross-sectional view of a semiconductor package 500D according to some embodiments of this disclosure. For the sake of brevity, it is... Figure 3 Components of the same or similar embodiments previously described will not be repeated here. Figure 3 and Figure 4As shown, the difference between semiconductor package 500C and semiconductor package 500D includes at least the following: semiconductor package 500D further includes thermal interface material (TIM) 246 and heat sink 250.

[0059] A heat sink 250 is disposed on the die 220 and the molding compound 340. The heat sink 250 can be mounted on the top surface 340T of the molding compound 340 by an adhesive (not shown). Furthermore, the molding compound 340 can extend laterally along direction 10 to cover the cavity 342. The heat sink 250 does not contact the first side surface 340S1, the second side surface 340S2, the third side surface 340S3, the first upper surface 340U1, and the second upper surface 340U2 of the molding compound 340.

[0060] In some embodiments, the heat sink 250 may include at least one protrusion 250P. The protrusion 250P extends upward from its upper surface 250T. In some embodiments, the fin-shaped protrusion 250P may increase the surface area of ​​the heat sink 250. Furthermore, the bottom surface 250B of the heat sink 250 may be planar. In other embodiments, the heat sink 250 may be a plate with a uniform (fixed) thickness.

[0061] like Figure 4As shown, TIM 246 is disposed between heat sink 250 and die 220. TIM 246 is disposed within cavity 342 of molding compound 340, which is formed on the top surface 220T of die 220 and surrounded by a second side surface 340S2, a second upper surface 340U2, and a third side surface 340S3 of molding compound 340. Furthermore, the top surface 220T of die 220, the second side surface 340S2, the second upper surface 340U2, and the third side surface 340S3 of molding compound 340, and the bottom surface 250B of heat sink 250 can collectively form a closed space to accommodate TIM 246. In some embodiments, TIM 246 can substantially fill the closed space. Furthermore, the TIM 246 contacts the top surface 220T of the die 220, the second side surface 340S2, the second upper surface 340U2, and the third side surface 340S3 of the molding compound 340, and the bottom surface 250B of the heat sink 250. In some embodiments, the TIM 246 is positioned within the cavity 342 of the molding compound 340. This design allows for precise control of the thickness of the TIM 246, thereby minimizing it and improving heat dissipation efficiency. Furthermore, the cavity 342 helps prevent accidental movement or misalignment of the TIM 246, ensuring safe and stable placement between the die 220 and the heat sink 250. Therefore, this configuration helps to form a robust semiconductor package structure and maintain consistent, efficient heat dissipation. In this embodiment of the invention, when the thermal interface material is subsequently applied to the top surface of the die, the installed thermal interface material can be precisely positioned, and after installation, it is surrounded by the molding compound, making the installed thermal interface material more stable and less prone to displacement or other unexpected situations. Furthermore, due to the stable containment cavity, the thickness of the thermal interface material is easier to control, allowing for a thinner thermal interface material, thereby further improving heat dissipation efficiency.

[0062] Figure 5 This is a cross-sectional view of a semiconductor package 500E according to some embodiments of this disclosure. For the sake of brevity, it is... Figure 1 Components of the same or similar embodiments previously described will not be repeated here. Figure 5 As shown, the semiconductor package 500E includes a substrate 200, a die 220, and a molding compound 440. (As...) Figure 1 and Figure 5 As shown, the difference between semiconductor package 500A and semiconductor package 500E includes at least the fact that the molding compound 440 of semiconductor package 500E has a different profile than the cavity 242 of the molding compound 240 of semiconductor package 500A.

[0063] like Figure 5As shown, molding compound 440 is disposed on the top surface 200T of substrate 200 and laterally surrounds the die 220 and conductive structure 230. More specifically, molding compound 440 fills the gap between substrate 200 and die 220 and extends upward above the top surface 220T of die 220. Molding compound 440 covers the bottom surface 220B of die 220 and the top surface 200T of substrate 200. Molding compound 440 also contacts the bottom surface 220B of die 220 and the top surface 200T of substrate 200. Molding compound 440 surrounds and completely covers the side surface 220S of die 220. Molding compound 440 can contact the side surface 220S of die 220. Furthermore, the edge 440E of molding compound 440 is flush with the corresponding edge 200E of substrate 200.

[0064] The molding compound 440 has cavities 442 formed directly on the top surface 220T of the grain 200. The entire top surface 220T of the grain 220 is exposed from the cavities 442 of the molding compound 440.

[0065] like Figure 5 As shown, the molding compound 440 further includes opposing first side surfaces 440S1 and opposing second side surfaces 440S2, these side surfaces being located within opposing edges 440E of the molding compound 440. Therefore, the first side surfaces 440S1 and the second side surfaces 440S2 can also serve as inner side surfaces 440S1 and 440S2 of the molding compound 440. Each first side surface 440S1 contacts a corresponding side surface 220S of the grain 220. Each second side surface 440S2 is directly connected between the top surface 440T of the molding compound 440 and the first side surface 440S1. Furthermore, the second side surfaces 440S2 abut and surround the top surface 220T of the grain 220.

[0066] In this embodiment, the angle A3 between the top surface 440T and the second side surface 440S2 of the molding compound 440 is an obtuse angle. The second side surface 440S2 can also be an inclined side surface 440S2. The inclined side surface 440S2 has a height Y3 in a direction 12 substantially perpendicular to the top surface 220T of the grain 220 and a width X3 in a direction 10 substantially parallel to the top surface 220T of the grain 220. In some embodiments, the width X3 measured along direction 10 can be a direction substantially perpendicular to the corresponding first side surface 440S1 of the molding compound 440 or the corresponding side surface 220S of the grain 220. In some embodiments, the height Y3 and width X3 of the inclined side surface 440S2 are between 40 μm and 300 μm. When the height Y3 is within this range, the thickness and uniformity of the thermal interface material (TIM) on the top surface 220T of the grain 220 can be more easily controlled. This allows for a thinner TIM, improving the heat dissipation performance of the semiconductor package 500E and preventing an unnecessary increase in overall height. Similarly, when the width x3 is within this range, the molding compound 440 formed by the molding process avoids covering the top surface 220T of the die 220, ensuring proper alignment between the mold and the die 220. This helps maintain good heat dissipation efficiency and prevents an unnecessary increase in the overall width of the semiconductor package 500E.

[0067] Depending on the range of height Y3 and width X3 of the inclined side surface 440S2, the angle A3 can be between 98 degrees and 172 degrees. Since angle A3 is an obtuse angle, the depth of cavity 442 can be gradually increased to the maximum depth of cavity 442 (i.e., height Y3). This forms the required inclined side surface to meet the requirements of different heat interface materials.

[0068] In some embodiments, the material of molding compound 440 may be the same as or similar to the material of molding compound 240. Molding compounds 240 and 440 may be manufactured using the same or similar processes.

[0069] Figure 6 This is a cross-sectional view of a semiconductor package 500F according to some embodiments of this disclosure. For the sake of brevity, it is consistent with previous references. Figure 5 Components of the same or similar embodiments described herein will not be repeated. Figure 5 and Figure 6 As shown, the difference between semiconductor package 500E and semiconductor package 500F includes at least that semiconductor package 500F further includes thermal interface material (TIM) 246 (or thermal interface material layer) and heat sink 250.

[0070] A heat sink 250 is disposed on the die 220 and the molding compound 440. The heat sink 250 can be disposed on the top surface 440T of the molding compound 440 by means of an adhesive (not shown). In addition, the molding compound 440 can extend laterally (along direction 10) onto the molding compound 440 to cover the cavity 442. The heat sink 250 does not contact the first side surface 440S1 and the inclined side surface (second side surface) 440S2 of the molding compound 440.

[0071] In some embodiments, the heat sink 250 may include at least one protrusion 250P. The protrusion 250P extends upward from its upper surface 250T. In some embodiments, the fin-shaped protrusion 250P may increase the surface area of ​​the heat sink 250. Furthermore, the bottom surface 250B of the heat sink 250 may be planar. In other embodiments, the heat sink 250 may be plate-shaped with a uniform thickness.

[0072] like Figure 6 As shown, TIM 246 is disposed between heat sink 250 and die 220. TIM 246 is disposed within cavity 442 of molding compound 440, which is formed on the top surface 220T of die 220 and surrounded by the second side surface 440S2 of molding compound 440. Furthermore, the top surface 220T of die 220, the second side surface 440S2 of molding compound 440, and the bottom surface 250B of heat sink 250 can collectively form a closed space to accommodate TIM 246. In some embodiments, TIM 246 can substantially fill the closed space. Additionally, TIM 246 is in contact with the top surface 220T of die 220, the second side surface 440S2 of molding compound 440, and the bottom surface 250B of heat sink 250. In this embodiment of the invention, when the thermal interface material is applied to the top surface of the grain in a subsequent process, the applied thermal interface material can be precisely positioned. Furthermore, after application, it is surrounded by a molding compound, making the applied thermal interface material more stable and less prone to displacement or other unexpected situations. In addition, due to the stable accommodating cavity, the thickness of the thermal interface material is easier to control, allowing for a thinner material, thereby further improving heat dissipation efficiency.

[0073] Methods for forming semiconductor packages 500A, 500C, and 500E may include the following steps. First, a die assembly carried by a carrier (not shown) is provided. In some embodiments, the die assembly includes a substrate 200 and a die 220 mounted on the substrate 200 via a conductive structure 230. In some embodiments, the die assembly may be formed by the following process: First, the substrate 200 is placed on the carrier. Next, flux (not shown) and conductive balls (not shown) are sequentially formed on the top surface 200T of the substrate 200. Next, a pick-and-place process is performed to place the separated die 220 onto the conductive structure 230. Next, a reflow process is performed to reflow the conductive balls to form the conductive structure 230. The method also includes a molding process (including compression or injection molding) using a mold (or mold tool) to form a molding compound material (not shown) on the substrate 200 and fill the gap between the die 220 and the substrate 200. In the molding process, a mold (or mold tool) is directly disposed on the grain 220, and a release film (not shown) is inserted between the mold and the molding compound material. In some embodiments, the mold may have protrusions (not shown) corresponding to cavities of the resulting molding compounds (including cavities 242 of molding compound 240, 342 of molding compound 340, and 442 of molding compound 440). Next, the molding compound material is cured to form molding compounds (including molding compounds 240, 340, and 440). Next, the mold is removed to form molding compounds on substrate 200 and around the grain 220. Next, the carrier is released to form substrate 200. The method further includes forming a conductive structure 210 on the bottom surface 200B of substrate 200.

[0074] The methods for forming semiconductor packages 500B, 500D, and 500F may further include the following steps after forming semiconductor packages 500A, 500C, and 500E. A TIM 246 is placed in a cavity of the resulting molding compound (containing cavity 242 of molding compound 240, cavity 342 of molding compound 340, and cavity 442 of molding compound 440) and contacts the top surface 220T of the die 220. Next, a heat sink 250 is placed on the die 220 and TIM 246 and attached to the top surface of the molding compound (containing top surfaces 240T, 340T, and 440T of molding compounds 240, 340, and 440) by an adhesive (not shown).

[0075] According to some embodiments of this disclosure, a semiconductor package (e.g., semiconductor packages 500A-500F) is manufactured as a structure in which a molding compound (e.g., the top surfaces 240T, 340T, and 440T of molding compounds 240, 340, and 440) has cavities (e.g., cavities 242, 342, and 442) to expose a die (e.g., die 220) such that the top surface of the exposed die (e.g., the top surface 220T of die 220) is lower than the top surface of the molding compound (e.g., the top surfaces 240T, 340T, and 440T of molding compounds 240, 340, and 440). In some embodiments (e.g., semiconductor packages 500B, 500D, and 500F), cavities of the molding compound directly located on the die (e.g., cavities 242, 342, and 442 of molding compounds 240, 340, and 440) can serve as stress buffers for a heat sink (e.g., heat sink 250) placed on the die 220. Furthermore, the cavities of the molding compound can have a fixed shape and a predetermined depth. When a thermal interface material (TIM) (e.g., thermal interface material 246) is disposed between the die and the heat sink, the TIM is confined within the enclosed space formed by the cavities of the molding compound and the heat sink 250. Therefore, the thickness of the TIM can be well controlled. The reliability and heat dissipation efficiency of the semiconductor package can be further improved.

[0076] This invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The molding compound includes a top surface and a first upper surface below the top surface. The die is exposed from the molding compound. The first upper surface of the molding compound is flush with the top surface of the die.

[0077] In some embodiments, the top surface of the molding compound and the first upper surface do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain.

[0078] In some embodiments, the distance between the first upper surface and the top surface of the molding compound is between 40 μm and 300 μm.

[0079] In some embodiments, the molding compound further includes a first side surface in contact with the side surface of the grain and a second side surface connected to the top surface of the molding compound. The distance between the first side surface and the second side surface is between 40 μm and 300 μm.

[0080] In some embodiments, the first angle between the top surface of the molding compound and the second side surface is a right angle or an obtuse angle.

[0081] In some embodiments, the molding compound further includes a second upper surface that is above the top surface of the grain and below the top surface of the molding compound.

[0082] In some embodiments, the second upper surface of the molding compound is parallel to the top surface of the molding compound and / or the first upper surface of the molding compound.

[0083] In some embodiments, the molding compound further includes a third side surface connecting the first upper surface of the molding compound to the second upper surface.

[0084] In some embodiments, the second angle between the second upper surface and the second side surface of the molding compound is a right angle or an obtuse angle.

[0085] In some embodiments, the semiconductor package further includes a heat sink and a thermal interface material. The heat sink is disposed on the die and the molding compound. The thermal interface material is disposed between the heat sink and the die.

[0086] In some embodiments, a thermal interface material is disposed in a cavity of the molding compound, the cavity being formed on the top surface of the grain and surrounded by a second side surface of the molding compound.

[0087] This invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The die is exposed from the molding compound. The molding compound includes a top surface and a sloped side surface. The top surface of the die is lower than the top surface of the molding compound. The sloped side surface connects the top surface of the die to the top surface of the molding compound.

[0088] In some embodiments, the top surface and inclined side surface of the molding compound do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain.

[0089] In some embodiments, the inclined side surface has a height in a direction substantially perpendicular to the top surface of the grain and a width in a direction substantially perpendicular to the corresponding first side surface of the molding compound, and the height and width of the inclined side surface are between 40 μm and 300 μm.

[0090] In some embodiments, the first angle between the top surface of the molding compound and the inclined side surface is between 98 degrees and 172 degrees.

[0091] In some embodiments, the semiconductor package further includes a heat sink and a thermal interface material. The heat sink is disposed on the die and the molding compound. The thermal interface material is disposed between the heat sink and the die.

[0092] In some embodiments, a thermal interface material is disposed in a cavity of the molding compound, the cavity being formed on the top surface of the grain and surrounded by a slope of the molding compound.

[0093] This invention provides a semiconductor package. The semiconductor package includes a substrate, a die, and a molding compound. The die is mounted on the substrate. The molding compound is disposed on the substrate and surrounds the die. The die is exposed from the molding compound. The molding compound includes a top surface and an inner surface connected to the top surface of the molding compound. The top surface and the inner surface of the molding compound do not overlap with the top surface of the die in a direction substantially perpendicular to the top surface of the die.

[0094] In some embodiments, the molding compound further includes a first upper surface below the top surface of the molding compound, the first upper surface being flush with the top surface of the grain, and an inner surface connecting the top surface and the first upper surface.

[0095] In some embodiments, the inner surface is an inclined side surface that directly connects the top surface of the grain to the top surface of the molding compound.

[0096] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor package, characterized in that, include: substrate; The die is mounted on the substrate; as well as A molding compound is disposed on the substrate and surrounding the grain, wherein the molding compound includes a top surface and a first upper surface below the top surface. The grain is exposed from the molding compound, and the first upper surface of the molding compound is flush with the top surface of the grain.

2. The semiconductor package as described in claim 1, characterized in that, The top surface and the first upper surface of the molding compound do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain.

3. The semiconductor package as described in claim 1, characterized in that, The distance between the first upper surface and the top surface of the molding compound is between 40 μm and 300 μm.

4. The semiconductor package as described in claim 1, characterized in that, The molding compound further includes: A first side surface, which contacts the side surface of the grain; and The second side surface is connected to the top surface of the molding compound, and the distance between the first side surface and the second side surface is between 40 μm and 300 μm.

5. The semiconductor package as described in claim 4, characterized in that, The first angle between the top surface and the second side surface of the molding compound is a right angle or an obtuse angle.

6. The semiconductor package as described in claim 1, characterized in that, The molding compound further includes: A second upper surface, which is higher than the top surface of the grain and lower than the top surface of the molding compound; A third side surface, which connects the first upper surface and the second upper surface.

7. A semiconductor package, characterized in that, include: substrate; The die is mounted on the substrate; as well as A molding compound is disposed on the substrate and surrounds the grain. The grain is exposed from the molding compound, and the molding compound includes a top surface above the top surface of the grain and an inclined side surface connecting the top surface of the grain and the top surface of the molding compound.

8. The semiconductor package as described in claim 7, characterized in that, The inclined side surface has a height in a direction substantially perpendicular to the top surface of the grain and a width in a direction substantially perpendicular to the corresponding first side surface of the molding compound, and the height and width of the inclined side surface are both between 40 μm and 300 μm; or / and, the first angle between the top surface of the molding compound and the inclined side surface is between 98 degrees and 172 degrees.

9. A semiconductor package, characterized in that, include: substrate; The die mounted on the substrate; and A molding compound is disposed on the substrate and surrounds the grain. The molding compound includes a top surface and an inner surface connected to the top surface of the molding compound, and the top surface and the inner surface of the molding compound do not overlap with the top surface of the grain in a direction substantially perpendicular to the top surface of the grain.

10. The semiconductor package as claimed in claim 9, characterized in that, The molding compound further includes a first upper surface that is lower than the top surface of the molding compound, the first upper surface being flush with the top surface of the grain, and the inner surface being connected between the top surface and the first upper surface; or, the inner surface is an inclined side surface directly connected between the top surface of the grain and the top surface of the molding compound.

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