Pin structure of QFN semiconductor device, processing method and application

Abstract

The invention relates to a pin structure of a QFN semiconductor device, a processing method and application, and relates to the field of semiconductor devices.The pin structure of the QFN semiconductor device comprises a pin of the QFN semiconductor device, the pin is provided with a material guide groove penetrating through the bottom face and the side end face, and the material guide groove can be filled with tin materials; the processing method comprises the following steps: processing a connecting groove on the bottom surface of a pin part of the lead frame, enabling a cutting line of the lead frame to pass through the connecting groove, cutting the lead frame along the cutting line, and forming a guide groove on the pin; the pin structure and the processing method can be applied to the packaging process of a semiconductor device and the structural design of a lead frame. The technical effects of increasing the effective wetting area of the side surface of the pin, improving the tin climbing height of the side end surface of the pin and improving the surface mounting qualification rate of the QFN semiconductor device are achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to the pin structure, fabrication method and application of a QFN semiconductor device. Background Technology

[0002] QFN (Quad Flat No-Lead) is a surface-mount semiconductor packaging technology characterized by its small size, light weight, and excellent electrical and thermal performance. Its package features exposed thermal pads on the bottom to improve heat dissipation efficiency, while electrical connection pads are distributed around the perimeter. Eliminating the need for traditional leads saves PCB space and reduces parasitic inductance and resistance. QFN is widely used in consumer electronics, communication equipment, automotive electronics, and the Internet of Things (IoT), where high integration and miniaturization are crucial. Due to its excellent high-frequency performance and cost advantages, QFN has become a key choice for modern integrated circuit packaging.

[0003] The structure of QFN semiconductor devices dictates that the back and side faces of their pins need to be exposed outside the plastic package for connection to pads on the PCB. However, when the side faces of the pins are exposed to air for a long time, they (especially copper without sufficient surface treatment) will react with moisture and oxygen to form an oxide layer. When the side faces are oxidized (such as forming copper oxide layers like CuO and Cu2O), their surface energy decreases, making it difficult for solder to spread and adhere, increasing the wetting angle, and thus inhibiting the solder from climbing up the sidewall. This reduces the solder climbing height on the side faces of the pins, leading to a decrease in the yield rate of QFN semiconductor device mounting. Summary of the Invention

[0004] To address the issue of reduced solder climb height on the pin side surface due to oxidation, which leads to a lower yield rate for QFN semiconductor device mounting, this application provides a pin structure, processing method, and application for a QFN semiconductor device.

[0005] The pin structure, fabrication method, and application of a QFN semiconductor device provided in this application adopt the following technical solution: A pin structure for a QFN semiconductor device includes pins of the QFN semiconductor device, wherein a guide groove is formed on the pin, the guide groove extending through the back and side end faces of the pin, so that solder can fill the guide groove.

[0006] By adopting the above technical solution, a solder plating layer can be formed on the side of the pin in the subsequent electroplating process using a guide groove on the back of the pin, which blocks the oxide layer of the copper substrate. The guide groove forms a capillary structure of trenches on the side of the pin, providing a physical guide path for the solder paste. This allows the solder paste to climb upwards along this path in the molten state. Furthermore, the design of the guide groove increases the effective wetting area on the side of the pin, making the attraction between the molten solder and the base material greater than gravity. This increases the solder climbing height on the side of the pin and improves the yield of QFN semiconductor device mounting.

[0007] Preferably, the maximum depth of the guide groove on the side end face of the pin is F, and the height of the side end face of the pin is H, where F ≥ 0.35H.

[0008] By adopting the above technical solution, the depth of the guide groove is limited, ensuring that the guide groove has sufficient depth on the side end face of the pin. This further enhances the physical guiding effect of the trench's capillary structure on the solder paste, making it easier for the solder paste to climb upwards along the path. At the same time, it greatly increases the effective wetting area on the side of the pin, more effectively improving the solder climbing height on the side end face of the pin and increasing the yield of QFN semiconductor device mounting.

[0009] Accordingly, this application also provides a method for processing a pin structure, including: processing a connection groove on the back side of the pin connection bridge area of ​​the lead frame, the cutting line of the lead frame passing through the connection groove, cutting the lead frame along the cutting line when cutting the lead frame, and forming a guide groove on the pin.

[0010] By adopting the above technical solution, a connecting groove is processed on the back of the lead frame pin connecting bridge area, and a guide groove is formed by cutting. This can efficiently realize the processing of the pin guide groove, creating conditions for the formation of tin plating on the side of the pin in the subsequent electroplating process, which is conducive to improving production efficiency and yield.

[0011] Preferably, the cutting lines of two adjacent lead frames pass through the connecting groove. After the lead frames are cut along the cutting lines, a guide groove is formed on the pin of each lead frame.

[0012] By adopting the above technical solution, a connecting groove is set at the connection point of adjacent pin connection bridge areas and the cutting wire passes through the connecting groove for cutting. This can efficiently form a guide groove on the pins of two lead frames at the same time, thereby improving production efficiency.

[0013] Preferably, during the processing of the connection groove, a semi-etching process is used to form the connection groove on the back side of the pin connection bridge area.

[0014] By adopting the above technical solution, the connection groove is processed on the back side of the pin connection bridge area using a semi-etching process, which can precisely control the depth and shape of the connection groove and ensure the dimensional accuracy of the subsequent material guide groove.

[0015] Preferably, the thickness of the pin connection bridge area is I, the depth of the connection groove is i, i=0.5I, and the tolerance is within the range of 0.15I.

[0016] By adopting the above technical solution, setting the depth of the connection groove to half the thickness of the pin and controlling the tolerance range, the forming effect of the guide groove on the pin can be precisely controlled, ensuring the stability of the guide groove's role in filling and guiding solder, and more effectively improving the solder climbing height on the side end face of the pin and the yield of QFN semiconductor devices.

[0017] Preferably, the pin connection bridge area forms a dam around the connection groove, and the dam is arranged in a circle around the circumference of the connection groove.

[0018] By adopting the above technical solution, during the chip encapsulation process, the connection groove is separated from the external injection space by the contact between the dam and the mold, which prevents epoxy resin from entering the connection groove during the encapsulation process and improves the convenience of pin structure processing.

[0019] Preferably, a virtual symmetry line is provided between the two cutting lines, the distance from the symmetry line to the two cutting lines is equal, and the connecting groove is symmetrically arranged about the symmetry line.

[0020] By adopting the above technical solution and symmetrically arranging the connection slots, it is possible to ensure that the guide slots formed on each pin after cutting the lead frame are of consistent specifications, thus ensuring uniform and stable solder creep performance on each pin. Accordingly, this application also provides an application of a pin structure fabrication method for QFN semiconductor devices in the semiconductor device packaging process.

[0021] Accordingly, this application also provides a method for fabricating the pin structure of a QFN semiconductor device and its application in the design of semiconductor device lead frame structures.

[0022] In summary, this application includes at least one of the following beneficial technical effects: 1. A guide groove is opened on the back of the pin. In the subsequent electroplating process, a solder plating layer can be formed on the side of the pin to block the oxide layer of the copper substrate. The guide groove forms a capillary structure of trenches on the side of the pin, providing a physical guide path for the solder paste. This allows the solder paste to climb upward along the path in the molten state and increases the effective wetting area on the side of the pin. This makes the attraction between the molten solder and the base material greater than gravity, increasing the solder climbing height on the side end of the pin, thereby improving the yield of QFN semiconductor device mounting. 2. By placing the connecting slot at the connection point of the pin connecting bridge area of ​​two adjacent lead frames, the cutting wire passes through the connecting slot for cutting, which can efficiently form a guide groove on the pins of two lead frames at the same time, thus improving production efficiency. 3. During the chip encapsulation process, the connection groove is separated from the external injection space by the contact between the cofferdam and the mold, which prevents epoxy resin from entering the connection groove during the encapsulation process and improves the convenience of pin structure processing. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the pin structure of a QFN semiconductor device according to Embodiment 1 of this application.

[0024] Figure 2 This is a bottom view of the pin structure.

[0025] Figure 3 It is along Figure 2 A cross-sectional view along line AA in the middle.

[0026] Figure 4 This is a schematic diagram of the back side of the lead frame in Embodiment 2 of this application.

[0027] Figure 5 yes Figure 4 Enlarged view of section B in the middle.

[0028] Figure 6 This is a schematic diagram showing the structure of the pins formed after the pin connection bridge area is cut along the cutting line in Embodiment 2.

[0029] Figure 7 This is a schematic diagram of the back side of the lead frame in Embodiment 3 of this application.

[0030] Figure 8 This is a structural diagram used to illustrate the pin connection bridge area.

[0031] Figure 9 It is a three-dimensional diagram used to display the pin connection bridge area.

[0032] Figure 10 This is a schematic diagram showing the structure of the pins formed after the pin connection bridge area is cut along the cutting line in Embodiment 3.

[0033] Explanation of reference numerals in the attached drawings: 1. Lead frame; 2. Pin; 21. Back side; 22. Side end face; 23. Feed trough; 3. Pin connection bridge area; 4. Connection groove; 5. Cutting line; 6. Symmetry line; 7. Dike. Detailed Implementation

[0034] The following will be combined with the appendix Figures 1-10The technical solutions in the embodiments of the present invention are further described in detail below. The described embodiments are only possible technical implementations of the present invention, but are not limited thereto. Those skilled in the art can certainly combine the embodiments of the present invention to obtain other embodiments without creative effort, which are also within the protection scope of the present invention.

[0035] This application mainly adopts the scheme of opening a guide groove 23 on the pin 2, which achieves the effect of increasing the solder crawling height of the side end face 22 of the pin 2 and improving the yield of QFN semiconductor devices. The following is a further detailed description of this application. Example 1

[0036] Reference Figure 1 , Figure 2 and Figure 3 This embodiment discloses a pin structure for a QFN semiconductor device, including pin 2 of the QFN semiconductor device. Taking one pin 2 of the QFN semiconductor device as an example, the two exposed sides of the pin 2's molding compound are a back surface 21 and a side surface 22, which are opposite to the pads on the PCB board. A guide groove 23 is formed on the back surface 21 of the pin 2. One side of the guide groove 23 penetrates through the side surface 22 of the pin 2, making the opening of the guide groove 23 continuous, and located on both the back surface 21 and the side surface 22 of the pin 2. In the subsequent electroplating process, a solder plating layer can be formed on the side end face 22 of pin 2, blocking the oxide layer of the copper substrate. The capillary structure of the groove formed on the side end face 22 of pin 2 through the guide groove 23 provides a physical guiding path for the solder paste in the SMT placement process, allowing the solder paste to climb upward along this path in the molten state. It also increases the effective wetting area of ​​the side end face 22 of pin 2, making the attraction between the molten solder and the base material greater than gravity, increasing the solder climbing height of the side end face 22 of pin 2, and thus improving the yield of QFN semiconductor devices.

[0037] According to industry requirements, the secondary standard for solder crawling height of the side end face 22 of pin 2 in QFN semiconductor devices is: F / H > 35%, where H is the height of the side end face 22 of pin 2, and F is the climbing height of the solder on the side end face 22 of pin 2. Therefore, in order to ensure that the solder crawling height meets the secondary standard requirements, the maximum depth of the guide groove 23 on the end face of pin 2 is set to F, then F ≥ 0.35H. This makes it easier for the solder to climb to the height that meets the secondary standard requirements during the SMT placement process, avoids the oxide layer on the side end face 22 of pin 2 from hindering solder crawling, and more effectively improves the solder crawling height of the side end face 22 of pin 2, thereby improving the yield of QFN semiconductor devices.

[0038] The implementation principle of Example 1 is as follows: By setting the guide groove 23, more metal substrate is exposed on the pin 2, and a continuous tin plating layer is formed during the tin plating process, which significantly improves the wetting ability of the sidewall; the guide groove 23 forms a capillary structure of grooves on the side end face 22 of the pin 2, which can provide a physical guiding path for the solder paste to climb during the SMT placement process, increase the solder climbing height of the side end face 22 of the pin 2, and improve the qualification rate of QFN semiconductor device placement. Example 2

[0039] This embodiment provides a method for fabricating the QFN semiconductor device pin structure as described in Embodiment 1, and its application in the semiconductor device packaging process. During semiconductor device packaging, without altering the original lead frame 1 design, the packaging process is changed to fabricate guide grooves 23 on the pins 2. The specific method is as follows: Reference Figure 4 , Figure 5 and Figure 6 The wafer undergoes processes such as film deposition, film application, dicing, film application, baking, wire bonding, post-film application, molding, curing, and grooving. In this embodiment, the grooving process can be either mechanical cutting or etching. Preferably, mechanical cutting is used to process the guide groove 23. The cutting position is selected on the back side 21 of the common pin connection bridge area 3 between adjacent QFN chips.

[0040] The cutting process of the feed channel 23 is as follows: using DISCO's new high-precision cutting equipment, the type of blade is a resin-bonded ultra-thin blade with a combination of diamond and resin, the diamond particle size is 1–3μm to ensure a smooth cut, and the blade thickness is ≤30μm to avoid excessive damage to pin 2. In this embodiment, the thickness of the pin connection bridge area 3 is I, and the depth of the connection groove 4 is i, where i = 0.5I and the tolerance is within the range of 0.15I. I = 200μm is selected, so the depth of the connection groove 4 is 100μm with a tolerance of ±30μm. Therefore, the cutting depth on the back side 21 of the pin connection bridge area 3 by the tool is 100μm with a depth error of ±30μm. The cutting process is adjusted in real time by SPC monitoring. The cutting speed of the tool is 0.5–2mm / s to avoid edge chipping. During the cutting process, deionized water at a temperature of 20–25°C is sprayed onto the cutting area with a flow rate of ≥1L / min. This can cool down the pin connection bridge area 3 during cutting and clean the debris generated during cutting, ensuring the cleanliness of the cutting area.

[0041] After the blade cutting is completed, a connection groove 4 is formed in the lead connection bridge area 3. The connection groove 4 is a recessed structure in the lead connection bridge area 3. The connection groove 4 spans the dicing lines 5 of the two lead frames 1. The so-called dicing line 5 of the lead frame 1 refers to the cutting treatment along the dicing line 5 during the subsequent single-unit separation process of the packaging process, which divides the QFN frame array into individual QFN devices. Both dicing lines 5 pass through the connection groove 4. A virtual symmetry line 6 is provided between the two dicing lines 5. The symmetry line 6 is parallel to the two dicing lines 5 and is equidistant from each dicing line 5. The connection groove 4 is symmetrically arranged about the symmetry line 6.

[0042] After the connection groove 4 is processed, the QFN lead frame 1 enters the subsequent process. During the electroplating of the lead frame 1, the setting of the connection groove 4 allows more metal substrate (such as Cu) to be exposed in the pin connection bridge area 3, enabling the electroplating solution to contact the lower part of the sidewall more evenly, forming a continuous tin plating layer and significantly improving the sidewall wetting ability. When the QFN frame array is divided into individual QFN devices, the part of the connection groove 4 outside the two cutting lines 5 forms the guide groove 23 on the pin 2 of the QFN semiconductor device, and the guide groove 23 is connected to the back surface 21 and the side end face 22 of the pin 2. Therefore, by cutting the connection groove 4 across the two cutting lines 5, the guide groove 23 can be formed on both pins 2 at one time, improving production efficiency.

[0043] In the subsequent SMT placement process, the slotting process pre-plats tin on the sidewall of pin 2, eliminating wetting barriers caused by oxidation. This allows the standard solder paste (such as ROL0 type) to have sufficient wetting ability to cover and climb to the sidewall, eliminating the need for highly active special solder paste. This not only directly reduces solder paste costs by 20%-50% and simplifies the SMT process, but also significantly improves solder climb consistency (F / H>35%) and product reliability, while reducing the risk of residual corrosion, achieving dual optimization of cost and process.

[0044] By applying the QFN semiconductor device pin structure fabrication method to the semiconductor device packaging process, and by adding packaging process steps, this solution eliminates the need to modify the product design, avoiding the NRE costs and time consumption of redesigning, verifying PCBs or packaging, significantly lowering the implementation threshold, and enabling customers to quickly deploy and solve soldering yield problems in mass production. Example 3

[0045] This embodiment also discloses a method for fabricating a QFN semiconductor device pin structure as described in Embodiment 1, and the application of this method in the design of semiconductor device lead frame structures. In the design of the QFN lead frame, the slotting process of the QFN semiconductor device is incorporated, fundamentally solving the problem of solder run-through height on the side end face 22 of pin 2. The specific slotting method is as follows: Reference Figure 7 , Figure 8 and Figure 9 In the design of the lead frame 1, a connection groove 4 needs to be machined in the lead bridge area 3. In this embodiment, the thickness of the lead bridge area 3 is I, and the depth of the connection groove 4 is i, where i = 0.5I and the tolerance is within the range of 0.15I. I = 200μm is selected, therefore the depth of the connection groove 4 is 100μm, with a tolerance of ±30μm. In this embodiment, a semi-etching process is used to machine the connection groove 4. The specific process includes: Step 1: Pre-treatment of lead frame 1 substrate. A 200μm thick QFN dedicated copper alloy lead frame 1 substrate is selected and degreased, acid-washed, washed with water, and dried in sequence to ensure the cleanliness of the substrate surface and prepare for uniform photoresist coating and precise exposure.

[0046] Step 2: Dry film photoresist coating and drying. A dry film laminating machine is used to hot-press dry film photoresist onto the pre-treated copper substrate surface. The coating is done on both the back side 21 (the processing surface of the pin 2 connecting bridge) and the front side (non-processing surface). The dry film covers and protects the non-etched areas, exposing only the areas of the groove to be processed and the dike 7.

[0047] Step 3: Alignment and Exposure, Customizing High-Precision Photolithography Film: The film pattern includes the pin 2 connecting bridge groove area (bare copper semi-etched area), the dam 7 forming area (ring-shaped full-etched area, width 0.15-0.2mm, height higher than the back of the groove 21), pin 2 and other areas of the frame (full protection area). The film alignment accuracy is controlled within ±10μm; UV Exposure: The film is precisely aligned with the coated lead frame 1, and UV light is used to cross-link and cure the dry film photoresist in the exposed area. The groove area and dam 7 area to be etched are defined by the film pattern. The unexposed areas will be removed by subsequent development.

[0048] Step 4: Development to remove uncured photoresist. Immerse the exposed lead frame 1 in alkaline developer with low-pressure spraying. After development, rinse with deionized water under high pressure to remove residual developer. Then, dry with hot air to expose the copper surface to be etched, forming a clear boundary between the protected area and the etched area. Step 5: Precision chemical semi-etching (groove + cofferdam 7 forming simultaneously) A spray-type chemical etching machine is used for single-sided precision deep etching, etching only the back side 21 (the processing surface of the pin 2 connecting bridge). The back side 21 is protected by dry film throughout the process. The core control is the etching depth and uniformity, which is suitable for groove depth requirements of 100μm±30μm.

[0049] Etching solution system: Use QFN lead frame 1 dedicated acidic copper chloride etching solution (Cu²+ concentration 180-220g / L, hydrochloric acid concentration 150-180g / L, temperature 45-50℃). The etching solution is continuously filtered and circulated to prevent copper powder residue from causing etching defects. Etching parameter control: Etching rate: The etching rate is controlled at 2-3 μm / min by adjusting the spray pressure (0.4-0.6 MPa) and spray angle (45°-60°). Precise timed etching is used, with a target etching time of 35-50 min (corresponding to a depth of 100 μm ± 30 μm). Online thickness measurement: During the etching process, a laser online thickness gauge is used to monitor the copper thickness in the etching area in real time. The measurement is performed every 5 minutes. When the thickness reaches 100μm (the remaining thickness after half etching of a 200μm substrate), the etching is stopped immediately to eliminate batch errors. Forming effect of cofferdam 7: The cofferdam 7 area forms an annular copper cofferdam 7 with a height of about 100μm, completely surrounding the groove area, and the inner wall of the cofferdam 7 is smooth and burr-free.

[0050] Post-etching treatment: Immediately rinse with deionized water under high pressure to remove residual etching solution, then neutralize, rinse again with water, and dry. A semi-etched groove with a depth of 100μm±30μm is formed in the pin connection bridge area 3 through a semi-etching process, and an annular dam 7 is formed simultaneously. The inside of the groove is bare copper surface, and the dam 7 achieves physical adhesive isolation.

[0051] Step 6: Remove adhesive and clean afterwards The etched lead frame 1 is immersed in a resist remover solution (sodium hydroxide solution, concentration 3-5%, temperature 60-70℃) to remove all cured photoresist from the surface. This is followed by multi-stage water washing, ultrasonic cleaning, and hot air drying. All resist layers are removed, exposing the complete metal surface of the lead frame 1. The groove contains a clean, semi-etched bare copper area, meeting the requirements of subsequent electroplating processes.

[0052] A connection groove 4 is machined on the connection bridge surface of pin 2 using a chemical semi-etching process. The remaining thickness of the pin 2 connection bridge is stabilized at around 100μm, preserving sufficient structural strength. This eliminates the risk of breakage or deformation during subsequent mechanical operations such as encapsulation, lead trimming, electroplating, and SMT, ensuring the structural integrity of the lead frame 1. A dike 7 is formed around the connection groove 4, effectively preventing epoxy resin from penetrating into it during subsequent epoxy resin encapsulation dispensing and molding processes, ensuring no adhesive residue in the bare copper area within the connection groove 4. After encapsulation and lead trimming, the bare copper area within the connection groove 4 is free of epoxy resin and impurities, allowing the electroplating solution to fully contact the front, back 21, and complete sides of pin 2 during electroplating.

[0053] Reference Figure 8 , Figure 10 Both lead frames 1 have dicing lines 5 passing through connecting slots 4. A virtual symmetry line 6 is provided between the two dicing lines 5, parallel to the two dicing lines 5 and equidistant from each dicing line 5. The connecting slots 4 are symmetrically arranged about the symmetry line 6. When the QFN frame array is divided into individual QFN devices, the portion of the connecting slot 4 outside the two dicing lines 5 forms a guide groove 23 on the pin 2 of the QFN semiconductor device, and the guide groove 23 is connected to the back surface 21 and side end face 22 of the pin 2.

[0054] This application integrates the connecting groove 4 into the initial design of the lead frame 1 and completes it simultaneously with the front-end basic etching process. In terms of process, it is fully compatible with the existing QFN mass production process, with no process interruptions or conflicts, and no need for additional dedicated equipment. This results in higher mass production efficiency and lower overall production costs, adapting to the needs of large-scale industrial production. In terms of processing, because high-precision photolithography and etching are performed on a pure copper bare substrate, there are no plating or adhesive layers to obstruct the process. This allows for more precise alignment and depth control, higher structural dimensional consistency, and stable fulfillment of design specifications such as groove depth. This ensures high product yield while maintaining sufficient structural strength in the lead frame 1. To avoid the risk of process breakage, the synchronously etched metal dam 7 forms a reliable physical barrier against epoxy resin seepage, completely preventing epoxy resin from contaminating the bare copper area of ​​the groove. Before electroplating, the front, back, and complete sides of the pin 2 are all exposed metal surfaces, enabling 100% side plating with precise and controllable tin plating height. Ultimately, relying on the above-mentioned process and structural advantages, a super-level 2 standard of F / H > 50% is achieved after SMT surface mount soldering. This fundamentally solves the soldering reliability problem of QFN packages from both structural and process perspectives, effectively avoiding problems such as cold solder joints and false solder joints, and ensuring the long-term stability of soldering performance.

[0055] The above are all preferred embodiments of this application and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A pin structure for a QFN semiconductor device, characterized in that: The device includes a pin (2) of a QFN semiconductor device, on which a guide groove (23) is provided. The guide groove (23) extends through the back (21) and side end (22) of the pin (2) so that solder can be filled into the guide groove (23).

2. The pin structure of the QFN semiconductor device according to claim 1, characterized in that: The maximum depth of the guide groove (23) on the side end face (22) of the pin (2) is F, and the height of the side end face (22) of the pin (2) is H, where F ≥ 0.35H.

3. A method for fabricating a pin structure as described in any one of claims 1-2, characterized in that: include: A connection groove (4) is machined on the back side (21) of the pin connection bridge area (3) of the lead frame (1). The cutting line (5) of the lead frame (1) passes through the connection groove (4). When cutting the lead frame (1), the lead frame (1) is cut along the cutting line (5) and a guide groove (23) is formed on the pin (2).

4. The method for fabricating the pin structure of the QFN semiconductor device according to claim 3, characterized in that: The cutting lines (5) of two adjacent lead frames (1) pass through the connecting groove (4). After the lead frames (1) are cut along the cutting lines (5), a guide groove (23) is formed on the pin (2) of each lead frame (1).

5. The method for fabricating the pin structure of the QFN semiconductor device according to claim 4, characterized in that: During the processing of the connection groove (4), a semi-etching process is used to process the connection groove (4) on the back side (21) of the pin connection bridge area (3).

6. The method for fabricating the pin structure of the QFN semiconductor device according to claim 3, characterized in that: The thickness of the pin (2) is I, and the depth of the connecting groove (4) is i, i=0.5I, with a tolerance within the range of 0.15I.

7. The method for fabricating the pin structure of the QFN semiconductor device according to claim 3, characterized in that: The pin connection bridge area (3) forms a dam (7) around the connection groove (4), and the dam (7) is arranged in a circle around the connection groove (4).

8. The method for fabricating the pin structure of the QFN semiconductor device according to claim 4, characterized in that: A virtual symmetry line (6) is provided between the two cutting lines (5). The distance between the symmetry line (6) and the two cutting lines (5) is equal. The connecting groove (4) is symmetrically set about the symmetry line (6).

9. The application of a method for fabricating the pin structure of a QFN semiconductor device as described in any one of claims 3-4 in the semiconductor device packaging process.

10. The application of a method for fabricating the pin structure of a QFN semiconductor device as described in any one of claims 3-8 in the design of semiconductor device lead frame structures.

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