Array substrate, display panel and display device

Abstract

An array substrate (001), a display panel (PNL) and a display device, comprising a substrate (101), the substrate (101) comprising a display area (AA) and a non-display area located on at least one side of the display area (AA); the plurality of binding terminal groups (104) are positioned in the non-display area, and each binding terminal group (104) comprises a plurality of first binding terminals (PD1); the multiple detection lines (105) are located in the non-display area, the multiple detection lines (105) are electrically connected with at least part of the first binding terminals (PD1), and at least part of the detection lines (105) comprise a main line (TL) and branch lines (BL); the plurality of gate signal output lines (106) are located in the non-display area, orthographic projections of the plurality of gate signal output lines (106) on the substrate (101) intersect with orthographic projections of at least part of the detection lines (105) on the substrate (101), and the total number of the main lines (TL) and the branch lines (BL) which intersect with at least part of the gate signal output lines (106) is the same.

Description

Array substrate, display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. PCT / CN2024 / 095814, filed on May 28, 2024, entitled "Array Substrate, Display Panel and Display Device", the contents of which are incorporated herein by reference in part. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0004] Over the decades, the television industry has undergone a dramatic transformation, much like the mobile phone industry, evolving from bulky black-and-white TVs to color TVs, and now to large-screen smart displays. Technological innovation has been relentless. With product updates and the increasing demands of users for monitors, there's a need to constantly break with traditional technologies. Beyond advancements in low cost, high transmittance, and high contrast, the integration of sensors into display products—such as adding light and temperature sensors—aims to enhance the user experience.

[0005] Summary of the Invention

[0006] The array substrate, display panel, and display device disclosed herein are specifically designed as follows:

[0007] On one hand, the array substrate provided in the embodiments of this disclosure includes:

[0008] A substrate, the substrate including a display area and a non-display area located on at least one side of the display area;

[0009] Multiple bonding terminal groups are located in the non-display area, and each bonding terminal group includes multiple first bonding terminals;

[0010] Multiple detection lines are located in the non-display area. The multiple detection lines are electrically connected to at least a portion of the first bonding terminals. At least a portion of the detection lines include main lines and branch lines.

[0011] Multiple gate signal output lines are located in the non-display area. The orthographic projections of the multiple gate signal output lines on the substrate intersect with the orthographic projections of at least a portion of the detection lines on the substrate, and the total number of main lines and branch lines intersecting with at least a portion of the gate signal output lines is the same.

[0012] In some embodiments, the array substrate provided in this disclosure further includes a plurality of transistor groups located in the non-display area, and at least a portion of the transistor groups and the plurality of gate signal output lines are located on the same side of the display area;

[0013] The multiple detection lines include multiple first photosensitive detection lines, and different transistor groups are electrically connected to different first photosensitive detection lines;

[0014] Among the multiple transistor groups arranged on the same side as the multiple gate signal output lines, the first photosensitive detection line connected to the transistor group closest to the multiple bonding terminal groups includes only the trunk line, while the first photosensitive detection lines connected to the other transistor groups include the trunk line and at least one branch line.

[0015] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines located in the display area;

[0016] The extension of the at least one branch line in the data line direction generally coincides with the extension of the main line of the first photosensitive detection line corresponding to the transistor group on the side near the plurality of bonding terminal groups in the data line direction.

[0017] In some embodiments, in the array substrate provided in the present disclosure, the bifurcation position of the at least one branch line is located between two adjacent transistor groups.

[0018] In some embodiments, in the array substrate provided in the present disclosure, at least one end of the branch line closest to the transistor group, away from the bifurcation position, is electrically connected to the transistor group.

[0019] In some embodiments, in the array substrate provided in the present disclosure, in the same first photosensitive detection line with a bifurcated design, the end of the at least one branch line away from the bifurcation position is continuously arranged with the main line.

[0020] In some embodiments, in the array substrate provided in the present disclosure, in the same first photosensitive detection line with a bifurcated design, the end of the at least one branch line away from the bifurcation position is disconnected from the main line.

[0021] In some embodiments, the array substrate provided in the present disclosure further includes a plurality of dummy transistors, the transistor group including at least one transistor, and the transistor and the dummy transistors being uniformly distributed in the non-display area where the plurality of transistor groups are located.

[0022] In some embodiments, in the array substrate provided in the present disclosure, the bifurcation position of the at least one branch line is located between the transistor group and the dummy transistor.

[0023] In some embodiments, the array substrate provided in this disclosure further includes a plurality of data lines and a plurality of gate lines intersecting in the display area, and a plurality of sub-pixels within the area defined by the plurality of data lines and the plurality of gate lines;

[0024] The projections of the transistor and the dummy transistor along the gate line direction correspond to the sub-pixels in two adjacent rows.

[0025] In some embodiments, in the array substrate provided in the present disclosure, the extension line of the gate line overlaps with the gate of the transistor or the dummy transistor.

[0026] In some embodiments, in the array substrate provided in the present disclosure, every four transistor groups constitute a photosensitive component, and a dummy transistor is provided between two adjacent transistor groups of the same photosensitive component.

[0027] In some embodiments, in the array substrate provided in this disclosure, the first electrode of the transistor is electrically connected to the first photosensitive detection line;

[0028] The orthogonal projection of the gate of the transistor on the substrate extends outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode of the transistor on the substrate.

[0029] In some embodiments, in the array substrate provided in the present disclosure, at least one of the gate, first electrode, and second electrode of the dummy transistor is floating.

[0030] In some embodiments, in the array substrate provided in the present disclosure, the plurality of bonding terminal groups are arranged along the gate line direction, and the first and last two bonding terminal groups are the first bonding terminal groups;

[0031] The plurality of detection lines also include a second photosensitive detection line and a third photosensitive detection line electrically connected to the two first binding terminal groups;

[0032] The gates of the plurality of transistor groups are connected to the second photosensitive detection line, and the second photosensitive detection lines corresponding to the two first bonding terminal groups are arranged independently or integrally in the non-display area opposite to the plurality of bonding terminal groups;

[0033] The second electrode of the plurality of transistor groups is connected to the third photosensitive detection line, and the third photosensitive detection lines corresponding to the two first bonding terminal groups are arranged independently or integrally in the non-display area opposite to the plurality of bonding terminal groups.

[0034] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines located in the display area and multiple fan-out lines located in the non-display area;

[0035] The plurality of bonding terminal groups are arranged along the direction of the grid line, and the bonding terminal group further includes a plurality of second bonding terminals, with the first and last two bonding terminal groups being the first bonding terminal groups;

[0036] The multiple fan-out lines are connected between the multiple data lines and the second binding terminals of the multiple binding terminal groups;

[0037] The plurality of detection lines are electrically connected to at least one second bonding terminal of the first bonding terminal group, and the orthographic projection of the plurality of detection lines on the substrate intersects with the orthographic projection of the fan-out line corresponding to the first bonding terminal group on the substrate.

[0038] In some embodiments, the array substrate provided in this disclosure further includes a plurality of gate lines that intersect with the plurality of data lines in the display area;

[0039] The fan-out line includes a first fan-out portion, and at least a portion of the detection line includes a first detection portion. One of the first fan-out portion and the first detection portion is on the same layer as the gate line, and the other is on the same layer as the data line.

[0040] The orthographic projection of the first detection unit on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the first bonding terminal group on the substrate.

[0041] In some embodiments, the array substrate provided in this disclosure further includes a first common electrode line located on the side of the plurality of gate signal output lines near the display area;

[0042] At least part of the detection line also includes a second detection section disposed on the same layer as the first fan-out section. The second detection section is connected to the first detection section, and the connection position between the first detection section and the second detection section is located on the side of the first common electrode line near the first fan-out section.

[0043] In some embodiments, the array substrate provided in this disclosure further includes a first electrostatic discharge structure connected to the first fan-out portion corresponding to the first bonding terminal group, and at least one second electrostatic discharge structure connected to the first electrostatic discharge structure; wherein...

[0044] The first electrostatic discharge structure extends along the gate line direction or the data line direction;

[0045] The second electrostatic discharge structure extends along the data line direction, and at least one of the second electrostatic discharge structures is located on the side of the first bonding terminal group away from the second detection part;

[0046] The first detection unit is disposed around the first electrostatic discharge structure and the second electrostatic discharge structure which is far away from the second detection unit.

[0047] In some embodiments, in the array substrate provided in the present disclosure, the bonding terminal group other than the first bonding terminal group is the second bonding terminal group;

[0048] The array substrate also includes multiple compensation lines disposed on the same layer as the first detection unit, and the orthographic projection of the compensation lines on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the second bonding terminal group on the substrate.

[0049] In some embodiments, in the array substrate provided in the present disclosure, the extension of the compensation line in the gate line direction substantially coincides with the extension of the detection line in the gate line direction.

[0050] In some embodiments, in the array substrate provided in the present disclosure, the compensation lines corresponding to two adjacent second bonding terminal groups are arranged approximately symmetrically.

[0051] In some embodiments, the array substrate provided in this disclosure further includes a third electrostatic discharge structure connected to the first fan-out portion corresponding to the second bonding terminal group, and a fourth electrostatic discharge structure connected to the third electrostatic discharge structure; wherein...

[0052] The third electrostatic discharge structure extends along the gate line direction or the data line direction, and the fourth electrostatic discharge structure extends along the data line direction;

[0053] The compensation wire is wound around the third electrostatic discharge structure and the fourth electrostatic discharge structure.

[0054] In some embodiments, the array substrate provided in this disclosure further includes a second common electrode line and multiple dummy lines; wherein,

[0055] The second common electrode line extends between adjacent bonding terminal groups;

[0056] The multiple dummy lines are located between the first detection unit and the second common electrode line, and between the compensation line and the second common electrode line.

[0057] In some embodiments, the array substrate provided in this disclosure further includes multiple data lines located in the display area and multiple fan-out lines located in the non-display area;

[0058] The plurality of bonding terminal groups are arranged along the direction of the grid line, and the bonding terminal group further includes a plurality of second bonding terminals, wherein the first and last two bonding terminal groups are the first bonding terminal groups, and the remaining bonding terminal groups are the second bonding terminal groups;

[0059] The multiple fan-out lines are connected between the multiple data lines and the second binding terminals of the multiple binding terminal groups;

[0060] The plurality of detection lines are electrically connected to the second binding terminal of at least one of the first binding terminal groups, and the plurality of detection lines are wound around the side of at least one of the first binding terminal groups away from the second binding terminal group.

[0061] On the other hand, this disclosure provides a display panel including an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate provided in this disclosure.

[0062] In some embodiments, in the display panel provided in the present disclosure, the array substrate includes multiple detection lines located in the non-display area, and multiple transistor groups electrically connected to at least a portion of the detection lines;

[0063] The opposing substrate includes a black matrix, and at least a portion of the orthogonal projections of the transistor array onto the substrate do not overlap with the orthogonal projections of the black matrix onto the substrate.

[0064] In some embodiments, in the display panel provided in the present disclosure, the opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate, the color resist layer including a plurality of color resists of different colors, the plurality of color resists covering at least a portion of the transistor group.

[0065] In some embodiments, in the display panel provided in the present disclosure, the array substrate includes multiple detection lines located in the non-display area, and multiple transistor groups electrically connected to at least a portion of the detection lines;

[0066] The opposing substrate includes a black matrix, and the orthogonal projections of the multiple detection lines and the multiple transistor groups on the substrate are all located within the orthogonal projection of the black matrix on the substrate.

[0067] On the other hand, this disclosure provides a display device, including the display panel provided in this disclosure and a backlight module located on the light-incident side of the display panel. Attached Figure Description

[0068] Figure 1 is a schematic diagram of a display device provided in an embodiment of this disclosure;

[0069] Figure 2 is a schematic diagram of load compensation for the detection line on the gate drive circuit side provided in an embodiment of this disclosure;

[0070] Figure 3 is a magnified structural diagram of region Z1 in Figure 1;

[0071] Figure 4 is a magnified structural diagram of region Z2 in Figure 3;

[0072] Figure 5 is a schematic diagram of the structure of a transistor provided in an embodiment of this disclosure;

[0073] Figure 6 is an equivalent circuit diagram of a light-sensing component in an embodiment of this disclosure;

[0074] Figure 7 is a schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0075] Figure 8 is a structural schematic diagram of the display panel corresponding to Figure 7;

[0076] Figure 9 is a schematic diagram of a transistor structure provided in an embodiment of this disclosure;

[0077] Figure 10 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0078] Figure 11 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0079] Figure 12 is a schematic diagram of another structure of a transistor provided in an embodiment of this disclosure;

[0080] Figure 13 is an enlarged structural diagram of region Z3 in Figure 1;

[0081] Figure 14 is an enlarged structural diagram of region Z4 in Figure 1;

[0082] Figure 15 is an enlarged structural diagram of region Z5 in Figure 7;

[0083] Figure 16 is an enlarged structural diagram of region Z6 in Figure 7;

[0084] Figure 17 is an enlarged structural diagram of region Z7 in Figure 7;

[0085] Figure 18 is an enlarged structural diagram of region Z8 in Figure 7;

[0086] Figure 19 is an enlarged structural diagram of region Z9 in Figure 7;

[0087] Figure 20 is an enlarged structural diagram of region Z10 in Figure 15;

[0088] Figure 21 is a schematic diagram of another structure of the display device provided in an embodiment of the present disclosure;

[0089] Figure 22 is a schematic diagram of another structure of the display device provided in an embodiment of the present disclosure;

[0090] Figure 23 is a schematic diagram of another structure of the display panel provided in an embodiment of this disclosure;

[0091] Figure 24 is a schematic diagram of another structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0092] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that, for clarity, the thickness of layers, films, panels, regions, etc., is enlarged in the drawings. Exemplary embodiments are described in this disclosure with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, deviations from the shape of the figures will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shape of the regions shown in this disclosure, but rather include deviations in shape caused, for example, by manufacturing processes. For example, a region illustrated or described as flat may typically have rough and / or non-linear characteristics; a sharp corner illustrated may be rounded, etc. Therefore, the regions shown in the figures are schematic in nature, and their dimensions and shapes are not intended to illustrate the precise shape of the regions or reflect true proportions; their purpose is merely to illustrate the content of this disclosure. And throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0093] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0094] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as "located on one side of" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as "directly on" or "directly connected to" another element or layer, no intermediate elements or intermediate layers are present. The term "and / or" includes any and all combinations of one or more of the related listed items.

[0095] While pursuing high image quality, related LCD products (such as TVs) are also gradually developing towards intelligence and multi-functionality. Light and / or temperature sensing detection functions are important means to realize the intelligent design of LCD products. In some embodiments, detection can be performed using an external integrated circuit (IC) on the liquid crystal cell (Cell), but this is costly, has limited detection location, and the test results are not accurate enough. Compared to external sensing detection solutions, integrated sensing detection designs have advantages such as low cost, process compatibility, and portability. However, integrated sensing detection solutions require wiring design inside the panel, which can easily lead to coupling interference with the existing display circuitry, affecting display performance.

[0096] To at least improve the aforementioned technical problems existing in related technologies, this disclosure provides an array substrate. Figure 1 is a structural schematic diagram of a display device provided in this disclosure, Figure 2 is a load compensation schematic diagram of the gate drive circuit side detection line provided in this disclosure, Figure 3 is an enlarged structural schematic diagram of region Z1 in Figure 1, and Figure 4 is an enlarged structural schematic diagram of region Z2 in Figure 3. As can be seen from Figures 1 to 4, the array substrate provided in this disclosure may include:

[0097] The substrate 101 includes a display area AA and a non-display area. The non-display area includes a first non-display area BB1, a second non-display area BB2 and a third non-display area BB3. The first non-display area BB1 is located on one side of the display area AA, the second non-display area BB2 is opposite to the first non-display area BB1, and the third non-display area BB3 is connected to the first non-display area BB1 and the second non-display area BB2. Optionally, the substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic and other materials.

[0098] Multiple data lines 102 and multiple gate lines 103 are arranged in a crisscross pattern within the display area AA. The data lines 102 may be located on the source / drain metal layer (SD), and the gate lines 103 may be located on the gate metal layer (Gate), or both may be located on the source / drain metal layer (SD). In some embodiments, the source / drain metal layer (SD) may be made of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni). The source / drain metal layer (SD) may be a single-layer structure or a multilayer structure; for example, the source / drain metal layer (SD) may be a multilayer structure composed of a titanium metal layer / an aluminum metal layer / a titanium metal layer. The gate metal layer (Gate) may be made of metals such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), chromium (Cr), and nickel (Ni). The gate metal layer (Gate) may be a single-layer structure or a multilayer structure; for example, the gate metal layer (Gate) may be a single-layer structure composed of a molybdenum metal layer.

[0099] Multiple bonding terminal groups 104 are located in the non-display area. In some embodiments, the multiple bonding terminal groups 104 can be arranged in the first non-display area BB1 along the X direction of the gate line 103. The bonding terminal group 104 includes multiple first bonding terminals PD1. The bonding terminal group 104 can be electrically connected to driving circuits such as chip-on-film (COF) and flexible printed circuit (FPC).

[0100] Multiple detection lines 105 are located in the non-display area. In some embodiments, the detection lines 105 extend from the first non-display area BB1 through the third non-display area BB3 to the second non-display area BB2. Optionally, within the third non-display area BB3, the detection lines 105 are located between the gate drive circuit area GOA and the display area AA. In some embodiments, the multiple detection lines 105 may be electrically connected to at least a portion of the first bonding terminal PD1, and at least a portion of the detection lines 105 include a main line TL and a branch line BL.

[0101] Multiple gate signal output lines 106 (also referred to as Gout lines) are located in the non-display area, such as the third non-display area BB3. The orthographic projection of the multiple gate signal output lines 106 on the substrate 101 intersects with the orthographic projection of at least some of the detection lines 105 (e.g., the first photosensitive detection line DL, the second photosensitive detection line GL, and the third photosensitive detection line SL) on the substrate 101, and the total number of trunk lines TL and branch lines BL that intersect with at least some of the gate signal output lines 106 is the same. For example, in Figure 3, the first to third gate signal output lines 106 from top to bottom intersect with 12 main lines TL and 0 branch lines BL; the fourth to sixth gate signal output lines 106 intersect with 11 main lines TL and 1 branch line BL; the seventh to ninth gate signal output lines 106 intersect with 10 main lines TL and 2 branch lines BL; the tenth to twelfth gate signal output lines 106 intersect with 9 main lines TL and 3 branch lines BL; and the thirteenth and fourteenth gate signal output lines 106 intersect with 8 main lines TL and 4 branch lines BL. Thus, the total number of main lines TL and branch lines BL that each gate signal output line 106 intersects with is 12.

[0102] If the detection lines 105 become less dense and less sparse in the direction from the first non-display area BB1 to the second non-display area BB2, the number of detection lines 105 coupled to different gate signal output lines 106 will be different, which will affect the display performance. This disclosure adds a load compensation design, designing at least some of the detection lines 105 to be branched, including trunk lines TL and branch lines BL, and ensuring that the sum of the number of trunk lines TL crossing on different gate signal output lines 106 is the same, so that the coupling pull effect is the same and no display abnormality problem occurs.

[0103] In some embodiments, FIG5 is a schematic diagram of the structure of a transistor 107' provided in the present disclosure. As shown in FIG2 to FIG5, the array substrate provided in the present disclosure may further include multiple transistor groups 107 located in the non-display area. The transistor group 107 includes at least one transistor 107'. At least some transistor groups 107 and multiple gate signal output lines 106 are located on the same side of the display area AA. For example, some transistor groups 107 and gate signal output lines 106 are located in the third non-display area BB3 (specifically, they may be located between the gate driving circuit area GOA and the display area AA), and the remaining transistor groups 107 are located in the second non-display area BB2. Multiple detection lines 105 may include multiple first light-sensing detection lines DL. Different transistor groups 107 (e.g., the first terminal d of transistor 107' contained in transistor group 107) may be electrically connected to different first light-sensing detection lines DL. Among the multiple transistor groups 107 arranged in the third non-display area BB3, the first light-sensing detection line DL connected to the transistor group 107 closest to the multiple bonding terminal groups 104 (e.g., the first transistor group RS) only includes the trunk line TL. The first light-sensing detection lines DL connected to the other transistor groups 107 (e.g., the second transistor group GS, the third transistor group BS, and the fourth transistor group DS) include the trunk line TL and at least one branch line BL, so as to improve the display defects caused by the different coupling capacitances between the different gate signal output lines 106 and the first light-sensing detection lines DL.

[0104] In some embodiments, in the array substrate provided in the present disclosure, as shown in Figures 2 to 4, for a first photosensitive detection line DL, the extension of at least one branch line BL in the data line 102 direction Y can substantially coincide with the extension of the main line TL of the first photosensitive detection line DL in the data line 102 direction Y of the transistor group 107 corresponding to the at least one branch line BL on the side near the multiple bonding terminal groups 104. For example, in Figure 3, for the first photosensitive detection line DL electrically connected to the second transistor group GS, the extension of one of its branch lines BL in the Y direction of the data line 102 roughly coincides with the extension of the main line TL of the first photosensitive detection line DL electrically connected to the first transistor group RS in the Y direction of the data line 102; for the first photosensitive detection line DL electrically connected to the third transistor group BS, the extensions of its two branch lines BL in the Y direction of the data line 102 roughly coincide with the main line TL of the first photosensitive detection line DL electrically connected to the first transistor group RS and the extension of the first photosensitive detection line DL in the Y direction of the data line 102 electrically connected to the second transistor group GS. For the first photosensitive detection line DL electrically connected to the fourth transistor group DS, the extensions of its three branch lines BL in the Y direction of the data line 102 roughly coincide with the main line TL of the first photosensitive detection line DL electrically connected to the first transistor group RS, the first photosensitive detection line DL electrically connected to the second transistor group GS, and the extensions of the first photosensitive detection line DL electrically connected to the third transistor group BS in the Y direction of the data line 102. This arrangement not only ensures that the coupling effect between different gate signal output lines 106 and the first photosensitive detection line DL is the same, but also improves the uniformity of the alignment layer (PI) rubbing environment.

[0105] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the error allowance, it is within the protection scope of this disclosure.

[0106] In some embodiments, in the array substrate provided in this disclosure, as shown in Figures 3 and 4, the branching position of the branch line BL can be located between two adjacent transistor groups 107, so as to ensure that the coupling effect between different gate signal output lines 106 and the first photosensitive detection line DL is the same. Referring again to Figures 3 and 4, in the first photosensitive detection line DL with a branching design, at least one end of the branch line BL closest to the transistor group 107 away from the branching position can be electrically connected to the transistor group 107; for example, the ends of each branch line BL away from the branching position can be continuously connected to the main line TL, that is, the ends of each branch line BL away from the branching position can be connected to the main line TL through a lateral connecting line, so that the main line TL and the ends of each branch line BL away from the branching position are all connected to the transistor group 107. Of course, in some embodiments, the ends of each branch line BL away from the branching position can also be disconnected from the main line TL, so that in the first photosensitive detection line DL with a branching design, only the branch line BL closest to the transistor group 107 is electrically connected to the transistor group 107.

[0107] In some embodiments, as shown in FIG3 and FIG4, the array substrate provided in the present disclosure may further include a plurality of dummy transistors 108. The transistors 107' contained in the transistor group 107 may be uniformly distributed with the dummy transistors 108 in the non-display area (e.g., the second non-display area BB2 and the third non-display area BB3) where the transistor group 107' is located, thereby improving the uniformity of the alignment layer (PI) orientation environment and obtaining a better alignment effect.

[0108] In some embodiments, as shown in FIG3, the gate line 103 and the data line 102 are intersected in the display area AA, and a plurality of sub-pixels SP are provided in the area defined by the data line 102 and the gate line 103; the projections of the transistor 107' and the dummy transistor 108 along the direction X of the gate line 103 correspond to the spaces between two adjacent rows of sub-pixels SP. In some embodiments, to maximize the uniformity of orientation, the gaps between two adjacent rows of sub-pixels SP are respectively provided with transistor 107' or dummy transistor 108. Continuing to refer to FIG3 to FIG5, it can be seen that the extension line of the gate line 103 may overlap with the gate g of the transistor 107' or the dummy transistor 108.

[0109] In some embodiments, as shown in Figures 3 and 4, the branching point of the branch line BL can be located between the transistor group 107 and the dummy transistor 108. Every four transistor groups 107 can be a photosensitive component LS, and a dummy transistor 108 is provided between two adjacent transistor groups 107 of the same photosensitive component LS. Figure 6 is an equivalent circuit diagram of a photosensitive component LS in an embodiment of the present disclosure. As can be seen from Figures 3 to 6, a photosensitive component LS in the present disclosure can specifically include a first transistor group RS, a second transistor group GS, a third transistor group BS, and a fourth transistor group DS. The first transistor group RS can be covered by the red color filter R of the opposing substrate (also called the color filter substrate CF), the second transistor group GS can be covered by the green color filter G of the opposing substrate, the third transistor group BS can be covered by the blue color filter B of the opposing substrate, and the fourth transistor group DS can be covered by the black matrix BM of the opposing substrate. The fourth transistor group DS, covered by the black matrix BM, can serve as a control. Since all transistors 107' have the same shape and size, and the second photosensitive detection line GL applies a uniform voltage to the gate g of all transistors 107' in the same photosensitive component LS, and the third photosensitive detection line SL applies a uniform voltage to the second electrode s of all transistors 107' in the same photosensitive component LS, the influence of transistor structure, voltage, temperature, and other factors on the detection current is eliminated. Based on this, the current value of transistors 107' not covered by the black matrix BM minus the current value of transistors 107' covered by the black matrix BM is the current value generated by ambient light illumination, thus achieving the detection of ambient light brightness. By combining the red color resistor R, green color resistor G, and blue color resistor B, the proportions of red, green, and blue light in ambient light or backlight can be detected, thus achieving the detection of both ambient light brightness and color temperature. In some embodiments, the current values ​​of the first transistor group RS, the second transistor group GS, the third transistor group BS, and the fourth transistor group DS can be fed back to the system on chip (SOC) or the timer control register (TCON) for processing, and the brightness and / or color temperature of the backlight module BLU can be adjusted according to the processing results.

[0110] This disclosure, by setting a dummy transistor 108 between two adjacent transistor groups 107 of the same photosensitive component LS, can ensure a uniform transition of the color resist layer, which is beneficial to improving the color temperature detection effect. Simultaneously, since the photosensitive component LS of this disclosure is used as a detection point to detect ambient light color temperature and brightness, and there is only one dummy transistor 108 between two adjacent transistor groups 107 of the same photosensitive component LS, the range of the detection point of the photosensitive component LS can be kept almost constant, which is beneficial to improving the accuracy of color temperature and brightness detection.

[0111] In some embodiments, FIG7 is a schematic diagram of an array substrate provided in the present disclosure, and FIG8 is a schematic diagram of a display panel corresponding to FIG7. As can be seen from FIG7 and FIG8, each transistor 107' of the present disclosure can also be completely covered by the black matrix BM. In this case, the transistor 107' is used to detect the backlight brightness.

[0112] In some embodiments, in the array substrate provided in the present disclosure, Figures 9 to 12 are schematic diagrams of the structure of transistor 107' provided in the present disclosure, and Figure 5 also shows a schematic diagram of the structure of transistor 107'. As can be seen from Figures 5 and 9 to 12, the gate g of transistor 107' includes a bottom gate gb and / or a top gate gp. Here, the bottom gate gb refers to the gate g being disposed between the substrate 101 and the semiconductor layer (also known as the active layer), and the top gate gp refers to the gate g being disposed on the side of the semiconductor layer away from the substrate 101. In this case, for the simultaneous provision of top gate gp and bottom gate gb, they can be disposed separately or electrically connected, which is not limited here. The bottom gate gb is a metal electrode or a transparent electrode, and the top gate gp is a transparent electrode. The transparent electrode can be disposed in the same layer and with the same material as the pixel electrode or common electrode of the display area AA. Optionally, when transistor 107' has both bottom gate gb and top gate gp, connecting the bottom gate gb and top gate gp can reduce the number of terminals connected to the gate g. During light sensing, the magnitude of the current in the first electrode d affects the accuracy of light sensing. Using both the bottom gate gb and the top gate gp as the gate g of transistor 107' can increase the current in the first electrode d, which is beneficial for light detection.

[0113] It should be noted that when the bottom gate (gb) is a metal electrode, the backlight brightness can be characterized by detecting scattered light and diffracted light within the liquid crystal cell. When the gate (g) is a transparent electrode, the backlight brightness can be characterized by detecting scattered light and diffracted light within the liquid crystal cell, as well as backlight incident on the transistor 107' through the substrate 101. Furthermore, in embodiments that detect ambient light, to minimize backlight interference, the transistor 107' should be a bottom-gate transistor or a dual-gate transistor with a metal bottom gate (gb).

[0114] In some embodiments, as shown in Figures 5 and 9 to 12, the orthogonal projection of the gate g of transistor 107' onto the substrate 101 can be extended outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode d of transistor G onto the substrate 101, for example, the extension distance D is greater than 0 μm. In some embodiments, the extension can be 5 μm, 10 μm, 15 μm, 20 μm, etc. Within this distance range, the sensitivity of the detection current of transistor 107' and the recoverability of characteristic drift can be balanced. Optionally, in this embodiment, the gate layer and the ITO electrode layer can be fabricated using a single mask. In addition, within the third non-display area BB3, the transistor 107' with the structure shown in Figure 5 is used to reduce the size of transistor 107', achieve a narrow bezel effect, and facilitate heat dissipation.

[0115] In some embodiments, to simplify the process, as shown in FIG4, the structure and size of the dummy transistor 108 of this disclosure can be the same as those of the transistor 107', and are not limited thereto. Since the dummy transistor 108 in this disclosure is not used to detect light brightness, it does not need to have conduction or cutoff characteristics. Based on this, at least one of the gate g, the first electrode d, and the second electrode s of the dummy transistor 108 of this disclosure can be floating.

[0116] In some embodiments, transistor 107' and dummy transistor 108 in this disclosure can be thin-film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSs), without limitation herein. In some embodiments, transistor 107' and dummy transistor 108 can be P-type transistors or N-type transistors. The first electrode d can be the source and the second electrode s can be the drain, or the first electrode d can be the drain and the second electrode s can be the source, without limitation herein. The active layer of transistor 107' and dummy transistor 108 can be one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene.

[0117] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG1, FIG2 and FIG7, a plurality of bonding terminal groups 104 can be arranged in the first non-display area BB1 along the direction X of the gate line 103, and the first and last bonding terminal groups 104 are the first bonding terminal groups 1041; the two first bonding terminal groups 1041 are electrically connected to the second light sensing line GL and the third light sensing line SL; the second light sensing line GL corresponding to the two first bonding terminal groups 1041 is arranged independently or integrally in the second non-display area BB2; the third light sensing line SL corresponding to the two first bonding terminal groups 1041 is arranged independently or integrally in the second non-display area BB2. For example, in Figures 1, 2, and 7, the second photosensitive detection line GL introduced from the left third non-display area BB3 to the second non-display area BB2 and the second photosensitive detection line SL introduced from the right third non-display area BB3 to the second non-display area BB2 are designed separately, that is, they are designed independently of each other. The second photosensitive detection line GL corresponding to the left third non-display area BB3 and the second photosensitive detection line GL corresponding to the right third non-display area BB3 can be provided with detection signals by different circuit boards. Similarly, the third photosensitive detection line SL introduced from the left third non-display area BB3 to the second non-display area BB2 and the second photosensitive detection line SL introduced from the right third non-display area BB3 to the second non-display area BB2 are designed separately, that is, they are designed independently of each other. The third photosensitive detection line SL corresponding to the left third non-display area BB3 and the third photosensitive detection line SL corresponding to the right third non-display area BB3 can be provided with detection signals by different circuit boards.

[0118] Figure 13 is an enlarged structural diagram of region Z3 in Figure 1; Figure 14 is an enlarged structural diagram of region Z4 in Figure 1; Figure 15 is an enlarged structural diagram of region Z5 in Figure 7; Figure 16 is an enlarged structural diagram of region Z6 in Figure 7; Figure 17 is an enlarged structural diagram of region Z7 in Figure 7; Figure 18 is an enlarged structural diagram of region Z8 in Figure 7; Figure 19 is an enlarged structural diagram of region Z9 in Figure 7; and Figure 20 is an enlarged structural diagram of region Z10 in Figure 15. As can be seen from Figures 13 to 20, the array substrate provided in the embodiments of this disclosure may further include multiple fan-out lines 109, which are connected between multiple data lines 102 and the second bonding terminals PD2 of multiple bonding terminal groups 104 (e.g., the first bonding terminal group 1041 and the second bonding terminal group 1042). Optionally, the fan-out line 109 includes a first fan-out portion 109' located on the source / drain metal layer (SD) and a second fan-out portion 109" located on the gate metal layer and bonded to the second bonding terminal PD2. Optionally, an electrostatic discharge circuit (e.g., a first electrostatic discharge structure 112 and a third electrostatic discharge structure 114) is provided between the first fan-out portion 109' and the second fan-out portion 109".

[0119] Multiple detection lines 105 are connected to at least one first bonding terminal PD1 of a first bonding terminal group 1041 and cross the fan-out line 109 connected by the first bonding terminal group 1041. In some embodiments, at least some of the detection lines 105 (e.g., the first light-sensing detection line DL, the second light-sensing detection line GL, and the third light-sensing detection line SL) include a first detection portion 105' located on the gate metal layer and a second detection portion 105" located on the source-drain metal layer (SD), wherein the orthographic projection of the first detection portion 105' on the substrate 101 intersects with the orthographic projection of the first fan-out portion 109' on the substrate 101, the second detection portion 105" is connected to the first detection portion 105', and the second detection portion 105" extends from the connection position C through the third non-display area BB3 to the second non-display area BB2.

[0120] The area where the second fan-out portion 109” corresponding to the first bonding terminal group 1041 is located is a patterned area (PLG). Due to the dense wiring, including gate drive circuit signal lines such as clock signal lines, initial trigger signal lines (STV), high voltage signal lines, and low voltage signal lines near the second fan-out portion 109”, the PLG area suffers from poor heat dissipation and high temperature. The multiple detection lines 105 of this disclosure are wound inside the fan-out lines 109 corresponding to the first bonding terminal group 1041, which can avoid the PLG location, prevent the detection lines 105 from overheating, and improve the accuracy of light sensing. Furthermore, the transistor 107' and detection lines 105 of this disclosure are integrated inside the array substrate, which does not occupy additional space or increase the panel volume; the transistor 107' can be manufactured using the same process as the transistors connected to the pixel electrodes in the display area AA, without the need for additional photolithography processes, and will not increase production costs. Therefore, this disclosure does not increase the process or cost, but can effectively detect light intensity and color temperature, and improve detection accuracy, which provides a new solution and idea for the design of light-sensing products.

[0121] It is worth noting that this disclosure illustrates the arrangement of the detection line 105 by taking the example of having multiple binding terminal groups 104. In some embodiments, there may be only one binding terminal group 104, and the detection line 105 may also adopt the above-described winding arrangement to avoid the PLG position.

[0122] In some embodiments, as shown in FIG13, FIG15 and FIG20, the array substrate provided in the present disclosure may further include a first common electrode line 110 extending along the second direction Y in the first non-display area BB1. Optionally, the first common electrode line 110 is located in the gate metal layer. The first common electrode line 110 is used to electrically connect with the common electrode of the display area AA. The connection position C between the first detection unit 105' and the second detection unit 105" is located on the side of the first common electrode line 110 away from the corner between the first non-display area BB1 and the third non-display area BB3 (i.e., the first common electrode line 110). 10 is located near the first fan-out portion 109' to prevent the first detection portion 105' of the gate metal layer from short-circuiting with the first common electrode line 110. On the other hand, to prevent the second detection portion 105" of the source / drain metal layer (SD) from short-circuiting with the first fan-out portion 109', a connection position C is provided between the first fan-out portion 109' closest to the third non-display area BB3 and the first common electrode line 110. The connection position C may optionally be provided with an electrode layer of the same layer and material as the pixel electrode of the display area AA or the common electrode, for realizing the electrical connection between the first detection portion 105' and the second detection portion 105".

[0123] In some embodiments, as shown in Figures 14, 17, and 19, the array substrate provided in this disclosure may further include multiple compensation lines 111 located in the gate metal layer. The compensation lines 111 are electrically connected to the first bonding terminal PD1 of the second bonding terminal group 1042, and the orthographic projection of the compensation lines 111 on the substrate 101 intersects with the orthographic projection of the first fan-out portion 109' corresponding to the second bonding terminal group 1042 on the substrate 101. For the first bonding terminal group 1041, the overlapping area of ​​the detection line 105 and the fan-out line 109 increases the capacitive load of the data line 102 corresponding to the fan-out line 109. To ensure that the load of all data lines 102 remains consistent, thereby ensuring the uniformity of the display image, it is necessary to perform overlapping capacitance compensation on the fan-out line 109 corresponding to the second bonding terminal group 1042. This disclosure provides a compensation line 111 that intersects with the fan-out line 109 corresponding to the second binding terminal group 1042 by leading out a compensation line 111 from the first binding terminal PD1 at both ends of the second binding terminal group 1042. This can reduce the load difference of the data line 102 to a certain extent and improve the uniformity of the display screen.

[0124] In some embodiments, the present disclosure may configure the extension of the compensation line 111 in the X direction of the gate line 103 to approximately coincide with the extension of the detection line 105 in the X direction of the gate line 103. In other words, the present disclosure may use metal traces of the same width and spacing as the detection line 105 as capacitor compensation traces drawn from the first binding terminals PD1 at both ends of the second binding terminal group 1042, thereby ensuring that the load of all data lines 102 is consistent and ensuring good image uniformity. In addition, as shown in FIG17, in order to ensure good uniformity of the compensation capacitor and simplify the wiring design, the compensation lines 111 corresponding to two adjacent second binding terminal groups 1042 may be approximately symmetrically arranged about the axis of symmetry MN of the gap between the two second binding terminal groups 1042.

[0125] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately coincident" may coincide exactly, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately coincident" between related features meets the allowable error, it is within the protection scope of this disclosure. Similarly, "approximately symmetrical" may be completely symmetrical, or there may be some deviation (e.g., a deviation of ±2μm). Therefore, as long as the relationship of "approximately symmetrical" between related features meets the allowable error, it is within the protection scope of this disclosure.

[0126] In some embodiments, the array substrate provided in this disclosure, as shown in Figures 14, 15, and 17 to 19, may further include a first fan-out portion 109' and a second fan-out portion 109" connected to the first bonding terminal group 1041, a first electrostatic discharge structure 112 connected to the first fan-out portion 109' and the second fan-out portion 109" via a first connecting line CL1 (located in the gate metal layer) and the first electrostatic discharge structure 113 (which may be located on the left and right sides of the first bonding terminal group 1041), and a second electrostatic discharge structure 113 connected to the first electrostatic discharge structure 112 via a first connecting line CL1 (located in the gate metal layer), and a second fan-out portion 109" connected to the second bonding terminal group 1042. The first electrostatic discharge structure 112 and the second electrostatic discharge structure 114 are connected to the first fan-out section 109' and the second fan-out section 109" respectively, and the fourth electrostatic discharge structure 115 (which may be located on the left and right sides of the second bonding terminal group 1042) is connected to the third electrostatic discharge structure 114 via the second connecting line CL2 (located in the gate metal layer). The first electrostatic discharge structure 112 and the third electrostatic discharge structure 114 extend along the X direction of the gate line 103 or the Y direction of the data line 102, and the second electrostatic discharge structure 113 and the fourth electrostatic discharge structure 115 extend along the Y direction of the data line 102. Optionally, the first electrostatic discharge structure 112 and the third electrostatic discharge structure 114 are connected to the first common electrode bus 117 through different short-circuit rings 116 (which may be located in the source and drain metal layers); or, the second electrostatic discharge structure 113 and the fourth electrostatic discharge structure 115 are connected to the first common electrode bus 117 through different short-circuit rings 116 (which may be located in the source and drain metal layers), or the second electrostatic discharge structure 113 near the third non-display area BB3 is directly connected to the first common electrode bus 117, and the first common electrode bus 117 may be integrally formed with the first common electrode line 110.

[0127] In some embodiments, as shown in FIG14, to avoid short-circuiting between the first detection unit 105' and the first electrostatic discharge structure 112 and the second electrostatic discharge structure 113, the first detection unit 105' can be provided around the second electrostatic discharge structure 113 on the side of the first bonding terminal group 1041 away from the third non-display area BB3 (i.e., the side close to the second bonding terminal group 1042). For example, the first detection unit 105 starts from the side of the first electrostatic discharge structure 112 close to the display area AA, and sequentially passes through the second electrostatic discharge structure 113 (located on the side of the first bonding terminal group 1041 away from the third non-display area BB3) on the side close to the second bonding terminal group 1042, the side away from the display area AA, and the side close to the first bonding terminal. After one side of group 1041, it is connected to the second binding terminal pd2 of the first binding terminal group 1041; similarly, to avoid short-circuiting between the compensation line 111 and the third electrostatic discharge structure 114 and the fourth electrostatic discharge structure 115, the compensation line 111 can be arranged to wind around the third electrostatic discharge structure 114 and the fourth electrostatic discharge structure 115. In some embodiments, the compensation line 111 can start from the side of the third electrostatic discharge structure 114 near the display area AA, pass sequentially to the left and right sides of the fourth electrostatic discharge structure 115 near the first binding terminal group 1041, away from the display area AA, and near the second binding terminal group 1042, and then connect to the second binding terminal PD2 of the second binding terminal group 1042. In some embodiments, to simplify the structural design, the structures of the first electrostatic discharge structure 112, the second electrostatic discharge structure 113, the third electrostatic discharge structure 114, and the fourth electrostatic discharge structure 115 can be the same.

[0128] In some embodiments, in the array substrate provided in the present disclosure, as shown in FIG3, FIG15 and FIG20, the third non-display area BB3 may include the gate driving circuit area GOA, and the multiple detection lines 105 of the third non-display area BB3 may be located between the gate driving circuit area GOA and the display area AA, so as to make full use of the space between the gate driving circuit area GOA and the display area AA and achieve a narrow bezel effect.

[0129] In some embodiments of the array substrate provided in this disclosure, as shown in FIG14, a second common electrode line 118 extending between adjacent bonding terminal groups 104 is further included. To improve etching uniformity, a first dummy line 119 may be provided between the detection line 105 and the second common electrode line 118, and between the compensation line 111 and the second common electrode line 118. Optionally, the line width and line spacing of the first dummy line 119 may be the same as the line width and line spacing of the detection line 105.

[0130] In some embodiments, as shown in FIG13 and FIG14, in the array substrate provided in the embodiments of this disclosure, the detection line 105 may further include a temperature sensing detection line TS located in the gate metal layer. The temperature sensing detection line TS may be located between the second fan-out portion 109” and the first detection portion 105” in the first non-display area BB1, between the gate driving circuit area GOA and the second detection portion 105” in the third non-display area BB3, and on the side of the first light sensing detection line DL away from the display area AA in the second non-display area BB2. This ensures that the temperature sensing detection line TS is relatively long and has a large resistance, which facilitates monitoring the voltage value change caused by temperature and improves the accuracy of temperature detection. In some embodiments, in order to shield electromagnetic interference and ensure that the detection voltage is caused only by temperature, this disclosure may provide a shielding line 120 on at least one side of the temperature sensing detection line TS. Optionally, the shielding line 120 may be a single signal line or may be formed by multiple segments, which is not limited here.

[0131] In some embodiments, as shown in FIG13, in order to avoid short-circuiting the temperature sensing line TS with the first common electrode line 110 and the first common electrode bus 117, an adapter cable 121 of the same layer and material as the pixel electrode or common electrode of the display area AA can be used to connect the first common electrode line 110 and the first common electrode bus 117, and the temperature sensing line TS can cross the adapter cable 121.

[0132] In some embodiments, as shown in Figures 13 and 14, to improve etching uniformity, a second dummy line 122 located on the gate metal layer can be provided between the temperature sensing line TS and the second electrostatic discharge structure 114 near the third display area BB3; a third dummy line 123 located on the source-drain metal layer (SD) can be provided at the inclined edge of the first fan-out portion 109'; a fourth dummy line 124 can be provided between the inclined edge of the second fan-out portion 109" and the first common electrode bus 117; a fifth dummy line 125 can be provided in the area enclosed by the first common electrode bus 117 and the temperature sensing line TS; a sixth dummy line 126 can be provided between the first common electrode bus 117 and the compensation line 111; and a seventh dummy line 127 can be provided between the first common electrode bus 117 and the detection line 105.

[0133] In some embodiments, FIG21 is a schematic diagram of another structure of the display device provided in the present disclosure. As can be seen from FIG21, the multiple detection lines 105 in the present disclosure can also be routed around the side of the first binding terminal group 1041 away from the second binding terminal group 1042. In this way, the detection lines 105 will not cross the first fan-out portion 109' corresponding to the first binding terminal group 1041, and there is no need to set a compensation line that intersects with the first fan-out portion 109' corresponding to the second binding terminal group 1042.

[0134] In some embodiments, FIG22 is a schematic diagram of another structure of the display device provided in the present disclosure. As can be seen from FIG22, the present disclosure can place the photosensitive component LS and the detection line 105 between the fan-out area FA, so that the width of the third non-display area BB3 is not affected, and the detection line 105 will not cross the first fan-out portion 109' corresponding to the first binding terminal group 1041. Therefore, there is no need to set a compensation line that intersects with the first fan-out portion 109' corresponding to the second binding terminal group 1042.

[0135] In some embodiments, the array substrate provided in the present disclosure, as shown in Figures 15, 17, and 20, may further include a second common electrode bus 128 extending along the X direction of the gate line 103. The second common electrode bus 128 may be integrally disposed with the first common electrode line 110 and the second common electrode line 118. Optionally, to ensure the curing effect of the sealant, a cutout structure may be provided on the traces with larger line widths (e.g., the second common electrode line 118 and the first common electrode bus 117). Other essential components of the array substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the present disclosure.

[0136] Based on the same inventive concept, this disclosure provides a display panel. Figures 8 and 23 are schematic diagrams of the structure of the display panel provided in this disclosure. As shown in Figures 8 and 23, the display panel of this disclosure includes the array substrate 001 provided in this disclosure embodiment, and a counter substrate 002 disposed opposite to the array substrate 001. Since the principle by which this display panel solves the problem is similar to the principle by which the array substrate solves the problem, the implementation of this display panel can refer to the embodiments of the array substrate described above, and repeated details will not be described again.

[0137] In some embodiments, as shown in Figures 5, 6, and 8, the opposing substrate 002 includes a black matrix BM, and at least a portion of the transistor group 107's orthogonal projection on the substrate 101 does not overlap with the orthogonal projection of the black matrix BM on the substrate. This ensures that after the array substrate 001 and the opposing substrate 002 are aligned, ambient light illuminates the transistor group 107 not covered by the black matrix BM, thereby enabling ambient light detection. When the transistor group 107 is completely covered by the black matrix BM, backlight detection can be achieved using the transistor group 107.

[0138] In some embodiments, as shown in Figures 5 and 6, the opposing substrate 001 further includes a color resist layer located on the side of the black matrix BM facing the array substrate. The color resist layer includes multiple color resists of different colors (e.g., red color resist R, green color resist G, and blue color resist B). Optionally, the red color resist R covers the first transistor group RS, the green color resist G covers the second transistor group GS, the blue color resist B covers the third transistor group BS, and the black matrix BM covers the fourth transistor group DS, so as to realize the detection of ambient light color temperature.

[0139] In some embodiments, as shown in FIG8, the orthographic projections of multiple data lines 102, multiple gate lines 103, multiple fan-out lines 109, multiple detection lines 105, and multiple transistors 107' on the substrate 101 are all located within the orthographic projection of the black matrix BM on the substrate 101. This not only avoids the interference of ambient light on backlight detection, but also avoids the reflection of metal lines from affecting the display effect.

[0140] In some embodiments, as shown in FIG23, the display panel provided in this disclosure may further include a liquid crystal layer 003 disposed between the array substrate 001 and the opposing substrate 002. A first polarizer 004 may be disposed on the side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be disposed on the side of the opposing substrate 002 away from the array substrate 001. The polarization direction of the first polarizer 004 and the polarization direction of the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0141] Based on the same inventive concept, this disclosure provides a display device. Figure 24 is a schematic diagram of the structure of the display device provided in this disclosure. As shown in Figure 24, the display device of this disclosure includes the display panel PNL provided in this disclosure and a backlight module BLU located on the light-incident side of the display panel PNL. The backlight module BLU can be a direct-lit backlight module or an edge-lit backlight module. Optionally, the edge-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism groups, etc., with the LED strips located on one side of the thickness direction of the light guide plate. The direct-lit backlight module may include a matrix light source, a reflective sheet, a diffuser plate, and a brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0142] In some embodiments, the LEDs can also be micro-light-emitting devices (such as Mini LEDs and Micro LEDs). Sub-millimeter or even micrometer-scale micro-light-emitting devices, like organic light-emitting devices (OLEDs), are self-emissive devices. Like OLEDs, they offer advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic light-emitting devices emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic light-emitting devices (based on organic materials) in terms of lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Moreover, when micro-light-emitting devices are used as backlights, they can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while also solving the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0143] In some embodiments, the display device provided in this disclosure can be any product or component with display function, such as a monitor, projector, 3D printer, virtual reality device, mobile phone, tablet computer, television, laptop computer, digital photo frame, navigator, smartwatch, fitness wristband, personal digital assistant, etc. Optionally, the display device provided in this disclosure includes, but is not limited to, components such as: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, and control chip. Optionally, the control chip is a central processing unit, digital signal processor, system-on-a-chip (SoC), etc. For example, the control chip may also include memory, power module, etc., and achieve power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code. The hardware circuit may include conventional very large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc. Furthermore, the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or arrange different components.

[0144] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0145] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area; Multiple bonding terminal groups are located in the non-display area, and each bonding terminal group includes multiple first bonding terminals; Multiple detection lines are located in the non-display area. The multiple detection lines are electrically connected to at least a portion of the first bonding terminals. At least a portion of the detection lines include main lines and branch lines. Multiple gate signal output lines are located in the non-display area. The orthographic projections of the multiple gate signal output lines on the substrate intersect with the orthographic projections of at least a portion of the detection lines on the substrate, and the total number of main lines and branch lines intersecting with at least a portion of the gate signal output lines is the same.

2. The array substrate as claimed in claim 1, wherein, It also includes a plurality of transistor groups located in the non-display area, at least a portion of the transistor groups and the plurality of gate signal output lines being located on the same side of the display area; The multiple detection lines include multiple first photosensitive detection lines, and different transistor groups are electrically connected to different first photosensitive detection lines; Among the multiple transistor groups arranged on the same side as the multiple gate signal output lines, the first photosensitive detection line connected to the transistor group closest to the multiple bonding terminal groups includes only the trunk line, while the first photosensitive detection lines connected to the other transistor groups include the trunk line and at least one branch line.

3. The array substrate as described in claim 2, wherein, It also includes multiple data lines located in the display area; The extension of the at least one branch line in the data line direction generally coincides with the extension of the main line of the first photosensitive detection line corresponding to the transistor group on the side near the plurality of bonding terminal groups in the data line direction.

4. The array substrate as described in claim 2 or 3, wherein, The bifurcation point of the at least one branch line is located between two adjacent transistor groups.

5. The array substrate according to any one of claims 2 to 4, wherein, In the at least one branch line, at least one of the branch lines closest to the transistor group has its end away from the fork position electrically connected to the transistor group.

6. The array substrate as claimed in claim 5, wherein, In the same first photosensitive detection line with a bifurcated design, the end of the at least one branch line away from the bifurcation position is continuously arranged with the main line.

7. The array substrate as claimed in claim 5, wherein, In the same first photosensitive detection line with a bifurcated design, at least one branch line is disconnected from the main line at one end away from the bifurcation position.

8. The array substrate according to any one of claims 2 to 7, wherein, It also includes multiple dummy transistors, each transistor group comprising at least one transistor, and the transistors and the dummy transistors are evenly distributed in the non-display area where the multiple transistor groups are located.

9. The array substrate as claimed in claim 8, wherein, The bifurcation point of the at least one branch line is located between the transistor group and the dummy transistor.

10. The array substrate as claimed in claim 8 or 9, wherein, It also includes multiple data lines and multiple gate lines intersecting in the display area, as well as multiple sub-pixels within the area defined by the multiple data lines and the multiple gate lines; The projections of the transistor and the dummy transistor along the gate line direction correspond to the sub-pixels in two adjacent rows.

11. The array substrate as claimed in claim 10, wherein, The extension of the gate line overlaps with the gate of the transistor or the dummy transistor.

12. The array substrate according to any one of claims 8 to 11, wherein, Each group of four transistors forms a photosensitive component, and a dummy transistor is provided between two adjacent groups of transistors in the same photosensitive component.

13. The array substrate according to any one of claims 8 to 12, wherein, The first electrode of the transistor is electrically connected to the first photosensitive detection line; The orthogonal projection of the gate of the transistor on the substrate extends outward by 0 μm to 20 μm relative to the orthogonal projection of the first electrode of the transistor on the substrate.

14. The array substrate according to any one of claims 8 to 13, wherein, The dummy transistor has at least one of its gate, first electrode, and second electrode floating.

15. The array substrate according to any one of claims 2 to 14, wherein, The plurality of bonding terminal groups are arranged along the direction of the grid line, and the first and last two bonding terminal groups are the first bonding terminal groups; The plurality of detection lines also include a second photosensitive detection line and a third photosensitive detection line electrically connected to the two first binding terminal groups; The gates of the plurality of transistor groups are connected to the second photosensitive detection line, and the second photosensitive detection lines corresponding to the two first bonding terminal groups are arranged independently or integrally in the non-display area opposite to the plurality of bonding terminal groups; The second electrode of the plurality of transistor groups is connected to the third photosensitive detection line, and the third photosensitive detection lines corresponding to the two first bonding terminal groups are arranged independently or integrally in the non-display area opposite to the plurality of bonding terminal groups.

16. The array substrate according to any one of claims 1 to 15, wherein, It also includes multiple data lines located in the display area, and multiple fan-out lines located in the non-display area; The plurality of bonding terminal groups are arranged along the direction of the grid line, and the bonding terminal group further includes a plurality of second bonding terminals, with the first and last two bonding terminal groups being the first bonding terminal groups; The multiple fan-out lines are connected between the multiple data lines and the second binding terminals of the multiple binding terminal groups; The plurality of detection lines are electrically connected to at least one second bonding terminal of the first bonding terminal group, and the orthographic projection of the plurality of detection lines on the substrate intersects with the orthographic projection of the fan-out line corresponding to the first bonding terminal group on the substrate.

17. The array substrate as claimed in claim 16, wherein, It also includes multiple gate lines that intersect with the multiple data lines in the display area; The fan-out line includes a first fan-out portion, and at least a portion of the detection line includes a first detection portion. One of the first fan-out portion and the first detection portion is on the same layer as the gate line, and the other is on the same layer as the data line. The orthographic projection of the first detection unit on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the first bonding terminal group on the substrate.

18. The array substrate as claimed in claim 17, wherein, It also includes a first common electrode line located on the side of the plurality of gate signal output lines closest to the display area; At least part of the detection line also includes a second detection section disposed on the same layer as the first fan-out section. The second detection section is connected to the first detection section, and the connection position between the first detection section and the second detection section is located on the side of the first common electrode line near the first fan-out section.

19. The array substrate as claimed in claim 17 or 18, wherein, It also includes a first electrostatic discharge structure connected to the first fan-out portion corresponding to the first bonding terminal group, and at least one second electrostatic discharge structure connected to the first electrostatic discharge structure; wherein, The first electrostatic discharge structure extends along the gate line direction or the data line direction; The second electrostatic discharge structure extends along the data line direction, and at least one of the second electrostatic discharge structures is located on the side of the first bonding terminal group away from the second detection part; The first detection unit is disposed around the first electrostatic discharge structure and the second electrostatic discharge structure which is far away from the second detection unit.

20. The array substrate according to any one of claims 17 to 19, wherein, The binding terminal group other than the first binding terminal group is the second binding terminal group; The array substrate also includes multiple compensation lines disposed on the same layer as the first detection unit, and the orthographic projection of the compensation lines on the substrate intersects with the orthographic projection of the first fan-out portion corresponding to the second bonding terminal group on the substrate.

21. The array substrate as claimed in claim 20, wherein, The extension of the compensation line in the direction of the grid line is approximately coincident with the extension of the detection line in the direction of the grid line.

22. The array substrate as claimed in claim 20 or 21, wherein, The compensation lines corresponding to two adjacent second binding terminal groups are arranged approximately symmetrically.

23. The array substrate according to any one of claims 20 to 22, wherein, It also includes a third electrostatic discharge structure connected to the first fan-out portion corresponding to the second bonding terminal group, and a fourth electrostatic discharge structure connected to the third electrostatic discharge structure; wherein, The third electrostatic discharge structure extends along the gate line direction or the data line direction, and the fourth electrostatic discharge structure extends along the data line direction; The compensation wire is wound around the third electrostatic discharge structure and the fourth electrostatic discharge structure.

24. The array substrate according to any one of claims 20 to 23, wherein, It also includes a second common electrode line and multiple dummy lines; among them, The second common electrode line extends between adjacent bonding terminal groups; The multiple dummy lines are located between the first detection unit and the second common electrode line, and between the compensation line and the second common electrode line.

25. The array substrate according to any one of claims 1 to 16, wherein, It also includes multiple data lines located in the display area, and multiple fan-out lines located in the non-display area; The plurality of bonding terminal groups are arranged along the direction of the grid line, and the bonding terminal group further includes a plurality of second bonding terminals, wherein the first and last two bonding terminal groups are the first bonding terminal groups, and the remaining bonding terminal groups are the second bonding terminal groups; The multiple fan-out lines are connected between the multiple data lines and the second binding terminals of the multiple binding terminal groups; The plurality of detection lines are electrically connected to the second binding terminal of at least one of the first binding terminal groups, and the plurality of detection lines are wound around the side of at least one of the first binding terminal groups away from the second binding terminal group.

26. A display panel, wherein, It includes an array substrate and a counter substrate placed opposite each other, wherein the array substrate is the array substrate as described in any one of claims 1 to 25.

27. The display panel of claim 26, wherein, The array substrate includes multiple detection lines located in the non-display area, and multiple transistor groups electrically connected to at least a portion of the detection lines; The opposing substrate includes a black matrix, and at least a portion of the orthogonal projections of the transistor array onto the substrate do not overlap with the orthogonal projections of the black matrix onto the substrate.

28. The display panel as claimed in claim 27, wherein, The opposing substrate further includes a color resist layer located on the side of the black matrix facing the array substrate, the color resist layer including multiple color resists of different colors, the multiple color resists covering at least a portion of the transistor group.

29. The display panel as claimed in claim 26, wherein, The array substrate includes multiple detection lines located in the non-display area, and multiple transistor groups electrically connected to at least a portion of the detection lines; The opposing substrate includes a black matrix, and the orthogonal projections of the multiple detection lines and the multiple transistor groups on the substrate are all located within the orthogonal projection of the black matrix on the substrate.

30. A display device, wherein, It includes a display panel as described in any one of claims 26 to 29, and a backlight module located on the light-incident side of the display panel.

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