Verification of correctness of computer vision during semiconductor inspection

Abstract

An image of the workpiece is propagated forward through a graph of the deep neural network model or a directed acyclic graph of the deep neural network model. The output is then recorded as an array. A self-test input buffer (X) and an expected output buffer (Y) are determined. Next, an actual output (Y ') is predicted using the input, and the shapes and floating point values of the expected output buffer (Y) and the actual output (Y') are compared using a tolerance [epsilon].

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to provisional patent application No. 63 / 607,109, filed and assigned on December 7, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor inspection. Background Technology

[0004] The evolution of the semiconductor manufacturing industry places higher demands on yield management and, specifically, metrology and inspection systems. Critical dimensions continue to shrink, and the industry needs to reduce the time required to achieve high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving it determines a semiconductor manufacturer's return on investment.

[0005] Manufacturing semiconductor devices, such as logic and memory devices, typically involves using numerous manufacturing processes to process workpieces, such as semiconductor wafers, to form various features and multiple layers of the semiconductor device. For example, photolithography is a semiconductor manufacturing process involving transferring a pattern from a photomask to a photoresist disposed on a semiconductor wafer. Further examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. The arrangement of multiple semiconductor devices manufactured on a single semiconductor wafer can be separated into individual semiconductor devices.

[0006] Inspection processes are used at various stages of semiconductor manufacturing to detect defects on wafers, thereby promoting higher yields and, consequently, higher profits in the manufacturing process. Inspection has always been a crucial part of manufacturing semiconductor devices such as integrated circuits (ICs). However, as the size of semiconductor devices shrinks, inspection becomes even more critical for the successful manufacture of acceptable semiconductor devices because even small defects can lead to device failure. For example, as the size of semiconductor devices decreases, the detection of defects in smaller sizes has become necessary because even relatively small defects can introduce undesirable aberrations in semiconductor devices.

[0007] However, with tighter design rules, semiconductor manufacturing processes can operate closer to the performance limits of the process. Furthermore, with tighter design rules, even smaller defects can affect the electrical parameters of the device, driving more sensitive inspection. As design rules tighten, the population of potential yield-related defects detected by inspection increases significantly, as does the population of nuisance defects detected by inspection. Therefore, more defects can be detected on the workpiece, and corrective processes to eliminate all defects can be difficult and expensive. Determining which defects actually affect the electrical parameters and yield of the device allows process control methods to focus on those defects while largely ignoring others. Moreover, under tighter design rules, process-induced failures tend to be systematic in some cases. That is, process-induced failures tend to occur under predetermined design patterns that are typically repeated many times within the design. Eliminating spatially systematic, electrically related defects can impact yield.

[0008] Deep neural networks (DNNs) can be used to identify and classify defects in images generated during semiconductor inspection, but DNNs have limitations. Test set predictions are performed after the DNN's training time. The combined graph or model is then fed to an inference engine (e.g., Tensorflow, PyTorch, TensorRT, etc.). This process has limitations in input processing before prediction. For example, pixel values ​​are typically divided by 255. When a DNN is fed pixel values ​​with image channels, pixel values ​​are typically divided by 255 to transform values ​​from 0..255 to 0..1, which is more common in scientific computing. The mismatch between training time and inference time can adversely affect subsequent inspection results using DNNs. Therefore, improved systems and techniques are needed. Summary of the Invention

[0009] A system is provided in a first embodiment. The system includes: a light source that generates a light beam; a stage configured to hold a workpiece (e.g., a semiconductor wafer) in the path of the light beam; a detector that receives the light beam reflected from the workpiece; and a processor that communicates electronically with the detector. The processor (e.g., a GPU or CPU) is configured to: receive an image of the workpiece based on data from the detector; forward propagate the image through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model; record the output as an array; determine a self-test input buffer (X) and a expected output buffer (Y); predict the actual output (Y') using the input; and compare the shape and floating-point value of the expected output buffer (Y) with the actual output (Y') using a tolerance ε. An electronic data storage unit communicates electronically with the processor. The deep neural network model or the directed acyclic graph of the deep neural network model is stored on the electronic data storage unit.

[0010] The example uses a directed acyclic graph from a deep neural network model. The output may include the output and input of each node.

[0011] The example uses a directed acyclic graph based on a deep neural network model. The record contains the output and input of each node in the array.

[0012] The processor may be further configured to transmit a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') are less than the tolerance ε.

[0013] A second embodiment provides a method. The method includes receiving an image of a workpiece (e.g., a semiconductor wafer) at a processor (e.g., a CPU or GPU). Using the processor, the image is forward-propagated through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model. Using the processor, the output is recorded as an array. Using the processor, a self-test input buffer (X) and a desired output buffer (Y) are determined. Using the processor, an actual output (Y') is predicted using the input. Using the processor, the shape and floating-point value of the desired output buffer (Y) are compared with the actual output (Y') using a tolerance ε.

[0014] The example uses a directed acyclic graph from a deep neural network model. The output may include the output and input of each node.

[0015] The example uses a directed acyclic graph based on a deep neural network model. The record contains the output and input of each node in the array.

[0016] The method may include transmitting a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') are less than the tolerance ε.

[0017] In a third embodiment, a non-transitory computer-readable storage medium comprising one or more programs is provided. The one or more programs can perform the following steps on one or more computing devices: receiving an image of a workpiece (e.g., a semiconductor wafer); forward propagating the image through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model; recording the output as an array; determining a self-test input buffer (X) and a desired output buffer (Y); predicting the actual output (Y') using the input; and comparing the shape and floating-point value of the desired output buffer (Y) with the actual output (Y') using a tolerance ε.

[0018] The example uses a directed acyclic graph from a deep neural network model. The output may include the output and input of each node.

[0019] The example uses a directed acyclic graph based on a deep neural network model. The record contains the output and input of each node in the array.

[0020] The step may include transmitting a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') are less than the tolerance ε. Attached Figure Description

[0021] For a fuller understanding of the nature and objectives of this disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0022] Figure 1 This is a flowchart illustrating an embodiment of the method according to the present disclosure;

[0023] Figure 2 It is a diagram of system operation according to this disclosure;

[0024] Figure 3 This is an example of using a user-defined function preprocessor;

[0025] Figure 4 This is a diagram illustrating a multiple-input multiple-output (MIMO) model that accepts multiple named tensors and outputs multiple named tensors; and

[0026] Figure 5 This is a block diagram demonstrating a demonstrative testing system. Detailed Implementation

[0027] While the claimed subject matter will be described with reference to certain embodiments, other embodiments (including those that do not provide all the benefits and features set forth herein) are also within the scope of this disclosure. Various structural, logical, process, and electronic changes may be made without departing from the scope of this disclosure. Therefore, the scope of this disclosure is defined only with reference to the appended claims.

[0028] In the embodiments disclosed herein, a model or a directed acrylic graph (DAG) of a model can be used. A DAG is a directed graph without cycles. A graph is a data structure with vertices and envelopes. Each vertex has an associated edge that connects it to every other vertex. Vertices and edges in a DAG are configured such that each edge points from one vertex to another, such that following the direction will never form a closed loop. During the graph saving phase, an instance of the workpiece is selected as an input image and the image is forward-propagated through the graph.

[0029] In the case of a single DNN, an output tensor containing the number of executions from the DNN is recorded; in the case of a DAG of the DNN, the output and input of each node are recorded. The inputs and outputs are stored as arrays. During the inference phase (e.g., when using C++ libraries such as Tensorflow, PyTorch, TensorRT, etc.), the model is loaded and the self-test input buffer (X) and expected output buffer (Y) are read. The model prediction is performed with the inputs, and the actual output (Y') is recorded. Shapes and floating-point values ​​are compared using a tolerance ε (e.g., 0.0001), and binary results can be reported. If all shapes match and all differences between Y and Y' are below the allowed ε, then success or failure is determined. In the case of a multi-DNN graph (e.g., a set of five DNNs with majority voting), the self-test process compares the inputs of each child node with the predicted outputs and the overall output of the combined model. This method ensures that, given the stored input data "X" and the recorded output "Y", the two prediction systems will still produce the same expected output value. This avoids errors during defect detection of semiconductor wafers, which can have adverse consequences during semiconductor manufacturing. The embodiments disclosed herein can be implemented automatically, thus avoiding the error-prone manual or semi-manual techniques previously used.

[0030] If, due to program errors or omissions, the DNN is fed incorrect input during inference (e.g., values ​​between 0..1 instead of 0..255), the results can be adversely affected. The DNN will output incorrect values, which can lead to incorrect decisions about the tool. In this example, this incorrect decision could involve the DNN expecting to classify an image into two output categories: defective or non-defective. When the input does not perfectly match the DNN's expectations, the DNN's output probabilities will be incorrect; therefore, a defective wafer might be classified as non-defective, or vice versa. This is a problem for semiconductor manufacturers. Previously, when using Python and Tensorflow packages, and also when using C++ and the Tensorflow C++ library alone, users would manually verify that the same pre-trained neural network predicted the same results.

[0031] Figure 1 This is the flowchart for method 100. Figure 2 It is a diagram of the system operation. Figure 2 Implementations may use processors such as GPUs, CPUs, Tensor Processing Units (TPUs), or another processor capable of performing interventions on the DNN. X, Y, and Y' are arrays supporting multiple inputs and multiple outputs. The model can accept any number of input tensors and output a set of prediction tensors. Therefore, Figure 2 X, Y, and Y'' in the tensor can be named dictionaries for the predicted output tensor.

[0032] exist Figure 2In step 101, an image of the workpiece can be received at the processor. For example, the workpiece could be a semiconductor wafer or a portion of a semiconductor wafer (e.g., a bare die or device). In step 102, the image is forward-propagated through a graph of the DNN model or a direct algebra (DAG) of the DNN model. In step 103, the output is recorded as an array. When the image is read from a file on disk or fed from a network port, it is saved as a long array of numbers. For example, a wafer image with 50 rows and 40 columns of pixels will be saved row by row as an array of 2000 (50*40) floating-point 32 numbers. First, the 40 numbers in row 1 are saved. Then, the next 40 numbers in row 2 are saved. This process continues until the last 40 numbers in row 50. When this array is ready, it is saved along with the DNN binary file. The recorded X array, Y array, and DNN structure and weights can be appended to a single binary file.

[0033] In step 104, determine the self-test input buffer (X) and the expected output buffer (Y). X is a list of arrays. Each array has a list of numbers and a data type. For example, this could be an image with 50 rows and 40 columns and a data type of float32 (e.g., 32-bit floating-point). Y is a list of outputs from the arrays of the DNN. Y is saved in the same way as X. For example, a DNN with two inputs and three outputs will be saved as five files (e.g., [input1.float32.bin, input2.int64.bin] and for the outputs [output1.float32.bin, output2.int16.bin, output3.float64.bin]).

[0034] Next, at step 105, the actual output (Y') is predicted using the input. This prediction may involve executing a DNN inference function in a programming language (e.g., Python, C++). Therefore, Y' is a list of numerical arrays returned from function calls to the DNN model loaded in memory. The input may be the same as described in other steps, such as step 104.

[0035] At step 106, the shape and floating-point value of the expected output buffer (Y) are compared with the actual output (Y') using a tolerance ε, which is a threshold used to determine equality or closeness. If the shape match and difference between the expected output buffer (Y) and the actual output (Y') are below the tolerance ε, a failure message can be transmitted. The comparison process can use two arrays of values ​​with the same data type (e.g., float32 or int64) and the same length (e.g., 2000 numbers). These two arrays can be compared value-by-value using a tolerance "tol" stored for each DNN model. The process is illustrated in the examples below.

[0036] For each v1, v2 from (Y,Y'):

[0037] If (abs(v1-v2)>tol):

[0038] Returns error_no_match

[0039] For arrays of integer types (int8, int16, int32, int64), we use exact comparison for comparison:

[0040] For each v1, v2 from (Y,Y'):

[0041] If (v1 != v2):

[0042] Returns error_no_match

[0043] When using a DAG of a DNN model, the output includes the output and input of each node. The record contains the output and input of each node in the array.

[0044] Figure 3 This is an example of using a user-defined function preprocessor. Figure 3 This section depicts example code in the Python programming language using the NumPy library. The function depicted on the upper left accepts a list or dictionary (X) as input and returns the processed input. For example, the function could test whether image pixel values ​​are between 0..255, and if so, scale them to between 0..1 to match the expectations of a DNN model. This function can be executed by the inference engine before the DNN model is executed.

[0045] A NumPy-compatible procedure can be saved in the model for input preprocessing. This Python computer program takes a dictionary X and a piece of code in a Python-like language as input. This optional procedure is saved along with other binary files, such as X, Y, the DNN model, and optional Python functions. The final model can save all these binary files in an encapsulated package, such as a zip file. In this program, the function takes a three-channel RGB color image and performs the following transformation on each pixel x (small X): x = (x - mean) / std. This process normalizes the image. Other functions can perform different tests and normalization processes. This function can be used as a gate before feeding the input into the DNN model.

[0046] During C++ inference, if this code exists, it can be just-in-time (JIT) compiled into optimized C++ code based on the NumPy C library. This implementation can be applied to deterministic models rather than random generator neural networks. When cross-predicting from Python to C++, this implementation ensures accurate input and output, and vice versa. Libraries such as Tensorflow, PyTorch, and others have different versions and different access points (APIs). Training a DNN in Python and then performing inference from C++ implies that the Tensorflow library is a perfect match from Python to C++, but this does not always happen. Figure 3 The implementation ensures that the same input will be fed into the model and the same output will be predicted by the DNN model.

[0047] Figure 4 This demonstrates a model that accepts multiple named tensors and outputs multiple named tensors in a MIMO manner. Figure 4 This describes an exemplary DNN model that accepts X as three distinct inputs: a color RGB image, a numerical matrix, and a list of trend values. The DNN model can use X as input to perform inference and return a list of probabilities.

[0048] DNNs (e.g., convolutional neural networks (CNNs), vision transformer networks (VITs), residual networks (ResNets), or autoencoders (UNETs)) can be executed by a processor. DNNs may have one of the configurations further described herein. Deep learning, rooted in neural network technology, is a probabilistic graphical model with many layers of neurons, often referred to as a deep architecture. Deep learning techniques process information such as images, text, and speech in a hierarchical manner. When using deep learning in this disclosure, the embodiments disclosed herein can be performed automatically.

[0049] Generally speaking, deep learning (also known as deep structured learning, hierarchical learning, or deep machine learning) is a branch of machine learning based on a set of algorithms that attempt to model higher-order abstractions in data. In a simple case, there can be two sets of neurons: neurons that receive input signals and neurons that send output signals. When an input layer receives input, it passes a modified version of the input to the next layer. In deep networks, there are many layers between input and output, allowing algorithms to use multiple processing layers consisting of multiple linear and nonlinear transformations.

[0050] Deep learning is part of a broader family of machine learning methods that learn representations based on data. Observations (e.g., features to be extracted for reference) can be represented in many ways (e.g., a vector of intensity values ​​per pixel) or in more abstract ways (e.g., a set of edges, a region of a specific shape, etc.). Some representations are superior to others in that they simplify the learning task (e.g., face recognition or facial expression recognition). Deep learning provides efficient algorithms for unsupervised or semi-supervised feature learning and hierarchical feature extraction.

[0051] Research in this field attempts to produce better representations and create models to learn these representations from large-scale data. Some representations are inspired by advances in neuroscience and are loosely based on the interpretation of information processing and communication patterns in the nervous system, such as neural codewriting that attempts to define the relationship between various stimuli and the responses of associated neurons in the brain.

[0052] Depending on the probability specification and network architecture, there are many variants of neural networks with deep architectures, including, but not limited to, Deep Belief Networks (DBNs), Restricted Boltzmann Machines (RBMs), and autoencoders. Another type of deep neural network (CNN) can be used for feature analysis. The practical implementation can vary depending on the size of the input image, the number of features to be analyzed, and the nature of the problem. In addition to the neural networks disclosed herein, other layers can also be included in the deep learning module.

[0053] In a further embodiment, the DNN may have a set of weights that model the world based on data fed to train the DNN. Neural networks can be broadly defined as computational methods based on relatively large assemblies of neural units, loosely modeling the way the biological brain solves problems using relatively large clusters of biological neurons connected by axons. Each neural unit is connected to many other neural units, and the links can strengthen or inhibit their influence on the activation state of the connected neural units. These systems are self-learning and trained rather than explicitly programmed, and perform well in domains where solutions or feature detection are difficult to express in traditional computer programs.

[0054] Neural networks typically consist of multiple layers, with signal paths traversing from front to back. The goal of neural networks is to solve problems in the same way as the human brain, but many neural networks are far more abstract. Contemporary neural network projects often operate using thousands to millions of neural units and millions of connections. Neural networks can have any suitable architecture and / or configuration known in their field.

[0055] Generally, the DNN described in this paper is a trained DNN. For example, the DNN may have been previously trained using one or more other systems and / or methods. The DNN has been generated and trained, and then the functionality of the module (as described herein) is determined, which may then be used to perform one or more additional functions of the deep learning module.

[0056] As stated above, although CNN is used herein to illustrate the architecture of DNN, this disclosure is not limited to CNN. Other variations of deep learning architectures may be used in embodiments.

[0057] exist Figure 5 An embodiment of system 200 is shown. System 200 includes an optical-based subsystem 201. Generally, the optical-based subsystem 201 is configured to generate an optical-based output for workpiece 202 by directing light to (or scanning light across) workpiece 202 and detecting the light from workpiece 202. In one embodiment, workpiece 202 includes a wafer. The wafer may include any wafer known in the art. In another embodiment, workpiece 202 includes a photomask. The photomask may include any photomask known in the art.

[0058] exist Figure 5 In an embodiment of system 200 shown, the optical-based subsystem 201 includes an illumination subsystem configured to direct light to workpiece 202. The illumination subsystem includes at least one light source. For example, such as... Figure 5 As shown, the lighting subsystem includes a light source 203. In one embodiment, the lighting subsystem is configured to direct light to the workpiece 202 at one or more incident angles, said one or more incident angles may include one or more tilt angles and / or one or more normal angles. For example, as... Figure 5 As shown, light from light source 203 is guided at an angle of incidence through optical element 204 and then through lens 205 to workpiece 202. The angle of incidence can include any suitable angle of incidence, which can vary depending on, for example, the characteristics of workpiece 202.

[0059] The optical-based subsystem 201 can be configured to guide light to the workpiece 202 at different incident angles at different times. For example, the optical-based subsystem 201 can be configured to change one or more characteristics of one or more elements of the illumination subsystem, such that the light can be directed at different angles than... Figure 5 The incident angle shown is guided to the workpiece 202. In one such example, the optical subsystem 201 can be configured to move the light source 203, optical element 204 and lens 205 such that light is guided to the workpiece 202 at different tilting incident angles or normal (or near-normal) incident angles.

[0060] In some examples, the optical-based subsystem 201 can be configured to direct light to the workpiece 202 at more than one incident angle at the same time. For example, the illumination subsystem may include more than one illumination channel, one of which may include, for example, Figure 5 The light source 203, optical element 204, and lens 205 are shown in the diagram. Another illumination channel (not shown) may contain similar elements (which may be configured differently or similarly) or may contain at least one light source and possibly one or more other components (such as those further described herein). If this light is directed to the workpiece at the same time as other light, one or more characteristics (e.g., wavelength, polarization, etc.) of the light directed to the workpiece 202 at different incident angles may differ, allowing the light originating from illuminating the workpiece 202 at different incident angles to be distinguished from each other at the detector.

[0061] In another example, the lighting subsystem may contain only one light source (e.g., Figure 5 The light source 203 shown in the diagram can be split into different optical paths (e.g., based on wavelength, polarization, etc.) by one or more optical elements (not shown) of the illumination subsystem. The light from each of these different optical paths can then be directed to the workpiece 202. Multiple illumination channels can be configured to direct light to the workpiece 202 at the same time or at different times (e.g., when different illumination channels are used to sequentially illuminate the workpiece). In another example, the same illumination channel can be configured to direct light with different characteristics to the workpiece 202 at different times. For example, in some examples, optical element 204 can be configured as a spectral filter and the properties of the spectral filter can be changed in various different ways (e.g., by changing the spectral filter) so that light of different wavelengths can be directed to the workpiece 202 at different times. The illumination subsystem can have any other suitable configuration known in the art for sequentially or simultaneously directing light with different or the same characteristics to the workpiece 202 at different or the same incident angles.

[0062] In one embodiment, light source 203 may comprise a broadband plasma (BBP) source. In this way, the light generated by light source 203 and directed to workpiece 202 may comprise broadband light. However, the light source may comprise any other suitable light source, such as a laser. The laser may comprise any suitable laser known in the art and may be configured to generate light of any suitable wavelength or wavelengths known in the art. Additionally, the laser may be configured to generate monochromatic or near-monochromatic light. In this way, the laser may be a narrowband laser. Light source 203 may also comprise a multicolor light source that generates light of multiple discrete wavelengths or bands.

[0063] Light from optical element 204 can be focused onto workpiece 202 by lens 205. Although lens 205... Figure 5While shown as a single refractive optical element, it should be understood that in practice, lens 205 may comprise a combination of refractive and / or reflective optical elements that focus light from the optical element onto the workpiece. Figure 5 The illumination subsystem shown and described herein may include any other suitable optical elements (not shown). Examples of such optical elements include (but are not limited to) several polarizing components, several spectral filters, several spatial filters, several reflective optics, several apodizers, several beam splitters (e.g., beam splitter 213), several apertures, and analogues of any such suitable optical elements known in the art. Additionally, the optical-based subsystem 201 may be configured to change one or more of the elements of the illumination subsystem based on the type of illumination to be used to generate the optical-based output.

[0064] The optical-based subsystem 201 may also include a scanning subsystem configured to allow light to scan across the workpiece 202. For example, the optical-based subsystem 201 may include a stage 206 on which the workpiece 202 is positioned during optical-based output generation. The scanning subsystem may include any suitable mechanical and / or robotic assembly (which includes the stage 206) that can be configured to move the workpiece 202 such that light can scan across the workpiece 202. Alternatively, the optical-based subsystem 201 may be configured such that one or more optical elements of the optical-based subsystem 201 perform some form of scanning of the workpiece 202. The light can scan across the workpiece 202 in any suitable manner (e.g., in a serpentine or helical path).

[0065] The optical-based subsystem 201 further includes one or more detection channels. At least one of the detection channels includes a detector 212 configured to detect light from the workpiece 202 attributable to the illumination of the workpiece 202 by the subsystem and to generate an output in response to the detected light. For example, Figure 5 The optical-based subsystem 201 shown includes two detection channels: one channel is formed by a light collector 207, an element 208, and a detector 209, and the other channel is formed by a light collector 210, an element 211, and a detector 212. For example... Figure 5 As shown, two detection channels are configured to collect and detect light at different collection angles. In some examples, the two detection channels are configured to detect scattered light, and the detection channels are configured to detect light scattered from the workpiece 202 at different angles. However, one or more of the detection channels may be configured to detect another type of light (e.g., reflected light) from the workpiece 202.

[0066] like Figure 5The diagram further illustrates that two detection channels are positioned within the plane of the paper, and the illumination subsystem is also positioned within the plane of the paper. Therefore, in this embodiment, the two detection channels are positioned (e.g., centered) within the plane of incidence. However, one or more of the detection channels may be positioned outside the plane of incidence. For example, the detection channel formed by the light collector 210, element 211, and detector 212 may be configured to collect and detect light scattered from the plane of incidence. Therefore, this detection channel may generally be referred to as a "side" channel, and this side channel may be centered in a plane substantially perpendicular to the plane of incidence.

[0067] although Figure 5 An embodiment of an optically based subsystem 201 comprising two detection channels is shown, but the optically based subsystem 201 may comprise a different number of detection channels (e.g., only one detection channel or two or more detection channels). In one example, the detection channel formed by the light collector 210, element 211, and detector 212 may form a side channel as described above, and the optically based subsystem 201 may include an additional detection channel (not shown) formed as another side channel positioned on the opposite side of the incident plane. Thus, the optically based subsystem 201 may include a detection channel comprising a light collector 207, element 208, and detector 209 and centered in the incident plane and configured to collect and detect light scattered at an angle normal to or near normal to the surface of the workpiece 202. Therefore, this detection channel may generally be referred to as the “top” channel, and the optically based subsystem 201 may also include two or more side channels configured as described above. Therefore, the optical-based subsystem 201 may include at least three channels (i.e., a top channel and two side channels), and each of the at least three channels has its own light collector, each of the light collectors being configured to collect light at a scattering angle different from that of each of the other light collectors.

[0068] As further described above, each of the detection channels included in the optical-based subsystem 201 can be configured to detect scattered light. Therefore, Figure 5 The optical-based subsystem 201 shown herein can be configured for generating a dark field (DF) output from a workpiece 202. However, the optical-based subsystem 201 may also, or alternatively, include a detection channel configured for generating a bright field (BF) output from the workpiece 202. In other words, the optical-based subsystem 201 may include at least one detection channel configured to detect light reflected from the specular surface of the workpiece 202. Therefore, the optical-based subsystem 201 described herein can be configured for DF-only imaging, BF-only imaging, or both DF and BF imaging. Although each of the light collectors is... Figure 5 While shown as a single refractive optical element, it should be understood that each of the light collectors may contain one or more refractive optical blanks and / or one or more reflective optical elements.

[0069] One or more detection channels may contain any suitable detector known in the art. For example, the detector may include a photomultiplier tube (PMT), a charge-coupled device (CCD), a time-delay integration (TDI) camera, and any other suitable detector known in the art. The detector may also include non-imaging detectors or imaging detectors. In this way, if the detector is a non-imaging detector, each of the detectors may be configured to detect certain characteristics (e.g., intensity) of the scattered light but not to detect such characteristics that vary depending on the position within the imaging plane. Thus, the output generated by each of the detectors in each of the detection channels of the optical-based subsystem may be a signal or data rather than an image signal or image data. In such examples, a processor (e.g., processor 214) may be configured to generate an image of the workpiece 202 from the non-imaging output of the detector. However, in other examples, the detector may be configured as an imaging detector configured to generate an imaging signal or image data. Therefore, the optical-based subsystem may be configured to generate optical images or other optical-based outputs as described herein in several ways.

[0070] It should be noted that the information provided in this article... Figure 5 The following describes the configuration of an optically based subsystem 201 that may be included in or produce optically based outputs used through the system embodiments described herein. As is typically done when designing commercial output acquisition systems, the configuration of the optically based subsystem 201 described herein may be modified to optimize its performance. Additionally, the systems described herein can be implemented using existing systems (e.g., by adding the functionality described herein to an existing system). For some such systems, the methods described herein may be provided as optional functionality of the system (e.g., in addition to other system functionalities). Alternatively, the systems described herein may be designed as entirely new systems.

[0071] Processor 214 may be coupled to components of system 200 in any suitable manner (e.g., via one or more transmission media, which may include wired and / or wireless transmission media) such that processor 214 can receive output. Processor 214 may be configured to perform certain functions using said output. System 200 may receive instructions or other information from processor 214. Processor 214 and / or electronic data storage unit 215 may optionally communicate electronically with wafer inspection tools, wafer metrology tools, or wafer re-inspection tools (not described) to receive additional information or send instructions. For example, processor 214 and / or electronic data storage unit 215 may communicate electronically with a scanning electron microscope.

[0072] The processor 214, other systems, or other subsystems described herein may be part of a variety of systems, including personal computer systems, graphics computers, mainframe computer systems, workstations, network devices, Internet devices, or other devices. A subsystem or system may also include any suitable processor known in the art, such as a parallel processor. Additionally, a subsystem or system may include a platform with high-speed processing and software, either as a standalone or network-linked tool.

[0073] The processor 214 and electronic data storage unit 215 may be housed in or otherwise become part of the system 200 or another device. In examples, the processor 214 and electronic data storage unit 215 may be part of a separate control unit or in a centralized quality control unit. Multiple processors 214 or electronic data storage units 215 may be used.

[0074] In practice, processor 214 can be implemented by any combination of hardware, software, and firmware. Similarly, its functions as described herein can be executed by a single unit or divided among different components, each of which can be implemented by any combination of hardware, software, and firmware. Code or instructions for enabling processor 214 to perform various methods and functions can be stored in a readable storage medium (e.g., memory in electronic data storage unit 215 or other memory).

[0075] If system 200 includes more than one processor 214, then different subsystems can be coupled to each other, enabling the transmission of images, data, information, instructions, etc., between the subsystems. For example, a subsystem can be coupled to an additional subsystem via any suitable transmission medium, which may include any suitable wired and / or wireless transmission medium known in the art. Two or more such subsystems can also be effectively coupled via a shared computer-readable storage medium (not shown).

[0076] Processor 214 may be configured to perform certain functions using the output of system 200 or other outputs. For example, processor 214 may be configured to send output to electronic data storage unit 215 or another storage medium. Processor 214 may be configured according to any of the embodiments described herein. Processor 214 may also be configured to perform other functions or additional steps using the output of system 200 or using images or data from other sources.

[0077] Program instructions for implementing a method (such as the method described herein) may be transmitted or stored on a carrier medium. The carrier medium may include storage media, such as read-only memory, random access memory, magnetic disk or optical disk, non-volatile memory, solid-state memory, magnetic tape, and the like. The carrier medium may include transmission media, such as wires, cables, or wireless transmission links. For example, the various steps described throughout this disclosure may be performed by a single processor 214 or alternatively by multiple processors 214. Furthermore, different subsystems of system 200 may include one or more computing or logic systems. Therefore, the foregoing description should not be construed as a limitation of this disclosure but is merely illustrative.

[0078] In this example, processor 214 communicates with system 200. Processor 214 is configured to operate a system that uses tolerance ε to compare the shape and floating-point value of the expected output buffer (Y) with the actual output (Y'), as disclosed herein.

[0079] Further embodiments relate to a non-transitory computer-readable medium whose storage is executable on a controller to perform program instructions for a computer-implemented method of comparing the shape and floating-point value of an expected output buffer (Y) with that of the actual output (Y') using a tolerance ε, as disclosed herein. Specifically, as Figure 5 As shown herein, electronic data storage unit 215 or other storage media may contain a non-transitory computer-readable medium containing program instructions executable on processor 214. The computer-implemented method may include any of the methods described herein (including...). Figures 1 to 3 Any step of the method.

[0080] Program instructions can be implemented in any of a variety of ways, including procedural, component-based, and / or object-oriented technologies, as well as others. For example, program instructions may be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or other technologies or methods as needed.

[0081] Although disclosed using inspection systems and semiconductor wafers, other systems and workpieces may benefit from the embodiments disclosed herein. For example, re-inspection or metrology tools may use the embodiments disclosed herein. Other superimposed measurement tools may also use the embodiments disclosed herein. The system may use an electron beam or ion beam instead of a light beam. The workpiece may be a flat panel, printed circuit board, or other substrate instead of a semiconductor wafer.

[0082] Each of the steps of the method can be performed as described herein. The method may also include any other steps that can be performed by the processor and / or computer subsystem or system described herein. The steps can be performed by one or more computer systems, which can be configured according to any of the embodiments described herein. Additionally, the methods described above can be performed by any of the system embodiments described herein.

[0083] Although this disclosure has been described with respect to one or more specific embodiments, it should be understood that other embodiments of this disclosure may be made without departing from the scope of this disclosure. Therefore, this disclosure is to be considered limited only by the appended claims and their reasonable interpretation.

Claims

1. A system comprising: A light source that produces a beam of light; A stage configured to hold the workpiece in the path of the beam; A detector that receives the light beam reflected from the workpiece; A processor that communicates electronically with the detector, wherein the processor is configured to: Receive an image of the workpiece based on data from the detector; The image is forward propagated through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model; Record the output as an array; Determine the self-test input buffer (X) and the expected output buffer (Y); Predict the actual output (Y') from the input; and The expected output buffer (Y) and the actual output (Y') shape and floating-point value are compared using the tolerance ε; and An electronic data storage unit that communicates electronically with the processor, wherein the deep neural network model or a directed acyclic graph of the deep neural network model is stored on the electronic data storage unit.

2. The system of claim 1, wherein the directed acyclic graph uses a deep neural network model, and wherein the output comprises the output and input of each node.

3. The system of claim 1, wherein the directed acyclic graph uses a deep neural network model, and wherein the record includes the output and input of each node in the array.

4. The system of claim 1, wherein the processor is further configured to transmit a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') is less than the tolerance ε.

5. The system of claim 1, wherein the processor is a GPU.

6. The system of claim 1, wherein the processor is a CPU.

7. The system of claim 1, wherein the workpiece is a semiconductor wafer.

8. A method comprising: Receive the image of the workpiece at the processor; Using the processor, the image is forward propagated through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model. The processor is used to record the output as an array; The processor is used to determine the self-test input buffer (X) and the expected output buffer (Y); The processor is used to predict the actual output (Y') from the input; and The processor is used to compare the shape and floating-point value of the expected output buffer (Y) with the actual output (Y') using a tolerance ε.

9. The method of claim 8, wherein the directed acyclic graph uses a deep neural network model, and wherein the output comprises the output and input of each node.

10. The method of claim 8, wherein the directed acyclic graph uses a deep neural network model, and wherein the record includes the output and input of each node in the array.

11. The method of claim 8, further comprising transmitting a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') is less than the tolerance ε.

12. The method of claim 8, wherein the processor is a GPU.

13. The method of claim 8, wherein the processor is a CPU.

14. The method of claim 8, wherein the workpiece is a semiconductor wafer.

15. A non-transitory computer-readable storage medium comprising one or more programs for performing the following steps on one or more computing devices: Receive images of the workpiece; The image is forward propagated through a graph of a deep neural network model or a directed acyclic graph of a deep neural network model; Record the output as an array; Determine the self-test input buffer (X) and the expected output buffer (Y); Predict the actual output (Y') from the input; and The expected output buffer (Y) and the actual output (Y') are compared using the tolerance ε.

16. The non-transitory computer-readable storage medium of claim 15, wherein the directed acyclic graph uses a deep neural network model, and wherein the output includes the output and input of each node.

17. The non-transitory computer-readable storage medium of claim 15, wherein the directed acyclic graph uses a deep neural network model, and wherein the record comprises the output and input of each node in the array.

18. The non-transitory computer-readable storage medium of claim 15, wherein the step further comprises transmitting a failure message if the shape match and difference between the expected output buffer (Y) and the actual output (Y') is less than the tolerance ε.

19. The non-transitory computer-readable storage medium of claim 15, wherein the workpiece is a semiconductor wafer.

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