3D heterogeneous integrated power electronic building block

Abstract

A power converter includes: a substrate; a control circuit disposed on the substrate; and a first circuit stack disposed on the substrate and coupled to the control circuit. The first circuit stack is in a stacked configuration. The first circuit stack comprises a first switch layer; a first interposer electrically coupled to the first switching layer; a second interposer electrically coupled to the first interposer; a first gate driver layer disposed between the first interposer and the second interposer and electrically coupled to the first interposer and the second interposer; and a first inductor layer electrically coupled to the first gate driver layer.

Description

priority

[0001] This application claims priority to provisional application 63 / 515,697, filed July 26, 2023, entitled “3D Heterogeneously Integrated Power Electronic Building Blocks,” pursuant to Section 119(e) of 35 USC, the entire contents of which are incorporated herein by reference.

[0002] Government Contract This invention was carried out with government support under Contract No. 140D0423C0038 issued by the Ministry of the Interior. The government has specific rights to this invention. Technical Field

[0003] This disclosure generally relates to the field of power converters. Summary of the Invention

[0004] In one aspect, this disclosure relates to a power converter comprising: a substrate; control circuitry disposed on the substrate; and a first circuit stack disposed on the substrate and coupled to the control circuitry. The first circuit stack is arranged in a stacked configuration. The first circuit stack includes a first switching layer; a first interposer layer electrically coupled to the first switching layer; a second interposer layer electrically coupled to the first interposer layer; a first gate driver layer disposed between the first interposer layer and the second interposer layer and electrically coupled to both the first interposer layer and the second interposer layer; and a first inductor layer electrically coupled to the first gate driver layer.

[0005] Although this disclosure relates to different aspects and embodiments, it should be understood that the different aspects and embodiments disclosed herein may be integrated, combined, or used together as a combined system, or in part as individual components, devices, and systems. Therefore, each embodiment disclosed herein may be incorporated into each of the aspects to varying degrees for a given implementation. Furthermore, the gallium nitride power devices, silicon MEMS capacitors, silicon MEMS inductor components, and methods for generating vertically stacked chips capable of handling power and converting from one voltage level to another disclosed herein can be used without limitation.

[0006] This article describes these and other characteristics of the applicant's teaching. Attached Figure Description

[0007] Unless otherwise specified, the accompanying drawings illustrate aspects of the innovations described herein. Referring to the figures in which the same numerals refer to the same parts in several views and throughout this specification, several embodiments of the principles currently disclosed are illustrated by way of example rather than limitation. The drawings are not intended to be to scale. A more complete understanding of this disclosure can be achieved by referring to the accompanying drawings, in which:

[0008] Figure 1 It is an existing power converter.

[0009] Figure 2 This describes the method for using a daisy-chain power converter.

[0010] Figure 3 It is the most advanced buck converter.

[0011] Figure 4A yes Figure 3 The voltage and current curves during the switching period of the buck converter.

[0012] Figure 4B yes Figure 3 A graph showing the power loss during switching of a buck converter.

[0013] Figure 5 It is a state-of-the-art power converter with horizontal power flow to the load it drives.

[0014] Figure 6 It is an integrated 3D HI-PEBB voltage regulator according to aspects of this disclosure.

[0015] Figure 7 This is a plan view of a vertically stacked voltage regulator consisting of four building blocks according to aspects of this disclosure, wherein each building block consists of vertically stacked chips.

[0016] Figure 8 The present disclosure describes a vertically stacked voltage regulator consisting of two building blocks, each building block consisting of vertically stacked chips.

[0017] Figure 9 The diagram illustrates a cross-sectional view of a vertically stacked voltage regulator according to aspects of this disclosure, which shows two main building blocks or power converter chips.

[0018] Figure 10 This describes the interconnects, through-holes, and gaskets according to aspects of this disclosure. Figure 9 Detailed view.

[0019] Figure 11 It is based on Figure 9 and Figure 8 An exploded 3D view of a voltage regulator consisting of two building blocks.

[0020] Figure 12A This is a description of the switch based on aspects of this disclosure.

[0021] Figure 12B This is a description of the switch based on aspects of this disclosure.

[0022] Figure 13 It is a circuit stack consisting of three building blocks according to aspects of this disclosure.

[0023] Figure 14 It is composed of four building blocks according to aspects of this disclosure. Figure 7 The circuit stacking.

[0024] Figure 15 This is a cross-sectional view of a silicon MEMS inductor according to aspects of this disclosure.

[0025] Figure 16 A plan view of a 3D silicon MEMS inductor according to an aspect of this disclosure is shown.

[0026] Figure 17 This describes a 3D silicon MEMS trench capacitor based on aspects of this disclosure.

[0027] Figure 18 This describes a 3D silicon MEMS trench capacitor based on aspects of this disclosure.

[0028] Figure 19 This describes the load efficiency and power density of a general-purpose power converter compared to the power converter described herein, based on aspects of this disclosure.

[0029] Figure 20 This describes the high-side switch (e.g., in a power converter (referring to a 4-cell SC-buck converter) having the switching frequency of the present disclosure. Figure 14 Compared to the on-time of the high-side switch in a general-purpose buck converter, the high-side switch (e.g., in a buck converter) has a switching frequency that allows it to operate at a higher frequency. Figure 3 The curve of the turn-on time of S1 in the figure.

[0030] Figure 21A This describes the voltage and current of the high-side switch during the switching of the power converter of this disclosure.

[0031] Figure 21B This describes the switching losses during the switching of the power converter disclosed herein.

[0032] Figure 22A This describes the assembly of a well-known power converter.

[0033] Figure 22B This section describes a comparison of the assembly of the power converter of this disclosure according to aspects of this disclosure. Detailed Implementation

[0034] This disclosure relates to power converters. Existing power converters, with their 2D construction and limited integration, result in trade-offs between switching frequency, efficiency, power density, and transient response. Furthermore, existing on-chip integration is limited by silicon and lacks effective wide-bandgap devices and passive components (inductors and capacitors). The lack of modularity and voltage or current scaling in existing power converters prevents the use of general-purpose building blocks (e.g., circuits or chips) that can be arranged to meet different input and output voltages and / or output currents.

[0035] This disclosure generally relates to three-dimensional chip stacking in circuits that achieves high power density (>1000 W / in) with high efficiency (>90%). 3 This allows for proximity to the load to achieve excellent transient response (>100 A / µs). The chip stacking in the disclosed circuit also achieves voltage scaling through an appropriate combination of cell-based stacks of building blocks arranged according to a scalable circuit topology. Voltage scaling allows for a wide range of inputs (e.g., 48 V / 28 V / 12 V) and outputs (e.g., 0.5 V to 5 V). Current scaling is achieved by tilting the different cells formed by the chip stack in the circuit. The power path impedance between the output terminals and the load is reduced, resulting in excellent transient response (>100 A / µs) and reduced radiated and electrical noise.

[0036] Please refer to the diagram below. Figure 1 This is the existing power converter 100. The existing power converter 100, with its 2D construction and limited integration, presents a trade-off between switching frequency, efficiency, power density, and transient response. In the existing power converter 100, on-chip integration is limited only to silicon and there is no integration of wide bandgap (WBG) devices (e.g., gallium nitride (GaN) and passive components). Furthermore, the existing power converter 100 lacks modularity and voltage / current scaling.

[0037] Figure 2 This describes a daisy chain 110 of power converters. The daisy chain 110 of converters results in lower system efficiency because the overall efficiency decreases with each converter in the chain. The daisy chain 110 includes a first converter 112, a second converter 114, and a third converter 116 for up to three (or more) stages of power conversion, as shown in the daisy chain 110.

[0038] In a daisy chain, it is not possible to directly convert from a higher input voltage to a lower voltage, as this would require a state-of-the-art buck converter. Figure 3 The extremely short on-time of the high-side switch (S1) shown in the diagram. As shown, converting 28 or 48 volts to 0.5 to 1.1 volts requires 3 stages of conversion. The switching on-time of a state-of-the-art buck converter is equal to the output voltage divided by the input voltage multiplied by the switching frequency. Unable to accurately control the short on-time, it will switch frequencies (f). sw The limits are set to low values. However, higher switching frequencies are needed to reduce the size of passive components and improve transient response for higher control bandwidth. Furthermore, circuitry with 2D integration and smaller size further restricts proximity to the load to meet transient response requirements and reduce the effects of parasitic and interconnect losses. These factors negatively impact dynamic voltage scaling that follows rapid changes in load activity and envelope tracking of the power amplifier, both of which improve system efficiency.

[0039] Figure 3 This is the state-of-the-art buck converter 120. The buck converter 120 is a DC-DC converter that steps down the voltage (while simultaneously stepping up the current) from its input (supply) to its output (load). It is a type of switching mode power supply. The buck converter converts a high voltage to a low voltage with a higher current.

[0040] Figure 4A yes Figure 3 The voltage and current curves of the buck converter 120 are shown in Figure 130. The switch S1122 in the buck converter 120 experiences high input voltage and current during switching, resulting in high switching losses.

[0041] Figure 4B yes Figure 3 The power loss curve 132 of the buck converter 120 illustrates the switching losses of switch S1 during turn-on and turn-off events, as well as the conduction losses during the turn-on cycle. During turn-on and turn-off events, the crossover 131 between the input voltage and current is directly related to the power loss.

[0042] Figure 5 This is power converter 140. Power converter 140 is used to generate lower drive voltages, typically from 0.5 V to 1.8 V, for the computing chip at higher currents. The input voltage is typically higher than the drive voltage. Direct conversion from higher input voltages (28 V or 48 V) to reduce distributed losses requires multi-stage conversion (e.g., from 48 V to 5 V, then to 1 V or lower). On-chip system components draw different currents and voltages at different locations or nodes. This creates a need for scalability of general-purpose building blocks, which is not feasible for state-of-the-art power converters. Furthermore, the horizontal power flow of state-of-the-art power converters generates induced noise and limits transient response. Therefore, many high-frequency capacitors are required near the load.

[0043] Inductive noise in electrical connections affects power quality and requires additional capacitors. This necessitates modular and integrated voltage regulators with low resistive losses and parasitic inductance. State-of-the-art DC-DC power converters are located away from the load. This results in long and lossy paths for horizontal current generation. This limits voltage regulation and transient response (measured in A / μs).

[0044] Figure 6 An integrated 3D HI-PEBB voltage regulator 200 is disclosed according to an aspect of this disclosure. The integrated 3D HI-PEBB voltage regulator (e.g., a power converter) 200 exhibits higher efficiency and reduced passive component size due to 3D integration, lower losses, higher effective frequency at the load terminals, and direct conversion from higher input voltages (e.g., direct conversion from a 28 V or 48 V input to a lower voltage, such as <1 V). In one aspect, vertical current provides precise voltage regulation and higher transient response measured in amperes / microseconds. In another aspect, voltage and current scaling provides direct conversion.

[0045] Figure 7 This is a vertically stacked power converter 300 according to aspects of the present disclosure. The power converter 300 includes a substrate 302 and control circuitry 304 disposed on the substrate 302. The power converter 300 also includes a first circuit stack 308 (e.g., building block BB 2) and a plurality of second circuit stacks 306a, 306b, 306c (e.g., building blocks BB 1a, 1b, and 1c). The control circuitry 304 is coupled to the first circuit stack 308 and the plurality of second circuit stacks 306a, 306b, 306c. The vertically stacked power converter achieves low impedance to load, extended duty cycle, higher efficiency, and voltage and current scaling. Figure 7 according to Figure 14 The circuit layout in the diagram. The vertically stacked voltage regulator measures 12 mm × 6 mm, while... Figure 1 The voltage regulator shown is 36 mm × 38 mm.

[0046] Figure 8 This describes two circuit stacks of a vertically stacked voltage regulator according to aspects of this disclosure.

[0047] The first circuit stack 308 includes an inductor L1 and multiple switches Q2 and Q3 coupled to a gate driver 305. The gate driver is controlled by a control circuit 304. A diode D2 may be coupled in parallel with switch Q4.

[0048] The second circuit stack 306 includes capacitor C. BAn inductor L2 and multiple switches Q1 and Q3 are included. Switches Q1 and Q3 are controlled by a gate driver 303 controlled by a control circuit 304. The control circuit 304 controls both a first circuit stack 308 and a second circuit stack 306. The second circuit stack 306 receives an input voltage 310. The input voltage (Vin) is regulated into an output voltage (Vout) by the first circuit stack 308 and the second circuit stack 306. The control circuit 304 controls the output voltage and switching time of switches Q1, Q2, Q3, and Q4. A diode D1 may be coupled in parallel with switch Q3.

[0049] In one aspect, switches Q1, Q2, Q3, and Q4 are integrated GaN switches, where all the required switches and diodes within a cell are integrated on the same chip (e.g., ...). Figures 12A to 12B (As shown in the image). GaN switches have 20 to 100 times higher Ro compared to silicon. on Q g This reduces switching, conduction, and gate drive losses. Generally, silicon pulse width modulators and gate drivers, Si-MEMS inductor and capacitor chips, and high-side and low-side GaN switches with diodes are assembled vertically, and according to... Figure 8 (2-cell unit) Figure 13 (3-cell unit) or Figure 14 (4-cell) circuit interconnection.

[0050] Figure 9 The illustration shows a cross-sectional view of a power converter 300 according to an aspect of this disclosure. The power converter 300 includes a substrate 302 and control circuitry 304 disposed on the substrate 302. A first circuit stack 308 is disposed on the substrate 302 and electrically coupled to the control circuitry 304. The first circuit stack 308 is arranged in a stacked configuration. The first circuit stack 308 includes a first switching layer 312 and a first interposer layer 314 electrically coupled to the first switching layer 312. The first circuit stack 308 also includes a second interposer layer 316 electrically coupled to the first interposer layer 314. A first gate driver layer 318 is disposed between the first interposer layer 314 and the second interposer layer 316 and electrically coupled to both the first interposer layer 314 and the second interposer layer 316. A first inductor layer 320 is electrically coupled to an underlying chip layer—the second interposer layer 316, the first interposer layer 314, the first switching layer 312, and the first gate driver layer 318.

[0051] In one aspect, the power converter 300 includes a second circuit stack 306 disposed on a substrate 302 and electrically coupled to a control circuit 304. The second circuit stack 306 is stacked. The second circuit stack 306 includes a second switching layer 322 disposed on the substrate 302. A third interposer layer 324 is electrically coupled to the second switching layer 322. A fourth interposer layer 326 is electrically coupled to the third interposer layer 324. A second gate driver layer 328 is disposed between the third interposer layer 324 and the fourth interposer layer 326 and is electrically coupled to both the third interposer layer 324 and the fourth interposer layer 326. A capacitor layer 332 is disposed within a fifth interposer layer 330 and is electrically coupled to the fourth interposer layer 326. A second inductor layer 334 is electrically coupled to the underlying chip layers – the fifth interposer layer 330, the fourth interposer layer 326, the third interposer layer 324, the second switching layer 322, and the capacitor layer 332.

[0052] Intermediate layers 314, 316, 324, 326, and 330 define multiple through-silicon vias (TSVs) for electrical coupling. Figure 10 and 11 (As shown in the figure). In one aspect, the layers of the circuit stack 306, 308 are connected by interconnects between the layers. In one aspect, the interconnects include copper. In one aspect, the interconnects extend through an interposer and are disposed on the surface of the interposer.

[0053] In one aspect, the circuit stacks 306, 308 include a plurality of capacitor layers 332 located between the second gate driver layer 328 and the second inductor 334.

[0054] In one aspect, control circuitry 304 controls the timing of the first and second switching layers 312, 322. In another aspect, control circuitry 304 controls which of the first and second circuit stacks 308, 306 receives the input voltage and modulates the output voltage. The timing control of the switches controls the output voltage.

[0055] In one aspect, capacitor layer 332 includes a microelectromechanical system (MEMS) barrier capacitor.

[0056] In one aspect, inductors 320 and 334 include microelectromechanical systems (MEMS) power inductors.

[0057] In one aspect, the switching layers 312 and 322 include Figures 12A to 12B The gallium nitride power device is further explained in the text.

[0058] In one aspect, the power converter 300 further includes a plurality of second circuit stacks disposed on a substrate 302 and electrically coupled to a control circuit 304.

[0059] Vertically stacked circuits (e.g., a second circuit stack 306 and a first circuit stack 308) enable efficient and regulated power delivery at the point of load. Reduced power path impedance allows the circuitry to meet load transients and reduces radiated and electrical noise. Vertical circuit stacking enables current scaling: the blocks of an n-cell 3D HI-PEBB share the load current. Figure 8 , 13 Alternatively, 14 can be used to increase the number of cells in a vertical circuit stack to achieve voltage scaling. Additionally, vertical circuit stacking reduces parasitic and interconnect losses.

[0060] Figure 10 yes Figure 9 Detailed views are provided. Each interposer defines a plurality of through-silicon vias (TSVs). In one aspect, interconnects 342 are disposed in the TSVs and form fan-outs disposed on the interposers. In one aspect, interconnects 342 comprise copper and are disposed between the interposers. Between interconnects 342 is a bonding layer 344, which may be an Au-AuSn eutectic bond or an Au-Au thermocompression bond, or a Cu-Cu thermocompression bond or a Cu-Sn bond. In one aspect, the thickness of the bonding layer 344 is approximately 20 micrometers.

[0061] Electrical interconnect 342 features high current handling (approximately 10 A) and low interconnect resistance (< 1 mΩ). The GaN switch circuit layer defines a via with a second interconnect 340. In one aspect, the second interconnect 340 comprises gold. The high thermal conductivity of the substrate with the GaN chip at the bottom facilitates heat dissipation. In one aspect, the substrate 302 comprises silicon carbide (SiC).

[0062] Figure 11 This is an exploded three-dimensional view of a power converter chip according to an aspect of the present disclosure. Control circuitry 304 is disposed on substrate 302. Switching layers 312, 322 are electrically coupled to control circuitry 304. Each switching layer 312, 322 is coupled to a corresponding interposer layer 314, 324. Each circuit stack also includes inductor layers 320, 334 coupled to interposers 314, 324, 330. In one aspect, the circuit stack includes a capacitor layer 332 within interposer 330. Interposers 314, 324, 330 define vias 350. In one aspect, the circuit stack includes a filter capacitor layer 354. In one aspect, interposers 314, 324, 330 define corresponding vias 350 such that each interposer 314, 324, 330 defines vias at the same location for alignment in a stack configuration.

[0063] A standardized chip assembly process is achieved using a silicon interposer chip with through-silicon vias 350 and interconnects / pads, accommodating any chip of arbitrary size and pad placement. In one aspect, an in-circuit test pad 352 is provided within the interposer chip. In one aspect, the interposer comprises silicon. Materials used for bonding include Au-Au / Sn, Au-Au, Cu-Cu, and Cu-Cu / Sn. Possible chip sizes range from 3 mm × 3 mm chips to 10 mm × 10 mm chips.

[0064] Figure 12A and 12B This is a description of an integrated gallium nitride switch according to an aspect of this disclosure. In one aspect, the integrated gallium nitride switch is... Figures 7 to 11 The switching layer in the process. In one aspect, the switching layer includes gallium nitride (GaN) with integrated high-side and low-side switches and diodes. Table 1 illustrates the differences between GaN and Si used as switches and diodes.

[0065] GaN HEMT Switch

[0066]

[0067] SOA Si switch

[0068]

[0069] GaN nano-Schottky diode

[0070]

[0071] SOA GaN Schottky diode

[0072]

[0073] Table 1

[0074] Figure 13 The circuit stack 400 is based on an aspect of this disclosure. The circuit stack 400 includes three cells or layers: a first capacitor layer 402a, a second capacitor layer 402b, and an inductor layer 404. The maximum duty cycle of the high-side switch in each cell is 0.33. The duty cycle is selected based on the input and output voltages.

[0075] For example, inductor layer 404 may include a switch S5 coupled to inductor L1 and a switch S6 coupled in parallel with switch S5 and inductor L1. First capacitor layer 402a may include an input voltage Vin coupled in series with switch S1 and capacitor C1. Capacitor C1 is coupled in parallel with switch S3 and in parallel with inductor L3.

[0076] For example, the second capacitor layer 402b includes a switch S2 coupled in series with capacitor C2. Capacitor C2 is coupled in parallel with switch S4 and in parallel with inductor L3.

[0077] The first capacitor layer 402a, the second capacitor layer 402b, and the inductor layer 404 can be coupled in parallel. One end of the switch S5 of the inductor layer 404 is coupled between the switch S2 and the capacitor C2 of the second capacitor layer 402b. One end of the switch S2 of the capacitor layer 402b is coupled between the switch S1 and the capacitor C1 of the capacitor layer 402a. F It is coupled in parallel with inductors L1, L2, and L3. Capacitor C O With capacitor C F Parallel connection. Output voltage V O With capacitor C O in parallel.

[0078] The control circuit (not shown) controls the switching frequency of each of the switches. For example, the duty cycle used for switching can be equal to 3. (V O / V in ).

[0079] Figure 14 The circuit stack 500 is based on aspects of this disclosure. The circuit stack 500 includes four cells or layers: a first capacitor layer 502a, a second capacitor layer 502b, a third capacitor layer 502c, and an inductor layer 504. The maximum duty cycle of the high-side switch in each cell is 0.25. The duty cycle is selected based on the input and output voltages.

[0080] For example, inductor layer 504 may include a switch S5 coupled to inductor L1 and a switch S6 coupled in parallel with switch S5 and inductor L1. First capacitor layer 502a may include an input voltage Vin coupled in series with switch S1 and capacitor C1. Capacitor C1 is coupled in parallel with switch S3 and in parallel with inductor L3.

[0081] For example, the second capacitor layer 502b includes a switch S2 coupled in series with capacitor C2. Capacitor C2 is coupled in parallel with switch S4 and in parallel with inductor L3. For example, the third capacitor layer 502c may include a switch S7 coupled in series with capacitor C3. Capacitor C3 is coupled in parallel with switch S8 and in parallel with inductor L4.

[0082] For example, the first capacitor layer 502a, the second capacitor layer 502b, the third capacitor layer 502c, and the inductor layer 504 can be coupled in parallel. One end of the switch S5 of the inductor layer 504 is coupled between the switch S7 and the capacitor C3. One end of the switch S7 of the capacitor layer 502c is coupled between the switch S2 and the capacitor C2 of the second capacitor layer 502b. One end of the switch S2 of the capacitor layer 502b is coupled between the switch S1 and the capacitor C1 of the first capacitor layer 502a.

[0083] Capacitor C F It can be coupled in parallel with inductors L1, L2, and L3. Capacitor C O Can be used with capacitor C F Parallel connection. Output voltage V O With capacitor C O in parallel.

[0084] The control circuit (not shown) controls the switching frequency of each of the switches. For example, the duty cycle used for switching can be equal to 4. (V O / V in ).

[0085] Compared to single-stage buck converters, these configurations offer greater transient response and achieve scalability by utilizing circuitry with an appropriate number of cells or layers. Each cell handles a small fraction of the total power.

[0086]

[0087] Table 2

[0088] Table 2 illustrates the number of cells or circuit layers required to convert the input voltage to the output voltage. Table 2 also shows the duty cycle of the control circuit for the gate driver and switches.

[0089] Figure 15 This is a cross-sectional view of a silicon MEMS inductor. Figure 16 The diagram illustrates a planar view of a 3D silicon MEMS inductor according to an aspect of this disclosure. The MEMS inductor 600 is formed by a 3D stack including a Si coil chip sandwiched between two yttrium iron garnet (YIG) magnetic material chips. The YIG chip is a 400 µm thick substrate with a full-wafer-thickness copper winding having an aspect ratio of 10:1 to 20:1.

[0090] When the copper winding carries current, it generates a magnetic field. Without YIG, no chip with metal wires, pads, or interconnects can be placed nearby because the edge magnetic field would introduce losses in the metal wires. Additionally, the bonding of the YIG layers increases the inductance by approximately 10 times. YIG maintains permeability and low losses at MHz switching frequencies. YIG also provides magnetic shielding to prevent eddy current losses from fields on adjacent chips and interconnects. The required inductance density of the n-cell power converter disclosed herein can be achieved in the range of approximately 3 to 7 nH / mΩ-mm², with a low series resistance of approximately 0.3 to approximately 0.5 mΩ in a 1-turn design and 2.3 to 3.3 mΩ in a 2- or 3-turn design.

[0091] Without YIG, the magnetic field would diffuse, making it impossible to place metal layers nearby. This creates a "barrier to approach" zone and prevents the stacking of chips containing metal interconnects and pads. YIG shields the magnetic field, allowing chips to be stacked nearby to create smaller chips.

[0092] Figure 17 and 18 A 3D MEMS trench capacitor 610 according to aspects of this disclosure is described. The 3D MEMS trench capacitor 610 is disposed within silicon of a circuit layer. The MEMS trench capacitor has a high capacitance density achievable within an area of ​​3 mm × 3 mm. The breakdown voltage of the capacitor is between 12 V and 48 V. The capacitor also has a low series resistance (<3 milliohms) to support high current with low power dissipation. The capacitor is integrated in a way that allows for compatibility with other components. The capacitor has low parasitic inductance, resulting in a self-resonance at least 10 times higher than the switching frequency and the ability to withstand thermomechanical stress from high current. Microfabricated high aspect ratio trench capacitors with conformal metal and dielectric layers are examples of such capacitors. Table 3 shows the capacitance in a 3 mm × 3 mm size.

[0093]

[0094] Table 3

[0095] In terms of capacitance density, Table 4 shows the available capacitance per square millimeter of physical area of ​​the chip. The target physical chip area can then be derived from the target capacitance.

[0096]

[0097] Table 4

[0098] Figure 19 The diagram 700 illustrates the full-load efficiency and power density curves of a general-purpose power converter compared to the power converter of this disclosure. The power converter of this disclosure has higher power density and load efficiency than the general-purpose power converter.

[0099] Figure 20 The graph 710 illustrates the on-time of the high-side switch in a buck converter with a switching frequency (red line) compared to the power converter of this disclosure, at an input voltage of 48 V and an output voltage of 1 V. The buck converter has an on-time approximately four times lower at the same switching frequency as the power converter of this disclosure. The small on-time of the high-side switch in the buck converter cannot be accurately controlled, which limits the switching frequency. Therefore, conventional buck converters do not provide adequate voltage scaling, and their low duty cycle limits the switching frequency and the extremely short conduction time of the high-side switch. This is insufficient for controlling the output voltage. The power converter of this disclosure is based on a switched-capacitor buck topology, which allows for higher switching frequencies and precise output voltage control, smaller size of passive components, and modularity.

[0100] Conventional buck converters have equal to The connection time. Figure 14 The 4-cell converter shown in the figure has equal to The connection time.

[0101] In one aspect, the power converters of this disclosure each turn on and off within approximately 2 ns. With a 48 V input and 1 V output, a 2.1 ns turn-on cycle at a 10 MHz switching frequency in a conventional buck converter is infeasible. The switched capacitor buck (SC-buck) topology solves this problem of the present disclosure. The 4-cell power converter of this disclosure achieves a device turn-on cycle of approximately 33.3 ns at the same effective frequency of 10 MHz under load, where each cell of the 4-cell SC-buck converter switches at 2.5 MHz. Therefore, a 2 ns turn-on and turn-off cycle can be achieved. Higher performance GaN devices can operate within a turn-on and turn-off cycle of approximately 1.25 ns and thus achieve even higher switching frequencies in each cell of the SC-buck converter.

[0102] Figure 21A The voltage and current curves of the power converter of this disclosure are shown in Figure 720. Figure 21B Graph 730 illustrates the switching losses during the turn-on and turn-off events of the high-side switch in the power converter of this disclosure. Due to the lower input voltage experienced by the high-side switch, the turn-on and turn-off switching losses are less than those of state-of-the-art buck converters (…). Figure 4A and 4B (As shown in the image). This results in lower power loss.

[0103] Figure 22A This describes a method for assembling a well-known power converter. Figure 22BThis disclosure describes the assembly of a power converter. Wafer fabrication utilizes a silicon wafer gate driver, GaN device, interposer, magnetic core and windings, and switched capacitors. These are assembled into a stacked power converter. Compared to existing methods, this disclosure reduces the need for separate fabrication and packaging to only two components (Si control and output capacitors). All remaining components can be integrated into a 3D vertically stacked chip (3D HI-PEBB).

[0104] For example, a method of manufacturing a power converter includes fabricating on a wafer: a gate driver, a switch, multiple interposers, an inductor, and a capacitor. The method may also include dicing the wafer and assembling a stack including the gate driver, the switch, the multiple interposers, the inductor, and the capacitor in a stacked configuration. The method may further include fabricating the stack on a substrate and assembling control circuitry on the substrate.

[0105] The stack may be at least one of a first stack 308, a second stack 306, or a combination thereof. The method may also include fabricating an output capacitor on the substrate.

[0106] Therefore, having described several aspects and embodiments of the technology of this application, it should be understood that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, or improvements are intended to be within the scope of the technology described in this application. Therefore, it should be understood that the foregoing embodiments are presented by way of example only and, within the scope of the appended claims and their equivalents, embodiments of the invention may be practiced in ways other than the specific description. Furthermore, any combination of two or more features, systems, articles, materials, and / or methods described herein is included within the scope of this disclosure, provided that such features, systems, articles, materials, and / or methods are not inconsistent with each other.

[0107] Additionally, as described, some aspects can be embodied as one or more methods. Actions performed as part of a method can be ordered in any suitable manner. Therefore, embodiments in which actions are performed in a different order than those described can be constructed, which may include the simultaneous execution of some actions, even if they are shown as sequential actions in the illustrative embodiments.

[0108] The phrase “and / or” as used herein in the specification and claims should be understood to mean “any or both” of the elements so combined, that is, elements that exist together in some cases and separately in others.

[0109] As used herein in the specification and claims, the phrase "at least one" referring to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, but not necessarily including at least one of every component specifically listed in the list of elements, and does not exclude any combination of elements in the list of elements. This definition also allows for the presence of elements, whether related to or unrelated to those specifically identified elements, in addition to those specifically identified in the list of elements referred to by the phrase "at least one".

[0110] In some embodiments, the terms "approximately" and "about" can be used to mean within ±20% of the target value, within ±10% of the target value in some embodiments, within ±5% of the target value in some embodiments, and within ±2% of the target value in other embodiments. The terms "approximately" and "about" may include the target value.

[0111] In the claims and the foregoing description, all transitional phrases (e.g., "comprising," "including," "carrying," "having," "containing," "involving," "holding," "constituting," and the like) shall be understood as open-ended (i.e., meaning encompassing but not limited to). The transitional phrases "constituting of," and "constituting substantially of," shall be closed or semi-closed transitional phrases, respectively.

[0112] When a range or list of values ​​is provided, each intermediate value between the upper and lower limits of the range or list of values ​​is individually and carefully considered and included within this disclosure, as if each value were specifically enumerated herein. Additionally, smaller ranges between the upper and lower limits of a given range, including both the upper and lower limits of the given range, are carefully considered and included within this disclosure. The listing of values ​​or ranges is not an omission of other values ​​or ranges between the upper and lower limits of a given range, including both the upper and lower limits of the given range.

[0113] The use of headings and sections in this application is not intended to limit this disclosure; each section may be applied to any aspect, embodiment, or feature of this disclosure. Claims that use only the phrase "component for..." are intended to be interpreted according to 35 USC 112(f). If a claim does not contain the phrase "component for...", then such claims should not be interpreted according to 35 USC 112. Limitations derived from the specification are not intended to be interpreted into any claim unless such limitations are expressly contained in the claim.

[0114] The embodiments disclosed herein may be embodied as systems, methods, or computer program products. Therefore, embodiments may take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or combinations thereof, encompassing both software and hardware aspects collectively referred to herein as “circuit,” “module,” or “system.” Furthermore, embodiments may take the form of computer program products embodied in one or more computer-readable media having computer-readable program code embodied therein.

Claims

1. A power converter comprising: Substrate; A control circuit, which is mounted on the substrate; and A first circuit stack, disposed on the substrate and coupled to the control circuit, wherein the first circuit stack is configured in a stacked arrangement, the first circuit stack comprising: First switching layer; A first intermediary layer, which is electrically coupled to the first switching layer; The second intermediary layer is electrically coupled to the first intermediary layer; A first gate driver layer is disposed between the first interposer layer and the second interposer layer and electrically coupled to the first interposer layer and the second interposer layer; and The first inductor layer is electrically coupled to the first gate driver layer.

2. The power converter of claim 1, wherein the first and second interposers define a plurality of through-silicon vias for electrical coupling.

3. The power converter of claim 1, further comprising a second circuit stack disposed on the substrate and coupled to the control circuitry, wherein the second circuit stack is in a stacked configuration, the second circuit stack comprising: A second switching layer is disposed on the substrate; The third intermediary layer is electrically coupled to the second switching layer; The fourth intermediary layer is electrically coupled to the third intermediary layer; A second gate driver layer is disposed between the third and fourth interposers and electrically coupled to the third and fourth interposers; A capacitor layer that is electrically coupled to the fourth intermediate layer within the fifth intermediate layer; and A second inductor layer is coupled to the capacitor layer.

4. The power converter of claim 3, wherein the third, fourth and fifth interposers define a plurality of through-silicon vias for electrical coupling.

5. The power converter of claim 3, wherein the second circuit stack includes a plurality of capacitor layers located between the second gate driver layer and the second inductor layer.

6. The power converter according to claim 3, wherein the control circuit is used to control the switching timing of the first and second switching layers.

7. The power converter of claim 3, wherein the control circuit is configured to control which of the first and second circuit stacks will receive the input voltage and modulate the output voltage.

8. The power converter of claim 3, further comprising a plurality of second circuit stacks disposed on the substrate and coupled to the control circuit.

9. The power converter of claim 3, wherein the capacitor layer comprises a microelectromechanical system (MEMS) barrier capacitor.

10. The power converter of claim 1, wherein the control circuit is used to control the timing of the first and second switching layers to control the output voltage.

11. The power converter of claim 1, wherein the first inductor layer comprises a microelectromechanical system (MEMS) power inductor.

12. The power converter of claim 1, wherein the first switching layer comprises gallium nitride and integrated high-side and low-side switches and diodes.

13. A power converter comprising: Substrate; A control circuit, which is mounted on the substrate; and A circuit stack disposed on the substrate and coupled to the control circuitry, wherein the circuit stack is configured in a stacked arrangement, the circuit stack comprising: A switching layer disposed on the substrate; A first intermediary layer, which is electrically coupled to the switching layer; The second intermediary layer is electrically coupled to the first intermediary layer; A gate driver layer is disposed between the first interposer and the second interposer and electrically coupled to the first interposer and the second interposer; A capacitor layer, electrically coupled to the second interposer within a third interposer layer; and An inductor layer that is coupled to the capacitor layer.

14. The power converter of claim 13, wherein the first, second, and third interposers define a plurality of through-silicon vias for electrical coupling.

15. The power converter of claim 13, wherein the circuit stack includes a plurality of capacitor layers located between the gate driver layer and the inductor layer.

16. The power converter of claim 13, wherein the control circuit is used to control the switching timing of the switching layer.

17. The power converter of claim 13, wherein the control circuit is used to control the timing of the switching layer to control the output voltage.

18. The power converter of claim 13, wherein the capacitor layer comprises a microelectromechanical system (MEMS) barrier capacitor.

19. A method of manufacturing a power converter, the method comprising: Manufacturing on a chip: Gate driver; switch; Multiple intermediary layers; Inductor; and Capacitor; Cut the wafer; Assemble a stack including the gate driver, the switch, the plurality of interposers, the inductor, and the capacitor in a stacked configuration; The stack is fabricated on the substrate; and The control circuit is assembled on the substrate.

20. The method of claim 19, further comprising fabricating an output capacitor on the substrate.

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