Semiconductor device

Abstract

The invention provides a semiconductor device which is provided with a transistor part and a diode part. The semiconductor device includes a drift region of a first conductivity type, a plurality of trench portions, a base region of a second conductivity type, an emitter region of the first conductivity type having a doping concentration higher than that of the drift region, and a contact region of the second conductivity type having a doping concentration higher than that of the base region. The transistor portion has a first transistor region including an emitter region and a gate trench portion, and a second transistor region including an emitter region and a gate trench portion and provided between the first transistor region and the diode portion, and a first mesa portion of the first transistor region has a first region of a first conductivity type. The second mesa portion of the second transistor region has a second region of the first conductivity type having a higher doping concentration than the first region.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Patent document 1 describes "between the p-doped region 130 and the n-doped drift region 115, for example, an adjacent second trench structure 128 ( Figure 4 An optional n-doped carrier confinement region may be arranged between the p-doped body region 130 and the n-doped drift region 115, e.g., in a mesa region between neighboring second trench structures 128 (not illustrated in FIG. 4). Figure 4 (Not shown in the image) Between the p-doped region 130 and the n-doped drift region 115. (

[0072] ) "The drift region 115 arranged between the emitter efficiency adjustment region 114 and the second main surface 111 of the semiconductor substrate 102 may have a minority carrier lifetime that is larger than 100 μs." (

[0074] ) Patent document 2 describes that "the semiconductor device 200 has an accumulation region 16 in both the transistor section 70 and the diode section 80. The dopant (donor in this example) in the accumulation region 16 is accumulated at a higher concentration than that in the drift region 18." (

[0083] ).

[0003] Existing technical documents Patent documents Patent Document 1: US2022 / 0384624 Patent Document 2: Japanese Patent Application Publication No. 2018-174295 Summary of the Invention

[0004] In a first aspect of the present invention, a semiconductor device comprising a transistor portion and a diode portion is provided. A semiconductor device includes: a drift region of a first conductivity type disposed on a semiconductor substrate; a plurality of trenches extending along a predetermined trench extension direction on the front side of the semiconductor substrate; a base region of a second conductivity type disposed above the drift region; an emitter region of the first conductivity type disposed on the front side of the semiconductor substrate and having a higher doping concentration than the drift region; and a contact region of the second conductivity type disposed above the drift region and having a higher doping concentration than the base region. The plurality of trenches have gate trenches. A transistor region includes: a first transistor region including the emitter region and the gate trenches; and a second transistor region including the emitter region and the gate trenches and disposed between the first transistor region and the diode region. A first portion of the first transistor region has a first region of the first conductivity type disposed between a depth position at the lower end of the base region and a depth position at the lower end of the trenches. A second portion of the second transistor region has a second region of the first conductivity type disposed between a depth position at the lower end of the base region and a depth position at the lower end of the trenches, and having a higher doping concentration than the first region.

[0005] Any of the above-described semiconductor devices may include an accumulation region of a first conductivity type, which is disposed above the drift region and has a higher doping concentration than the drift region. In any of the above-described semiconductor devices, the accumulation region may be disposed from the second portion of the second transistor region to the third portion of the diode region.

[0006] In any of the aforementioned semiconductor devices, the transistor portion may have a boundary region disposed closer to the second transistor region and the diode portion. Any of the aforementioned semiconductor devices may include an accumulation region of a first conductivity type, disposed above the drift region, and having a higher doping concentration than the drift region. In any of the aforementioned semiconductor devices, the accumulation region may extend from the second facet of the second transistor region to the fourth facet of the boundary region.

[0007] In any of the above semiconductor devices, the first region may be the drift region.

[0008] In any of the semiconductor devices described above, the peak of the doping concentration in the second region may be larger than the peak of the doping concentration in the first region.

[0009] In any of the above semiconductor devices, the number of peaks of doping concentration in the second region may be greater than the number of peaks of doping concentration in the first region.

[0010] Any of the above-described semiconductor devices may include an accumulation region of a first conductivity type, disposed above the drift region, and having a higher doping concentration than the drift region. In any of the above-described semiconductor devices, the second region and the first region may include accumulation regions with the same doping concentration. In any of the above-described semiconductor devices, the width in the depth direction of the accumulation region in the second region may be greater than the width in the depth direction of the accumulation region in the first region.

[0011] In any of the above-described semiconductor devices, the integral concentration of the dopant of the first conductivity type in the second region may be greater than the integral concentration of the dopant of the first conductivity type in the first region.

[0012] In any of the aforementioned semiconductor devices, the diode portion may have an anode region of a second conductivity type disposed above the drift region. In any of the aforementioned semiconductor devices, the third portion of the diode portion may have a third region of a first conductivity type disposed between a depth position at the lower end of the anode region and a depth position at the lower end of the trench portion. In any of the aforementioned semiconductor devices, the third region may have a first conductivity type with a doping concentration higher than that of the drift region.

[0013] In any of the above semiconductor devices, the doping concentration of the anode region can be higher than the doping concentration of the base region.

[0014] In any of the above semiconductor devices, the doping concentration of the anode region can be the same as the doping concentration of the base region.

[0015] Any of the above-mentioned semiconductor devices may have a lifetime control region, which is located in the depth direction of the semiconductor substrate at a position closer to the front side than the center of the semiconductor substrate.

[0016] In any of the above semiconductor devices, the lifetime control region can extend from the diode portion to the second transistor region.

[0017] In any of the aforementioned semiconductor devices, the lifetime control region may be located below the accumulation region.

[0018] In any of the aforementioned semiconductor devices, the second transistor region may be an adjustment region having the lifetime control region. In any of the aforementioned semiconductor devices, the first transistor region may be a non-adjustment region without the lifetime control region.

[0019] In any of the above semiconductor devices, the semiconductor substrate may not have a lifetime control region.

[0020] In any of the above semiconductor devices, the transistor section may have a boundary region that is disposed closer to the second transistor region and the diode section.

[0021] In any of the above-mentioned semiconductor devices, the accumulation region may also be located in the boundary region.

[0022] In any of the above-described semiconductor devices, the front side of the semiconductor substrate in the boundary region can be the contact area.

[0023] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0024] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0025] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0026] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0027] Figure 4 It is shown Figure 2 A diagram of an example of the ff section.

[0028] Figure 5 It is shown Figure 3 A diagram showing an example of the doping concentration distribution at the r-r' and s-s' lines.

[0029] Figure 6 This is an enlarged view of the periphery of the groove contact portion 58 in the boundary area 200.

[0030] Figure 7 This is a diagram showing an example of the configuration of the first transistor region 201 and the second transistor region 202 when viewed from above.

[0031] Figure 8 The diagram shows other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63.

[0032] Figure 9 It is shown Figure 8 A diagram showing an example of the doping concentration distribution at the r-r' and s-s' lines.

[0033] Figure 10The diagram shows other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63.

[0034] Figure 11 It is shown Figure 10 A diagram showing an example of the doping concentration distribution at the r-r' and s-s' lines.

[0035] Figure 12 The diagram shows other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63.

[0036] Figure 13 It is shown Figure 10 A diagram showing an example of the doping concentration distribution at the r-r' and s-s' lines.

[0037] Figure 14 The diagram shows other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63.

[0038] Figure 15 It is shown Figure 14 A diagram showing an example of the doping concentration distribution at the r-r' and s-s' lines.

[0039] Figure 16 It is shown Figure 2 Figures of other examples of the ee section.

[0040] Figure 17 It is shown Figure 2 Figures of other examples of the ee section.

[0041] Figure 18 yes Figure 1 Other examples of magnified views of region D in the image.

[0042] Figure 19 yes Figure 1 Other examples of magnified views of region D in the image.

[0043] Figure 20 It is shown Figure 19 A diagram of an example of the ee section.

[0044] Symbol Explanation 10 Semiconductor substrate Launch Area 12 13 Insertion Area 14 base regions 15 Contact Area 16 Accumulation Area 17 Anode Zone 18 Drift Zone 20 Buffer 21 Front 22 power collection areas 23 Lower surface 24 Collector Electrodes 29. Straight Line Section 30. Dummy trench section 31 Front end 32. Fictitious insulation film 34. Fictitious conductive part 38-layer interlayer insulating film 39. Straight Line Section 40 Gate trench 41 Front end 42 Gate insulating film 44 Gate conductive portion 52 Emitting Electrode 53 Barrier Metals 54 Contact Hole 58. Groove contact area 59. Insertion section 60 facial 61 The first face 62 Second face 63 Third face 64. Fourth face 70 Transistor Section 80 Diode Section 81 Extended Area 82 Cathode Region 90 Edge Terminal Structure Section 100 Semiconductor Devices 130 peripheral gate wiring 131 Active-side gate wiring 160 Active Unit 162 end edge 164 gate pads 200 Boundary Zone 201 First transistor region 202 Second Transistor Region 204 Lattice Defects 206 Lifetime Control Zone 207 Non-adjustment zone 208 Adjustment Zone 301 First Area 302 Second Zone 303 Third Zone Detailed Implementation

[0045] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as described in the claims. Furthermore, not all combinations of the features described in the embodiments are necessary for the technical solution of the invention.

[0046] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when mounting the semiconductor device.

[0047] In this specification, rectangular coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Rectangular coordinate axes only determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0048] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0049] Sometimes the region extending from the center of the semiconductor substrate along its depth direction to the top surface of the semiconductor substrate is called the top surface side. Similarly, sometimes the region extending from the center of the semiconductor substrate along its depth direction to the bottom surface of the semiconductor substrate is called the bottom surface side.

[0050] In the context of this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors may be, for example, within 10%.

[0051] In this specification, the conductivity type of the doped region is described as P-type or N-type. In this specification, "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to introducing a donor or acceptor into a semiconductor substrate, thereby creating a semiconductor exhibiting either an N-type conductivity type or a P-type conductivity type.

[0052] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account charge polarity. For example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the actual net doping concentration at any position becomes N. D -N A In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0053] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of accepting electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in a semiconductor, function as electron-supplying donors. Hydrogen donors can be donors formed by the combination of at least vacancies (V) and hydrogen (H). Alternatively, interstitial Si-H defects, formed by the combination of interstitial silicon (Si-i) and hydrogen in a silicon semiconductor, also function as electron-supplying donors. In this specification, VOH defects or interstitial Si-H are sometimes referred to as hydrogen donors.

[0054] In this specification, the semiconductor substrate is uniformly distributed with N-type body donors. Body donors are donors formed by dopants that are contained substantially uniformly within the ingot during the manufacture of the raw material for the semiconductor substrate. In this example, the body donors are elements other than hydrogen. Dopants for body donors may be, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the body donor is phosphorus. The body donors are also contained within P-type regions. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip obtained by monolithizing wafers. The semiconductor ingot can be manufactured by any of the Czochralski process (CZ process), magnetic field applied Czochralski process (MCZ process), or floating zone melting process (FZ process). In this example, the ingot is manufactured by the MCZ process. The substrate manufactured by the MCZ process contains an oxygen concentration of 1 × 10⁻⁶. 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10⁻⁶. 15 ~5×10 16 / cm 3 The side with a higher oxygen concentration tends to more readily generate hydrogen donors. The bulk donor concentration can be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or a value between 90% and 100% of that chemical concentration. Alternatively, an undoped substrate, free of dopants such as phosphorus, can be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the undoped substrate is, for example, 1 × 10⁻⁶. 10 / cm3 Above and 5×10 12 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 The above. The bulk donor concentration (D0) of the undoped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 It should be noted that the concentrations used in this invention can be values ​​at room temperature. As an example, values ​​at room temperature can be those at 300 K (Kelvin) (approximately 26.9°C).

[0055] In this specification, "P+" or "N+" refers to a doping concentration higher than that of "P" or "N" type. "P-" or "N-" refers to a doping concentration lower than that of "P" or "N" type. Similarly, "P++" or "N++" refers to a doping concentration higher than that of "P+" or "N+" type. Unless otherwise specified, the units used in this specification are in the SI unit system. Sometimes length is expressed in cm, but calculations can be performed after conversion to meters (m).

[0056] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be set to a value under thermal equilibrium conditions. Furthermore, in the N-type region, since the donor concentration is sufficiently large compared to the acceptor concentration, the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0057] When the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of the donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of the donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atoms / cm³. 3 or / cm 3 This unit is used to describe the donor or acceptor concentration, or chemical concentration, within a semiconductor substrate. The specification of "atoms" can be omitted.

[0058] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of diffusion resistance, the carrier mobility of the semiconductor substrate is sometimes lower than that of the crystalline state within the range of current flow. This decrease in carrier mobility is caused by the dispersion of carriers due to crystal structure disorder caused by lattice defects, etc.

[0059] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. For example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which acts as a donor) or the acceptor concentration of boron (which acts as an acceptor) is about 99% of their chemical concentration. On the other hand, the donor concentration of hydrogen (which acts as a donor) in silicon semiconductors is about 0.1% to 10% of the chemical concentration of hydrogen.

[0060] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 The image shows the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10. Figure 1 In this paper, only a portion of the components of the semiconductor device 100 are shown, while the other portion of the components are omitted.

[0061] Semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. For example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" refers to the view from the upper surface of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that are opposite each other when viewed from above. Figure 1 In this configuration, the X and Y axes are parallel to either end edge 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0062] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region in which a main current flows along the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active portion 160, but... Figure 1 The active portion 160 may refer to the area that overlaps with the emitting electrode when viewed from above. Alternatively, the area sandwiched between the active portions 160 when viewed from above may also be included within the active portions 160.

[0063] The active section 160 includes a transistor section 70 containing transistor elements such as IGBTs (insulated gate bipolar transistors) and a diode section 80 containing diode elements such as freewheeling diodes (FWDs). Figure 1In this example, transistor sections 70 and diode sections 80 are alternately arranged along a predetermined first direction (the X-axis direction in this example) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT). In the X-axis direction, although a boundary region is arranged between the transistor section 70 and the diode section 80, in... Figure 1 Omitted in .

[0064] exist Figure 1 In this specification, the area where the transistor section 70 is configured is marked with the symbol "I", and the area where the diode section 80 is configured is marked with the symbol "F". In this specification, a direction different from the first direction when viewed from above is sometimes referred to as a second direction (in...). Figure 1 (The first direction is perpendicular to the Y-axis). The transistor section 70 and the diode section 80 may each have a long side in the second direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The second direction of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section and the long side direction of the mesa section, as described later.

[0065] The diode section 80 has an N+ type cathode region in the area that is in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode section 80. That is, the diode section 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in the area other than the cathode region. In this specification, sometimes an extension region 81 extending the diode section 80 along the Y-axis direction to the gate wiring described later is also included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0066] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near the edge 162. "Near the edge 162" refers to the area between edge 162 and the emitter electrode when viewed from above. When mounting semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0067] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, the shaded lines are used to mark the gate wiring.

[0068] The gate wiring in this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. In this example, the peripheral gate wiring 130 surrounds the active portion 160 when viewed from above. Alternatively, the area surrounded by the peripheral gate wiring 130 when viewed from above can also be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region described later, and it is formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the base region. The area surrounded by the well region when viewed from above can also be considered the active portion 160.

[0069] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum, or a wiring formed of a semiconductor such as polysilicon doped with impurities.

[0070] An active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the deviation of the wiring length measured from the gate pad 164 in each region of the semiconductor substrate 10 can be reduced.

[0071] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 may be metal wiring including aluminum, or wiring formed of semiconductors such as polysilicon doped with impurities.

[0072] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 is configured to extend along the X-axis from the outer peripheral gate wiring 130 holding the active portion 160 to the outer peripheral gate wiring 130 on the other side, in a manner that it is divided approximately equally in the Y-axis direction and traverses the active portion 160. When the active portion 160 is divided using the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0073] The semiconductor device 100 may also include a temperature sensing unit and a current sensing unit (not shown). The temperature sensing unit is a PN junction diode formed of polysilicon or the like, and the current sensing unit simulates the operation of the transistor unit disposed in the active unit 160. It should be noted that the temperature sensing unit may also be connected to an anode pad and a cathode pad disposed near the end edge 162.

[0074] In this example, the semiconductor device 100, when viewed from above, has an edge termination structure 90 between the active portion 160 and the edge 162. The edge termination structure 90 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a protective ring surrounding the active portion 160 in a ring shape, a field plate, and a surface electric field reducing element.

[0075] Figure 2 yes Figure 1 An enlarged view of region D in the diagram. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. Although in Figure 1 The details are omitted, but a boundary region 200 is disposed between the transistor section 70 and the diode section 80 in the X-axis direction. In this example, the boundary region 200 may be part of the transistor section 70, that is, the transistor section 70 may have the boundary region 200. Alternatively, the boundary region 200 may also be part of the diode section 80. It should be noted that in the following description, the transistor section 70, the diode section 80, and the boundary region 200 will sometimes be described separately as different parts from each other.

[0076] The semiconductor device 100 of this example includes a gate trench 40, a dummy trench 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench 40 and the dummy trench 30 are examples of trenches. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 disposed above the upper surface of the semiconductor substrate 10 and an active-side gate wiring 131. The emitter electrode 52 is an example of a metal electrode. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0077] An interlayer insulating film is provided between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but... Figure 2 (Omitted). In this example, the interlayer insulating film has contact holes 54 provided in a manner that penetrates the interlayer insulating film. Figure 2 In the middle, the shading lines of the oblique lines marked on each contact hole 54 are shown.

[0078] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Additionally, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole disposed in the interlayer insulating film. The emitter electrode 52 can be connected to the dummy conductive portion of the dummy trench portion 30 at its front end in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 may not be connected to the emitter electrode 52 and the gate conductive portion, and can be controlled to have a potential different from that of the emitter electrode 52 and the gate conductive portion.

[0079] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at the front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0080] The emitting electrode 52 is formed of a material containing metal. Figure 2 The diagram shows the area where the emitter electrode 52 is provided. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an alloy with aluminum as the main component, such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 may have a barrier metal formed of titanium, titanium compounds, or the like in the layer beneath the area formed of aluminum or the like. Furthermore, a plug portion formed by embedding tungsten or the like in contact with the barrier metal and aluminum or the like may also be provided in the contact hole.

[0081] Base region 14 is a region of the second conductivity type. Well region 11 is disposed overlapping with active-side gate wiring 131. Well region 11 is also disposed with a predetermined width in a region that does not overlap with active-side gate wiring 131. In this example, well region 11 is disposed separately from the end of contact hole 54 in the Y-axis direction toward active-side gate wiring 131. Well region 11 is a region of the second conductivity type with a doping concentration higher than that of base region 14. In this example, base region 14 is P-type and well region 11 is P+ type.

[0082] The transistor section 70, the diode section 80, and the boundary region 200 each have a plurality of trench sections arranged along a first direction. The plurality of trench sections extend on the front side of the semiconductor substrate 10 along a second direction perpendicular to the first direction. The second direction is an example of a predetermined trench extension direction. The plurality of trench sections include a gate trench section 40.

[0083] In this example, the transistor section 70 alternately has one or more gate trench sections 40 and one or more dummy trench sections 30 along the first direction. In this example, the diode section 80 has multiple dummy trench sections 30 along the first direction. In this example, the diode section 80 does not have gate trench sections 40. In this example, the boundary region 200 has multiple dummy trench sections 30 along the first direction. In this example, the boundary region 200 does not have gate trench sections 40.

[0084] In this example, the gate trench portion 40 may have two straight portions 39 (the portion of the trench that is straight along the second direction) extending along the second direction and a front end portion 41 connecting the two straight portions 39. Figure 2 The second direction is the Y-axis direction.

[0085] At least a portion of the front end portion 41 is preferably curved when viewed from above. Since the front end portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, it can mitigate the electric field concentration at the ends of the straight portions 39.

[0086] In the transistor section 70, dummy trench sections 30 are provided between each straight section 39 of the gate trench section 40. There may be one dummy trench section 30 or multiple dummy trench sections 30 between each straight section 39. The dummy trench section 30 may have a straight shape extending along the second direction, or it may have the same straight section 29 and front end portion 31 as the gate trench section 40. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31 and a dummy trench portion 30 with a front end portion 31.

[0087] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are provided in the well region 11 when viewed from above. That is, at the Y-axis end of each trench portion, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0088] In the first direction, a mesa 60 is provided between each trench portion. The mesa 60 refers to the area within the semiconductor substrate 10 that is held between the trench portions. For example, the upper end of the mesa 60 is the upper surface of the semiconductor substrate 10. The depth of the lower end of the mesa 60 is the same as the depth of the lower end of the trench portion. In this example, the mesa 60 is configured to extend along the trench in the second direction (Y-axis direction) along the upper surface of the semiconductor substrate 10. The mesa 60 of the transistor portion 70, the mesa 60 of the diode portion 80, and the mesa 60 of the boundary region 200 may have different structures. In this specification, the term "mesa 60" refers to the mesa 60 of each transistor portion 70, the mesa 60 of the diode portion 80, and the mesa 60 of the boundary region 200.

[0089] A base region 14 is provided on the mesa 60 of the transistor section 70 and the boundary region 200. The base region 14 is a region of the second conductivity type. In this example, the base region 14 is P-type. The doping concentration of the base region 14 in the boundary region 200 can be the same as or different from the doping concentration of the base region 14 in the transistor section 70. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa 60 of the transistor section 70 and the mesa 60 of the boundary region 200, that is closest to the active-side gate wiring 131, is designated as base region 14-e. Figure 2 The image shows a base region 14-e disposed at one end of each stage 60 in a second direction, but also at the other end of each stage 60.

[0090] In the mesa 60 of the transistor section 70, a first conductivity type emitter region 12 and a second conductivity type contact region 15 are provided in the area sandwiched between the base regions 14-e when viewed from above. In the mesa 60 of the boundary region 200, a second conductivity type contact region 15 may be provided in the area sandwiched between the base regions 14-e when viewed from above. The contact region 15 is a second conductivity type region with a doping concentration higher than that of the base region 14. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be disposed between the base region 14 and the upper surface of the semiconductor substrate 10 in the depth direction.

[0091] An anode region 17 is provided on the isthmus 60 of the diode section 80. The anode region 17 is a region of the second conductivity type. In this example, the anode region 17 is P-type. The region closest to the active-side gate wiring 131 of the anode region 17 exposed on the upper surface of the semiconductor substrate 10 in the isthmus 60 of the diode section 80 is designated as anode region 17-e. Figure 2 In the diagram, although an anode region 17-e is shown at one end of the mesa 60 of the diode section 80 in the second direction, an anode region 17-e is also provided at the other end.

[0092] In the mesa 60 of the diode section 80, a contact region 15 of a second conductivity type may be provided in the area sandwiched by the anode region 17-e when viewed from above. The contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. The contact region 15 may be provided between the anode region 17 and the upper surface of the semiconductor substrate 10 in the depth direction. It should be noted that in the mesa 60 of the diode section 80, the entire surface of the area sandwiched by the anode region 17-e when viewed from above may have the anode region 17, without the contact region 15.

[0093] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is grounded to the gate trench portion 40. A contact region 15 exposed on the upper surface of the semiconductor substrate 10 may be provided on the mesa portion 60 that is in contact with the gate trench portion 40.

[0094] The contact area 15 and the emission area 12 in the platform 60 are respectively provided from one groove portion in the X-axis direction to another groove portion. As an example, the contact area 15 and the emission area 12 of the platform 60 are alternately arranged along the second direction (Y-axis direction) of the groove portion.

[0095] In another example, the contact area 15 and the emission area 12 of the platform 60 can be arranged in a strip shape along the second direction (Y-axis direction) of the groove. For example, the emission area 12 is provided in the area that contacts the groove, and the contact area 15 is provided in the area that is held by the emission area 12.

[0096] The emitter region 12 is not provided on the mesa 60 of the diode section 80 and the boundary region 200. The boundary region 200 may be a region on the mesa 60 where no channel is formed. The boundary region 200 may be a region where the proportion of channels formed is less than that formed in the transistor section 70.

[0097] On the upper surface of the mesa 60 of the diode portion 80, an anode region 17 may be provided in the area clamped by the contact region 15. The anode region 17 may be disposed over the entire area clamped by the contact region 15. The mesa 60 of the boundary region 200 may have the same structure as the mesa 60 of the diode portion 80, or it may have a different structure. In this example, the mesa 60 of the boundary region 200 has a contact region 15 provided over the entire area clamped by the base regions 14-e. That is, the area of ​​the contact region 15 of the mesa 60 of the boundary region 200 may be larger than the area of ​​the contact region 15 of the mesa 60 of the diode portion 80. In this case, holes in the semiconductor substrate 10 can be easily extracted to the emitter electrode 52 via the mesa 60 of the boundary region 200.

[0098] Alternatively, an N-type impurity region with a doping concentration equal to or lower than that of the emitter region 12 may be provided on the mesa 60 of the boundary region 200. However, in this case, the gate trench 40 is not provided in the boundary region 200. In the following description, this impurity region is sometimes referred to as an accumulation region.

[0099] Furthermore, the trench portion at the boundary between the transistor section 70 and the boundary region 200 is a dummy trench portion 30. Since the N-type impurity region of the mesa 60 of the boundary region 200 is not in contact with the gate trench portion 40, no more current flows in the boundary region 200 than in the transistor section 70. As a result, hole injection from the mesa 60 of the boundary region 200 can be suppressed, reducing reverse recovery losses.

[0100] A contact hole 54 is provided above each stage 60. The contact hole 54 is located in the area held by the base region 14-e. In this example, the contact hole 54 is located above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not located in the region corresponding to the base region 14-e and the sink region 11. The contact hole 54 may be located at the center of the stage 60 in the first direction (X-axis direction).

[0101] In the diode section 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in a region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are located between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. Figure 2 In the diagram, the boundary between the cathode region 82 and the collector region 22 is shown by a dashed line. Additionally, in the transistor section 70 and the boundary region 200, a P+ type collector region 22 is provided in a region adjacent to the lower surface of the semiconductor substrate 10.

[0102] The cathode region 82 is configured to be located away from the well region 11 in the Y-axis direction. This ensures a sufficient distance between the cathode region 82 and the P-type region (well region 11) with a high doping concentration and deep formation, thus improving breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is configured to be further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In another example, the end of the cathode region 82 in the Y-axis direction may be located between the well region 11 and the contact hole 54.

[0103] Figure 3 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0104] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass containing impurities such as boron or phosphorus, a thermally oxidized film, or other insulating films. The interlayer insulating film 38 has a layer containing... Figure 2 Contact hole 54, which has been described in the text.

[0105] The emitter electrode 52 is disposed above the interlayer insulating film 38. The emitter electrode 52 contacts the front surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction. As will be explained in detail later, the emitter electrode 52 may have a barrier metal containing titanium in the portion that contacts the front surface 21 of the semiconductor substrate 10. The barrier metal may have a titanium nitride layer or a stacked structure of titanium nitride and titanium layers. As will be explained in detail later, the emitter electrode 52 may also have a plug portion of tungsten or the like that filled into the interior of the contact hole 54.

[0106] The semiconductor substrate 10 has a drift region 18 of a first conductivity type, such as N-type or N-type. In this example, the drift region 18 is an N-type region. The drift region 18 is respectively disposed in the transistor section 70, the diode section 80, and the boundary region 200. The base region 14 and the contact region 15 are disposed above the drift region 18.

[0107] The semiconductor substrate 10 also has an accumulation region 16 of a first conductivity type, such as N-type or N+-type. The accumulation region 16 and the aforementioned emitter region 12 are regions of the first conductivity type with a doping concentration higher than that of the drift region 18. In this example, both the accumulation region 16 and the emitter region 12 are N+-type regions.

[0108] Holes are accumulated in the accumulation region 16 below the drift region 18. By providing a high-concentration accumulation region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be improved, and the on-state voltage can be reduced. The doping concentration of the accumulation region 16 can be more than 10 times, more than 50 times, or more than 100 times that of the drift region 18.

[0109] The transistor section 70 has a first transistor section 201 including an emitter region 12 and a gate trench section 40, and a second transistor section 202 including an emitter region 12 and a gate trench section 40. The second transistor section 202 is disposed between the first transistor section 201 and the diode section 80.

[0110] As described above, the transistor section 70 has a boundary region 200 that is disposed closer to the second transistor region 202 and the diode section 80. The accumulation region 16 extends from the mesa 60 of the second transistor region 202 to the mesa 60 of the boundary region 200. In this example, the accumulation region 16 extends from the mesa 60 of the second transistor region 202 to both the mesa 60 of the boundary region 200 and the mesa 60 of the diode section 80. It should be noted that the accumulation region 16 may not be disposed on the mesa 60 of the diode section 80.

[0111] In this example, the front side of the semiconductor substrate 10 in the boundary region 200 where the accumulation region 16 is provided on the mesa 60 is the contact region 15. When the front side of the semiconductor substrate 10 at the boundary region 200 is used as the contact region 15, although hole injection increases, hole injection can be suppressed in the accumulation region 16 of the mesa 60 in the boundary region 200.

[0112] In this example, the plurality of facets 60 include one or more first facets 61, one or more second facets 62, one or more third facets 63, and one or more fourth facets 64. The first facets 61 and second facets 62 are disposed in the transistor section 70. More specifically, the first facet 61 is disposed in the first transistor region 201, and the second facet 62 is disposed in the second transistor region 202. That is, the second facet 62 is positioned between the first facet 61 and the diode section 80. The third facet 63 is disposed in the diode section 80, and the fourth facet 64 is disposed in the boundary region 200.

[0113] An N+ type emitter region 12 and a P type base region 14 are sequentially disposed on the first surface 61 of the first transistor region 201 and the second surface 62 of the second transistor region 202, starting from the front side 21 of the semiconductor substrate 10.

[0114] The emitter region 12 is exposed on the front side 21 of the semiconductor substrate 10 and is grounded to the gate trench portion 40. The emitter region 12 can be connected to the trench portions on both sides of the mesa portion 60.

[0115] In the transistor section 70, the base region 14 is disposed below the emitter region 12. In this example, the base region 14 in the transistor section 70 is grounded to the emitter region 12. In the transistor section 70, the base region 14 can be connected to the trench portions on both sides of the first faceplate 61 and the second faceplate 62.

[0116] The first surface portion 61 of the first transistor region 201 has a first region 301 of a first conductivity type disposed between a depth position at the lower end of the base region 14 and a depth position at the lower end of the trench portion. In this example, the first region 301 of the first conductivity type is a drift region 18 of the first conductivity type.

[0117] The second surface portion 62 of the second transistor region 202 has a second region 302 of a first conductivity type disposed between a depth position at the lower end of the base region 14 and a depth position at the lower end of the trench portion. The second region 302 includes an accumulation region 16 of the first conductivity type. The doping concentration of the second region 302 of the second surface portion 62 is higher than the doping concentration of the first region 301 of the first surface portion 61. This suppresses hole injection near the diode portion 80. Furthermore, it narrows the width of the boundary region 200 in the X-axis direction.

[0118] The diode section 80 has an anode region 17 of a second conductivity type disposed above the drift region 18. The anode region 17 in the diode section 80 is in contact with the front side 21 of the semiconductor substrate 10. The doping concentration of the anode region 17 of the second conductivity type can be the same as or different from the doping concentration of the base region 14 of the second conductivity type. The third stage 63 of the diode section 80 has a third region 303 of a first conductivity type disposed between the depth position of the lower end of the anode region 17 and the depth position of the lower end of the trench section. In this example, the third region 303 includes an accumulation region 16. The doping concentration of the third region 303 of the first conductivity type of the third stage 63 is higher than the doping concentration of the drift region 18 of the first conductivity type.

[0119] The doping concentration of the anode region 17 of the second conductivity type in the diode section 80 can be greater than, less than, or the same as the doping concentration of the base region 14 in the transistor section 70. Similarly, the doping concentration of the anode region 17 can be greater than, less than, or the same as the doping concentration of the base region 14 in the boundary region 200. As an example, the doping concentration of the anode region 17 of the second conductivity type in the diode section 80 is greater than or equal to the doping concentration of the base region 14 in both the transistor section 70 and the boundary region 200.

[0120] In this example, a P+ type contact region 15 is provided on the fourth facet 64 of the boundary region 200, grounded to the front surface 21 of the semiconductor substrate 10. A base region 14 is also provided between the contact region 15 and the drift region 18 in the fourth facet 64. The fourth facet 64 has a fourth region 304 of a first conductivity type, located between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. An accumulation region 16 is included in the fourth region 304. The doping concentration of the fourth region 304 of the first conductivity type in the fourth facet 64 is higher than the doping concentration of the first region 301 of the first conductivity type in the first facet 61.

[0121] The first region 301 to the fourth region 304 can all be provided across the entire X-axis direction of each isthmus 60. The first region 301 to the fourth region 304 can all be provided in such a way that they cover the entire lower surface of the base region 14 of each isthmus 60. In each isthmus 60, the doping concentration of the plurality of first regions 301, etc., in each transistor section 70, diode section 80, and boundary region 200 can be the same or different. As an example, the doping concentration of the second region 302 of the second transistor region 202 can be higher the closer it is to the second isthmus 62 of the diode section 80.

[0122] As described above, the first region 301 to the fourth region 304 are all located between the depth of the lower end of the base region 14 and the depth of the lower end of the trench portion. In this example, the depth of the lower end of the base region 14 is consistent in the transistor portion 70, the diode portion 80, and the boundary region 200. Furthermore, the depth of the lower end of the trench portion is also consistent in the transistor portion 70, the diode portion 80, and the boundary region 200. Therefore, in this example, the widths of the first region 301, the second region 302, the third region 303, and the fourth region 304 are approximately uniform in the depth direction. In the transistor portion 70, the diode portion 80, and the boundary region 200, when the spacing between adjacent trench portions is consistent, the volumes of the first region 301, the second region 302, the third region 303, and the fourth region 304 can also be approximately uniform.

[0123] Groove contact portions 58 are provided on the first surface 61, the second surface 62, the third surface 63, and the fourth surface 64. The groove contact portion 58 is a portion where metal electrodes such as the emitter electrode 52 are disposed inside the semiconductor substrate 10. A groove is formed on the front surface 21 of the semiconductor substrate 10 exposed through the contact hole 54, and the groove is filled with a metal electrode to form the groove contact portion 58. The area of ​​the first surface 61, etc., that contacts the metal electrodes such as the emitter electrode 52 corresponds to the contact portion.

[0124] Although the groove contact portion 58 in this example has the same width in the depth direction in the first face 61, the second face 62, the third face 63, and the fourth face 64, they can also be different from each other. For example, the groove contact portion 58 and the contact area 15 of the second face 62 can be deeper toward the drift area 18 than the groove contact portion 58 and the contact area 15 of the first face 61.

[0125] In each transistor section 70, diode section 80, and boundary region 200, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 may have a concentration peak with a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 can be the average doping concentration in a region where the doping concentration distribution is almost flat.

[0126] The buffer 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer 20 may be set at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer 20 may function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0127] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0128] In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The donor concentration in the cathode region 82 is higher than that in the drift region 18. The donors in the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above.

[0129] In the boundary region 200, a P+ type collector region 22 is provided below the buffer zone 20. The collector region 22 of the boundary region 200 may have the same doping concentration as the collector region 22 of the transistor section 70. The boundary position of the cathode region 82 and the collector region 22 in the X-axis direction may be set as the boundary position of the diode section 80 and the boundary region 200 in the X-axis direction.

[0130] In another example, in the boundary region 200, a portion or all of the collector region 22 can be replaced with the cathode region 82. When the cathode region 82 is provided on the lower surface of the boundary region 200, the region where the contact region 15 and the anode region 17 are alternately arranged in the area sandwiched by the anode regions 17-e can be designated as the diode section 80, and the region where the contact region 15 is arranged in the entire area sandwiched by the base regions 14-e can be designated as the boundary region 200. When the cathode region 82 is provided on the lower surface of the boundary region 200, the boundary region 200 can also be considered as part of the diode section 80.

[0131] The trench portion adjacent to the mesa portion forming the channel, the one closest to the diode portion 80 in the X-axis direction, can be positioned at the boundary between the transistor portion 70 and the boundary region 200, or between the transistor portion 70 and the diode portion 80, in the X-axis direction. The trench portion on the diode portion 80 side of the two trench portions connected to the emitter region 12 positioned closest to the diode portion 80 in the X-axis direction can be a dummy trench portion 30. In this case, the dummy trench portion 30 can be positioned at the boundary between the transistor portion 70 and the boundary region 200, or between the diode portion 80, in the X-axis direction.

[0132] An emitter region 12 may also be provided in the boundary region 200. However, in this case, a gate trench portion 40 is not provided in the boundary region 200. Furthermore, the trench portion at the boundary between the transistor portion 70 and the boundary region 200 is a dummy trench portion 30. That is, no transistor operation occurs in the boundary region 200. A gate trench portion 40 may also be provided in the boundary region 200. However, in this case, an emitter region 12 is not provided in the boundary region 200, or even if an emitter region 12 is provided, it is not connected to the gate trench portion 40. That is, no transistor operation occurs in the boundary region 200.

[0133] The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0134] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front side 21 of the semiconductor substrate 10. Each trench portion extends from the front side 21 of the semiconductor substrate 10 through the base region 14 and extends below the base region 14 (reaching the drift region 18). In the region where at least one of the emitter region 12 and the contact region 15 is provided, each trench portion also extends through these doped regions. The trench portion extending through the doped region is not limited to being manufactured in the order of forming the trench portion after forming the doped region. The case where doped regions are formed between the trench portions after the trench portions are formed is also included in the case where the trench portion extends through the doped region.

[0135] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. In this example, the diode section 80 and the boundary region 200 are provided with a dummy trench section 30, but the gate trench section 40 is not provided. However, either the gate trench section 40 or the dummy trench section 30 may be provided at the boundary between the boundary region 200 and the transistor section 70.

[0136] It should be noted that the boundary region 200 is a buffer structure used to arrange the different structures of the transistor section 70 and the diode section 80 side by side. Therefore, the width of the boundary region 200 in the X-axis direction can also be relatively short. For example, one or more fourth face sections 64 can be provided in the boundary region 200, or the boundary region 200 can be omitted.

[0137] Furthermore, the boundary region 200 may have multiple fourth mesa 64 in the X-axis direction. This allows for the suppression of the influence of the transistor section 70 on the characteristics of the diode section 80, such as the effects of the operation of the gate trench section 40, or the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics. Here, the number of mesa refers to the number of mesa arranged in the X-axis direction.

[0138] The gate trench portion 40 has a gate trench disposed on the front side 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position further inward than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0139] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. For the gate trench portion 40 at this cross-section, the front side 21 of the semiconductor substrate 10 is covered by an interlayer insulating film 38. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that is in contact with the gate trench portion 40.

[0140] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the front side 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and at a position further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0141] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the front side 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section).

[0142] The semiconductor device 100 in this example includes a lifetime control region 206 disposed in the depth direction of the semiconductor substrate 10 at a position closer to the front side than the center of the semiconductor substrate 10. The lifetime control region 206 includes a lifetime inhibitor that adjusts the lifetime of charge carriers. The lifetime control region 206 reduces the threshold voltage and also reduces the switching losses of the semiconductor device 100.

[0143] In this example, the lifetime control region 206 is a region with a locally small lifetime of charge carriers. Charge carriers are either electrons or holes. Sometimes, charge carriers are simply referred to as charge carriers. In this example, the lifetime control region 206 is formed by injecting charged particles such as helium ions from the front side 21 of the semiconductor substrate 10. In this example, the concentration distribution of helium, etc., in the depth direction of the semiconductor substrate 10 can have a shape that trails from the lifetime control region 206 to the front side 21 of the semiconductor substrate 10. That is, from the lifetime control region 206 to the front side 21, the concentration of helium, etc. ( / cm³) 3 It can decrease monotonically.

[0144] The concentration of helium, etc., on the front side 21 can be greater than 0. On the other hand, the concentration of helium, etc., can also have a tail-like shape in the direction from the lifetime control region 206 toward the lower surface 23. However, compared with the tail toward the front side 21, the concentration of helium, etc., in the tail toward the lower surface 23 decreases more sharply. The concentration of helium, etc., on the lower surface 23 is lower than the concentration of helium, etc., on the front side 21. The concentration of helium, etc., on the front side 21 can be below the measurement limit or can be 0. It should be noted that the lifetime control region 206 can also be formed by implanting charged particles such as helium ions from the lower surface 23 side of the semiconductor substrate 10.

[0145] By injecting charged particles such as helium ions into a semiconductor substrate 10, lattice defects 204, such as vacancies, are formed near the injection sites. These lattice defects 204 generate recombination centers. The lattice defects 204 can be dominated by vacancies such as single-atom vacancies (V) or multi-atom vacancies (VV), and can be dislocations, interstitial atoms, or transition metals. For example, atoms adjacent to vacancies may have dangling bonds. In a broader sense, lattice defects 204 can also contain donors and / or acceptors, but in this specification, lattice defects 204 dominated by vacancies are sometimes referred to as vacancy-type lattice defects, vacancy-type defects, or simply lattice defects. In this specification, lattice defects 204 are sometimes referred to as recombination centers that facilitate carrier recombination and are simply called recombination centers or lifetime inhibitors.

[0146] A lifetime inhibitor can be formed by implanting helium ions into the semiconductor substrate 10. The helium chemical concentration can be used as the density of lattice defects 204. It should be noted that lifetime inhibitors formed by helium ion implantation are sometimes terminated by hydrogen present in the buffer zone 20; therefore, the depth position of the lifetime inhibitor's density peak sometimes does not coincide with the depth position of the helium chemical concentration peak. Furthermore, when hydrogen ions are implanted into the semiconductor substrate 10, the lifetime inhibitor can be formed in the hydrogen ion passage region further along the implantation surface than the range.

[0147] Lattice defect 204 is an example of a lifetime inhibitor. Figure 3 The lattice defect 204 at the injection site of charged particles is schematically indicated by an "×". In regions where a large number of lattice defects 204 remain, charge carriers are captured by the lattice defects 204, thus shortening the charge carrier lifetime. By adjusting the charge carrier lifetime, characteristics such as the reverse recovery time and reverse recovery loss of the diode section 80 can be adjusted. In the depth direction of the semiconductor substrate 10, the location where the charge carrier lifetime exhibits a minimum value can be set as the depth location of the lifetime control region 206.

[0148] The lifetime control region 206 is disposed on the front side 21 of the semiconductor substrate 10. The front side 21 refers to the area extending from the center position in the depth direction of the semiconductor substrate 10 to the front side 21 of the semiconductor substrate 10. In this example, the lifetime control region 206 is disposed at a position lower than the lower end of the trench portion.

[0149] Furthermore, when the lifetime control region 206 is formed by irradiation with a particle beam with high transmission power, such as an electron beam, lattice defects are formed approximately uniformly from the front surface 21 of the semiconductor substrate 10 to the lower surface 23. In this case, the depth of the lifetime control region 206 can also be considered as being disposed on the front surface 21 side of the semiconductor substrate 10.

[0150] The lifetime control region 206 extends from the diode section 80 to the second transistor region 202. When the semiconductor device 100 has a boundary region 200, the lifetime control region 206 is also provided in the boundary region 200. The lifetime control region 206 can be provided throughout the entire diode section 80 in the X-axis direction. The lifetime control region 206 is also provided throughout the entire boundary region 200. In this example, the lifetime control region 206 is provided below the accumulation region 16.

[0151] The lifetime control region 206 of the diode section 80 and the lifetime control region 206 of the transistor section 70 are provided at the same depth. In the transistor section 70, the second transistor region 202 may be an adjustment region 208 provided with the lifetime control region 206, and the first transistor region 201 may be a non-adjustment region 207 without the lifetime control region 206.

[0152] Here, the boundary between the adjustment region 208 and the non-adjustment region 207 may not be consistent with the boundary between the first transistor region 201 and the second transistor region 202. For example, the lattice defect 204 (lifetime control region 206) may be set from the second transistor region 202 and extend throughout a part of the first transistor region 201.

[0153] Adjustment region 208 is the region that overlaps with lifetime control region 206 when viewed from above. Non-adjustment region 207 is the region that does not overlap with lifetime control region 206 when viewed from above. Non-adjustment region 207 is a region where the carrier lifetime at the same depth as lifetime control region 206 is longer than the carrier lifetime of lifetime control region 206 of diode section 80. Non-adjustment region 207 may also be a region where charged particles such as helium ions, used to form lifetime inhibitors such as lattice defects 204, have not been injected. The chemical concentration of helium, etc., in non-adjustment region 207 ( / cm³) is... 3 The chemical concentration of the charged particle at the center of the Z-axis direction of the drift region 18 can be the same.

[0154] Figure 4 It is shown Figure 2 A diagram illustrating an example of the ff section. The ff section is the XZ plane passing through contact region 15 and cathode region 82. This example section has the following characteristics: Figure 3 In the example shown, the emission region 12 is replaced with the structure of the contact region 15. The structure other than the contact region 15 is the same as... Figure 3 same.

[0155] Figure 5 It is shown Figure 3 A diagram illustrating an example of the doping concentration distribution at the r-r' and s-s' lines. The r-r' line is a line passing through the second region 302 and parallel to the Z-axis, and the s-s' line is a line passing through the first region 301 and parallel to the Z-axis.

[0156] The integrated concentration of the first conductivity type dopant in the second region 302 is greater than the integrated concentration of the first conductivity type dopant in the first region 301. Alternatively, the dose ( / cm²) of the N-type dopant in the second region 302 is greater than the dose of the N-type dopant in the first region 301. The dose in each region can be obtained by integrating the doping concentration of each region.

[0157] In this example, the doping concentration of the first region 301 is higher than that of the drift region 18 but lower than that of the second region 302. The peak value can be used for the doping concentration of each region. The doping concentration of the first region 301 can also be the same as that of the drift region 18. That is, the drift region 18 located on the first face 61 can be treated as the first region 301. The doping concentration of the first region 301 can be higher than that of the drift region 18. The doping concentration of the first region 301 can be less than half, less than 1 / 10, or less than 1 / 100 of the doping concentration of the second region 302.

[0158] In this example, a PN junction is formed at the boundary between the second region 302 and the base region 14. The depth of this boundary is set to Z14. The doping concentration distribution in the second region 302 has a peak. The doping concentration at the peak is set to P302. Additionally, the doping concentration of the drift region 18 is set to D18. The peak concentration P302 is higher than the doping concentration D18. The depth of the lower end of the second region 302 is set to Z302.

[0159] In this example, a PN junction is formed at the boundary between the first region 301 and the base region 14. The depth of this boundary is set to Z14. The doping concentration of the first region 301 in this example is the same as the doping concentration of the drift region 18. In this example, the number of doping concentration peaks in the first region 301 is 0. The doping concentration in the depth direction of the first region 301 in this example can be constant. The depth of the lower end of the first region 301 is set to Z301.

[0160] The dose per unit area (ions / cm²) of dopant ions targeting the first region 301 2 Let Do301 be the dose of the first region 301. Do301 can be obtained by integrating the doping concentration of the first region 301 from depth position Z14 to Z301. The dose per unit area (ions / cm²) of the dopant ions for the second region 302 is then expressed as... 2 Let Do302 be the dose of the second region 302. Do302 can be obtained by integrating the doping concentration of the second region 302 from depth position Z14 to Z302. Figure 5 In the diagram, the area of ​​the shaded portion marked with a diagonal line corresponds to the respective dose.

[0161] Dot 302 is higher than dot 301. Dot 302 can be more than twice, more than ten times, or more than one hundred times the dot 301. Furthermore, the doping concentration D18 of the first region 301 is lower than the peak concentration P302. It should be noted that, in this example, it can also be said that the number of peaks with doping concentration in the second region 302 is greater than the number of peaks with doping concentration in the first region 301.

[0162] Figure 6 This is an enlarged view of the periphery of the trench contact portion 58 in the boundary region 200. In the fourth surface portion 64 of the boundary region 200, a barrier metal 53 is provided on the sidewalls and bottom surface of the contact hole 54. The barrier metal 53 can be provided on the entire bottom surface of the contact hole 54. The material of the barrier metal 53 can be titanium or a titanium compound. If the semiconductor substrate 10 is silicon, the barrier metal 53 can react with the semiconductor substrate 10 to form silicon.

[0163] In the contact hole 54, a plug portion 59 is provided inside the barrier metal 53. The material of the plug portion 59 can be tungsten. The material of the plug portion 59 can also be the same as the material of the emitter electrode 52. The barrier metal 53 and the plug portion 59 are also provided in each contact hole 54 of the transistor section 70 and the diode section 80.

[0164] At least a portion of the mesa 60 may have a plug region 13 disposed in the area adjacent to the lower end of the contact portion. The plug region 13 is disposed above the drift region 18 and has a doping concentration higher than that of the base region 14. In this example, the plug region 13 is disposed below the trench contact portion 58. In this example, the plug region 13 is adjacent to the bottom surface of the trench contact portion 58. The plug region 13 may be adjacent to the sidewall of the trench contact portion 58. The plug region 13 is a region of a second conductivity type with a doping concentration higher than that of the base region 14. In this example, the doping concentration of the plug region 13 is higher than that of the contact region 15. In this example, the plug region 13 is a P++ type region.

[0165] The plug area 13 can be provided on the bottom surface of the groove contact portion 58, extending along the groove extension direction. The plug area 13 can be provided on the entire bottom surface of the groove contact portion 58. By providing each plug area 13, it is easy to remove cavities in each platform 60. Therefore, it is possible to suppress the decrease in tolerance.

[0166] Figure 7 This diagram illustrates an example configuration of the adjustment area 208 and the non-adjustment area 207 when viewed from above. This example configuration can be applied to any of the semiconductor devices 100 described in this specification. Figure 7 The image shows two diode sections 80 and one transistor section 70; other areas are omitted. Additionally, in... Figure 7In the middle, the area marked with a diagonal line is shaded.

[0167] In this example, in the transistor section 70, the adjustment region 208, which has a lifetime control region 206, may include the second transistor region 202, and the non-adjustment region 207, which does not have a lifetime control region 206, may coincide with the first transistor region 201. The adjustment region 208 may also be provided throughout the entire diode section 80 in the X-axis direction. Furthermore, the adjustment region 208 is also provided in the transistor section 70 in the region adjacent to the diode section 80 or the boundary region 200. The area of ​​the first transistor region 201 in the transistor section 70 may be larger than the area of ​​the second transistor region 202. That is, in this example, the area of ​​the non-adjustment region 207 in the transistor section 70 may be larger than the area of ​​the adjustment region 208 in the transistor section 70.

[0168] In the transistor section 70, the number of first faceplates 61 can be greater than the number of second faceplates 62. Therefore, even if the turn-off of the second transistor region 202 is later than that of the first transistor region 201, local current concentration can be suppressed. In the transistor section 70, the threshold voltage of the first faceplate 61 can be lower than the threshold voltage of the second faceplate 62. By adjusting the depth of the trench contact portion 58 in the second faceplate 62 and the dosage of each plug region 13, the threshold voltage of each faceplate 60 can be adjusted. It should be noted that the threshold voltage of a faceplate 60 refers to the voltage at which at least one channel region in that faceplate 60 transitions from off to on.

[0169] Figure 8 This diagram illustrates other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63. In this example, the first region 301 of the first faceplate 61 includes an N-type accumulation region 16. The second region 302 of the second faceplate 62 and the third region 303 of the third faceplate 63 each include an N+ type accumulation region 16. Structures other than the first region 301, the second region 302, and the third region 303 can be used with... Figures 1 to 7 The implementation method described is the same, and repeated descriptions are omitted. Additionally, as an example, the third region 303 may have the same doping concentration as the second region 302, and repeated descriptions are omitted. This is also true in the subsequent embodiments.

[0170] Figure 9 It is shown Figure 8 A diagram illustrating an example of the doping concentration distribution at the r-r' and s-s' lines. The doping concentration distribution in the first region 301 of this example is... Figure 5 Unlike other examples, this one has a peak. The doping concentration at the apex of this peak is set as P301. Peak concentration P301 is higher than doping concentration D18.

[0171] The integrated concentration of the first conductivity type dopant in the second region 302 is greater than the integrated concentration of the first conductivity type dopant in the first region 301. It can be said that the dose Do302 is greater than the dose Do301. The dose Do302 can be more than twice the dose Do301, more than ten times the dose Do301, or even more than one hundred times the dose Do301.

[0172] The doping concentration peak in the second region 302 is larger than that in the first region 301. In this example, the peak concentration P302 is larger than the peak concentration P301. The peak concentration P301 can be more than twice, more than ten times, or more than one hundred times that of the peak concentration P302.

[0173] Figure 10 This diagram illustrates other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63. In this example, as with... Figure 8 In some different configuration examples, the second stage 62 and the third stage 63 have multiple accumulation regions 16 in the depth direction. The multiple accumulation regions 16 in the second stage 62, etc., can have regions with lower doping concentrations than the accumulation regions 16 interspersed with each other; for example, N-type regions can be interspersed with each other similarly to the drift region 18. In other examples, the region between the multiple accumulation regions 16 can have a higher doping concentration than the drift region 18. The first region 301 of the first stage 61, the second region 302 of the second stage 62, and the third region 303 of the third stage 63 each have one or more peaks of doping concentration in the depth direction.

[0174] In this example, the second region 302 of the second faceplate 62 has a greater number of accumulation regions 16 than the first region 301 of the first faceplate 61. Figure 10 In this example, the first region 301 has one accumulation region 16, and the second region 302 has two accumulation regions 16. That is, the second region 302 in this example has two peaks of doping concentration.

[0175] Figure 11 It is shown Figure 10 A diagram illustrating an example of the doping concentration distribution at the r-r' and s-s' lines. In the second region 302, one doping concentration P302-1 and another doping concentration P302-2 can be the same or different.

[0176] The integrated concentration of the first conductivity type dopant in the second region 302 is greater than the integrated concentration of the first conductivity type dopant in the first region 301. It can be said that the dose Do302 is greater than the dose Do301. The dose Do302 can be more than twice the dose Do301, more than ten times the dose Do301, or even more than one hundred times the dose Do301.

[0177] The doping concentration peak in the second region 302 can be equal to or larger than the doping concentration peak in the first region 301. In this example, peak concentration P302 is equal to peak concentration P301. Peak concentration P301 can be more than 1 times, more than 2 times, more than 10 times, or more than 100 times that of peak concentration P302. The number of peaks P302-1 and P302-2 in the second region 302 is greater than the number of peaks P301 in the first region 301.

[0178] Figure 12 This diagram illustrates other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63. In this example, as with... Figure 10 Unlike other configurations, the first facet 61 also has multiple accumulation regions 16 in the depth direction. The multiple accumulation regions 16 in the first facet 61 can have regions with lower doping concentrations than the accumulation regions 16 interspersed with each other, for example, N-type regions can be interspersed with each other in the same way as the drift region 18.

[0179] In other examples, the region between multiple accumulation regions 16 may have a higher doping concentration than the drift region 18. The first region 301 of the first facet 61, the second region 302 of the second facet 62, and the third region 303 of the third facet 63 each have multiple peaks of doping concentration in the depth direction.

[0180] In this example, the second region 302 of the second faceplate 62 has the same number of accumulation regions 16 as the first region 301 of the first faceplate 61. Figure 12 In this example, the first region 301 and the second region 302 each have two accumulation regions 16. That is, in this example, the first region 301 and the second region 302 each have two peaks of doping concentration. In this example, the first region 301 has two N-type accumulation regions 16, and the second region 302 has two N+ type accumulation regions 16.

[0181] Figure 13 It is shown Figure 10A diagram illustrating an example of the doping concentration distribution at the r-r' and s-s' lines. In the first region 301, one doping concentration P301-1 and another doping concentration P301-2 can be the same or different. Similarly, in the second region 302, one doping concentration P302-1 and another doping concentration P302-2 can be the same or different.

[0182] The integrated concentration of the first conductivity type dopant in the second region 302 is greater than the integrated concentration of the first conductivity type dopant in the first region 301. It can be said that the dose Do302 is greater than the dose Do301. The dose Do302 can be more than twice the dose Do301, more than ten times the dose Do301, or even more than one hundred times the dose Do301.

[0183] The doping concentration peak in the second region 302 is larger than that in the first region 301. In this example, peak concentrations P302-1 and P302-2 are both larger than each of peak concentrations P301-1 and P301-2. Peak concentrations P302-1 and P302-2 can be more than twice, more than ten times, or more than one hundred times the peak concentrations P301-1 and P301-2.

[0184] Figure 14 This diagram illustrates other configuration examples of the first faceplate 61, the second faceplate 62, and the third faceplate 63. In this example, as with... Figure 10 The difference in the configuration is that the second region 302 in the second face 62 and the third region 303 in the third face 63 have an accumulation area 16 that is relatively wider in the depth direction compared to the first region 301 in the first face 61.

[0185] In this example, the second region 302 and the first region 301 both include accumulation regions 16 with the same doping concentration. The depth-direction width of the accumulation region 16 in the second region 302 is greater than the depth-direction width of the accumulation region 16 in the first region 301.

[0186] Figure 15 It is shown Figure 14 A diagram illustrating an example of the doping concentration distribution at the r-r' and s-s' lines. The integrated concentration of the first conductivity type dopant in the second region 302 is greater than the integrated concentration of the first conductivity type dopant in the first region 301. It can be said that the dose Do302 is greater than the dose Do301. The dose Do302 can be more than twice the dose Do301, more than ten times the dose Do301, or more than one hundred times the dose Do301.

[0187] Figure 16 It is shown Figure 2 Figures show other examples of the ee section. The semiconductor device 100 in this example uses... Figures 1 to 15 The difference between the semiconductor device 100 in the various embodiments described is that the semiconductor substrate 10 does not have a lifetime control region 206. Other structures and uses in the semiconductor device 100 of this example are similar. Figures 1 to 15 The corresponding structures in the semiconductor device 100 in the various embodiments described are the same, and corresponding reference numerals are used, omitting repeated descriptions.

[0188] exist Figure 16 In, it is shown that from Figure 3 The example shown has removed the lifetime control region 206, but in the structures shown in other figures, the lifetime control region 206 can also be removed.

[0189] Figure 17 It is shown Figure 2 Figures show other examples of the ee section. The semiconductor device 100 in this example uses... Figures 1 to 16 The difference between the semiconductor device 100 in the described embodiments is that the semiconductor substrate 10 has a lifetime control region 206 across its entire surface, and the lifetime control region 206 is continuously provided at the same depth in the transistor portion 70 and the diode portion 80. Other structures and uses in the semiconductor device 100 of this example are similar. Figures 1 to 16 The corresponding structures in the semiconductor device 100 in the various embodiments described are the same, and corresponding reference numerals are used, omitting repeated descriptions.

[0190] exist Figure 17 In China, according to Figure 3 The structure shown illustrates an example where the semiconductor substrate 10 has a lifetime control region 206 across its entire surface, and the lifetime control region 206 is continuously provided at the same depth in the transistor section 70 and the diode section 80. However, in the structures shown in other figures, the lifetime control region 206 may also be provided across its entire surface, and the lifetime control region 206 may be continuously provided at the same depth in the transistor section 70 and the diode section 80.

[0191] Figure 18 yes Figure 1 Other examples of enlarged views of region D in this example. The semiconductor device 100 in this example uses... Figures 1 to 17 The difference between the semiconductor device 100 in the various embodiments described is that the boundary region 200 is a mesa 60. Other structures and uses in the semiconductor device 100 of this example are similar. Figures 1 to 17 The corresponding structures in the semiconductor device 100 in the various embodiments described are the same, and corresponding reference numerals are used, omitting repeated descriptions.

[0192] exist Figure 18 In China, according to Figure 2 The structure shown illustrates an example where the boundary region 200 is a single facet 60, but in other structures shown, the boundary region 200 may also have a single facet 60. Furthermore, in this example, the contact area 15 and the base area 14 are alternately arranged along the Y direction in the facet 60 of the boundary region 200. As in this example, when viewed from above, the contact area 15 may not be provided on the entire surface of the region sandwiched by the base areas 14-e, but rather only partially. It should be noted that in cases where the boundary region 200 has two or more facets 60, other than in this example, it may also have a facet 60 with a partially provided contact area 15. On the other hand, in this example, when viewed from above, the contact area 15 may be provided on the entire surface of the region sandwiched by the base areas 14-e.

[0193] Figure 19 yes Figure 1 Other examples of enlarged views of region D in this example. The semiconductor device 100 in this example has multiple mesa sections 60 in the boundary region 200. The semiconductor device 100 in this example is used with... Figures 1 to 18 The semiconductor device 100 in the described embodiments differs in that a portion of the mesa 60 in the boundary region 200 that is in contact with the front surface 21 of the semiconductor substrate 10 and adjacent to the transistor portion 70 has a contact region 15, while the remaining mesa 60 has a base region 14 but no contact region 15. Here, having a base region 14 but no contact region 15 may include having a contact region 15 only in the region sandwiched by the base region 14-e when viewed from above, at the end adjacent to the base region 14-e; or, it may include having a base region 14 but no contact region 15 on the entire surface.

[0194] Other structures and uses in the semiconductor device 100 in this example Figures 1 to 18 The corresponding structures in the semiconductor device 100 in the various embodiments described are the same, and corresponding reference numerals are used, omitting repeated descriptions.

[0195] exist Figure 19 In China, according to Figure 2The structure shown illustrates an example where the mesa portion 60 in the boundary region 200, which is in contact with the front surface 21 of the semiconductor substrate 10 and adjacent to the transistor portion 70, has a contact region 15. Other mesa portions 60 have a base region 14 but no contact region 15. However, in other structures shown, the upper surface of the boundary region 200 may have a contact region 15 on a portion of the mesa portion 60 adjacent to the transistor portion 70, while other mesa portions 60 may have a base region 14 but no contact region 15. Furthermore, when viewed from above, the boundary region 200 may consist only of mesa portions 60 that have a base region 14 but no contact region 15 in the region sandwiched by the base regions 14-e.

[0196] Figure 20 It is shown Figure 19 The diagram shows an example of the ee cross-section. In this example, in the boundary region 200, a plurality of fourth facets 64 are provided in the X-axis direction. A contact region 15 is provided on the fourth facet 64 adjacent to the second transistor region 202, in a manner that contacts the front surface 21 of the semiconductor substrate 10. A base region 14 is provided between the contact region 15 and the drift region 18. Additionally, in this example, a base region 14 is provided on the fourth facet 64 of the boundary region 200 that is not adjacent to the second transistor region 202, in a manner that contacts the front surface 21 of the semiconductor substrate 10. The base region 14 is in contact with the drift region 18.

[0197] In this example, multiple fourth faces 64, with Figure 3 Similarly, the structure shown has a fourth region 304 of a first conductivity type disposed between the depth position of the lower end of the base region 14 and the depth position of the lower end of the trench portion. An accumulation region 16 is included in the fourth region 304. The doping concentration of the fourth region 304 of the first conductivity type of the fourth platform 64 is higher than the doping concentration of the first region 301 of the first conductivity type of the first platform 61.

[0198] By providing multiple fourth facets 64 in the X-axis direction in the boundary region 200 of this example, the influence of the transistor section 70 on the characteristics of the diode section 80 can be suppressed. For example, the influence of the operation of the gate trench section 40 and the discharge or injection of holes in the contact region 15 on the forward voltage and reverse recovery characteristics can be suppressed.

[0199] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As will be clearly understood from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0200] It should be noted that the execution order of actions, sequences, steps, stages, etc., in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, as long as there is no specific indication of "before" or "before," and as long as the output of the previous process is not used in the later process. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly," "next," etc., for convenience, it does not mean that they must be implemented in that order.

Claims

1. A semiconductor device, characterized in that, It is a semiconductor device comprising a transistor section and a diode section, and includes: A drift region of the first conductivity type is disposed on a semiconductor substrate; Multiple trench portions extend along a predetermined trench extension direction on the front side of the semiconductor substrate; The base region of the second conductivity type is disposed above the drift region; The emitter region of the first conductivity type is disposed on the front side of the semiconductor substrate and has a higher doping concentration than the drift region. as well as The contact region of the second conductivity type is disposed above the drift region and has a higher doping concentration than the base region. The plurality of trench portions include gate trench portions. The transistor section has: The first transistor region includes the emitter region and the gate trench portion; as well as The second transistor region includes the emitter region and the gate trench portion, and is disposed between the first transistor region and the diode portion. The first surface portion of the first transistor region has a first region of a first conductivity type disposed between a depth position at the lower end of the base region and a depth position at the lower end of the trench portion. The second facet of the second transistor region has a second region of a first conductivity type. The second region of the first conductivity type is located between the depth of the lower end of the base region and the depth of the lower end of the trench, and the doping concentration is higher than that of the first region.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes an accumulation region of a first conductivity type, which is disposed above the drift region and has a higher doping concentration than the drift region. The accumulation region extends from the second facet of the second transistor region to the third facet of the diode region.

3. The semiconductor device according to claim 1, characterized in that, The transistor section has a boundary region that is disposed closer to the ground than the second transistor region and the diode section.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device includes an accumulation region of a first conductivity type, which is disposed above the drift region and has a higher doping concentration than the drift region. The accumulation region extends from the second facet of the second transistor region to the fourth facet of the boundary region.

5. The semiconductor device according to claim 4, characterized in that, The front side of the semiconductor substrate in the boundary region is the contact area.

6. The semiconductor device according to claim 1, characterized in that, The first region is the drift region.

7. The semiconductor device according to claim 1, characterized in that, The peak of doping concentration in the second region is larger than that in the first region.

8. The semiconductor device according to claim 1, characterized in that, The number of peaks with doping concentration in the second region is greater than the number of peaks with doping concentration in the first region.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes an accumulation region of a first conductivity type, which is disposed above the drift region and has a higher doping concentration than the drift region. The second region and the first region both include the accumulation region with the same doping concentration. The width of the accumulation zone in the second region in the depth direction is greater than the width of the accumulation zone in the depth direction in the first region.

10. The semiconductor device according to claim 1, characterized in that, The integral concentration of the first conductivity type dopant in the second region is greater than the integral concentration of the first conductivity type dopant in the first region.

11. The semiconductor device according to claim 1, characterized in that, The diode section has an anode region of a second conductivity type disposed above the drift region. The third portion of the diode has a third region of a first conductivity type located between the depth position at the lower end of the anode region and the depth position at the lower end of the trench portion. The third region has a first conductivity type with a higher doping concentration than the drift region.

12. The semiconductor device according to claim 11, characterized in that, The doping concentration of the anode region is greater than or equal to the doping concentration of the base region.

13. The semiconductor device according to claim 11, characterized in that, The doping concentration of the anode region is the same as that of the base region.

14. The semiconductor device according to claim 1, characterized in that, The semiconductor device includes a lifetime control region, which is located in the depth direction of the semiconductor substrate at a position closer to the front side than the center of the semiconductor substrate.

15. The semiconductor device according to claim 14, characterized in that, The lifetime control region extends from the diode portion to the second transistor portion.

16. The semiconductor device according to claim 14, characterized in that, The semiconductor device includes an accumulation region of a first conductivity type, which is disposed above the drift region and has a higher doping concentration than the drift region. The lifespan control zone is located below the accumulation zone.

17. The semiconductor device according to claim 14, characterized in that, The second transistor region is an adjustment region in which the lifetime control region is located. The first transistor region is a non-adjustment region where the lifetime control region is not configured.

18. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate does not have a lifetime control region.

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