Laterally expanded transistor structure for minimizing sub-threshold hump effect

Abstract

The semiconductor structure may include a substrate, an active region formed on the substrate, a gate region extending on the active region in a first direction parallel to a surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction. The source region may include a first sub-region and a second sub-region such that the second sub-region is between the first sub-region and the gate region. The first sub-region may include a first width in the first direction and the second sub-region may include a second width in the first direction. The first width may be less than the second width.

Description

Technical Field

[0001] This disclosure relates generally to semiconductor manufacturing, and more particularly to the manufacture and use of laterally extended (e.g., cross-shaped) metal-oxide-semiconductor field-effect transistors (MOSFETs) to minimize the subthreshold hump effect present in the MOSFET. Background Technology

[0002] Semiconductor device fabrication is the process used to create integrated circuits that are found in many electrical and electronic devices. It is a multi-step sequence of photolithography, mechanical, and chemical processing steps during which electronic circuits are gradually created on a wafer made of semiconductor material. For example, during semiconductor device fabrication, many discrete circuit components, including transistors, resistors, capacitors, inductors, and diodes, can be formed on a single semiconductor die.

[0003] A transistor is a semiconductor device with many applications. Generally, a transistor is a semiconductor device used to amplify or switch electronic signals and electrical power. It is made of semiconductor material and typically has at least three terminals for connection to external circuits. Typically, the voltage or current applied to one pair of transistor terminals controls the current through the other pair of terminals. A common type of transistor is the metal-oxide-semiconductor field-effect transistor (MOSFET). A typical MOSFET includes an insulated gate, the voltage of which determines the conductivity of the device, as seen between the device's two other non-gate terminals (called the drain and source terminals). The ability of a MOSFET to change its conductivity with the amount of voltage applied allows it to be used to amplify or switch electronic signals.

[0004] A particular problem with MOSFETs can be termed the subthreshold hump effect. This effect stems from the shallow-trench isolation (STI) process used in MOSFET manufacturing, where divots can appear along the edges of the MOSFET's active region. The presence of these divots can cause inhomogeneities along the polysilicon and STI edges, resulting in parasitic transistors within the MOSFET having lower threshold voltages than the core transistor. Both the parasitic transistor and the core transistor can contribute to the MOSFET's total drain current. Due to the smaller threshold voltage of the parasitic transistor, the resulting MOSFET drain current versus gate-to-source voltage curve may exhibit a "hump" (i.e., a "subthreshold hump") at the smaller gate-to-source voltage in the subthreshold region of the MOSFET. Subthreshold humps can lead to higher drain current, local mismatches, and undesirable noise behavior in analog circuits. Therefore, it may be desirable to reduce or eliminate this subthreshold hump effect. Summary of the Invention

[0005] Based on the teachings of this disclosure, some of the disadvantages and problems associated with existing methods of manufacturing MOSFETs can be reduced or eliminated.

[0006] According to embodiments of this disclosure, a semiconductor structure may include a substrate, an active region formed on the substrate, a gate region extending on the active region along a first direction parallel to the surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction. The source region may include a first sub-region and a second sub-region, such that the second sub-region is located between the first sub-region and the gate region. The first sub-region may include a first width along the first direction, and the second sub-region may include a second width along the first direction. The first width may be smaller than the second width.

[0007] According to these and other embodiments of the present disclosure, an integrated circuit may include a substrate and transistors on the substrate. The transistors may include an active region formed on the substrate, a gate region extending over the active region along a first direction parallel to a surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction. The source region may include a first sub-region and a second sub-region, such that the second sub-region is located between the first sub-region and the gate region. The first sub-region may include a first width along the first direction, and the second sub-region may include a second width along the first direction. The first width may be smaller than the second width.

[0008] According to these and other embodiments of the present disclosure, a semiconductor chip may include a substrate, a first active region having a first width along a first direction parallel to the surface of the substrate, a gate extending over the first active region along the first direction, and a second active region formed on a surface adjacent to the first oxide diffusion region and having a second width along the first direction that is shorter than the first width.

[0009] According to these and other embodiments of the present disclosure, a method may include forming an active region on a substrate, forming a gate region extending over the active region along a first direction parallel to a surface of the substrate, and forming a source region within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein the source region includes a first sub-region and a second sub-region, such that the second sub-region is between the first sub-region and the gate region, the first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction, and the first width is less than the second width.

[0010] According to these and other embodiments of the present disclosure, a computer program product for implementing a semiconductor structure may include a substrate, an active region formed on the substrate, a gate region extending on the active region along a first direction parallel to a surface of the substrate, and a source region formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein the source region includes a first sub-region and a second sub-region, such that the second sub-region is between the first sub-region and the gate region, the first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction, and the first width is less than the second width. The computer program product includes a computer-usable medium having computer-readable code physically embodied therein, and the computer program product also includes computer-readable program code for describing the semiconductor structure.

[0011] The technical advantages of this disclosure will be readily apparent to those skilled in the art from the accompanying drawings, description, and claims included herein. The objects and advantages of the embodiments will be realized and achieved, at least by means of the elements, features, and combinations particularly pointed out in the claims.

[0012] It should be understood that both the foregoing general description and the following detailed description are illustrative examples and do not limit the claims set forth in this disclosure. Attached Figure Description

[0013] A more complete understanding of this embodiment and its advantages can be obtained from the following description taken in conjunction with the accompanying drawings, wherein similar reference numerals indicate similar features, and wherein:

[0014] Figure 1 A top-down plan view of a conventional MOSFET as known in the art is shown;

[0015] Figure 2 A top-down plan view of a laterally extended MOSFET according to an embodiment of the present disclosure is shown;

[0016] Figure 3 An embodiment according to this disclosure is shown. Figure 2 An example equivalent circuit diagram of a laterally extended MOSFET;

[0017] Figure 4 An embodiment according to this disclosure is shown. Figure 2 A top-down plan view of the laterally extended MOSFET, with some physical dimensions annotated;

[0018] Figure 5A and Figure 5B Embodiments according to this disclosure are shown respectively. Figure 2 Top-down plan view of the laterally extended MOSFET and Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0019] Figure 6A and Figure 6B Embodiments according to this disclosure are shown respectively. Figure 2 Top-down plan view of the laterally extended MOSFET and Figure 2 Another cross-sectional side view of the laterally extended MOSFET;

[0020] Figure 7A and Figure 7B Embodiments according to this disclosure are shown respectively. Figure 2 Top-down plan view of the laterally extended MOSFET and Figure 2 Another cross-sectional side view of the laterally extended MOSFET;

[0021] Figure 8A and Figure 8B Embodiments according to this disclosure are shown respectively. Figure 2 Top-down plan view of the laterally extended MOSFET and Figure 2 Another cross-sectional side view of the laterally extended MOSFET;

[0022] Figure 9 A top-down plan view of a tapered, laterally extended MOSFET according to an embodiment of the present disclosure is shown;

[0023] Figure 10 A top-down plan view of a MOSFET having two gate sub-regions with lateral extensions according to an embodiment of the present disclosure is shown.

[0024] Figure 11A , Figure 11B and Figure 11C Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of a laterally extended MOSFET during the first step of the manufacturing process. Figure 2 A first cross-sectional side view of a laterally extended MOSFET and during the first step of the manufacturing process. Figure 2 A second cross-sectional side view of a laterally extended MOSFET;

[0025] Figure 12A and Figure 12B Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of the laterally extended MOSFET and during the second step of the manufacturing process. Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0026] Figure 13A and Figure 13B Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of the laterally extended MOSFET and during the third step of the manufacturing process. Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0027] Figure 14A and Figure 14B Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of the laterally extended MOSFET and during the alternative third step of the manufacturing process. Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0028] Figure 15A and Figure 15B Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of the laterally extended MOSFET and during the fourth step of the manufacturing process. Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0029] Figure 16A and Figure 16B Embodiments according to this disclosure are shown respectively. Figure 2 A top-down plan view of the laterally extended MOSFET and during the fifth step of the manufacturing process. Figure 2 A cross-sectional side view of a laterally extended MOSFET;

[0030] Figure 17 A block diagram of an example circuit design system according to an embodiment of the present disclosure is shown;

[0031] Figure 18 A block diagram of a synthesis software tool according to an embodiment of the present disclosure is shown; and

[0032] Figure 19 A flowchart is shown of an example method for designing MOSFET composite integrated circuits as illustrated and described herein, according to this disclosure. Detailed Implementation

[0033] Figure 1 A top-down plan view of a conventional MOSFET 100, as known in the art, is shown. Figure 1 As shown, MOSFET 100 may include an active region 102 formed in a semiconductor substrate (e.g., a silicon wafer), wherein a gate 104 is formed on a portion of the active region 102, and one or more vias 106 are formed on the active region 102 and the gate 104, thereby dividing the active region 102 into a drain region 108, a source region 110, and a channel region 112. In MOSFET 100, the width of the channel region 112 (e.g., in...) Figure 1 The width of the drain region 108 and / or the source region 110 (as depicted on the x-axis) can be approximately equal to the width of the drain region 108 and / or the source region 110. The MOSFET 100 can be formed using an STI process, resulting in a parasitic transistor 116 existing in a recess created by the STI process, in addition to the core transistor 114, as described in the background section.

[0034] Figure 2 A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown. Figure 2 As shown, the MOSFET 200 may include a laterally extended active region 202 formed in a semiconductor substrate (e.g., a silicon wafer), wherein a gate 204 is formed on the active region 202, and one or more vias 206 are formed on the active region 202 and the gate 204, thereby dividing the active region 202 into a drain region 208, a source region 210 and a channel region 212.

[0035] MOSFET 200 can be formed using an STI process, resulting in a parasitic transistor 216 existing in a recess created by the STI process, in addition to the core transistor 214. However, compared to MOSFET 100, the parasitic transistor 216 of MOSFET 200 can be laterally spaced from the core transistor 214 (e.g., compared to the spacing between parasitic transistor 116 and core transistor 114 in MOSFET 100). This additional lateral distance created by the laterally extended active region 202 may introduce additional resistance between the source region 210 / drain region 208 and the channel region 212 of the parasitic transistor 216 (as compared to MOSFET 100), as... Figure 2 The annotation for resistor 218 is shown above.

[0036] Figure 3 An example equivalent circuit diagram 300 of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown. Figure 3 As shown, the laterally extended MOSFET 200 can be represented by each of two combinations connected in parallel: a core transistor 214 in series with resistor 218, a parasitic transistor 216, and another resistor 218. Therefore, the path shown for the parasitic transistor 216 includes a resistor (represented by resistor 218) that might not be present in a conventional MOSFET 100. Consequently, the gate-source voltage V across the parasitic transistor 216... GS_PARA It can be less than the gate-source voltage V across the core transistor 214. GS_CORE This means that the drain current of MOSFET 200 contributed by parasitic transistor 216 can be reduced (e.g., compared to the drain current of MOSFET 100 contributed by parasitic transistor 116), which can reduce (e.g., compared to MOSFET 100) or eliminate subthreshold bumps in MOSFET 200.

[0037] Figure 4 A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of this disclosure is shown, with some physical dimensions annotated. (See figure.) Figure 4 As shown, the source region 210 may include at least two sub-regions 222 and 224, wherein sub-region 222 is further away from the channel region 212 than sub-region 224. Figure 4 As shown, sub-region 222 can have a width W S1 and length L S1 Subregion 224 can have a width W S2 >W S1 and length L S2 In some cases, sub-region 224 may contact channel region 212, and therefore its width W S2It can be equal to the width W of the channel region 212. CHANNEL And W S1 <W CHANNEL .

[0038] In some embodiments, in order to provide maximum resistance in the path of parasitic transistor 216, Furthermore, in some embodiments, the distance represents the distance on the x-axis between the edges of sub-regions 222 and 224. It can be sized such that This is to provide sufficient physical layout squares for a given chip resistance (e.g., ohms per layout square) in the active region 202. For example, in some instances, for a typical silicide chip resistance of approximately 10 ohms / square, the distance... It may need to be several times the length L S2 (For example, This is to provide a sufficient number of squares to generate enough resistance in the path of the parasitic transistor 216. As another example, in these and other instances, based on the doping density of the active region 202, the distance... and / or length L S2 It may need to be larger than the surface depletion width of the active region (e.g., such as and / or (using existing process technology specifications and device dimensions) in order to separate the channel region of parasitic transistor 216 from the edge of sub-region 222.

[0039] In some embodiments, in order to provide maximum resistance along the path of parasitic transistor 216, sub-region 224 must be more resistive along the x-direction than sub-region 222 along the y-direction. For example, it may be necessary to or Either or both of them are used to ensure that subregion 224 has more layout squares than subregion 222.

[0040] In these and other embodiments, in order to provide maximum resistance along the path of parasitic transistor 216, sub-region 224 must be more resistive along the x-direction than the entire source region 210 along the y-direction. For example, it may be necessary to This ensures that subregion 224 has a layout squared size that is larger than the entire source region 210.

[0041] In some embodiments, the drain region 208 may have its own subregions of similar or the same size as those described above with respect to the source region 210.

[0042] Figure 5A A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown, and Figure 5BThe following is illustrated according to an embodiment of the present disclosure. Figure 5A A cross-sectional side view of the laterally extended MOSFET 200, taken along line A'. It is worth noting that... Figure 5B An STI 502 made of silicon oxide (SiO) is depicted, which is formed on the surface of substrate 501 adjacent to the channel region 212 of active region 202, which may leave a recess 506 in the channel region 212 along the edge of active region 202. In some embodiments, substrate 501 and active region 202 may be made of the same material, such as silicon. Figure 5B A gate oxide 504 is also depicted between the electrode of the gate 204 and the channel region 212 to provide dielectric insulation between the gate 204 and the channel region 212. Figure 5B The diagram further depicts a gate spacer 510 formed adjacent to the gate 204, a dielectric layer 508 formed on the gate 204 and the gate spacer 510, and a via 206 formed in the dielectric layer 508 to provide an electrical connection to the gate 204.

[0043] Figure 6A A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown, and Figure 6B The following is illustrated according to an embodiment of the present disclosure. Figure 6A A cross-sectional side view of the laterally extended MOSFET 200, taken at B-B'. (See attached image.) Figure 6B As shown, the silicide layer 602 can be formed on the source region 210 of the active region 202.

[0044] Figure 7A A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown, and Figure 7B The following is illustrated according to an embodiment of the present disclosure. Figure 7A A cross-sectional side view of the laterally extended MOSFET 200, taken at C-C'. (See attached image.) Figure 7B As shown, a silicide layer 602 can be formed on the source region 210 of the active region 202, and a via 206 can be formed in the dielectric layer 508 to electrically couple to the silicide layer 602 in order to provide an electrical connection with the channel region 212.

[0045] Figure 8A A top-down plan view of a laterally extended MOSFET 200 according to an embodiment of the present disclosure is shown, and Figure 8B The following is illustrated according to an embodiment of the present disclosure. Figure 8A A cross-sectional side view of the laterally extended MOSFET 200, taken from the D-D' section. (See attached image.) Figure 8BAs shown, gate oxide 504 may be present between the electrode of gate 204 and channel region 212 to provide dielectric insulation between gate 204 and channel region 212. Figure 8B The gate spacer 510 formed adjacent to the gate 204 and the silicide layer 602 formed on the source region 210 and the drain region 208 are further depicted. Figure 8B Also shown are source doping 802 in source region 210 and drain doping 804 in drain region 208. Figure 8B Also shown is a dielectric layer 508 formed on the gate 204, gate spacer 510, source region 210, and drain region 208, and a via 206 formed within the dielectric layer 508 to provide electrical connections to the source region 210 and drain region 208. Furthermore, Figure 8B The formation of a lightly-doped drain (LDD) layer 806 beneath the gate spacer 510 is depicted.

[0046] Above Figures 5A to 8B In the various views depicted, some portions of the laterally extended MOSFET 200 may not be shown for clarity and illustrative purposes.

[0047] Figure 9 A top-down plan view of a tapered, laterally extended MOSFET 900 according to an embodiment of the present disclosure is shown. Figure 9 As shown, the MOSFET 900 may include a laterally extended active region 902 formed in a semiconductor substrate (e.g., a silicon wafer), wherein a gate 904 is formed on the intersection of the active region 902, and one or more vias 906 are formed on the active region 902 and the gate 904, thereby dividing the active region 902 into a drain region 908, a source region 910 and a channel region 912.

[0048] MOSFET 900 may be similar to the laterally extended MOSFET 200 in many respects, but the difference lies in that the source region 910 may include three or more sub-regions 922, 924, and 926, where, for example, sub-region 926 may be closer to the channel region 912 than sub-region 924, and sub-region 924 may be closer to sub-region 922. Although for clarity and illustrative purposes, the source region 910... Figure 9 The region is shown as having three subregions 922, 924 and 926, but the source region 910 may include four or more subregions.

[0049] For example Figure 9 As shown, in some embodiments, some sub-regions of the source region 910 (e.g., sub-regions 924 and 926) may have a trapezoidal or conical shape. For example, sub-region 924 may have a width W on one edge.S2 The width gradually narrows to the width W of sub-region 922. S1 Furthermore, subregion 926 can have a width W on one edge. S3 The width gradually tapers to the width W of the sub-region 924. S2 One advantage of this tapered shape is that it avoids sharp edges (e.g., 90° edges) between adjacent sub-regions and / or between a sub-region (e.g., sub-region 926) and the channel region 912. Sharp 90° edges can lead to high local electric fields, which can reduce the lifetime of the MOSFET 900. In these and other embodiments, the sub-region closest to the channel region 912 (e.g., sub-region 926) can have a width (e.g., width W) on one edge. S3 ), which is equal to the width W of the channel region 912. CHANNEL .

[0050] Otherwise, in some embodiments, the various features of the tapered laterally extended MOSFET 900 may be the same as or similar to those of the laterally extended MOSFET 200. In these and other embodiments, the drain region 908 may have the same characteristics as described above with respect to the source region 910. Figure 9 The examples shown are those sub-regions of similar or identical size.

[0051] Figure 10 A top-down plan view of a MOSFET 1000 having two gate sub-regions 1004a and 1004b, according to an embodiment of the present disclosure, is shown. Figure 10 As shown, MOSFET 1000 may include a laterally extended active region 1002 formed in a semiconductor substrate (e.g., a silicon wafer), wherein a gate 1004 having two sub-regions 1004a and 1004b is formed on the active region 1002, and one or more vias 1006 are formed on the active region 1002 and the gate 1004, thereby dividing the active region 1002 into a drain region 1008, a source region 1010, and a channel region 1012. Similar to MOSFET 200, the source region 1010 of MOSFET 1000 may have multiple sub-regions (e.g., sub-regions 1022 and 1024). In these and other embodiments, the drain region 1008 may have the same characteristics as described above with respect to the source region 1010. Figure 10 The examples shown are those subregions of similar or identical size.

[0052] MOSFET 1000 may be similar to the laterally extended MOSFET 200 in many respects, but differs in that the gate 1004 may include two or more sub-regions 1004a and 1004b, wherein the gate sub-region 1004b is formed vertically (e.g., in the z-direction) on the parasitic transistor of MOSFET 1000 and on the STI near the active region 1002. Each gate sub-region 1004a, 1004b has different doping, so that the gate sub-regions 1004a and 1004b can have different work functions, providing different threshold capacitors for the core transistor and the parasitic transistor of MOSFET 1000. In some embodiments, the doping concentration of the gate sub-region 1004b may be less than that of the gate sub-region 1004a. In these and other embodiments, the gate sub-regions 1004a and 1004b may have different doping polarities. In these and other embodiments, via 1006 may overlap with both gate sub-region 1004a and gate sub-region 1004b so as to provide the same voltage to both gate sub-region 1004a and gate sub-region 1004b simultaneously.

[0053] like Figure 10 As shown, the gate sub-region 1004b may overlap with the sub-region 1024 of the source region 1010 along the x-direction, but may not overlap with the sub-region 1022 of the source region 1010 along the x-direction. Further as... Figure 10 As shown, the gate sub-region 1004a can have a length L G1 Furthermore, the gate sub-region 1004b can have a length L G2 ,in Additionally, the gate sub-region 1004b may have a width W that does not overlap with the active region 1002. G2A The width W overlapping with the active region 1002 G2B The width of the sum. In some embodiments, ,and ,in This represents the distance on the x-axis between the edges of subregions 1022 and 1024.

[0054] Figure 11A , Figure 11B and Figure 11C The following are top-down plan views of a laterally extended MOSFET 200 according to an embodiment of the present disclosure, shown during the first step of the manufacturing process. Figure 11A A first cross-sectional side view of the laterally extended MOSFET 200 taken from A-A' and during the first step of the manufacturing process. Figure 11A The second cross-sectional side view of the laterally extended MOSFET 200, taken from the D-D' section. (See attached image.) Figures 11A to 11C As shown, during this first step, a laterally extended active region 202 can be formed on the substrate (e.g., an oxide diffusion (OD) region including n-type and / or p-type regions is formed on substrate 501), and STI can be performed to form SiO 502 near the active region 202, leaving a recess 506 between the active region 202 and the SiO 502. A similar first step can also be used to fabricate the MOSFET 1000.

[0055] Figure 12A and Figure 12B The following are top-down plan views of a laterally extended MOSFET 200 according to an embodiment of the present disclosure and views of it during a second step of the manufacturing process. Figure 12A A cross-sectional side view of the laterally extended MOSFET200, taken from the D-D' section. (See attached image.) Figure 12A and Figure 12B As shown, during this second step, a gate structure can be formed on the intersection of the active region 202. This gate structure includes a gate 204, a gate oxide 504, and a gate spacer 510. A similar second step can also be used to fabricate the MOSFET 1000.

[0056] Figure 13A and Figure 13B The following are top-down plan views of a laterally extended MOSFET 200 according to an embodiment of the present disclosure, and views of it during the third step of the manufacturing process. Figure 13A A cross-sectional side view of the laterally extended MOSFET200, taken from the D-D' section. (See attached image.) Figure 13A and Figure 13B As shown, during this third step, the source region 210 can be doped with source dopant 802, the drain region 208 can be doped with drain dopant 804, and a lightly doped drain layer 806 can be formed on either side of the gate 204.

[0057] Figure 14A and Figure 14B The following are top-down plan views of a laterally extended MOSFET 1000 according to an embodiment of the present disclosure and during the alternative third step of the manufacturing process. Figure 14A A cross-sectional side view of the laterally extended MOSFET 1000, taken at E-E'. (See attached image.) Figure 14A and Figure 14BAs shown, during this third step of the alternative, the source region 1010 may be doped with source dopant 802, the drain region 1008 may be doped with drain dopant 804, and a lightly doped drain layer 806 may be formed on either side of the gate 1004. Simultaneously with the doping of the source region 1010 and the drain region 1008, a gate sub-region 1004b may also be formed. In some embodiments, the gate sub-region 1004b may be formed using a lightly doped drain layer of a MOSFET of opposite polarity on the substrate 501. For example, the MOSFET 1000 may be an n-channel MOSFET on the substrate 501, wherein a p-channel MOSFET formed on the substrate 501 may be used. Figure 14A and Figure 14B The gate sub-region 1004b of the n-channel MOSFET 1000 is formed using an LDD layer implantation process (not shown in the diagram). Similarly, as another example, the MOSFET 1000 can be a p-channel MOSFET on substrate 501, where an n-channel MOSFET (not shown in the diagram) can be formed on substrate 501. Figure 14A and Figure 14B The gate sub-region 1004b of the p-channel MOSFET 1000 is formed by implanting an LDD layer (not shown). This alternative third step can be used instead of the third step described above to manufacture the MOSFET 1000.

[0058] Figure 15A and Figure 15B The following are top-down plan views of a laterally extended MOSFET 200 according to an embodiment of the present disclosure and views of it during the fourth step of the manufacturing process. Figure 15A A cross-sectional side view of the laterally extended MOSFET200, taken from the D-D' section. (See attached image.) Figure 15A and Figure 15B As shown, during this fourth step, silicide 602 can be formed on the source region 210 and the drain region 208. A similar fourth step can also be used to fabricate the MOSFET 1000.

[0059] Figure 16A and Figure 16B The following are top-down plan views of a laterally extended MOSFET 200 according to an embodiment of the present disclosure and views of it during the fifth step of the manufacturing process. Figure 16A A cross-sectional side view of the laterally extended MOSFET200, taken from the D-D' section. (See attached image.) Figure 16A and Figure 16BAs shown, during this fifth step, via 206 can be formed to provide electrical coupling with gate 204, source region 210, and drain region 208, and dielectric 508 can be formed on the components of MOSFET 200 such that the via is formed within dielectric 508. A similar fifth step can also be used to manufacture MOSFET 1000.

[0060] although Figures 11A to 16B Specific steps in the manufacture of MOSFET 200 and MOSFET 1000 are shown, but steps other than those depicted can be used in the manufacture of MOSFET 200 and MOSFET 1000. Furthermore, compared to... Figures 11A to 16B Similar or identical steps can also be used in the manufacture of MOSFET 900.

[0061] Figure 17 A block diagram of an example circuit design system 1700 according to an embodiment of the present disclosure is shown. The circuit design system 1700 may be able to receive and synthesize, analyze, and / or optimize initial circuit designs including one or more of MOSFETs 200, 900, and / or 1000. The circuit design system 1700 may include any computing device, such as a computer having a processor 1702, a user interface 1704, and a memory device 1706.

[0062] Processor 1702 may include any system, device, or apparatus configured to interpret and / or execute program instructions and / or process data, and may include, but is not limited to, a microprocessor, microcontroller, digital signal processor (DSP), application-specific integrated circuit (ASIC), or any other digital or analog circuit configured to interpret and / or execute program instructions and / or process data. In some embodiments, processor 1702 may interpret and / or execute program instructions and / or process data stored in memory device 1706 and / or another component of circuit design system 1700.

[0063] Memory device 1706 may be communicatively coupled to processor 1702 and may include any system, device, or apparatus (e.g., computer-readable medium) configured to retain program instructions and / or data for a period of time. Memory device 1706 may include any suitable selection and / or array of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic storage devices, opto-magnetic storage devices, or volatile or non-volatile memory that retains data after the circuit design system 1700 is powered off. Memory device 1706 can store different types of instructions and / or data, including but not limited to one or more software modules 1708, which include executable instructions that can be executed by processor 1702 (e.g., circuit design synthesis, analysis, and / or optimization tools) to control processor 1702 to perform its various operations, input circuit design files 1710, output circuit design files 1712, circuit design specifications and constraints 1714, component libraries 1716, and / or other data, information, or instructions. One or more of the input circuit design files 1710, circuit design specifications and constraints 1714, and component libraries 1716 may include data and information for defining MOSFETs 200, 900, and / or 1000.

[0064] User interface 1704 may include any tools or set of tools through which a user can interact with circuit design system 1700. For example, user interface 1704 may allow a user to input data and / or instructions into circuit design system 1700, and / or otherwise manipulate circuit design system 1700 and its associated components (e.g., via keyboard, mouse, touchpad, or other pointing devices). User interface 1704 may also allow circuit design system 1700 to communicate data to the user, for example, through a display device.

[0065] Figure 18A block diagram of an example synthesis software tool 1800 according to an embodiment of the present disclosure is shown. The synthesis software tool 1800 may be stored as computer-readable instructions in a memory device 1706 and is readable and executable by a processor 1702 of a circuit design system 1700. The synthesis software tool 1800 may include a logic synthesizer module 1802, a clock tree synthesizer module 1804, and a timing verifier 1806. The logic synthesizer module 1802 may receive a high-level description language (HDL) or register transfer level (RTL) circuit description 1801 and a standard cell technology document 1803. Functional logic may be generated by the logic synthesizer module 1802 from the standard cell technology document 1803, including various MOSFETs 200, 900, and / or 1000 in the data path of the circuit description 1801. The standard cell technology document 1803 may include data and information for characterizing the MOSFETs 200, 900, and / or 1000 as one or more standard cells. Clock tree synthesizer module 1804 can generate clock tree paths in the integrated circuit from the clock source to various components, including various MOSFETs 200, 900, and / or 1000 in the data path. Timing verifier module 1806 can receive a netlist including the data path and clock tree path of the integrated circuit design to verify that the timing specifications meet the given logic design of the integrated circuit. Timing verifier module 1806 can verify that the timing specifications of the logic design are indeed met to output netlist 1808. Netlist 1808 can be sent to a foundry for manufacturing the integrated circuit described by netlist 1808.

[0066] Figure 19A flowchart of an example method 1900 for synthesizing an integrated circuit design using MOSFETs 200, 900, and / or 1000 according to the present disclosure is shown. Method 1900 can be embodied in instructions stored in memory device 1706 of circuit design system 1700 and read and executed by processor 1702. For example, method 1900 can be implemented by synthesis software tool 1800. According to method 1900, at block 1902, standard cell circuit design and layout for integrated circuit design can be provided to timing and noise characterization block 1906, and at block 1904, multi-bit cell circuit design and layout of an integrated circuit design including MOSFETs 200, 900, and / or 1000 according to the present disclosure can also be provided to timing and noise characterization block 1906. Timing and noise characterization block 1906 can provide timing and noise characterization of the integrated circuit design to logic synthesizer module 1802 at logic synthesizer processing block 1910. At the logic synthesizer processing block 1910, the logic synthesizer module 1802 can also be provided with characterizations of the laid-out standard cells and the laid-out multi-bit cells (including MOSFETs 200, 900, and / or 1000). The digital RTL behavioral model of block 1908 can be found in the RTL circuit description 1801 provided to the logic synthesizer processing block 1910. The RTL behavioral model of block 1908 can include, but is not limited to, digital signal processing (DSP) cores, peripheral blocks, and other digitally designable blocks. Furthermore, design constraints of block 1916, which can include, but are not limited to, various parameters used to characterize MOSFETs 200, 900, and / or 1000, can also be provided to the logic synthesizer processing block 1910. Within logic synthesizer processing block 1910, logic synthesizer 1802 synthesizes data and information related to the laid-out standard cells, laid-out multi-bit cells, timing and noise characterizations, various digital RTL behavioral models, and design constraints to provide a physical design layout. This leads to an RTL-to-Graphic Data System (GDS) digital design implementation at block 1912. GDS is a format that can be used to control the drawing of photomasks for integrated circuits. The RTL-to-GDS digital design implementation includes at least timing information and noise signature information. At block 1914, the GDS file containing the physical design layout information can be sent to the foundry for the generation of masks and semiconductor chips.

[0067] Those skilled in the art will recognize that one or more of the MOSFETs 200, 900 and / or 1000 can be integrated into an integrated circuit or semiconductor chip.

[0068] As used herein, when two or more elements are referred to as “coupled” to each other, the term indicates that the two or more elements are connected in electronic or mechanical communication (where applicable), whether indirectly or directly, with or without intervening elements.

[0069] This disclosure covers all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Similarly, where appropriate, the appended claims cover all changes, substitutions, variations, alterations, and modifications to the exemplary embodiments herein that will be understood by those skilled in the art. Furthermore, in the appended claims, references to means or systems adapted to, arranged to, capable of, configured to, enabled, operable to, or operated to perform a particular function cover such means, whether or not it or the particular function is activated, turned on, or unlocked, provided that the means, system, or component is so adapted, arranged, capable of, configured, enabled, operable, or operated. Therefore, modifications, additions, or omissions can be made to the systems, apparatuses, and methods described herein without departing from the scope of this disclosure. For example, components of systems and apparatuses can be integrated or separated. Furthermore, the operation of the systems and apparatuses disclosed herein can be performed by more, fewer, or other components, and the described methods can include more, fewer, or other steps. Additionally, steps can be performed in any suitable order. As used in this document, “each” means each member of a set or each member of a subset of a set.

[0070] Although exemplary embodiments are shown in the accompanying drawings and described below, the principles of this disclosure can be implemented using any number of techniques, whether currently known or not. This disclosure should not be limited in any way to the exemplary embodiments and techniques shown in the drawings and described above.

[0071] Unless otherwise specified, the items depicted in the drawings are not necessarily drawn to scale.

[0072] All examples and conditional language described herein are intended for educational purposes to aid the reader in understanding the contents of this disclosure and the concepts contributed by the inventors to further advance the art, and are not to be construed as being limited to these specific examples and conditions. Although embodiments of this disclosure have been described in detail, it should be understood that various changes, substitutions, and modifications can be made thereto without departing from the spirit and scope of this disclosure.

[0073] While specific advantages have been listed above, various embodiments may include some, none, or all of the listed advantages. Furthermore, other technical advantages may readily become apparent to those skilled in the art upon review of the foregoing figures and description.

[0074] To assist the Patent Office and any reader of any patent issued under this application in interpreting the appended claims, the applicants wish to draw attention to the fact that, unless the terms “means for…” or “steps for…” are expressly used in a particular claim, they do not intend any of the appended claims or claim elements to invoke 35 USC. 112(f).

Claims

1. A semiconductor structure, comprising: Substrate; An active region is formed on the substrate; A gate region that extends over the active region along a first direction parallel to the surface of the substrate; as well as A source region is formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein: The source region includes a first sub-region and a second sub-region, such that the second sub-region is located between the first sub-region and the gate region; The first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction; and The first width is smaller than the second width.

2. The semiconductor structure according to claim 1, further comprising a channel region formed in the active region between the substrate and the gate region, wherein: The channel area has a channel width along the first direction; and The width of the channel is substantially equal to the second width.

3. The semiconductor structure according to claim 1 or 2, wherein: The second sub-region includes a length along the second direction; The second sub-region extends beyond the third width of the first sub-region along the first direction; and The length is less than or equal to the third width.

4. The semiconductor structure according to claim 1 or 2, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and The second length is less than the first length.

5. The semiconductor structure according to claim 1 or 2, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and Wherein, the first ratio of the first length to the first width is less than or equal to the second ratio of the second width to the second length.

6. The semiconductor structure according to any one of claims 1 to 5, further comprising a drain region formed in the active structure in the second direction and adjacent to the gate region, wherein: The gate region is located between the source region and the drain region; The drain region includes a third sub-region and a fourth sub-region; The fourth sub-region is located between the third sub-region and the gate region; The third sub-region includes a third width along the first direction, and the fourth sub-region includes a fourth width along the first direction; and The third width is smaller than the fourth width.

7. The semiconductor structure according to any one of claims 1 to 6, wherein: The first portion of the gate structure has a first doping, and the second portion of the gate structure has a second doping; and The first doping is different from the second doping.

8. The semiconductor structure according to any one of claims 1 to 5, wherein: The source region also includes a third sub-region; The third sub-region is located between the first sub-region and the second sub-region; The first sub-region includes a first width along the first direction, the second sub-region includes a second width along the first direction, and the third sub-region includes a third width along the first direction; and The first width is smaller than the third width, and the third width is smaller than the second width.

9. The semiconductor structure according to claim 8, wherein, At least one of the first sub-region and the third sub-region forms a cone shape, wherein the width of such region varies in the first direction.

10. An integrated circuit, comprising: Substrate; as well as The transistors on the substrate include: An active region formed on the substrate; A gate region extending over the active region along a first direction parallel to the surface of the substrate; and A source region is formed within the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein: The source region includes a first sub-region and a second sub-region, such that the second sub-region is located between the first sub-region and the gate region; The first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction; and The first width is smaller than the second width.

11. The integrated circuit according to claim 10, wherein, The transistor further includes a channel region formed in the active region, wherein: The channel area has a channel width along the first direction; and The width of the channel is substantially equal to the second width.

12. The integrated circuit according to claim 10 or 11, wherein: The second sub-region includes a length along the second direction; The second sub-region extends beyond the third width of the first sub-region along the first direction; and The length is less than or equal to the third width.

13. The integrated circuit according to claim 10 or 11, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and The second length is less than the first length.

14. The integrated circuit according to claim 10 or 11, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and Wherein, the first ratio of the first length to the first width is less than or equal to the second ratio of the second width to the second length.

15. The integrated circuit according to any one of claims 10 to 14, wherein, The transistor further includes a drain region formed in the active region and adjacent to the gate region in the second direction, wherein: The gate region is located between the source region and the drain region; The drain region includes a third sub-region and a fourth sub-region; The fourth sub-region is located between the third sub-region and the gate region; The third sub-region includes a third width along the first direction, and the fourth sub-region includes a fourth width along the first direction; and The third width is smaller than the fourth width.

16. The integrated circuit according to any one of claims 10 to 15, wherein: The first portion of the gate region has a first doping, and the second portion of the gate region has a second doping; and The first doping is different from the second doping.

17. The integrated circuit according to any one of claims 10 to 14, wherein: The source region also includes a third sub-region; The third sub-region is located between the first sub-region and the second sub-region; The first sub-region includes a first width along the first direction, the second sub-region includes a second width along the first direction, and the third sub-region includes a third width along the first direction; and The first width is smaller than the third width, and the third width is smaller than the second width.

18. The integrated circuit according to claim 17, wherein, At least one of the first sub-region and the third sub-region forms a cone shape, wherein the width of such region varies in the first direction.

19. A semiconductor chip, comprising: Substrate; A first active region having a first width along a first direction parallel to the surface of the substrate; A gate that extends over the first active region along the first direction; as well as The second active region is formed on the surface adjacent to the first oxide diffusion region and has a second width along the first direction that is shorter than the first width.

20. The semiconductor chip of claim 19, further comprising a channel region formed in a first active region between the surface and the gate, wherein: The channel area has a channel width along the first direction; and The width of the channel is substantially equal to the first width.

21. The semiconductor chip according to claim 19 or 20, wherein: The first active region includes a length along the second direction; The first active region extends along the first direction beyond the third width of the second active region; and The length is less than or equal to the third width.

22. The semiconductor chip according to claim 19 or 20, wherein The first active region includes a first length along the second direction; The second active region includes a second length along the second direction; and The first length is less than the second length.

23. The semiconductor chip according to claim 19 or 20, wherein: The first oxide diffusion region includes a first length along the second direction; The second oxide diffusion region includes a second length along the second direction; and Wherein, the first ratio of the first length to the first width is greater than or equal to the second ratio of the second width to the second length.

24. The semiconductor chip of claim 23 further includes a third oxide diffusion region formed on a surface adjacent to the second oxide diffusion region and having a third width along the first direction that is shorter than the second width.

25. The semiconductor chip according to claim 24, wherein, At least one of the second oxide diffusion region and the third oxide diffusion region forms a conical shape, wherein the width of such region varies in the first direction.

26. A method comprising: An active region is formed on the substrate; A gate region is formed extending over the active region along a first direction parallel to the surface of the substrate; and A source region is formed in the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein: The source region includes a first sub-region and a second sub-region, such that the second sub-region is located between the first sub-region and the gate region; The first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction; and The first width is smaller than the second width.

27. The method of claim 26, further comprising forming a channel region in the active region between the substrate and the gate region, wherein: The channel area has a channel width along the first direction; and The width of the channel is substantially equal to the second width.

28. The method according to claim 26 or 27, wherein: The second sub-region includes a length along the second direction; The second sub-region extends beyond the third width of the first sub-region along the first direction; and The length is less than or equal to the third width.

29. The method according to claim 26 or 27, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and The second length is less than the first length.

30. The method according to claim 26 or 27, wherein: The first sub-region includes a first length along the second direction; The second sub-region includes a second length along the second direction; and Wherein, the first ratio of the first length to the first width is less than or equal to the second ratio of the second width to the second length.

31. The method according to any one of claims 26 to 30, further comprising forming a drain region in the active region and adjacent to the gate region in the second direction, wherein: The gate region is located between the source region and the drain region; The drain region includes a third sub-region and a fourth sub-region; The fourth sub-region is located between the third sub-region and the gate region; The third sub-region includes a third width along the first direction, and the fourth sub-region includes a fourth width along the first direction; and The third width is smaller than the fourth width.

32. The method according to any one of claims 26 to 31, wherein: The first portion of the gate region has a first doping, and the second portion of the gate region has a second doping; and The first doping is different from the second doping.

33. The method according to any one of claims 26 to 30, wherein: The source region also includes a third sub-region; The third sub-region is located between the first sub-region and the second sub-region; The first sub-region includes a first width along the first direction, the second sub-region includes a second width along the first direction, and the third sub-region includes a third width along the first direction; and The first width is smaller than the third width, and the third width is smaller than the second width.

34. The method according to claim 33, wherein, At least one of the first sub-region and the third sub-region forms a cone shape, wherein the width of such region varies in the first direction.

35. A computer program product for implementing a semiconductor structure, the semiconductor structure comprising: Substrate; An active region formed on the substrate; A gate region extending over the active region along a first direction parallel to the surface of the substrate; And a source region formed in the active region and adjacent to the gate region in a second direction parallel to the surface and perpendicular to the first direction, wherein the source region includes a first sub-region and a second sub-region, such that the second sub-region is between the first sub-region and the gate region, the first sub-region includes a first width along the first direction, and the second sub-region includes a second width along the first direction, and the first width is smaller than the second width, the computer program product includes a computer-usable medium having computer-readable code physically embodied therein, and the computer program product further includes computer-readable program code for describing the semiconductor structure.

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