Dummy cell design for nanosheet devices

Abstract

Various integrated circuit transistor device structures that implement nanosheet fin transistors are disclosed. A layout for a transistor device structure includes active cells, wherein dummy cells are positioned between the active cells. The active cell and the dummy cell may include nanosheet fin regions having different widths. In some examples, transitions (e.g., mutations in width) between different nanosheet fin region widths are positioned inside the dummy cell, rather than at the interface between the dummy cell and the active cell. Placing a mutation in width inside the dummy cell reduces the mechanical stress between the active cell and the dummy cell and allows design variations in the size of the active transistor during the manufacturing process.

Description

Technical Field

[0001] The embodiments described herein relate to transistor structures for semiconductor devices. More specifically, the embodiments described herein relate to the structure and design of integrated circuit devices having active nanosheet transistors and passive nanosheet transistors. Background Technology

[0002] Nanosheet (e.g., all-around gate) transistors are increasingly used in integrated circuits. Due to the increased gate control of the channel provided by the geometry of nanosheet transistor designs, nanosheet transistors can exhibit more efficient turn-on / turn-off transistor characteristics than planar FETs or FinFETs. This increased efficiency in turn-on or turn-off transistors can provide reduced leakage and better power utilization (e.g., voltage reduction) for integrated circuits utilizing nanosheet transistors. Nanosheet transistors can have more complex designs than planar FETs or FinFETs. As integrated circuit design evolves, more avenues for utilizing more complex nanosheet transistor designs are envisioned. Attached Figure Description

[0003] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood when taken in conjunction with the accompanying drawings, by referring to the following detailed description of the currently preferred, but only exemplary, embodiments according to which the present disclosure is described: Figure 1 A perspective representation of a nanosheet transistor according to some implementation schemes is depicted.

[0004] Figure 2 An end view representation of the trench area according to some implementation schemes is depicted.

[0005] Figure 3 A top plan view depicting an example layout of a transistor device having multiple active cells and dummy cells according to some embodiments, wherein the multiple active cells and dummy cells have nanosheet fin regions.

[0006] Figure 4 A top plan view depicts a contemplated layout of a transistor device with multiple active cells and dummy cells according to some embodiments, wherein some of the dummy nanosheet fin regions have different widths within the dummy cells.

[0007] Figure 5 The following describes the possible implementation schemes based on some schemes. Figure 4 The diagram shows a top plan view of a transistor device layout that implements a dummy gate structure that defines the boundary between active cells and dummy cells.

[0008] Figure 6The diagram depicts a top plan view representation of a contemplated transistor device layout according to several embodiments, some of which have had dummy gate structures moved to increase the initial based... Figure 4 The length of the active cell in the device layout.

[0009] Figure 7 This is a block diagram of one implementation of the example system.

[0010] While the embodiments disclosed herein are susceptible to various modifications and alternatives, specific embodiments of the invention are illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to cover all modifications, equivalents, and alternatives that fall within the substance and scope of the disclosure of this application as defined by the appended claims. Detailed Implementation

[0011] As used herein, the term "standard cell" refers to a set of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions for a variety of specific implementation standards. For example, a single standard cell may be one cell from a library of cells from which various suitable cells can be selected to implement a particular cell design. As a further example, a standard cell may be a cell design created (e.g., designed) and then implemented multiple times to produce an integrated circuit device via, for example, synthesis or automated processes. Integrated circuit cells may also include custom circuit design cells designed separately for a specific implementation. Implementations of the circuit design cells described herein can be implemented in various specific implementations of logic integrated circuits or memory integrated circuits.

[0012] Figure 1 A perspective representation of a nanosheet transistor according to some embodiments is depicted. In an illustrated embodiment, a nanosheet transistor 100 is formed on a substrate 150. In some embodiments, the transistor 100 includes a gate 110 and a channel region 120. The gate 110 may be a polysilicon gate or a metal gate. The channel region 120 includes nanosheet fins 130 and a substrate channel 140. The nanosheet fins 130 are fins made of silicon, another semiconductor, or a combination of semiconductors, that pass through the structure (e.g., material) of the gate 110. In various embodiments, the nanosheet fins 130 are relatively thin (in the vertical dimension) rectangular regions (e.g., sheets) of semiconductor material aligned parallel to the substrate 150 (e.g., the horizontal plane of the nanosheet fins 130 is parallel to the horizontal plane of the substrate 150). The transistor 100 typically includes a plurality of nanosheet fins 130 passing through the gate 110. For example, as Figure 1 As shown, transistor 100 includes three nanosheet fins 130 extending through gate 110.

[0013] In various embodiments, a substrate channel 140 is formed in a substrate 150 beneath the nanosheet fin 130. The substrate channel 140 can be formed by forming shallow trench isolation (STI) 145 on either side of the substrate channel in the substrate 150. Thus, the substrate channel 140 is the portion of the substrate 150 located between the STIs 145. In some embodiments, the substrate channel 140 is aligned with the nanosheet fin 130 and has similar horizontal dimensions (e.g., length or width) to the nanosheet fin. In some embodiments, the substrate channel 140 is made of the same semiconductor material as the nanosheet fin 130. For example, both the nanosheet fin 130 and the substrate channel 140 can be silicon.

[0014] Figure 2 An end view representation of a channel region 120 according to some embodiments is depicted. In an illustrated embodiment, the channel region 120 includes a nanofin 130 within a gate 110 above a substrate channel 140. In some embodiments, the gate 110 substantially surrounds (e.g., “fully surrounds”) the nanofin 130. It should be noted that at least some gate dielectric material (not shown) may be present between the nanofin 130 and the gate 110. Using the gate 110 to surround the nanofin 130 provides better control over gate operation and reduces current leakage from the gate, resulting in more efficient characteristics for turning the gate on and off.

[0015] Figure 3 A top plan view depicting an example layout of a transistor device having multiple active cells and dummy cells according to some embodiments, wherein the multiple active cells and dummy cells have nanosheet fin regions. The transistor device layout 300 has a cell height direction 302 (vertical direction in the figure) and a cell width direction 304 (horizontal direction in the figure). The device layout 300 includes active cells 310 and dummy cells 320. Active cells 310 may be, for example, cells actively involved in signal processing within the device. For example, active cells 310 may have connections (e.g., power or signal connections) to one or more gates within the cell.

[0016] Dummy cell 320 can be a cell in device layout 300 that does not participate in signal processing. For example, dummy cell 320 may not have any connection to the gate within the cell. In various embodiments, dummy cell 320 may be referred to as a passive cell or a filler cell. In some embodiments, such as Figure 3As shown, dummy cells 320 are positioned between active cells 310 in the cell width direction 304 to provide electrical isolation between the active cells. While dummy cells 320 may have similar channel regions, gate structures, or source / drain regions as active cells 310, there are no connections for signal processing to the gate structures or source / drain regions in the dummy cells. In some embodiments, in a specific implementation of the device based on device layout 300, a dummy gate structure 325 is placed at the boundary between the dummy cells 320 and the active cells 310. Active gate structures may be located inside the active cells 310, but are not shown in the figures for simplicity.

[0017] In various embodiments, the active unit 310 includes an active nanofin region 330, and the dummy unit 320 includes a dummy nanofin region 340. The active nanofin region 330 and the dummy nanofin region 340 may be formed of the same material, wherein the only difference between the nanofin regions is whether they are connected to a gate associated with the nanofin region (e.g., connected to a gate associated with the active nanofin region). In some embodiments, such as Figure 3 As shown, active nanofin regions 330 and dummy nanofin regions 340 are positioned along nanofin rows 350. The nanofin rows 350 may include consecutive rows of alternating active nanofin regions 330 and dummy nanofin regions 340. For example, the alternating active nanofin regions 330 and dummy nanofin regions 340 are adjacent to each other along the length of the row in the cell width direction 304, wherein dummy nanofin regions are positioned between active nanofin regions.

[0018] In some embodiments, active unit 310 and dummy unit 320 include combinations of active nanofin regions 330 and dummy nanofin regions 340 from a plurality of nanofin rows 350. For example, active unit 310 and dummy unit 320 may be units that include active nanofin regions 330 and dummy nanofin regions 340 in two nanofin rows 350 in each unit. For example, in an exemplary embodiment, active units 310A-310D and dummy units 320A-320C include active nanofin regions 330 and dummy nanofin regions 340 in both nanofin rows 350A and 350B, while active units 310E-310F and dummy unit 320D include active nanofin regions 330 and dummy nanofin regions 340 in both nanofin rows 350C and 350D.

[0019] It should be noted that, in the contemplated embodiments, the number of rows 350 of nanofin regions in the active unit 310 or dummy unit 320 may vary. For example, it is contemplated that the active unit 310 and dummy unit 320 include only one row of nanofin regions 350 having active nanofin regions 330 and dummy nanofin regions 340. Alternatively, it is contemplated that the active unit 310 and dummy unit 320 include three or more rows 350 of nanofin regions 330 and dummy nanofin regions 340.

[0020] In the illustrated embodiment, device layout 300 includes six active cells 310 (e.g., active cells 310A-310F) and four dummy cells 320 (e.g., dummy cells 320A-320D), which encompass four nanofin rows 350 (e.g., nanofin rows 350A, 350B, 350C, 350D) distributed along the cell height direction 302. As described above, each nanofin row 350 includes an alternating combination of active nanofin regions 330 and dummy nanofin regions 340 along the cell width direction 304. For example, nanofin row 350A includes four active nanofin regions 330A-330D, wherein three dummy nanofin regions 340A-340C separate the active nanofins along the cell width direction 304 (e.g., positioned between the active nanofin regions). In addition, each active unit 310 and each dummy unit 320 includes two nanosheet fin rows 350.

[0021] Therefore, active unit 310A includes both active nanofin region 330A in nanofin row 350A and active nanofin 330E in nanofin row 350B. Furthermore, dummy unit 320A includes both dummy nanofin region 340A in nanofin row 350A and dummy nanofin 340D in nanofin row 350B. Similarly, the remaining active units 310B-310F include two active nanofin regions 330 from two different nanofin rows 350, and the remaining dummy units 320B-320D include two dummy nanofin regions 340 from two different nanofin rows 350.

[0022] In various embodiments, in a specific implementation of a transistor device based on device layout 300, a dummy gate structure 325 is placed along the boundary between active cell 310 and dummy cell 320. The dummy gate structure 325 may be a gate structure that provides isolation between active cell 310 and dummy cell 320 and has no connection to a gate structure. For example, the dummy gate structure 325 may be an isolation structure between active cell 310 and dummy cell 320. In the illustrated embodiments, dummy gate structures 325A-325F are placed along the boundary between active cell 310 and dummy cell 320. Depending on device layout 300, the dummy gate structure 325 may include various lengths in the cell height direction 302. In some embodiments, dummy gate structures 325A and 325F are dummy gate structures extending along the cell height direction 302 to the boundaries of multiple active cells 310 and dummy cells 320 (e.g., dummy gate structure 325A extends along the boundary between active cell 310A and dummy cell 320A, and the boundary between active cell 310E and dummy cell 320D). Dummy gate structures 325B-325E are dummy gate structures for a single boundary between an active cell 310 and a dummy cell 320. For example, dummy gate structure 325B is positioned only along the boundary between active cell 310B and dummy cell 320A.

[0023] The characteristic that can be obtained by using nanofins in transistor devices is that, in addition to changing the length of the nanofin regions (note that the length of these regions is in the cell width direction 304), the width of the nanofin regions (note that the width of these regions is in the cell height direction 302) and the width of the corresponding nanofins in these regions can vary between different cells in the device layout. For example, as Figure 3 As shown, both the width and length of the active nanosheet fin region 330 vary among the different active units 310 in the device layout 300. The variation in the width and length of the active nanosheet fin region 330 can be designed to provide different operating characteristics for the active units 310.

[0024] However, altering the width of the active nanosheet fin region 330 may present different problems or limitations during operation of the device layout 300 and during the device fabrication steps. In some variations, the width of the active nanosheet fin region 330 may differ from the width of adjacent dummy nanosheet fin regions. For example, as Figure 3As shown, the active nanosheet fin region 330G in the active cell 310C has a width different from that of the adjacent dummy nanosheet fin regions 340E and 340F in the dummy cells 320B and 320C, respectively. This difference in width creates a shoulder region 360, where there is a jog between the two different widths. These jogs can produce layout-dependent effects (LDEs), where the performance of the active cell 310C is affected by the dummy cells 320B and 320C. For example, a jog in width can generate mechanical stress affecting the source / drain regions of the active cell 310C. This mechanical stress can translate into changes in the electrical characteristics of the active cell 310C, such as the threshold voltage of the transistor in the active cell. Changes in electrical characteristics can affect transistor performance. Furthermore, a large jog in width can lead to greater mechanical stress and greater degradation in transistor performance.

[0025] Fabrication issues based on device layout 300 may arise from time delays between different manufacturing process stages (e.g., steps) and limitations on the available modifications to the device layout depending on the stage of the manufacturing process. For example, the first stage of the manufacturing process may be based on DAPO (“Device / Active and Polysilicon Sequence”), where all active device regions (e.g., oxide diffusion regions) and gate material (e.g., polysilicon) layers are fabricated based on device layout 300. The process stage for forming the active regions and polysilicon layers may take approximately several weeks after DAPO. The next stage may be the formation of metal interconnects and other connections to the active regions and polysilicon layers. Due to the delay between the implementation of DAPO and the next stage of the manufacturing process, changes to any originally planned connections may be possible using an ECO (“Engineering Change Instruction”). An ECO may, for example, change how the connections to the active regions and polysilicon layers are formed. However, these changes cannot include any alteration to the dimensions of the active regions or polysilicon layers that have already been fabricated. For example, the length or width of the nanosheet fin regions 330 / 340 cannot be changed, and the physical dimensions of the transistors cannot be altered via an ECO (e.g., to increase gain). Gain can only be increased by changing the metal interconnect logic to the active region that has already been fabricated, thus substantially increasing the horizontal size of the transistor. Furthermore, the transistor's drive is fixed by the layout in the DAPO and is difficult to change by altering the interconnect logic.

[0026] This disclosure recognizes that additional flexibility in the design and fabrication of transistor devices with nanosheet fins can be achieved by positioning the steps (e.g., abrupt changes between different nanosheet fin widths) within the initial layout of the device (e.g., the layout in the DAPO of the device). For example, moving some of the steps / abrupt changes between different nanosheet fin widths inside the dummy cells in the layout can provide greater flexibility when changing the device design after an ECO implementation of the layout from the DAPO. Changing the physical dimensions of the transistor via an ECO is now possible, whereas it was not possible before. Furthermore, moving the steps / abrupt changes between different nanosheet fin widths inside the dummy cells can reduce performance degradation from the LDE during device operation because the number and size of shoulder regions with abrupt changes between the dummy cells and active cells can be reduced.

[0027] Some embodiments disclosed herein have three broad elements: 1) a first active transistor cell including a first nanofin region having a first width; 2) a second active transistor cell including a second nanofin region having a second width different from the first width; and 3) a dummy transistor cell positioned between the first and second active transistor cells, wherein the dummy transistor cell includes a third nanofin region having a first portion having a first width adjacent to the first nanofin region and a second portion having a second width adjacent to the second nanofin region. In various embodiments, the first and second active transistor cells are part of a plurality of active cells in the device, and the first dummy transistor cell is one of a plurality of dummy transistor cells in the device. In some embodiments, the dummy transistor cell is positioned between the first and second active transistor cells in the cell width direction, while the width of the nanofin region is in the cell height direction.

[0028] Various illustrations of embodiments having these key elements are now described in this disclosure. It should be noted that the exemplary embodiments of this disclosure depict design templates for devices having various active and dummy cells with nanosheet fin regions. These design templates provide basic building blocks from which many different types of devices can be constructed based on the interconnection schemes of transistors into the design templates. For example, simple devices (such as inverters, NAND devices, multiplexers (MUX)) as well as more complex devices (e.g., complex FETs) can be constructed based on the basic building blocks of this disclosure.

[0029] Figure 4A top plan view depicting a contemplated layout of a transistor device having multiple active cells and dummy cells according to some embodiments is provided, wherein some of the dummy nanosheet fin regions have different widths within the dummy cells. An exemplary embodiment of device layout 400 includes six active cells 410 (e.g., active cells 410A-410F) and four dummy cells 420 (e.g., dummy cells 420A-420D) and four nanosheet fin rows 450 (e.g., nanosheet fin rows 450A-450D). The dummy cells 420 may be positioned between the active cells 410 in the cell width direction 404. For example, as... Figure 4 As shown, in the unit width direction 404, the dummy unit 420A is positioned between the active unit 410A and the active unit 410B, the dummy unit 420B is positioned between the active unit 410B and the active unit 410C, the dummy unit 420C is positioned between the active unit 410C and the active unit 410D, and the dummy unit 420D is positioned between the active unit 410E and the active unit 410F.

[0030] In some embodiments, active units 410A-410D and dummy units 420A-420C are positioned along nanofin rows 450A and 450B, and active units 410E-410F and dummy unit 420D are positioned along nanofin rows 450C and 450D. Therefore, active unit 410A includes nanofin regions 430A and 430E, active unit 410B includes nanofin regions 430B and 430F, active unit 410C includes nanofin regions 430C and 430G, active unit 410D includes nanofin regions 430D and 430H, active unit 410E includes nanofin regions 430I and 430K, and active unit 410F includes nanofin regions 430J and 430L. In addition, dummy unit 420A includes nanofin regions 440A and 440D, dummy unit 420B includes nanofin regions 440B and 440E, dummy unit 420C includes nanofin regions 440C and 440F, and dummy unit 420D includes nanofin regions 440G and 440H.

[0031] It should be understood that Figure 4The number and arrangement of the active cells 410, dummy cells 420, nanosheet fin regions 430, nanosheet fin regions 440, and nanosheet fin rows 450 shown are presented as a contemplated embodiment of a transistor device layout (e.g., device layout 400), and additional embodiments of the transistor device layout are contemplated within the scope of this disclosure. For example, the contemplated transistor device layout may have different numbers or locations of active cells, dummy cells, nanosheet fin regions, or nanosheet fin rows determined based on transistor device design considerations. Variations in the contemplated embodiments may additionally include the height of the active cells 410 and dummy cells 420 in the cell height direction 402 and the length of the active cells 410 and dummy cells 420 in the cell width direction 404.

[0032] In some embodiments, one or more dummy units 420 include nanosheet fin regions 440 having portions of varying widths within the dummy unit (note that the width of the nanosheet fin regions is along the unit height direction 402, such as...). Figure 4 (As shown). For example, the nanosheet fin region 440 within such a dummy unit 420 may include a stepped change (e.g., abrupt change) in width between a first portion and a second portion. This stepped change in width between the first and second portions may be implemented as part of the initial design of the device layout 400. In some embodiments, the device layout 400 is implemented as a layout in a DAPO. In various embodiments, a stepped change is implemented for the nanosheet fin region within the dummy unit adjacent to (e.g., positioned between two active units) two active units with different nanosheet fin widths. Thus, the stepped change can allow the width of the first portion to match the width of the nanosheet fin region of the first active unit adjacent to the first portion, and the width of the second portion to match the width of the nanosheet fin region of the second active unit adjacent to the second portion.

[0033] exist Figure 4In the illustrated embodiments, dummy units 420B, dummy units 420C, and dummy units 420D are examples of dummy units including portions with different nanosheet fin widths. Dummy unit 420B includes a nanosheet fin region 440B having a first portion 442B and a second portion 444B, and a nanosheet region 440E having a first portion 442E and a second portion 444E. The width of the first portion 442B changes to the width of the second portion 444B at step 460B, and the width of the first portion 442E changes to the width of the second portion 444E at step 460E. Dummy unit 420C includes a nanosheet fin region 440C having a first portion 442C and a second portion 444C, and a nanosheet fin region 440F having a first portion 442F and a second portion 444F. The width of the first portion 442C changes to the width of the second portion 444C at step 460C, and the width of the first portion 442F changes to the width of the second portion 444F at step 460F. The dummy unit 420D includes a nanosheet fin region 440G having a first portion 442G and a second portion 444G, and a nanosheet fin region 440H having a first portion 442H and a second portion 444H. The width of the first portion 442G changes to the width of the second portion 444G at step 460G, and the width of the first portion 442H changes to the width of the second portion 444H at step 460H.

[0034] First, moving to dummy unit 420B, the width of the first portion 442B matches the width of the nanofin region 430B in the adjacent active unit 410B. The width of the nanofin region 440B changes at step 460B to the width of the second portion 444B, which matches the width of the nanofin region 430C in the active unit 410C. Additionally, the width of the first portion 442E in dummy unit 420B matches the width of the nanofin region 430F in the adjacent active unit 410B, while the width of the nanofin region 440E changes at step 460E to the width of the second portion 444E, which matches the width of the nanofin region 430G in the active unit 410C.

[0035] Next, we move to dummy unit 420C. The width of the first portion 442C matches the width of the nanofin region 430C in the adjacent active unit 410C. The width of the nanofin region 440C changes at step 460C to the width of the second portion 444C, which matches the width of the nanofin region 430D in the active unit 410D. Furthermore, the width of the first portion 442F in dummy unit 420C matches the width of the nanofin region 430G in the adjacent active unit 410C, while the width of the nanofin region 440F changes at step 460F to the width of the second portion 444F, which matches the width of the nanofin region 430H in the active unit 410D.

[0036] Finally, moving to dummy unit 420D, the width of the first portion 442G matches the width of the nanofin region 430I in the adjacent active unit 410E. The width of the nanofin region 440G changes to the width of the second portion 444G at step 460G, which matches the width of the nanofin region 430J in the active unit 410F. Furthermore, the width of the first portion 442H in dummy unit 420D matches the width of the nanofin region 430K in the adjacent active unit 410E, while the width of the nanofin region 440H changes to the width of the second portion 444H at step 460H, which matches the width of the nanofin region 430L in the active unit 410F.

[0037] By placing abrupt changes in width (e.g., steps 460B to 460C and steps 460E to 460H) within dummy cells (e.g., dummy cells 420B to 420D), the dummy cells have different fin widths that match the widths of the nanosheet fins in adjacent active cells (e.g., active cells 410B to 410F) on either side of the dummy cell. Placing these abrupt changes in width within the dummy cells removes any shoulder regions along the boundary between the active cells and the dummy cells. Therefore, based on Figure 4 Any transistor device formed by the device layout 400 shown may have a reduced LDE, such as those caused by mechanical stress from abrupt changes in width at the boundary between active and dummy cells, as described above.

[0038] Figure 5 The following describes the possible implementation schemes based on some schemes. Figure 4 The device layout 400 is a top plan view representation of a contemplated transistor device layout having a dummy gate structure defining the boundary between active cells and dummy cells. In the illustrated embodiment, device layout 500 includes along... Figure 4 A dummy gate structure 525 is placed at the boundary between the active cell 410 and the dummy cell 420 found in the device layout 400. For example, dummy gate structure 525A is placed along the boundary between the active cell 410A and the dummy cell 420A, dummy gate structure 525B is placed along the boundary between the dummy cell 420A and the active cell 410B, dummy gate structure 525C is placed along the boundary between the active cell 410B and the dummy cell 420B, dummy gate structure 525D is placed along the boundary between the dummy cell 420B and the active cell 410C, dummy gate structure 525E is placed along the boundary between the active cell 410C and the dummy cell 420C, and dummy gate structure 525F is placed along the boundary between the dummy cell 420C and the active cell 410D.

[0039] In various embodiments, dummy gate structures 525A and 525F are dummy gate structures extending along a continuous boundary between a plurality of active cells and dummy cells. For example, dummy gate structure 525A may extend along the boundary between active cell 410E and dummy cell 420D, which is continuous with the boundary between active cell 410A and dummy cell 420A. Dummy gate structure 525F may also extend along the boundary between dummy cell 420D and active cell 410F, which is continuous with the boundary between active cell 410D and dummy cell 420C.

[0040] Device layout 500 is an example of a transistor device layout, which can be used in different ways. Figure 4 The dimensions (e.g., width or length) of the active cells 410 and dummy cells 420 of the device layout 400 shown are implemented (and manufactured) with any changes. For example, Figure 4 The device layout 400 shown can be a layout implemented in the DAPO at the start of the manufacturing process, and Figure 5 The device layout 500 shown may be a layout achieved after applying an ECO during manufacturing, which adds a dummy gate structure 525 (and other gate or metal connections), but the ECO does not include any change in the size of the active cells and dummy cells. While the size (e.g., width or length) of the active cells 410 and dummy cells 420 in device layout 500 is unchanged compared to device layout 400, the dummy gate structure 525 is positioned along the boundary between the active cells and the dummy cells, and the number and size of abrupt changes in width (e.g., steps) are reduced (e.g., compared to device layout 300), and therefore any LDE is reduced in the device manufactured according to device layout 500.

[0041] Back Figure 4 Because device layout 400 includes abrupt changes in width (e.g., a step 460) located within dummy cells 420, an ECO (Electronic Control Order) can be implemented to alter the physical dimensions of active cells 410. Changing the physical dimensions of active cells alters the electrical characteristics of transistors in transistor devices fabricated based on device layout 400. In various embodiments, the physical dimensions of active cells can be altered by changing the location of the dummy gate structure to change the length of active cell 410 (in the cell width direction 404). For example, because the abrupt change in width (e.g., a step) is within a dummy cell adjacent to an active cell, and therefore the width of the nanosheet fin region in the dummy cell from the boundary of the active cell to the step matches the width of the nanosheet fin region in the active cell, the dummy gate structure can be moved from its original intended location at the boundary between the active cell and the dummy cell in device layout 400 (e.g., ...). Figure 5The length of the active cell is increased by moving it to any location along a portion of the nanosheet fin region in the dummy cell that has the same width as the nanosheet fin region in the active cell (e.g., up to any location where the width changes stepwise in the dummy cell). Increasing the length of the active cell increases the gain of the active cell. Additionally, the location and number of active gates in the active cell can be changed as the length of the active cell increases. Furthermore, the drive in the active cell can be changed based on the increase in the length of the active cell.

[0042] Figure 6 The diagram depicts a top plan view representation of a contemplated transistor device layout according to several embodiments, some of which have had dummy gate structures moved to increase the initial based... Figure 4 The active cell length of device layout 400 in the example. In the embodiment of device layout 600, with Figure 5 The device layout 500 shown is the same, with dummy gate structures 525A, 525B, 525D, and 525E placed along the boundary between active cell 410 and dummy cell 420. However, in device layout 600, the placement of dummy gate structures 525C and 525F is changed to increase the length of active cells 410B, 410D, and 410F in the cell width direction 404.

[0043] In various implementations, the dummy gate structure is moved to a location covering a portion of the nanosheet fin region in the dummy cell, the portion having a width matching the width of the nanosheet fin region in the adjacent active cell. Moving the dummy gate structure to this location covering the portion of the nanosheet fin region in the dummy cell causes the dummy gate structure to shift from its original intended position at the interface between the dummy cell and the active cell, and redefines the length of the active cell based on the new position of the dummy gate structure above the portion of the nanosheet fin region in the dummy cell. For example, the length of the active cell now becomes the sum of the original length of the nanosheet fin region in the active cell and the length of the shift of the dummy gate structure above the portion of the nanosheet fin region in the dummy cell from the original interface between the dummy cell and the active cell.

[0044] For example, first turn to the placement of the dummy gate structure 525C between the active cell 410B and the dummy cell 420B, line 625C shows the... Figure 4 The original planned location of the dummy gate structure in the device layout 400 shown is in Figure 5 The device layout shown is implemented in 500. Figure 6In the illustrated embodiment, the dummy gate structure 525C' is a new shifted position of the dummy gate structure, located to the right of its original position, and now situated within the region of the first portion 442B of the nanofin region 440B and the first portion 442E of the nanofin region 440E. The new position of the dummy gate structure 525C' can be implemented, for example, by modifying the ECO of the original layout based on DAPO. As shown, moving the dummy gate structure 525C' to its new position increases the length (in the cell width direction 404) and area of ​​the nanofin regions 430B' and 430F' in the active cell 410B' from their original areas, where the new areas are indicated by a dot pattern. Furthermore, increasing the area of ​​the nanofin regions 430B' and 430F' correspondingly reduces the area of ​​the nanofin regions 440B' and 440E' in the dummy cell 420B'. Now, the dot pattern has a new area defined by the sum of the length of the original nanosheet fin region in the active cell 410B' and the length of a portion of the original nanosheet fin region in the dummy cell 420B' now in the dot pattern. For example, the dot pattern may have an area defined by the sum of the length of the nanosheet fin region 430B' and the length of a portion of the nanosheet fin region 440B' now in the dot pattern, based on the shifted location of the dummy gate structure 525C'.

[0045] It should be noted that the dummy gate structure 525C' can be moved to the right from its original intended position, all the way to the positions of steps 460B and 460E within the dummy cell 420B'. However, in the illustrated embodiment, the dummy gate structure 525C' is only partially moved toward the positions of steps 460B and 460E, and some portions of the first portions 442B and 442E remain within the dummy cell 420B'. Retaining some portions of the first portions 442B and 442E within the dummy cell 420B' preserves steps 460B and 460E within the dummy cell. Preserving the steps within the dummy cell 420B' (e.g., abrupt changes in width) suppresses LDE between the active cell 410B' and the dummy cell because there is no shoulder region between the cells that would cause mechanical stress that could translate into changes in the electrical characteristics of the active cell.

[0046] However, in some embodiments, the location of the dummy gate structure can be moved to occupy the entire portion of the nanosheet fin region within the dummy cell that has the same width as the nanosheet fin region within the adjacent active cell. For example, turning to the placement of the dummy gate structure 525F along the boundary extending between the active cell 410D and the dummy cell 420C and between the active cell 410F and the dummy cell 420D, line 625F shows the distribution from... Figure 4The original planned location of the dummy gate structure in the device layout 400 shown is in Figure 5 The device layout shown is implemented in 500. Figure 6 In the exemplary implementation, the dummy gate structure 525F' ​​is a new location for the dummy gate structure, which can be implemented, for example, by ECO, as described above. As shown, moving the dummy gate structure 525F' ​​to its new location increases the length and area of ​​the nanofin regions 430D' and 430H' in the active cell 410D' from their original areas, wherein the new areas are shown by a dot pattern. Additionally, moving the dummy gate structure 525F' ​​to its new location increases the length (in the cell width direction 404) and area of ​​the nanofin regions 430J' and 430L' in the active cell 410F' from their original areas, wherein the new areas are shown by a dot pattern. The areas of nanofin regions 440C' and 440F' in dummy unit 420C', together with the areas of nanofin regions 440G' and 440H' in dummy unit 420D', decrease as the area of ​​the nanofin region of the active unit increases.

[0047] like Figure 6 As shown, the dummy gate structure 525F' ​​is moved to the positions of steps 460C, 460F, 460G, and 460H. Therefore, based on Figure 4 The original layout of the devices in the illustrated device layout 400 increases the area of ​​active cells 410D' and 410F' to their maximum possible area. It should be noted that increasing the area of ​​the active cells to their maximum size allowed by the original layout does create shoulder regions between active cell 410D' and dummy cell 420C', and between active cell 410F' and dummy cell 420D'. However, the abrupt changes in width at these shoulder regions can be small to reduce LDEs in the device. Furthermore, increasing the area of ​​the active cells reduces any mechanical stress caused by adjacent dummy cells, also lowering the likelihood of LDEs in the device.

[0048] As mentioned above, such as Figures 4 to 6 As shown, creating a device layout with abrupt changes in the width of the nanosheet fin region within the dummy cell in the device layout (e.g., a step that changes the width of the nanosheet fin region) provides superior performance compared to layouts where... Figure 3The width abrupt change shown illustrates various advantages of the previous device layout fixed at the boundary between the active cell and the dummy cell. For example, moving the width abrupt change inside the dummy cell reduces the likelihood of device performance degradation due to mechanical stress, which could affect the source / drain regions in the active cell and translate into changes in the electrical characteristics of the active cell. Additionally, moving the width abrupt change inside the dummy cell allows for changes to the physical dimensions (e.g., length and area) of the active cell after the device has undergone DAPO processing. For example, an ECO can be implemented after DAPO processing, which alters the location of the dummy gate structure to increase the length and area of ​​the active cell by utilizing the location of the steps within the dummy cell. Changing the physical dimensions of the active cell through ECO enables previously unavailable capabilities to be modified according to the ECO, allowing for changes in the gain and drive of transistors in the nanosheet fin device.

[0049] Example computer system Next, turn to Figure 7 This diagram illustrates a block diagram of one embodiment of system 700, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 700 includes at least one instance of a system-on-a-chip (SoC) 706, which may include various types of processing units (such as a central processing unit (CPU), graphics processing unit (GPU), or others), communication architectures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 706 include multiple execution channels and instruction dispatch queues. In various embodiments, SoC 706 is coupled to external memory 702, peripheral devices 704, and power supply 708.

[0050] A power supply 708 is also provided, which supplies power voltage to the SoC 706 and one or more power voltages to the memory 702 and / or peripheral devices 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, or tablet computer, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0051] Memory 702 is any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, the devices may be mounted with a SoC or integrated circuit in a chip stack configuration, package stack configuration, or multi-chip module configuration.

[0052] Depending on the type of system 700, peripheral device 704 may include any desired circuitry. For example, in one embodiment, peripheral device 704 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular phones, GPS, etc. In some embodiments, peripheral device 704 may also include additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 704 may include user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0053] As illustrated, system 700 is shown to have applications in a wide range of fields. For example, system 700 can be used as part of a chip, circuit, component, etc., in a desktop computer 710, laptop computer 720, tablet computer 730, cellular or mobile phone 740, or television 750 (or a set-top box coupled to a television). Smartwatches and health monitoring devices 760 are also illustrated. In some embodiments, a smartwatch may include various general computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0054] System 700 can be further used as part of a cloud-based service 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 700 can be used in one or more devices in the home 780, in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and should provide an alert to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 7 The document also exemplifies the application of system 700 to various modes of transportation 790. For example, system 700 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) motorcycles. In various cases, system 700 can be used to provide automated guidance (e.g., autonomous vehicles) and general system control. Many other implementations are possible and contemplated. It should be noted that... Figure 7 The devices and applications illustrated are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0055] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0056] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0057] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0058] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the filing of this application (or an application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0059] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and such combinations may be claimed in this application or in another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0060] In appropriate circumstances, it is also contemplated that a claim drafted in one format or statutory type (e.g., apparatus) is intended to support a corresponding claim in another format or statutory type (e.g., method).

[0061] Since the present disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0062] References to items in the singular form (i.e., a noun or noun phrase preceded by “a,” “an,” or “the”) are meant to mean “one or more” unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to “an item” in a claim does not exclude additional instances of that item. “Multiple” items means a collection of two or more items.

[0063] The word “may” is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0064] The terms “comprising” and “including” and their forms are open-ended and mean “including but not limited to.”

[0065] When the term “or” is used in the present disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement “x or y” is equivalent to “x or y, or both,” and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0066] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0067] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0068] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0069] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0070] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Thus, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0071] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0072] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0073] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. No Referencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0074] Different “circuits” may be described in this disclosure. These circuits, or “circuits”, constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuitry.

[0075] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many instances, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of “processing the opcode of an instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0076] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, their relationship to each other, and the manner in which such circuits / cells / components interact form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit may include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0077] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0078] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An integrated circuit device, the integrated circuit device comprising: substrate; A plurality of active transistor units, the plurality of active transistor units having nanosheet fin regions, the nanosheet fin regions having a width in a first direction in a horizontal dimension above the substrate and a length in a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, wherein the plurality of active transistor units include: A first active transistor unit, the first active transistor unit including a first nanosheet fin region having a first width; and The second active transistor unit includes a second nanosheet fin region having a second width different from the first width; A plurality of dummy transistor units, each dummy transistor unit having a nanosheet fin region having a width in a first direction and a length in a second direction, wherein the plurality of dummy transistor units include: A first dummy transistor unit is positioned in the second direction between the first active transistor unit and the second active transistor unit, wherein the first dummy transistor unit includes a third nanosheet fin region, the third nanosheet fin region having: A first portion, the first portion having a first interface with the first nanosheet fin region, the first portion having the first width; and The second portion, having a second interface with the second nanosheet fin region, and having the second width; and An isolation structure is located between the first active transistor unit and the first dummy transistor unit, wherein the isolation structure extends longitudinally over a portion of the first portion of the third nanosheet fin region in the first direction, and the portion is displaced from the first interface in the second direction.

2. The device of claim 1, further comprising a second dummy transistor unit, the second dummy transistor unit being positioned adjacent to the first active transistor unit on a side opposite to the first dummy transistor unit in the second direction, wherein the second dummy transistor unit includes a fourth nanosheet fin region, wherein a portion of the fourth nanosheet fin region is interface-bonded to the first nanosheet fin region and has the first width.

3. The device according to claim 2, further comprising: A third active transistor unit is positioned adjacent to the second dummy transistor unit on the side opposite to the first active transistor unit in the second direction. The third active transistor unit includes a fifth nanosheet fin region, which is interface-bonded with the fourth nanosheet fin region and has a third width.

4. The device according to claim 1, the device further comprising a second isolation structure positioned along the second interface and extending along the second interface in the first direction.

5. The device according to claim 1, further comprising: A fourth active transistor unit, the fourth active transistor unit including a sixth nanosheet fin region having the first width, wherein the sixth nanosheet fin region is spaced apart from the first nanosheet fin region in the first direction, and wherein the end of the sixth nanosheet fin in the second direction is aligned with the end of the first nanosheet fin region. as well as A fifth active transistor unit, the fifth active transistor unit including a seventh nanosheet fin region having the second width, wherein the seventh nanosheet fin region is spaced apart from the second nanosheet fin region in the first direction, and wherein the end of the seventh nanosheet fin in the second direction is aligned with the end of the second nanosheet fin region.

6. The device according to claim 5, further comprising: A third dummy transistor unit is positioned in the second direction between the fourth active transistor unit and the fifth active transistor unit, wherein the third dummy transistor unit includes an eighth nanosheet fin region, the eighth nanosheet fin region having: The first portion has a third interface with the sixth nanosheet fin region, and the first portion has the first width; as well as The second part has a fourth interface with the seventh nanosheet fin region, and the second part has the second width.

7. The device of claim 6, wherein the isolation structure is further positioned between the fourth active transistor unit and the third dummy transistor unit, wherein the isolation structure extends longitudinally over a portion of the first portion of the sixth nanosheet fin region in the first direction, the portion being displaced from the third interface in the second direction.

8. The device of claim 6, wherein the first portion of the eighth nanosheet fin region has an end aligned with the end of the first portion of the third nanosheet fin region in the second direction, and wherein the second portion of the eighth nanosheet fin region has an end aligned with the end of the second portion of the third nanosheet fin region in the second direction.

9. The device of claim 1, wherein the portion of the first portion of the third nanosheet fin region beneath the isolation structure is located at the interface between the first portion and the second portion of the third nanosheet fin region.

10. The device of claim 1, wherein the second active transistor unit comprises at least one active gate structure having a portion covering the second nanosheet fin region in a vertical dimension above the substrate.

11. An integrated circuit device, the integrated circuit device comprising: substrate; A transistor region located on the substrate, the transistor region having a width in a first direction in a horizontal dimension above the substrate and a length in a second direction in the same horizontal dimension, the second direction being perpendicular to the first direction, wherein the transistor region comprises: A nanosheet fin region extending a length in the second direction, wherein the nanosheet fin region comprises: An active portion, the active portion having a width in the first direction and a length in the second direction; and A dummy portion having a width in the first direction and a length in the second direction, wherein at least a first dummy portion is positioned in the second direction between at least a first active portion and a second active portion; The first active portion has a first width, and the second active portion has a second width; and The first dummy portion includes a first portion having the first width that is joined to the first active portion via an interface, and a second portion having the second width that is joined to the second active portion via an interface; and An isolation structure defining a boundary between an active cell and a dummy cell in the transistor region, wherein the isolation structure extends longitudinally in the first direction over a portion of the first portion of the first dummy portion, the portion being displaced from the interface between the first portion and the first active portion.

12. The device of claim 11, wherein the active unit has an active region comprising the first active portion and the first portion of the first dummy portion up to the boundary defined by the isolation structure.

13. The device of claim 11, further comprising: The second dummy portion is interface-engaged with the first active portion on the side opposite to the first dummy portion in the second direction, wherein the portion of the second dummy portion that is interface-engaged with the first active portion has the first width. as well as A third active portion, wherein the third active portion is interface-engaged with the second dummy portion on the side opposite to the first active portion in the second direction, wherein the third active portion has a third width.

14. The device of claim 13, wherein the third width is approximately the same as the second width.

15. The device of claim 11, further comprising an active gate structure positioned in the second active portion.

16. The device of claim 11, wherein the isolation structure defining the boundary between the active cell and the dummy cell in the transistor region is longitudinally positioned along the interface between the first portion and the second portion of the first dummy portion.

17. An integrated circuit device, the integrated circuit device comprising: substrate; A plurality of active transistor units, the plurality of active transistor units having nanosheet fin regions, the nanosheet fin regions having a width in a first direction in a horizontal dimension above the substrate and a length in a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, wherein the plurality of active transistor units include: A first active transistor unit, the first active transistor unit including a first nanosheet fin region having a first width; and The second active transistor unit includes a second nanosheet fin region having a second width different from the first width; A plurality of dummy transistor units, each dummy transistor unit having a nanosheet fin region having a width in a first direction and a length in a second direction, wherein the plurality of dummy transistor units include: A first dummy transistor unit is positioned in the second direction between the first active transistor unit and the second active transistor unit, wherein the first dummy transistor unit includes a third nanosheet fin region, the third nanosheet fin region having: A first portion, the first portion being adjacent to the first nanosheet fin region, the first portion having the first width; and The second portion, adjacent to the second nanosheet fin region, has the second width; and A dummy gate structure extends longitudinally in a first direction, wherein the dummy gate structure is positioned at a location covering a first portion of the third nanosheet fin region in a vertical dimension, the location being shifted in a second direction from the interface between the first portion of the third nanosheet fin region and the first nanosheet fin region, and wherein the position of the dummy gate structure in the second direction defines the length of the first active transistor unit in the second direction as the sum of the length of the first nanosheet fin region and the length of the shift of the dummy gate structure from the interface in the second direction.

18. The device of claim 17, wherein the dummy gate structure defines the boundary between the first active transistor cell and the dummy transistor cell.

19. The device of claim 18, wherein at least some portions of the first portion of the third nanosheet fin region are retained in the dummy transistor unit.

20. The device of claim 18, wherein the entire first portion of the third nanosheet fin region is located within the first active transistor unit.

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