Yield improvements in package on package
By measuring and modeling to predict stress induced by shape changes in the bonded wafer, and adjusting the bonding parameters, the centering problem of the bonded wafer was solved, manufacturing errors and failure risks were reduced, and the yield and efficiency of semiconductor manufacturing were improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- KLA CORP
- Filing Date
- 2024-10-29
- Publication Date
- 2026-04-21
AI Technical Summary
In semiconductor manufacturing, the centrality of the bonded wafers leads to manufacturing errors, affecting CMP processes and manufacturing equipment, increasing the risk of failure, and shape-induced stress may cause voids or cracks at the bonding interface, affecting reliability.
By measuring the shape of the top and bottom wafers, the model predicts the stress induced by shape change, determines the bonding strength, and adjusts the bonding parameters to form bonded wafers within specifications. The bonding process is optimized by combining machine learning algorithms.
It reduces the risk of failure during thinning or grinding processes, improves bonding yield and defect inspection efficiency, and reduces unwanted downtime and production interruptions.
Smart Images
Figure CN121909769A_ABST
Abstract
Description
[0001] Cross-reference of related applications
[0002] This application claims priority to provisional patent application No. 63 / 546,251, filed October 30, 2023, the disclosure of which is hereby incorporated by reference. Technical Field
[0003] This disclosure relates to the measurement of bonded wafers. Background Technology
[0004] The evolution of the semiconductor manufacturing industry places increasingly higher demands on yield management, and specifically on metrology and inspection systems. Critical dimensions continue to shrink, but the industry needs to reduce the time spent achieving high-yield, high-value production. Minimizing the total time from detecting a yield problem to resolving it maximizes the semiconductor manufacturer's return on investment.
[0005] Manufacturing semiconductor devices (such as logic and memory devices) typically involves using numerous manufacturing processes to process semiconductor wafers to form the various features and multiple layers of the semiconductor device. For example, photolithography is a semiconductor manufacturing process that involves transferring a pattern from a mask to a photoresist disposed on a semiconductor wafer. Additional examples of semiconductor manufacturing processes include, but are not limited to, chemical mechanical polishing (CMP), etching, deposition, and ion implantation. The arrangement of multiple semiconductor devices manufactured on a single semiconductor wafer can be separated into individual semiconductor devices.
[0006] Bonded (or stacked) wafers are frequently used in the semiconductor industry. One or more ultra-thin wafers bonded to a carrier wafer are examples of bonded wafers, but other semiconductor wafer designs can also be bonded wafers. For example, a bonded wafer may contain a top wafer (e.g., a device wafer) bonded to a carrier wafer. These bonded wafers can be used for both memory and logic applications. Three-dimensional integrated circuits (3D ICs) can be manufactured using bonded wafers.
[0007] Manufacturing errors in the bonding wafer can cause problems during manufacturing. For example, the centering of the bonding wafer affects the CMP process or increases disposal risk. During CMP, centering affects the placement of the polishing pad relative to the center of the bonding wafer and subsequent planarization. During wafer disposal, the balance of the bonding wafer or the clearance within the manufacturing equipment can be affected by the centering of the bonding wafer.
[0008] Improper centering can even damage the bonded wafers or manufacturing equipment. If the bonded wafers are undercut, improperly bonded together, or contain too much adhesive, they may crack inside the CMP tool, contaminating or damaging the tool. This contamination or damage can lead to unwanted downtime or even halt production within the semiconductor wafer fab.
[0009] Shape-induced stress changes occur during the packaging process. Thinning or other polishing processes can affect shape changes, which can lead to bonding failure. Evidence suggests that if the top wafer is thinned, the shape of the bonding stack tends to resemble that of the bottom wafer due to the gradual release of mechanical strength associated with the top wafer. Untreated shape changes can lead to bonding interface stresses, especially at the copper / dielectric oxide interface. Bonding interface stresses can induce voids or even wafer cracks at the bonding interface. Furthermore, delamination is more likely to occur at the bonding interface as the bonding pitch decreases because the small-pitch oxide space is not wide enough to release stress. Von Mises stresses are higher at bonding pad corners and triple points (i.e., the corners of the pads) formed by the bonding interface and pad walls. This can negatively impact reliability.
[0010] Thinning or other polishing processes (such as those using grinding wheels to remove material) are rough and can induce localized cracks or the entry of polishing debris from the edges. This can damage the resulting device. Stress changes in post-bonding processes are not considered. Therefore, the risk of failure induced by thinning / polishing or other post-bonding processes cannot be reduced. Improved techniques and systems are needed for measuring bonded wafers and for refining these processes. Summary of the Invention
[0011] A method is provided in the first embodiment. The method includes measuring the top wafer shape of a top wafer and the bottom wafer shape of a bottom wafer. Using a processor, a model is used to determine shape change induced stresses for a target thickness of a bonded wafer including the top and bottom wafers. Using the processor, the shape change induced stresses are used to determine a bonding strength. Using the processor, bonding parameters are determined for the bonding strength. Using the processor, a comparison is made between the bonding strength and an in-line bonding strength used to form the bonded wafer.
[0012] The shape change-induced stress can be determined for the interface between copper and dielectric oxide.
[0013] The model can be a hypermodel or a machine learning algorithm.
[0014] The online bonding strength may be a value used in the bonding machine to form the bonding wafer or a value to be used in the bonding machine to form the bonding wafer.
[0015] The method may include, prior to the bonding, bonding the top wafer and the bottom wafer to form the bonded wafer when the comparison is within specifications.
[0016] The method may include: thinning the top wafer of the bonded wafer; measuring the wafer shape of the bonded wafer after the thinning; and comparing the wafer shape with a simulated wafer shape of the bonded wafer. The method may further include inspecting for defects in areas of the bonded wafer based on the comparison of the wafer shape and the simulated wafer shape. The method may further include using the results of the inspection as feedback to the model. The method may further include using the results of the inspection in a feedforward manner for a next manufacturing process of the bonded wafer.
[0017] The shape change-induced stress at the target thickness may be based on one or more of the target thickness, the interface structure of the bonded wafer, the material of the bonded wafer, or the parameters of the thinning process of the bonded wafer.
[0018] A second embodiment provides a system. The system includes a metrology tool having: a light source; a stage; a detector for receiving light from the light source; and a processor electronically communicating with the detector. The processor is configured to: receive measurements of the top wafer shape of the top wafer and the bottom wafer shape of the bottom wafer from the detector when a top wafer and a bottom wafer are placed on the stage; determine shape change induced stress for a target thickness of a bonded wafer including the top and bottom wafers using a model; determine a bonding strength using the shape change induced stress; determine bonding parameters for the bonding strength; and determine a comparison between the bonding strength and an in-line bonding strength used to form the bonded wafer.
[0019] The model can be a hypermodel or a machine learning algorithm.
[0020] An embodiment provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium includes one or more programs for performing the following steps on one or more computing devices: Receiving measurements of the top wafer shape of a top wafer and the bottom wafer shape of a bottom wafer; Determining shape change induced stress for a target thickness of a bonded wafer including the top wafer and the bottom wafer using a model; Determining a bonding strength using the shape change induced stress; Determining bonding parameters for the bonding strength; Determining a comparison of the bonding strength with an in-line bonding strength used to form the bonded wafer.
[0021] The model can be a hypermodel or a machine learning algorithm.
[0022] The online bonding strength may be a value used in the bonding machine to form the bonding wafer or a value to be used in the bonding machine to form the bonding wafer. Attached Figure Description
[0023] For a more complete understanding of the nature and purpose of this disclosure, reference should be made to the following detailed description taken in conjunction with the accompanying drawings, wherein:
[0024] Figure 1 This is a flowchart illustrating an embodiment of the method according to the present disclosure;
[0025] Figure 2 yes Figure 1 Flowcharts of embodiments of the method; and
[0026] Figure 3 It is a block diagram of an exemplary system based on this disclosure. Detailed Implementation
[0027] Although the claimed subject matter will be described based on certain embodiments, other embodiments (including those that do not provide all the benefits and features set forth herein) are also within the scope of this disclosure. Various structural, logical, process, and electronic changes may be made without departing from the scope of this disclosure. Accordingly, the scope of this disclosure is defined only by reference to the appended claims.
[0028] The embodiments disclosed herein relate to advanced packaging, such as hybrid bonding technologies. They can improve bonding yield and defect inspection efficiency. They reduce the risk of failure due to changes in wafer or die shape during thinning or other polishing processes. In this example, the wafer shapes of the top and bottom wafers are measured. The process corner of the bonding process can be determined based on the target thickness. The applied bonding formulation is checked to determine if it is within specifications for the determined process corner. If the top and bottom wafers are within specifications, they can be bonded. The back side of the top wafer can be thinned / polished. The stacking and / or shape of the bonded wafers can then be determined, and defects in the bonding interface can be inspected. Thermal cycling results can be inspected as required.
[0029] Figure 1 This is a flowchart of method 100. Method 100 can reduce the risk of failure caused by stress changes in post-bonding processes. Method 100 may be particularly useful in reducing the risk of failure caused by thinning or other polishing processes. Some steps of method 100 can be performed using a processor.
[0030] At point 101, the shapes of the top wafer 110 and the bottom wafer 111 are measured. These measurements can be performed in one or two steps. For example, the top wafer 110 and the bottom wafer 111 can be measured separately. The top wafer 110 is typically a wafer that has undergone thinning or other polishing processes. The bottom wafer 111 can be a carrier wafer. Therefore, it can be assumed that the top wafer 110 has undergone thinning or polishing, while it can be assumed that the bottom wafer 111 remains unchanged during manufacturing.
[0031] At point 102, a model is used to determine the shape change induced stress 113 for the target thickness of the bonded wafer, comprising a top wafer 110 and a bottom wafer 111. The shape change induced stress 113 is measured, for example, the deformation of the bonding interface between the top wafer 110 and the bottom wafer 111. The model can be, for example, a hypermodel (i.e., a hyperparameter model), another physical model, a machine learning algorithm (e.g., a neural network), or a combination thereof. For example, the shape change induced stress can be determined for the interface between copper and dielectric oxide, but other locations are also possible. The target thickness can be a preset or designed thickness of the top wafer 110 after a thinning / grinding or CMP process. Therefore, the target thickness can be the thickness of the bonded wafer after thinning or grinding.
[0032] In this embodiment, the supermodel includes a physical model and a specific model of the top and bottom wafer shapes and bonder parameters, such as yaw settings and vacuum fall times. The coefficients of the model boundary conditions can be adjusted for bonding or other aspects of the manufacturing process. In this example, the supermodel can perform a design of experiment (DOE) for correlation. The supermodel can be based on historical data. In this example, the supermodel is used in conjunction with machine learning algorithms.
[0033] The shape change-induced stress of the target thickness can be based on one or more of the following: the target thickness, the interface structure of the bonded wafer, the material of the bonded wafer, or the parameters of the thinning process of the bonded wafer.
[0034] At point 103, shape change induced stress is used to determine the bonding strength. Shape change induced stress may include changes in stress and / or distribution. Bond strength can be determined based on physical equations. Bond strength can conform to interfacial stresses induced by wafer shape differences. Bond strength can be configured to prevent wafer delamination.
[0035] At point 104, the bonding parameters for bond strength are determined. These parameters can be determined using a data-driven model. Bonding parameters may include bonding formulation parameters specific to the bond strength, such as bonding temperature, bonding pressure, bonding duration, vacuum fall time, yaw setting, heating and / or cooling profiles, or dielectric roughness. This correlates the bond strength and / or bonding energy with other bonding parameters, such as bonding temperature, bonding duration, or bonding pressure.
[0036] At point 105, the bonding strength from step 103 is compared with the in-line bonding strength used to form the bonded wafer. The in-line bonding strength can be the value used in the bonder to form a similar bonded wafer. If the bonded wafer has not yet been manufactured, the in-line bonding strength can also be the value to be used in the bonder to form the bonded wafer. If the bonding strength from step 103 matches the in-line bonding strength, then, for example, a data-based model can be used to determine the risk of non-compliance and the type / location of defects after thinning and / or polishing processes with in-line bonding parameters. If the bonding strength from step 103 matches the in-line bonding strength, then this risk is likely low. For example, if the bonding strength is not within the appropriate range, then cracks or voids at the copper / dielectric oxide edges are more likely to occur. If the comparison does not match, then the top and bottom wafers can be repaired or the bonding formulation can be evaluated. The predictive model can be based on historical data or another trained model.
[0037] At 106, the top wafer 110 and the bottom wafer 111 are then bonded to form a bonded wafer 113. Bonding at step 106 may occur if the comparison from step 105 is within specifications prior to bonding. Therefore, bonded wafer 113 cannot be formed unless it passes the evaluation during step 105. In this example, the fatal defect rate may be the specification used in step 106.
[0038] In another embodiment, the shape-induced stress calculation is based on multiple conditions. These may include not only the target thickness after thinning, but also one or more of the following: thinning steps or parameters, design interface structure, material properties, etc. Here, the thinning steps or parameters may include thinning methods, such as mechanical processes, chemical mechanical processes, thinning rates, etc. The design interface structure may include pitch, dielectric oxide type, critical copper pad dimensions, etc. Material properties may include binding energy. It should be noted that the top wafer 110 may contain a bare die, and therefore, the thinning process may require more attention to avoid device damage.
[0039] Turn Figure 2 After forming the bonding wafer 113 in step 106, the top wafer 110 of the bonding wafer 113 may optionally be thinned at 107 or subjected to another polishing process. If the target thinning thickness of the top wafer 110 is ultrathin (e.g., <100 nm), surface defect monitoring can be performed after thinning. The top wafer 110 can be thinned using CMP or wet etching.
[0040] Following the thinning at step 107, the wafer shape 114 of the bonded wafer 113 can be measured at 108. This can be used to verify the model. The measurement can also be used to determine whether inspection of high-risk areas should be performed or to determine whether inspection can be skipped in certain areas due to low defect risk. In this example, a patterned wafer geometry metrology tool can be used to measure the wafer shape 114.
[0041] At point 109, the wafer shape 114 can be compared with the simulated wafer shape 115 for bonding the wafer. The simulated wafer shape 115 can be calculated for an ideal or anticipated bonding wafer. The simulated wafer shape 115 can also be an actual measurement of the bonding wafer. If the two match, one or more defect inspection parameters, including sampling, categories of defects of concern, etc., can be determined using previous non-conformance predictions. Otherwise, the prediction model is unreliable and may require additional training.
[0042] At point 110, defects in the bonded wafer 113 can be inspected. The thickness of the bonded wafer 113 can be selected using a metrological tool for measurement. These defects may be fatal. The area for defect inspection can be based on a comparison between wafer shape 114 and simulated wafer shape 115. Figure 2 The inspection area is shown as X on the bonding wafer 113.
[0043] Optionally, the results of the inspection at step 110 can be used as feedback for the model used in step 102. Optionally, the results of the inspection at step 110 can be used in a feedforward manner for the next manufacturing process of the bonded wafer 113. Thus, previous manufacturing steps can be adjusted for other bonded wafers to improve results or subsequent manufacturing steps can be adjusted to compensate for the current bonded wafer.
[0044] In another embodiment, the top and bottom wafer shapes are measured. These measurements, along with the target thickness, bonding parameters, and other information, are input into a machine learning model. The machine learning model (e.g., a neural network) can output possible defect categories and distributions after the thinning and / or polishing process. If the output is within specifications, bonding may occur. Otherwise, the bonding parameters can be tuned. The machine learning model can be created using historical data or from a software library. The machine learning model may also incorporate one or more physical analogues (e.g., formulas from materials mechanics) as constraints. For example, the target thickness can be designed or predetermined after the thinning / polishing process or before the next lithography process. Bonding parameters may include online bonding formulation parameters such as bonding temperature, bonding cycle, bonding pressure, alignment model, etc. Other information may include thinning and / or polishing parameters, stacking material parameters, etc. The method may include thinning and / or polishing the top wafer. Here, it is assumed that the top wafer is the wafer to be thinned or polished. If the wafer thickness is less than 100 nm, the thinned surface becomes likely to affect the bonding interface. Therefore, surface defects on the top wafer may require more thorough inspection. It should be noted that defect inspection can still be performed if the wafer thickness exceeds 100 nm. The defect inspection can then be based on the predicted defect type and distribution. The inspection results can be used as feedback to a machine learning model and to improve the model's accuracy.
[0045] Figure 3 This is a block diagram of a system that includes a measuring tool 200, a bonding device 205, and a grinding / thinning tool 206. The measuring tool 200 may include a light source 201, a stage 202, a detector 203 for receiving light from the light source 201 (e.g., light reflected from the bonding wafer 113), and a processor 204 in electronic communication with the detector 203. The measuring tool 200 can generate... Figures 1 to 2 The bonding wafer 113 used in method 100 is measured. The bonding device 205 and the grinding / thinning tool 206 can perform other steps of method 100.
[0046] Processor 204 may include one or more processors configured to perform any of a variety of process steps. In an embodiment, processor 204 is configured to generate and provide one or more control signals configured to perform one or more adjustments on one or more process tools based on information from detector 203.
[0047] Processor 204 may comprise any processor or processing element known in the art. For the purposes of this disclosure, the terms "processor" or "processing element" may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application-specific integrated circuit (ASIC) devices, one or more field-programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, one or more processors may comprise any device configured to execute algorithms and / or instructions (e.g., program instructions stored in memory). In embodiments, one or more processors may be embodied as a desktop computer, mainframe computer system, workstation, graphics computer, parallel processor, networked computer, or any other computer system configured to execute a program configured to operate or in conjunction with the measuring tool 200, as described throughout this disclosure. Furthermore, different subsystems of the measuring tool 200 may include processors or logic elements suitable for performing at least a portion of the steps described in this disclosure. Therefore, the foregoing description should not be construed as limiting the embodiments of this disclosure, but is merely illustrative. Furthermore, the steps described throughout this disclosure can be performed by a single processor or alternatively by multiple processors. Additionally, processor 204 may comprise one or more processors housed within a common housing or multiple housings. In this manner, any processor or combination of processors can be separately packaged as a module suitable for integration into the image measuring tool 200. Furthermore, processor 204 can analyze data received from detector 203 and feed the data to additional components inside or outside the measuring tool 200.
[0048] The bonder 205 can be configured to bond the bonding wafer 113 using heat and / or mechanical force. The grinding / thinning tool 206 can remove material from the top wafer 110 of the bonding wafer 113. The bonder 205 and / or the grinding / thinning tool 206 can communicate electronically with and / or receive instructions from the processor 204.
[0049] Additional embodiments relate to a non-transitory computer-readable medium storing program instructions executable on a processor to perform a computer-implemented method for mitigating the risk of failure caused by changes in wafer or die shape during thinning or other polishing processes, as disclosed herein. Electronic data storage units or other storage media may contain a non-transitory computer-readable medium comprising program instructions executable on processor 204. The computer-implemented method may include any of the methods described herein (e.g., Figures 1 to 2 Any step of method 100 in the process.
[0050] Program instructions for implementing methods (such as those described herein) may be stored on a computer-readable medium, such as an electronic data storage unit or other storage medium. The computer-readable medium may be a storage medium, such as a magnetic disk or optical disk, magnetic tape, or any other suitable non-transitory computer-readable medium known in the art. The electronic data storage unit may be housed together with one or more processors in a common enclosure. The electronic data storage unit may also be remotely located relative to the physical location of one or more processors. For example, one or more processors may access a remote memory (e.g., a server) accessible via a network (e.g., the Internet, an intranet, and the like).
[0051] Program instructions can be implemented in any of a variety of ways, including programmatic, component-based, and / or object-oriented technologies. For example, program instructions can be implemented using ActiveX controls, C++ objects, JavaBeans, Microsoft Foundation Classes (MFC), Streaming SIMD Extensions (SSE), or other technologies or methodologies, as desired.
[0052] Each of the steps in the method may be performed as described herein. The method may also include any other steps that may be performed by the processor and / or computer subsystem or system described herein. The steps may be performed by one or more computer systems that may be configured according to any of the embodiments described herein. Additionally, the method described above may be performed by any of the system embodiments described herein.
[0053] Although this disclosure has described with respect to one or more specific embodiments, it should be understood that other embodiments of this disclosure may be made without departing from the scope of this disclosure. Therefore, this disclosure is considered to be limited only by the appended claims and their reasonable interpretation.
Claims
1. A method comprising: Measure the top wafer shape of the top wafer and the bottom wafer shape of the bottom wafer; Using a processor and a model, shape change-induced stresses are determined for the target thickness of the bonded wafer, which includes the top wafer and the bottom wafer. Using the processor, the shape change-induced stress is used to determine the bonding strength; Using the processor, the bonding parameters for the bonding strength are determined; and Using the processor, a comparison is made between the bonding strength and the in-line bonding strength used to form the bonded wafer.
2. The method of claim 1, wherein the shape change induced stress is determined for the interface between copper and dielectric oxide.
3. The method according to claim 1, wherein the model is a supermodel.
4. The method according to claim 1, wherein the model is a machine learning algorithm.
5. The method of claim 1, wherein the online bonding strength is a value used in the bonding machine to form the bonded wafer.
6. The method of claim 1, wherein the online bonding strength is a value to be used in the bonding machine to form the bonded wafer.
7. The method of claim 1, further comprising bonding the top wafer and the bottom wafer to form the bonded wafer, wherein the comparison is within specifications prior to the bonding.
8. The method of claim 7, further comprising: Thin the top wafer of the bonding wafer; The wafer shape of the bonded wafer is measured after the thinning process; and The wafer shape is compared with the simulated wafer shape of the joined wafer.
9. The method of claim 8, further comprising inspecting defects in the region of the bonded wafer based on the comparison between the wafer shape and the simulated wafer shape.
10. The method of claim 9, further comprising using the result of the test as feedback to the model.
11. The method of claim 9, further comprising using the results of the inspection in a feedforward manner for a next manufacturing process of the bonded wafer.
12. The method of claim 1, wherein the shape change induced stress of the target thickness is based on one or more parameters of the target thickness, the interface structure of the bonded wafer, the material of the bonded wafer, or the thinning process of the bonded wafer.
13. A system comprising: Measurement tools, which include: light source; Stage; A detector used to receive light from the light source; and A processor that communicates electronically with the detector; The processor is configured to: When the top wafer and the bottom wafer are placed on the stage, the detector receives measurements of the top wafer shape of the top wafer and the bottom wafer shape of the bottom wafer. The model was used to determine the shape change-induced stress of the target thickness of the bonded wafer, which includes the top wafer and the bottom wafer; The joint strength is determined using the shape change-induced stress. Determine the bonding parameters for the bonding strength; and The bonding strength is determined by comparing it with the in-line bonding strength used to form the bonded wafer.
14. The system of claim 13, wherein the model is a supermodel.
15. The system of claim 13, wherein the model is a machine learning algorithm.
16. A non-transitory computer-readable storage medium comprising one or more programs for performing the following steps on one or more computing devices: Receive measurements of the top wafer shape of the top wafer and the bottom wafer shape of the bottom wafer; The model was used to determine the shape change-induced stress of the target thickness of the bonded wafer, which includes the top wafer and the bottom wafer; The joint strength is determined using the shape change-induced stress. Determine the bonding parameters for the bonding strength; and The bonding strength is determined by comparing it with the in-line bonding strength used to form the bonded wafer.
17. The non-transitory computer-readable storage medium of claim 16, wherein the model is a hypermodel.
18. The non-transitory computer-readable storage medium of claim 16, wherein the model is a machine learning algorithm.
19. The non-transitory computer-readable storage medium of claim 16, wherein the in-line bonding strength is a value used in the bonding machine to form the bonded wafer.
20. The non-transitory computer-readable storage medium of claim 16, wherein the in-line bonding strength is a value to be used in the bonding machine to form the bonded wafer.