Fault detection method and device and storage medium

Abstract

The invention discloses a fault detection method and device and a storage medium, and relates to the technical field of vehicles, the fault detection method is applied to a vehicle-mounted audio system, the system comprises a slave node, and the fault detection method comprises the following steps: determining a smooth clock period according to a current clock period of the slave node; determining a period deviation rate according to the current clock period and the smooth clock period; determining a clock fault level of the slave node according to a comparison result of the periodic deviation rate and a preset deviation rate tolerance threshold; and executing a fault processing strategy corresponding to the clock fault level. The invention aims to solve the technical problem of low accuracy of clock fault detection.

Description

Technical Field

[0001] This application relates to the field of vehicle technology, and in particular to fault detection methods, equipment and storage media. Background Technology

[0002] A2B (Automotive Audio Bus) is a digital audio bus technology for automotive applications. It employs a single-master, multi-slave, two-wire differential architecture, enabling the transmission of up to 32 channels of 24-bit / 48 kHz digital audio signals at 50 Mbps over cables up to 50 meters long. It also supports remote I2C register access, power supply, and basic diagnostic functions. A2B technology is widely used in advanced driver assistance systems and smart cockpits, becoming a mainstream solution for achieving immersive audio functions such as active noise cancellation (ANC) and road noise suppression (RNC).

[0003] However, the clock architecture of the A2B system determines the vulnerability of the entire network. In an A2B system, the master node generates a periodic SYNC (synchronization signal) using a highly stable crystal oscillator. All slave nodes rely on an internal phase-locked loop (PLL) to lock onto this SYNC signal, thereby recovering their local bit clock to complete the sampling and playback of audio data. If the SYNC signal is lost due to factors such as a drop in supply voltage, electromagnetic interference, or PCB (printed circuit board) layout defects, the slave node's PLL will lose lock, causing an interruption in the audio clock. This, in turn, will cause the speaker to output a pop sound, severely impacting user experience and functional safety.

[0004] Currently, clock fault detection in A2B systems mainly relies on simple timeout or edge loss detection. However, this method is prone to misinterpreting momentary jitter in the system as clock faults, leading to unnecessary audio interruptions or system resets. Conversely, it may be difficult to identify slow crystal drift or intermittent SYNC degradation in a timely manner, resulting in missed fault reports. Summary of the Invention

[0005] The main objective of this application is to provide a fault detection method, device, and storage medium. The embodiments of this application aim to solve the technical problem of low accuracy in conventional clock fault detection.

[0006] To achieve the above objectives, this application proposes a fault detection method applied to an in-vehicle audio system, the in-vehicle audio system comprising: a slave node, the method comprising: Determine the smoothed clock cycle based on the current clock cycle of the slave node; Determine the cycle deviation rate based on the current clock cycle and the smoothed clock cycle; The clock fault level of the slave node is determined based on the comparison result between the cycle deviation rate and the preset deviation rate tolerance threshold. Execute the fault handling strategy corresponding to the clock fault level.

[0007] In one embodiment, the step of determining the smoothed clock period based on the current clock period of the slave node includes: Calculate the exponentially weighted moving average of the current clock cycle; The exponentially weighted moving average of the current clock cycle is determined as the smoothed clock cycle.

[0008] In one embodiment, the step of determining the clock fault level of the slave node based on the comparison result of the cycle deviation rate and a preset deviation rate tolerance threshold includes: Based on the comparison results and the historical fault scores of the slave node, the current fault score of the slave node is determined, wherein, when the cycle deviation rate is less than or equal to the deviation rate tolerance threshold, the fault severity represented by the historical fault score is higher than or equal to the fault severity represented by the current fault score; when the cycle deviation rate is greater than the deviation rate tolerance threshold, the fault severity represented by the historical fault score is lower than the fault severity represented by the current fault score. The clock fault level of the slave node is determined based on the current fault score.

[0009] In one embodiment, the comparison result includes: the difference in deviation rate between the periodic deviation rate and the deviation rate tolerance threshold; the step of determining the current fault score of the slave node based on the comparison result and the historical fault scores of the in-vehicle audio system includes: The scoring adjustment amount is determined based on the deviation rate difference and the preset gain coefficient; The historical fault score is adjusted based on the aforementioned score adjustment amount to obtain the current fault score.

[0010] In one embodiment, the in-vehicle audio system includes: a master node, and the step of determining the cycle deviation rate based on the current clock cycle and the smoothed clock cycle includes: The current clock cycle of the slave node is determined based on the synchronization signal sent by the master node; If the synchronization signal is not detected within a preset time period, the period deviation rate is set to a preset maximum deviation rate, wherein the maximum deviation rate is greater than the deviation rate tolerance threshold.

[0011] In one embodiment, the in-vehicle audio system includes: a master node, and the step of executing the fault handling strategy corresponding to the clock fault level includes: If the clock fault level is Level 1, set the fault indication flag of the slave node; Upon receiving the fault indication flag, the master node performs a network reset operation.

[0012] In one embodiment, the step of performing the network reset operation includes: The master node is used to determine the historical fault information of the slave node; Based on the historical fault information, determine whether the slave node meets the preset frequent fault conditions; If the slave node meets the preset frequent failure conditions, the slave node is isolated.

[0013] In one embodiment, the step of executing the fault handling strategy corresponding to the clock fault level includes: In the case where the clock fault level is a level 2 fault, the trend of the fault score change of the slave node is determined, wherein the severity of the level 1 fault is higher than that of the level 2 fault, and the fault score is used to determine the clock fault level; If the trend of the fault score change of the slave node meets the preset upward trend, the amplitude information of the audio data currently played by the vehicle audio system is identified. Based on the amplitude information, an exponential decay curve of the amplitude is generated; The audio data is processed based on the exponential decay curve of the amplitude.

[0014] Furthermore, to achieve the above objectives, this application also proposes a fault detection device, which is applied to an in-vehicle audio system. The in-vehicle audio system includes: a slave node, and the device includes: The period determination module is used to determine a smooth clock period based on the current clock period of the slave node; The deviation rate determination module is used to determine the cycle deviation rate based on the current clock cycle and the smoothed clock cycle; The fault level determination module is used to determine the clock fault level of the slave node based on the comparison result between the cycle deviation rate and the preset deviation rate tolerance threshold. The execution module is used to execute the fault handling strategy corresponding to the clock fault level.

[0015] Furthermore, to achieve the above objectives, this application also proposes an electronic device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the fault detection method described above.

[0016] Furthermore, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the fault detection method described above.

[0017] In addition, to achieve the above objectives, this application also proposes a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the fault detection method described above.

[0018] The one or more technical solutions proposed in this application have at least the following technical effects: By using a smoothed clock cycle determined by the current clock cycle of the slave node, instantaneous periodic fluctuations are effectively filtered out, obtaining a dynamic benchmark that can stably reflect the long-term operating trend of the slave node's clock; furthermore, the periodic deviation rate is determined by comparing the current clock cycle with the smoothed clock cycle, and the periodic deviation rate is compared with a preset deviation rate tolerance threshold, thereby enabling the system to determine whether the clock deviates from the normal range during operation, and to distinguish between normal fluctuations and potential faults, while quantifying and assessing the severity of the clock deviation, and determining the clock fault level of the slave node; and then executing a fault handling strategy matching the fault level. The embodiments of this application avoid misjudgments of faults caused by instantaneous interference, and can respond promptly to serious events such as continuous degradation or loss of synchronization signals; at the same time, faults are repaired through fault handling strategies, thereby enhancing the system's autonomous recovery capability and operational reliability while ensuring the safety of audio functions. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the structure of the in-vehicle audio system involved in the embodiments of this application; Figure 2 This is a flowchart illustrating an embodiment of the fault detection method of this application. Figure 3 This is a flowchart illustrating Embodiment 3 of the fault detection method of this application; Figure 4 This is a schematic diagram of the frame structure of the fault detection device involved in the embodiments of this application; Figure 5 This is a schematic diagram of the hardware operating environment of the electronic device involved in the embodiments of this application.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0025] In conventional technologies, clock fault detection for A2B systems primarily focuses on the Discovery phase, i.e., a one-time clock validity verification when the system powers on or a node joins the network. This mechanism struggles to continuously monitor clock stability during normal system operation. Furthermore, conventional technologies rely heavily on simple timeout or edge loss detection, which is highly susceptible to misinterpreting transient jitter as clock faults, leading to unnecessary audio interruptions or system resets. Conversely, slow-onset crystal drift or intermittent SYNC (synchronization) degradation may be difficult to identify in a timely manner, resulting in missed fault reports.

[0026] In view of this, this application provides a solution that effectively filters out instantaneous periodic fluctuations by using a smoothed clock period determined by the current clock period of the slave node, obtaining a dynamic benchmark that stably reflects the long-term operating trend of the slave node's clock. Furthermore, it determines the periodic deviation rate by comparing the current clock period with the smoothed clock period and compares the periodic deviation rate with a preset deviation rate tolerance threshold. This allows the system to determine whether the clock deviates from the normal range during operation, distinguishing between normal fluctuations and potential faults, and quantifying the severity of the clock deviation to determine the clock fault level of the slave node. Finally, it executes a fault handling strategy matching the fault level. This application avoids misjudgments of faults caused by instantaneous interference and can respond promptly to serious events such as continuous degradation or loss of synchronization signals. Simultaneously, it repairs faults through fault handling strategies, thereby ensuring the safety of audio functions while enhancing the system's autonomous recovery capability and operational reliability.

[0027] It should be noted that the fault detection method can be applied to in-vehicle audio systems (e.g., A2B systems). An in-vehicle audio system includes a master node, at least one slave node, and a microcontroller module individually associated with each slave node. The execution entity of the fault detection method can be an electronic device or the microcontroller module within the in-vehicle audio system. The microcontroller module executes the fault detection method to detect clock faults in its associated slave nodes. Because each slave node in the in-vehicle audio system has its own associated microcontroller module, slave nodes with clock faults can be quickly and accurately identified, thus resolving issues such as audio interruptions, insufficient diagnostics, and delayed recovery caused by clock loss.

[0028] For example, refer to Figure 1 The in-vehicle audio system includes: Master Node 101: Master Node 101 is the brain and control center of the A2B network, undertaking core functions such as network initiation, clock synchronization, data exchange, and power management. After system power-on or reset, Master Node 101 first initiates the Discovery process, identifying and configuring all slave nodes 102 hop-by-hop, completing topology construction and parameter initialization. Simultaneously, Master Node 101 generates and broadcasts the required synchronization signal for the entire network through its high-precision master crystal oscillator, serving as the system clock source and ensuring strict synchronization of the bit clocks and sampling clocks of all slave nodes 102, laying the foundation for high-quality, low-latency audio transmission. In terms of data communication, Master Node 101 acts as the uplink and downlink data exchange center, sending audio and control data to each slave node 102 via the downlink and receiving audio signals (such as microphone and accelerometer data), status information, and fault indications from slave nodes 102 via the uplink. Upon receiving such requests, Master Node 101 can trigger a network-wide reset process to reinitialize the A2B network and restore stable clock output. In addition, the master node 101 is typically connected to the upper-layer application processor through audio interfaces such as I2S / TDM and control interfaces such as I2C, and is powered by the vehicle power supply. At the same time, it provides phantom power to the downstream slave node 102 through the A2B bus, realizing the integration of power supply and communication.

[0029] Slave Node 102; Slave Node 102 is the terminal execution unit in the system. A network can support up to 16 slave nodes 102, typically connected in a daisy-chain configuration. Slave Node 102 primarily undertakes specific functional input or output tasks: Input slave nodes 102 (such as digital microphones, sensors, etc.) are responsible for converting the collected analog signals into digital audio data and uploading them to the master node 101 via the uplink; Output slave nodes 102 (such as audio amplifiers) receive digital audio data from the master node 101, convert it into analog signals to drive speakers. In the daisy-chain topology, each slave node 102 not only processes its own data but also acts as a data relay—transparently forwarding data packets from upstream or to downstream, allowing audio and control information to be passed step-by-step like a relay baton, ultimately reaching the master node 101 or the target node. None of the slave nodes 102 have independent clock sources; instead, they are strictly locked to and follow the synchronization signal provided by the master node 101 through an internal phase-locked loop (PLL), thus ensuring a high degree of consistency in audio sampling and timing across the entire network. In addition, most of the slave nodes 102 do not require local power supply, but instead obtain their operating voltage directly from the master node 101 via the A2B bus, which significantly simplifies the wiring harness design and power supply architecture of the vehicle system.

[0030] The audio processing module 103 is used to receive raw data, receive multi-channel synchronous raw audio data from slave node 102 through interfaces such as I2S / TDM, perform reverberation, noise reduction and other algorithm processing on the received signal, and finally output the processed audio data to the signal amplification module.

[0031] The signal amplification module 104 is used to convert the digital signal received from the audio processing module 103 into an analog signal. It can also amplify weak analog electrical signals to a power level sufficient to drive the terminal speaker and make the speaker emit sound.

[0032] The microcontroller module 105 is used to interact with the above-mentioned multiple modules and execute the fault handling method of this application.

[0033] Optionally, the interaction between the microcontroller module 105 and the slave node 102 includes: capturing the synchronization signal of the slave node 102 through a timer; and handling faults based on the fault score of the slave node 102 when the synchronization signal is lost. For example, when a level 2 fault is determined, a general fault code is recorded and written to non-volatile memory, and a diagnostic request is sent through a diagnostic tool to read the fault code. When a level 1 fault is determined, a severity fault code is recorded and written to non-volatile memory, and the GPIO pin of the slave node 102 is pulled high. During operation, the master node 101 continuously acquires the GPIO pin status of the slave node 102, and immediately performs a network reset operation once it detects that a GPIO pin is pulled high.

[0034] Optionally, the interaction between the microcontroller module 105 and the audio processing module 103 includes: the microcontroller module 105 can send a smoothing command to the audio processing module 103 based on the current fault level of the slave node 102, thereby effectively avoiding the pop-up sound caused by the instantaneous loss of audio data. In addition, the microcontroller module 105 will also send a sound effect switching command to the audio processing module 103 based on the CAN message information sent by the vehicle's infotainment system, thereby realizing the control of the audio processing module 103.

[0035] Optionally, the interaction between the microcontroller module 105 and the signal amplification module 104 includes: the microcontroller module 105 configuring the signal amplification module 104 according to the audio data format, such as configuring the sampling rate and the number of channels. Simultaneously, the microcontroller module 105 continuously performs fault diagnosis on the signal amplification module 104 during system operation and saves the diagnosis results to non-volatile memory, facilitating problem localization by after-sales personnel. This ensures the reliability and robustness of the system.

[0036] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the fault detection method of this application.

[0037] For ease of description, the following embodiments are described using a microcontroller module in an in-vehicle audio system as the execution entity. The fault detection method is applied to an in-vehicle audio system (e.g., an A2B system), which includes slave nodes. The fault detection method includes steps S10-S40: Step S10: Determine the smoothed clock cycle based on the current clock cycle of the slave node; In one feasible embodiment, the in-vehicle audio system includes at least one slave node and a microcontroller module associated with each slave node. To detect clock faults in its associated slave nodes, the microcontroller module obtains the current clock cycle of the slave node and determines a smoothed clock cycle based on the current clock cycle.

[0038] The current clock cycle refers to the time interval between two consecutive synchronization signals received by the slave node during the operation of the in-vehicle audio system. This time interval is the actual clock cycle observed by the slave node at the current sampling moment. The current clock cycle reflects the true frequency characteristics of the synchronization signal at the current moment, but it may deviate from the ideal value due to factors such as power supply noise, electromagnetic interference, crystal oscillator drift, or master node abnormalities.

[0039] A smoothed clock period is a reference period value generated based on the current clock period and historical clock periods. It is used to characterize the long-term stability trend of the synchronization signal while suppressing short-term jitter caused by transient interference. The smoothed clock period is not a fixed constant but an adaptive benchmark that is continuously updated as the system operates. Its update mechanism ensures that the recent period has a greater impact on the current estimate, thereby effectively filtering out random noise while retaining information about the slow clock drift.

[0040] Optionally, the timer of the microcontroller module in the vehicle audio system is configured to rise-edge capture mode to accurately capture each rising edge of the synchronization signal, and then record the timestamps of the continuous rising edges (T1, T2, T3, ..., T...). n ), by calculating the time interval sequence T1, T2, T3, ..., T n Determine the current clock cycle.

[0041] Optionally, the microcontroller module dynamically captures the synchronization signal received from the node and records the capture timestamp; the current clock cycle is determined based on two adjacent capture timestamps.

[0042] In one feasible implementation, step S10, determining the smoothed clock cycle based on the current clock cycle of the slave node, includes steps S11-S12: Step S11: Calculate the exponentially weighted moving average of the current clock cycle; Step S12: Determine the smoothed clock cycle by the exponentially weighted moving average of the current clock cycle.

[0043] In one feasible embodiment, to filter out instantaneous jitter and track the long-term trend of the clock, the microcontroller module calculates the exponentially weighted moving average of the current clock cycle using an EWMA (Exponentially Weighted Moving Average) model, and determines the exponentially weighted moving average of the current clock cycle as the smoothed clock cycle. This allows the smoothed clock cycle to effectively filter out random noise while retaining information about the slow clock drift.

[0044] Optionally, the microcontroller module calculates the exponentially weighted moving average of the current clock cycle using the following EWMA model: t =λ×T t +(1 λ)× t-1 ; in, t T is the exponentially weighted moving average (i.e., smoothed clock cycle) of the current clock cycle.t For the current clock cycle, t-1 The EWMA model assigns higher weights to recent data, allowing the baseline (i.e., the smoothed clock cycle) to adjust adaptively and slowly. This effectively filters out random noise and more accurately reflects the normal operating state of the clock.

[0045] In this embodiment, by calculating the exponentially weighted moving average of the current clock cycle, the determined sliding clock cycle can effectively filter out random noise while retaining the information of slow clock drift, thereby supporting the improvement of the accuracy of clock fault detection.

[0046] Step S20: Determine the cycle deviation rate based on the current clock cycle and the smoothed clock cycle; In one feasible embodiment, the microcontroller module determines the cycle deviation rate based on the difference information between the current clock cycle and the smoothed clock cycle, thereby measuring the degree to which the current clock cycle deviates from the reference (i.e., the smoothed clock cycle).

[0047] Optionally, the cycle deviation rate refers to the normalized deviation of the current clock cycle from the smooth clock cycle, used to quantify the degree of abnormality of the current synchronization signal (i.e., the clock).

[0048] Optionally, the microcontroller module calculates the absolute difference between the current clock cycle and the smoothed clock cycle; and determines the cycle deviation rate based on the quotient of the absolute difference and the smoothed clock cycle.

[0049] Alternatively, the periodic deviation rate can be calculated using the following formula: ; Among them, e t The periodic deviation rate, t To smooth the clock cycle, T t This represents the current clock cycle.

[0050] Step S30: Determine the clock fault level of the slave node based on the comparison result between the cycle deviation rate and the preset deviation rate tolerance threshold. In one feasible embodiment, the microcontroller module compares the difference between the cycle deviation rate and a preset deviation rate tolerance threshold to obtain a comparison result; and then determines the clock fault level of the slave node based on the comparison result.

[0051] The deviation rate tolerance threshold is a pre-defined dimensionless threshold parameter (e.g., denoted as α) used to define the maximum acceptable relative deviation range of the slave node's current clock cycle relative to its smoothed clock cycle. This threshold can be configured according to the clock source specifications used by the in-vehicle audio system (e.g., crystal oscillator accuracy, A2B protocol requirements for synchronization signal stability, etc.), representing the upper limit of clock jitter or drift that the system can tolerate under normal operating conditions.

[0052] Optionally, the microcontroller module determines the current fault score of the slave node based on the comparison between the periodic deviation rate and a preset deviation rate tolerance threshold; and determines the clock fault level corresponding to the current fault score based on the mapping relationship between the current fault score and the preset score and level. By using fault scoring, the severity of clock deviation can be quantitatively assessed, and multiple fault levels can be classified accordingly, thereby solving the problem that traditional in-vehicle audio systems have difficulty in determining the severity of clock faults.

[0053] Step S40: Execute the fault handling strategy corresponding to the clock fault level.

[0054] In one feasible embodiment, the microcontroller module executes the fault handling strategy corresponding to the determined clock fault level of the slave node, thereby enhancing the system's autonomous recovery capability and operational reliability while ensuring the safety of audio functions.

[0055] In this embodiment, by using a smoothed clock cycle determined from the current clock cycle of the slave node, instantaneous periodic fluctuations are effectively filtered out, obtaining a dynamic benchmark that stably reflects the long-term operating trend of the slave node's clock. Then, the periodic deviation rate is determined by comparing the current clock cycle with the smoothed clock cycle, and compared with a preset deviation rate tolerance threshold. This allows the system to determine whether the clock deviates from the normal range during operation, distinguishing between normal fluctuations and potential faults, and quantifying the severity of clock deviations to determine the clock fault level of the slave node. A fault handling strategy matching the fault level is then executed. This embodiment avoids misjudgments of faults caused by instantaneous interference and can respond promptly to serious events such as continuous degradation or loss of synchronization signals. Furthermore, by repairing faults through fault handling strategies, it enhances the system's autonomous recovery capability and operational reliability while ensuring audio function safety.

[0056] Based on the first embodiment described above, a second embodiment of the fault detection method of this application is proposed. In this embodiment, step S30, which determines the clock fault level of the slave node based on the comparison result of the cycle deviation rate and the preset deviation rate tolerance threshold, includes steps S31 to S32: Step S31: Based on the comparison results and the historical fault scores of the slave node, determine the current fault score of the slave node. Wherein, if the period deviation rate is less than or equal to the deviation rate tolerance threshold, the fault severity represented by the historical fault score is higher than or equal to the fault severity represented by the current fault score. If the period deviation rate is greater than the deviation rate tolerance threshold, the fault severity represented by the historical fault score is lower than the fault severity represented by the current fault score. In one feasible embodiment, to quantify the severity of clock skew, the microcontroller module can calculate a fault score for the slave node. The microcontroller module then obtains the historical fault scores of the slave node and adjusts them based on a comparison between the periodic skew rate and a preset skew rate tolerance threshold to obtain the current fault score for the slave node. If the comparison determines that the periodic skew rate is less than the skew rate tolerance threshold, the fault severity represented by the historical fault score is higher than that represented by the current fault score; that is, the current fault score is configured to indicate a trend of system state improvement. If the comparison determines that the periodic skew rate is greater than the skew rate tolerance threshold, the fault severity represented by the historical fault score is lower than that represented by the current fault score; that is, the current fault score is configured to indicate a trend of system state deterioration. If the comparison determines that the periodic skew rate is equal to the skew rate tolerance threshold, the historical fault score is determined as the current fault score, i.e., no adjustment is made.

[0057] Optionally, the historical fault rating customer is the fault rating of the previous period.

[0058] In one feasible implementation, the comparison result includes the difference in deviation rate between the periodic deviation rate and the deviation rate tolerance threshold. Step S31, determining the current fault score of the slave node based on the comparison result and the historical fault scores of the vehicle audio system, includes steps S311-S312: Step S311: Determine the scoring adjustment amount based on the deviation rate difference and the preset gain coefficient; Step S312: Adjust the historical fault scores based on the score adjustment amount to obtain the current fault score.

[0059] In one feasible embodiment, the microcontroller module calculates the deviation rate difference between the cycle deviation rate and the deviation rate tolerance threshold, determines the score adjustment amount based on the product of the deviation rate difference and a preset gain coefficient, and then adjusts the historical fault scores based on the score adjustment amount to obtain the current fault score.

[0060] Optionally, the microcontroller module determines the current fault score according to the following formula: ; Among them, S t S is the score for the current fault.t-1 Historical fault rating (i.e., fault rating of the previous cycle). This is the periodic deviation rate. For deviation rate tolerance threshold (e.g., (This indicates that a 5% deviation is allowed) This is the gain coefficient, used to control the response speed of the current fault score to deviations (e.g., ).

[0061] Understandably, the fault score is equivalent to a health score (Scroe). A higher fault score indicates a lower health level and a more severe fault; conversely, a lower fault score indicates a higher health level and a less severe fault. When When the microcontroller module considers the clock to be in a healthy state, the fault score is reduced; when At this time, the microcontroller module considers an anomaly to have occurred, which increases the fault score.

[0062] In one feasible embodiment, the in-vehicle audio system includes: a master node; step S20, determining the cycle deviation rate based on the current clock cycle and the smoothed clock cycle, includes steps A10~A20: Step A10: Determine the current clock cycle of the slave node based on the synchronization signal sent by the master node; Step A20: If no synchronization signal is detected within a preset time period, the period deviation rate is set to the preset maximum deviation rate, wherein the maximum deviation rate is greater than the deviation rate tolerance threshold.

[0063] In one feasible embodiment, the current clock cycle of the slave node will be determined based on the synchronization signal received by the slave node. If the microcontroller module does not detect the synchronization signal within a preset time, it means that the synchronization signal is lost. This will be regarded as the most serious deviation, and the cycle deviation rate will be set to the preset maximum deviation rate (for example, the preset maximum deviation rate is 1), thereby rapidly increasing the severity of the fault represented by the current fault score.

[0064] Optionally, if no synchronization signal is detected within a preset time period, the microcontroller module is set to... =1, thus rapidly increasing S t .

[0065] Optionally, the maximum deviation rate is greater than the deviation rate tolerance threshold.

[0066] Optionally, the microcontroller module is equipped with a watchdog timer. If the watchdog timer fails to detect a synchronization signal within a preset duration, the microcontroller module sets the period deviation rate to the preset maximum deviation rate.

[0067] In this embodiment, if no synchronization signal is detected within a preset time period, the periodic deviation rate is forcibly set to the preset maximum deviation rate (e.g., 1, which represents 100% deviation). This eliminates the need for an additional fault judgment branch; instead, a unified deviation rate calculation and scoring update mechanism naturally triggers the most severe fault response. This approach maintains the consistency and simplicity of the fault detection logic while ensuring that the extreme anomaly of complete synchronization signal loss can be quickly and reliably identified. Since the periodic deviation rate far exceeds the deviation rate tolerance threshold, the scoring mechanism in this embodiment immediately generates the maximum score adjustment, causing the fault score to quickly approach the extreme value representing a severe fault, thereby promptly initiating an appropriate fault handling strategy.

[0068] Step S32: Determine the clock fault level of the slave node based on the current fault score.

[0069] In one feasible embodiment, the microcontroller module determines the clock fault level of the slave node based on the current fault score and a preset score-level mapping relationship.

[0070] Optionally, the mapping relationship between the score and the level can include: if the fault score is >90, the fault level is Level 1; if the fault score is 50 < 90, the fault level is Level 2; if the fault score is ≤50, the fault level is Level 3; wherein, the severity of Level 1 faults is higher than that of Level 2 faults, and the severity of Level 2 faults is higher than that of Level 3 faults.

[0071] In this embodiment, the microcontroller module calculates the current fault score of the slave node using a cumulative deviation model. This allows small, random deviations to be tolerated, while continuous, unidirectional deviations are accumulated and amplified. This accurately reflects the clock degradation level of the slave node, improving the robustness and sensitivity of fault detection. It avoids misjudgments caused by transient interference and can promptly capture slowly evolving potential faults, providing the system with reliable early warnings and accurate health status assessments.

[0072] Based on any of the above embodiments, a third embodiment of the fault detection method of this application is proposed. In this embodiment, the vehicle audio system includes: a master node; step S40, the step of executing the fault handling strategy corresponding to the clock fault level includes steps S41~S42: Step S41: In the case of a clock fault level of Level 1, set the fault indication flag of the slave node. In one feasible embodiment, the vehicle audio system includes a master node, and the microcontroller module sets a fault indication flag for the slave node when it determines that the clock fault level of the slave node is a level one fault.

[0073] Optionally, setting the fault indication flag of the slave node includes setting the fault flag GPIO pin of the slave node to a high level.

[0074] Optionally, if the clock fault is determined to be a Level 1 fault, information including the fault type and timestamp is stored in non-volatile memory.

[0075] In step S42, the master node performs a network reset operation upon receiving a fault indication flag.

[0076] In one feasible embodiment, if a fault indication flag is set, the master node will perform a reset operation if it detects the fault indication flag. After the reset, the fault indication flag of the slave node will be cleared, and the current fault score will be reset to the default value (e.g., 0) as the historical fault score for the next cycle, thus entering the next monitoring cycle.

[0077] Optionally, based on the mapping relationship between the above scores and levels, it can be seen that the higher the current fault score, the higher the degree of fault. Therefore, Level 1 fault is the most serious fault level, which means that the slave node has a long-term loss of synchronization signal. Therefore, it is necessary to restore it through the network reset operation of the master node.

[0078] Optionally, the master node will periodically poll all slave nodes in the system to determine whether they have a fault indication flag set.

[0079] In one feasible implementation, step S42, the step of performing the network reset operation, includes: steps S421~S423: Step S421: Determine the historical fault information of the slave node through the master node; Step S422: Based on historical fault information, determine whether the slave node meets the preset frequent fault conditions; Step S423: If the slave node meets the preset frequent failure conditions, isolate the slave node.

[0080] In one feasible embodiment, the master node determines the historical fault information of the slave node; it then determines whether the historical fault information of the slave node meets a preset frequent fault condition. If it does, it indicates that the slave node has a high fault frequency, and the slave node is isolated to ensure maximum system availability. If it does not meet the condition, a normal network reset operation is performed on the slave node.

[0081] In this embodiment, by setting the fault indication flag of the slave node, the master node will automatically perform a network reset operation, thereby realizing system protection and intelligent recovery.

[0082] In one feasible implementation, refer to Figure 3 Step S40, the steps for executing the fault handling strategy corresponding to the clock fault level include steps S43~S46: Step S43: In the case of a clock fault level of level 2, determine the trend of the fault score of the slave node, wherein the severity of level 1 fault is higher than that of level 2 fault, and the fault score is used to determine the clock fault level. In one feasible embodiment, when the microcontroller module determines that the clock fault level of the slave node is a level 2 fault, it determines the changing trend of the slave node's fault score. Based on the mapping relationship between the score and the level, the higher the current fault score, the more severe the fault. Therefore, level 1 fault is the most severe fault level, representing a long-term loss of synchronization signal from the slave node, requiring recovery through a network reset operation of the master node. Level 2 fault is the next most severe fault level, representing a possible short-term loss of synchronization signal from the slave node, but not yet reaching a very serious level. This may correspond to short-term or intermittent synchronization loss. In this case, the system does not immediately perform strong intervention but continuously monitors the changing trend of the fault score. If the score shows a continuous upward trend, it indicates that the signal loss is worsening or evolving into a persistent fault, requiring intervention. If the score tends to stabilize or fall back, it is determined to be a transient interference, and the current operating state can be maintained while continuing observation.

[0083] Step S44: If the trend of the fault score change of the slave node meets the preset upward trend, identify the amplitude information of the audio data currently played by the vehicle audio system. In one feasible embodiment, if the trend of the fault score change of the slave node meets the preset upward trend, it means that the signal loss is deteriorating or evolving into a persistent fault, and intervention is required to identify the amplitude information of the audio data currently played by the vehicle audio system.

[0084] Optionally, if the clock fault is determined to be a level two fault, information including the fault type and timestamp is stored in non-volatile memory.

[0085] Optionally, the clock fault levels include: Level 1 fault, Level 2 fault, and Level 3 fault. Level 1 fault is more severe than Level 2 fault, representing long-term data loss; Level 2 fault is more severe than Level 3 fault, representing short-term data loss; and Level 1 fault is the least severe, representing tolerable jitter.

[0086] Optionally, if the trend of the fault score of the slave node does not meet the preset upward trend, then only the information including the fault type and timestamp is stored in the non-volatile memory, and further fault detection is carried out.

[0087] Step S45: Generate an exponential decay curve of the amplitude based on the amplitude information; Step S46: Process the audio data based on the exponential decay curve of the amplitude.

[0088] In one feasible embodiment, an exponential decay curve of the amplitude is generated based on the amplitude information of the audio data currently played by the vehicle audio system. Then, based on the exponential decay curve of the amplitude, the audio data currently played by the vehicle audio system is processed to achieve adaptive smooth muting processing of the audio data and avoid the generation of a harsh "POP" sound due to sudden audio interruption.

[0089] In this embodiment, based on the changing trend of the fault score of the slave node, when it is determined that the signal loss of the slave node is worsening or evolving into a persistent fault, an exponential decay curve of the amplitude is generated based on the amplitude information of the audio data currently played by the vehicle audio system. The audio data is then processed based on this curve to achieve adaptive smooth muting of the audio data, avoiding the harsh "POP" sound caused by sudden audio interruptions. This embodiment uses a three-step strategy of "identification-recording-recovery" to achieve a closed loop, solving the problems of audio interruption, insufficient diagnosis, and delayed recovery caused by clock loss.

[0090] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the fault detection method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0091] This application provides a fault detection device, referring to... Figure 4 The device is used in an in-vehicle audio system, the in-vehicle audio system including: a slave node, the device including: The period determination module 10 is used to determine a smooth clock period based on the current clock period of the slave node; The deviation rate determination module 20 is used to determine the cycle deviation rate based on the current clock cycle and the smoothed clock cycle; The fault level determination module 30 is used to determine the clock fault level of the slave node based on the comparison result between the cycle deviation rate and the preset deviation rate tolerance threshold. The execution module 40 is used to execute the fault handling strategy corresponding to the clock fault level.

[0092] The fault detection device provided in this application, employing the fault detection method described in the above embodiments, can solve the technical problem of low accuracy in clock fault detection. Compared with the prior art, the beneficial effects of the fault detection device provided in this application are the same as those of the fault detection method described in the above embodiments, and other technical features in the fault detection device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0093] This application provides an electronic device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, which are executed by the at least one processor to enable the at least one processor to perform the fault detection method in the first embodiment described above.

[0094] The following is for reference. Figure 5 The diagrams show structural schematics of electronic devices suitable for implementing the embodiments of this application. The electronic devices in the embodiments of this application may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0095] like Figure 5 As shown, the electronic device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage device 1003 into a random access memory (RAM) 1004. The RAM 1004 also stores various programs and data required for the operation of the electronic device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touchscreen, touchpad, keyboard, mouse, camera, microphone, accelerometer, gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), speaker, vibrator, etc.; storage devices 1003 including, for example, magnetic tape, hard disk, etc.; and communication devices 1009. Communication device 1009 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. While electronic devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0096] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0097] The electronic device provided in this application, employing the fault detection method described in the above embodiments, can solve the technical problem of low accuracy in clock fault detection. Compared with the prior art, the beneficial effects of the electronic device provided in this application are the same as those of the fault detection method provided in the above embodiments, and other technical features of the electronic device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0098] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0099] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0100] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the fault detection method in the above embodiments.

[0101] The computer-readable storage medium provided in this application embodiment may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0102] The aforementioned computer-readable storage medium may be included in an electronic device or may exist independently without being assembled into an electronic device.

[0103] The aforementioned computer-readable storage medium carries one or more programs. When the aforementioned one or more programs are executed by an electronic device, the electronic device causes the electronic device to: determine a smoothed clock cycle based on the current clock cycle of the slave node; determine a cycle deviation rate based on the current clock cycle and the smoothed clock cycle; determine the clock fault level of the slave node based on a comparison between the cycle deviation rate and a preset deviation rate tolerance threshold; and execute a fault handling strategy corresponding to the clock fault level.

[0104] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0105] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0106] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0107] The readable storage medium provided in this application embodiment is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described fault detection method, thereby solving the technical problem of low accuracy in clock fault detection. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application embodiment are the same as the beneficial effects of the fault detection method provided in the above embodiments, and will not be repeated here.

[0108] The above are only some embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A fault detection method, characterized in that, The method is applied to an in-vehicle audio system, the in-vehicle audio system comprising: a slave node, the method comprising: Determine the smoothed clock cycle based on the current clock cycle of the slave node; Determine the cycle deviation rate based on the current clock cycle and the smoothed clock cycle; The clock fault level of the slave node is determined based on the comparison result between the cycle deviation rate and the preset deviation rate tolerance threshold. Execute the fault handling strategy corresponding to the clock fault level.

2. The method as described in claim 1, characterized in that, The step of determining the smoothed clock period based on the current clock period of the slave node includes: Calculate the exponentially weighted moving average of the current clock cycle; The exponentially weighted moving average of the current clock cycle is determined as the smoothed clock cycle.

3. The method as described in claim 1, characterized in that, The step of determining the clock fault level of the slave node based on the comparison result of the period deviation rate and the preset deviation rate tolerance threshold includes: Based on the comparison results and the historical fault scores of the slave node, the current fault score of the slave node is determined, wherein, when the cycle deviation rate is less than or equal to the deviation rate tolerance threshold, the fault severity represented by the historical fault score is higher than or equal to the fault severity represented by the current fault score; when the cycle deviation rate is greater than the deviation rate tolerance threshold, the fault severity represented by the historical fault score is lower than the fault severity represented by the current fault score. The clock fault level of the slave node is determined based on the current fault score.

4. The method as described in claim 3, characterized in that, The comparison result includes the deviation rate difference between the period deviation rate and the deviation rate tolerance threshold. The step of determining the current fault score of the slave node based on the comparison result and the historical fault scores of the vehicle audio system includes: The scoring adjustment amount is determined based on the deviation rate difference and the preset gain coefficient; The historical fault score is adjusted based on the aforementioned score adjustment amount to obtain the current fault score.

5. The method as described in claim 1, characterized in that, The in-vehicle audio system includes a master node, and the step of determining the cycle deviation rate based on the current clock cycle and the smoothed clock cycle includes: The current clock cycle of the slave node is determined based on the synchronization signal sent by the master node; If the synchronization signal is not detected within a preset time period, the period deviation rate is set to a preset maximum deviation rate, wherein the maximum deviation rate is greater than the deviation rate tolerance threshold.

6. The method as described in claim 1, characterized in that, The in-vehicle audio system includes a master node, and the step of executing the fault handling strategy corresponding to the clock fault level includes: If the clock fault level is Level 1, set the fault indication flag of the slave node; Upon receiving the fault indication flag, the master node performs a network reset operation.

7. The method as described in claim 6, characterized in that, The steps for performing the network reset operation include: The master node is used to determine the historical fault information of the slave node; Based on the historical fault information, determine whether the slave node meets the preset frequent fault conditions; If the slave node meets the preset frequent failure conditions, the slave node is isolated.

8. The method as described in claim 6, characterized in that, The steps for executing the fault handling strategy corresponding to the clock fault level include: In the case where the clock fault level is a level 2 fault, the trend of the fault score change of the slave node is determined, wherein the severity of the level 1 fault is higher than that of the level 2 fault, and the fault score is used to determine the clock fault level; When the trend of the fault score change of the slave node meets the preset upward trend, the amplitude information of the audio data currently played by the vehicle audio system is identified. Based on the amplitude information, an exponential decay curve of the amplitude is generated; The audio data is processed based on the exponential decay curve of the amplitude.

9. An electronic device, characterized in that, The electronic device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the fault detection method as described in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the steps of the fault detection method as described in any one of claims 1 to 8.

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