Semiconductor packaging structure, information transmission method, manufacturing method and optical interconnection equipment
By employing optical interconnect substrates and optical waveguide units in semiconductor packaging, optical signal transmission between chips is achieved, solving the energy consumption and delay problems of electrical interconnect methods and improving interconnect performance and the degree of packaging integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI XIZHI TECH CO LTD
- Filing Date
- 2021-11-26
- Publication Date
- 2026-04-24
AI Technical Summary
In existing semiconductor packaging, electrical interconnection methods suffer from energy consumption, delay, and crosstalk issues in high-speed communication between chiplets, making it difficult to meet the requirements of high-speed communication.
An optical interconnect substrate is used to realize optical signal transmission between chips through optical waveguide units and conversion units. By utilizing the conversion between optical signals and electrical signals, energy loss and delay are reduced, and interconnect performance is improved.
It reduces energy loss and crosstalk between chips, improves interconnect performance, and helps to miniaturize and integrate chip packaging.
Smart Images
Figure CN121918249A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure, information transmission method, manufacturing method, and optical interconnect device. Background Technology
[0002] With the development of VLSI technology, people have not only put forward performance requirements for chips, such as high speed, low power consumption, and high reliability, but also requirements for miniaturization and integrated packaging. In existing semiconductor packaging, electrical wires, such as copper dielectric, are typically used to interconnect different chips to achieve signal transmission. In some scenarios, such as the interconnection of chiplets, this electrical interconnection method suffers from problems such as energy consumption, delay, and crosstalk, making it difficult to meet the high-speed communication requirements between chiplets. Summary of the Invention
[0003] In view of the above problems, this application is made to provide a semiconductor packaging structure, information transmission method, manufacturing method and optical interconnect device that solves or at least partially solves the above problems.
[0004] Therefore, in one embodiment of this application, a semiconductor packaging structure is provided. The packaging structure includes: an optical interconnect substrate; the optical interconnect substrate includes: a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals; the first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first conversion unit; the second conductive wiring unit is electrically connected to the second conversion unit. A first chip and a second chip mounted on the optical interconnect substrate; The first chip is electrically connected to the first conductive wiring unit, and the second chip is electrically connected to the second conductive wiring unit. Communication between the first chip and the second chip is achieved through the optical interconnect substrate.
[0005] In another embodiment of this application, an information transmission method for a semiconductor package structure is provided, wherein the semiconductor package structure includes: an optical interconnect substrate and a first chip and a second chip mounted on the optical interconnect substrate; the optical interconnect substrate includes: a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals; the first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first conversion unit; the second conductive wiring unit is electrically connected to the second conversion unit; the first chip is electrically connected to the first conductive wiring unit; and the second chip is electrically connected to the second conductive wiring unit. The method includes: The first chip transmits a first electrical signal carrying information to the first conductive wiring unit; The first conversion unit converts the first electrical signal into a first optical signal; The second conversion unit converts the first optical signal transmitted from the optical waveguide unit into a second electrical signal; The second chip receives the second electrical signal transmitted by the second conductive wiring unit.
[0006] In another embodiment of this application, a semiconductor manufacturing method is provided, comprising: Provide wafers; Multiple photonic integrated circuits are formed on the wafer. Each of the multiple photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals. The first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit. The first conductive wiring unit is electrically connected to the first conversion unit. The second conductive wiring unit is electrically connected to the second conversion unit. A first chip and a second chip are mounted on each of the plurality of photonic integrated circuits, such that the first chip is electrically connected to the first conductive wiring unit and the second chip is electrically connected to the second conductive wiring unit. The wafer is divided to obtain multiple independent semiconductor package structures; each semiconductor package structure includes the photonic integrated circuit and the first chip and the second chip mounted on the photonic integrated circuit; The first chip and the second chip can communicate through the first conductive wiring unit, the first conversion unit, the optical waveguide unit, the second conversion unit, and the second conductive wiring unit.
[0007] In another embodiment of this application, a semiconductor manufacturing method is provided, comprising: Provide wafers; Multiple photonic integrated circuits are formed on the wafer. Each of the multiple photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals. The first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit. The first conductive wiring unit is electrically connected to the first conversion unit. The second conductive wiring unit is electrically connected to the second conversion unit. The wafer is divided to obtain multiple independent photonic integrated circuit chips; each photonic integrated circuit chip includes the photonic integrated circuit. A first chip and a second chip are mounted on each of the plurality of photonic integrated circuit chips, such that the first chip is electrically connected to the first conductive wiring unit and the second chip is electrically connected to the second conductive wiring unit. The first chip and the second chip can communicate through the first conductive wiring unit, the first conversion unit, the optical waveguide unit, the second conversion unit, and the second conductive wiring unit.
[0008] In another embodiment of this application, a semiconductor package structure is provided, comprising: An optical interconnect interposer layer has a first surface and a second surface opposite to the first surface. The optical interconnect interposer layer includes: a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals. The first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit. The first conductive wiring unit is electrically connected to the first conversion unit. The second conductive wiring unit is electrically connected to the second conversion unit. A first chip and a second chip mounted on the first surface of the optical interconnect interposer layer; The first chip is electrically connected to the first conductive wiring unit, and the second chip is electrically connected to the second conductive wiring unit, so that the optical interconnect interposer is used to realize communication between the first chip and the second chip; and A carrier substrate, wherein the optical interconnect interposer is disposed on the carrier substrate, and the second surface of the optical interconnect interposer faces the carrier substrate.
[0009] In another embodiment of this application, an optical interconnect device is provided, comprising: the semiconductor packaging structure described in any of the preceding claims.
[0010] In the technical solution provided in this application embodiment, the first chip and the second chip are packaged on an optical interconnect substrate. Signal transmission between them can be achieved using light based on the first conversion unit, the second conversion unit, and the waveguide unit of the optical interconnect substrate. Compared to transmitting electrical signals via electrical wires, transmitting optical signals via waveguides reduces energy loss, delay, and crosstalk, thus improving the interconnection performance between chips and facilitating miniaturization and integration of chip packaging. Attached Figure Description
[0011] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 This is a cross-sectional schematic diagram of a semiconductor packaging structure provided in an embodiment of this application; Figure 2 This is a schematic diagram showing the connection between the first conversion unit and the second conversion unit in one embodiment of this application; Figure 3 This is a schematic diagram showing the connection between the first conversion unit and the second conversion unit in one embodiment of this application; Figure 4 This is a schematic diagram showing the connection between the first conversion unit and the second conversion unit in one embodiment of this application; Figure 5 A schematic flowchart illustrating an information transmission method provided in an embodiment of this application; Figure 6 A schematic flowchart illustrating a manufacturing method provided in an embodiment of this application; Figure 7 This is a cross-sectional schematic diagram of the relevant structures during the fabrication of a photonic integrated circuit according to an embodiment of this application; Figure 8 This is a cross-sectional schematic diagram of the relevant structures during the fabrication of a photonic integrated circuit according to an embodiment of this application; Figure 9 This is a cross-sectional schematic diagram of the relevant structures during the fabrication of a photonic integrated circuit according to an embodiment of this application; Figure 10 This is a schematic flowchart of a manufacturing method provided in another embodiment of this application. Detailed Implementation
[0013] Currently, very large-scale integrated circuit (VLSI) technology has become a pillar supporting the development and evolution of the information society. Various chips widely used in information systems typically rely on upgrades in chip manufacturing processes to improve performance and optimize power consumption. However, as chip manufacturing processes gradually approach their physical limits, the pace of Moore's Law is slowing, and further development requires new approaches. Previously, one chip architecture integrated multiple functions into a single chip to meet requirements. In recent years, the area of this type of single chip has increased, integration complexity has risen, production yields have decreased, and costs have increased, posing challenges to this approach.
[0014] To address the aforementioned issues, chiplet technology has been proposed. This involves replacing a single, multifunctional large chip with multiple chiplets, overcoming the physical bottleneck of chip area and representing a crucial pathway to achieving higher-performance chips. Because each die (chiplet) has a smaller area, the number of dies that can be placed on a single wafer during manufacturing increases, thereby improving yield and reducing costs. Furthermore, when improving system performance, chiplet technology allows for flexible upgrades of only specific modules, thus accelerating the system upgrade iteration cycle. However, the feasibility of chiplets is often limited by the performance, availability, and power consumption of inter-chip electrical interconnects. On the other hand, with the development of artificial intelligence, deep learning algorithms often require high-speed transmission of large amounts of data between computing and storage units within a computing chip. This makes the power consumption, bandwidth density, and latency of traditional electrical interconnects even more critical issues, thus limiting the development of higher-performance AI chips.
[0015] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.
[0016] Furthermore, some processes described in the specification, claims, and accompanying drawings of this application include multiple operations that appear in a specific order. These operations may be performed out of order or in parallel. Operation numbers such as 101, 102, etc., are merely used to distinguish different operations and do not represent any execution order. Additionally, these processes may include more or fewer operations, and these operations may be performed sequentially or in parallel. It should be noted that the terms "first," "second," etc., used herein are used to distinguish different messages, devices, modules, etc., and do not represent a sequential order, nor do they limit "first" and "second" to different types.
[0017] In some embodiments, a photonic integrated circuit (PIC) is provided, which can be used for optical interconnection. The photonic integrated circuit includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals; the first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first conversion unit; and the second conductive wiring unit is electrically connected to the second conversion unit. The photonic integrated circuit can optically interconnect multiple chips with electrical signal inputs / outputs. In the photonic integrated circuit, the electrical signals of the external chip to be communicated with are converted into optical signals for transmission, thereby realizing communication between multiple chips. The above-mentioned photonic integrated circuit can be manufactured using conventional semiconductor processes to form a photonic integrated circuit chip or a photonic integrated circuit interposer. In some embodiments, the above-mentioned photonic integrated circuit chip or photonic integrated circuit interposer can serve as an optical interconnect substrate. This optical interconnection is particularly suitable for interconnect packages such as chiplets.
[0018] Figure 1 A schematic diagram of a semiconductor packaging structure provided in an embodiment of this application is shown. Figure 1As shown, a semiconductor package structure 100 includes: an optical interconnect substrate 10; the optical interconnect substrate 10 includes: a first conductive wiring unit 101, a second conductive wiring unit 102, an optical waveguide unit 103, and a first conversion unit 104 and a second conversion unit 105 for converting optical signals to electrical signals; the first conversion unit 104 and the second conversion unit 105 are respectively coupled to the optical waveguide unit 103; the first conductive wiring unit 101 is electrically connected to the first conversion unit 104; the second conductive wiring unit 102 is electrically connected to the second conversion unit 105; a first chip 20 and a second chip 30 are mounted on the optical interconnect substrate 10; wherein the first chip 20 is electrically connected to the first conductive wiring unit 101, and the second chip 30 is electrically connected to the second conductive wiring unit 102, and signal transmission between the first chip 20 and the second chip 30 is realized through the optical interconnect substrate 10. The optical interconnect substrate 10 includes a first surface and a second surface opposite to the first surface. For example, the first chip 20 and the second chip 30 are disposed on the first surface of the optical interconnect substrate 10. The first conversion unit 104 described above can be used to realize the mutual conversion between electrical signals and optical signals, that is, the first conversion unit 104 can not only be used to convert electrical signals into optical signals, but also to convert optical signals into electrical signals. The second conversion unit 105 can be used to realize the mutual conversion between electrical signals and optical signals, that is, the second conversion unit 105 can not only be used to convert electrical signals into optical signals, but also to convert optical signals into electrical signals.
[0019] In some embodiments, the first conversion unit 104 and the second conversion unit 105 may each include different types of devices, such as photoelectric converters and electro-optic converters. The number of related devices is not particularly limited. The number of electrical connection lines in the first conductive wiring unit 101 and the second conductive wiring unit 102 corresponds to the electrical connection requirements, for example, it depends on the number of devices and the number of electrical connection ports of the devices. A device may have one or more electrical connection ports. For example, the first conductive wiring unit may have, for example, four electrical connection lines to electrically connect the four devices of the first conversion unit 104 to the four ports of the first chip 20, respectively.
[0020] For example, both the first conversion unit 104 and the second conversion unit 105 can realize the mutual conversion between electrical signals and optical signals, and the first chip 20 and the second chip 30 can communicate with each other. For example, when the first chip 20 needs to transmit information to the second chip 30, the first chip 20 can transmit a first electrical signal carrying information to the first conductive wiring unit 101; the first conversion unit 104 converts the first electrical signal received by the first conductive wiring unit 101 into a first optical signal, and the first optical signal is transmitted to the second conversion unit 105 through the optical waveguide unit 103; the second conversion unit 105 converts the first optical signal into a second electrical signal, and transmits it to the second chip 30 through the second conductive wiring unit 102, thereby completing the information transmission from the first chip 20 to the second chip 30. When the second chip 30 needs to transmit data to the first chip 20, the second chip 30 can transmit a third electrical signal carrying information to the second conductive wiring unit 102; the second conversion unit 105 converts the third electrical signal received by the second conductive wiring unit 102 into a second optical signal, and the second optical signal is transmitted to the first conversion unit 104 through the optical waveguide unit 103; the first conversion unit 104 converts the second optical signal into a fourth electrical signal, and transmits it to the first chip 20 through the first conductive wiring unit 101, thereby completing the information transmission from the second chip 30 to the first chip 20. The first electrical signal may include one or a group of signals, for example, it represents a signal (or a signal from one or more ports or channels) of the first chip 20. For example, when the first chip has four ports communicating via an optical interconnect substrate, the first electrical signal includes electrical signals transmitted through these four ports. The second to fourth electrical signals, which are also from or output to the corresponding first / second chip, are understood similarly; the first optical signal and the second optical signal are also understood similarly, they include one or a group of signals, which may be signals transmitted through one or more ports / waveguides / channels.
[0021] In some embodiments, in addition to the first chip 20 and the second chip 30, a third chip or more chips may be connected to the optical interconnect substrate. The type of chip is not particularly limited, as long as the chip can input and / or output appropriate electrical signals. They communicate with the optical interconnect substrate through electrical signals, and the electrical signals are converted into optical signals for transmission in the optical interconnect substrate.
[0022] In some embodiments, certain chips can be electrically connected to the first chip 20 to send electrical signals to and / or receive electrical signals from the first chip 20. In the technical solution provided by this application embodiment, the first chip and the second chip are packaged on an optical interconnect substrate, and signal transmission between them can be achieved using light based on the first conversion unit, the second conversion unit, and the waveguide of the optical interconnect substrate. Compared to transmitting electrical signals through electrical wires, transmitting optical signals through waveguides can reduce energy loss, delay, crosstalk, and other problems, helping to improve the interconnection performance between chips, especially providing a solution for chiplet interconnection. Furthermore, the aforementioned optical interconnect substrate includes photonic integrated circuits, which have high integration and can be directly applied to the interconnection between chips with electrical signal input / output, thereby facilitating the miniaturization and integration of chip packaging.
[0023] In one example, the optical interconnect substrate 10 further includes: a dielectric layer 106; the optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105 are located in the dielectric layer 106; the first conductive wiring unit 101 includes a first electrical connection structure 101a, which passes through at least a portion of the dielectric layer 106; the second conductive wiring unit 102 includes a second electrical connection structure 102a, which passes through at least a portion of the dielectric layer 106; the first chip 20 and the second chip 30 are mounted on the mounting surface of the dielectric layer 106.
[0024] In one feasible embodiment, the material of the dielectric layer 106 may include silicon oxide and / or silicon nitride. The chemical formula of silicon oxide is... Where x and y > 0, their ratio is not particularly limited, and other elements may be doped. In one example, the aforementioned silicon oxide may specifically include silicon dioxide.
[0025] The first electrical connection structure 101a is exposed on the mounting surface of the dielectric layer 106. The second electrical connection structure 102a is exposed on the mounting surface of the dielectric layer 106. In one specific embodiment, the first chip 20 is electrically connected to the portion of the first electrical connection structure 101a exposed on the mounting surface of the dielectric layer 106, and the second chip 30 is electrically connected to the portion of the second electrical connection structure 102a exposed on the mounting surface of the dielectric layer 106. In another specific embodiment, such as... Figure 9As shown, the first conductive wiring unit 101 may further include a first bonding structure 101b formed on the mounting surface and electrically connected to the first electrical connection structure 101a. The second conductive wiring unit 102 may further include a second bonding structure 102b formed on the mounting surface and electrically connected to the second electrical connection structure 102a. The first bonding structure 101b and the second bonding structure 102b are not essential and can be set according to bonding requirements.
[0026] The optical waveguide unit 103, the first conversion unit 104 and the second conversion unit 105 are located inside the dielectric layer 106, that is, the optical waveguide unit 103, the first conversion unit 104 and the second conversion unit 105 are wrapped inside the dielectric layer 106.
[0027] The optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105 are formed by patterning and doping a semiconductor layer. After the optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105 are formed, a dielectric layer 106 is deposited to cover the optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105. A first opening and a second opening are formed in the dielectric layer 106 by etching. A first electrical connection structure 101a is formed in the first opening, and a second electrical connection structure 102a is formed in the second opening.
[0028] In one example, the aforementioned optical interconnect substrate may include a photonic integrated circuit (PIC). The photonic integrated circuit may include a first conductive wiring unit 101, a second electrical connector (second conductive wiring unit 102), an optical waveguide unit 103, and a first conversion unit 104 and a second conversion unit 105 for converting optical signals to electrical signals. The photonic integrated circuit can be manufactured using conventional semiconductor processes, such as the common CMOS process. The photonic integrated circuit can optically interconnect multiple chips with electrical signal inputs / outputs. In the photonic integrated circuit, the electrical signals of the external chip to be communicated with are converted into optical signals for transmission, thereby realizing communication between multiple chips. Since the aforementioned photonic integrated circuit can transmit, receive, and convert electrical signals, it can realize the interconnection of chips with electrical signal inputs / outputs. In some embodiments, the aforementioned optical interconnect substrate may further include a semiconductor substrate and an insulating layer disposed on the semiconductor substrate. The optical waveguide unit, the first conversion unit, and the second conversion unit are formed on the insulating layer, and the dielectric layer is disposed on the insulating layer and covers the optical waveguide unit, the first conversion unit, and the second conversion unit. For example, the aforementioned optical interconnect substrate may be formed based on an SOI (Silicon-On-Insulator) substrate / wafer, wherein the aforementioned semiconductor substrate is specifically the back substrate in the SOI substrate / wafer, and the aforementioned insulating layer is specifically a buried oxide layer introduced between the top silicon layer and the back substrate in the SOI substrate / wafer, and the optical waveguide unit, the first conversion unit, and the second conversion unit are formed based on the top silicon layer in the SOI substrate / wafer.
[0029] In another example, the aforementioned optical interconnect substrate can be an optical interconnect interposer, such as a photonic integrated circuit interposer. Figure 1 As shown, the semiconductor package structure 100 may further include: a carrier substrate 40; the optical interconnect substrate 10 is mounted on the carrier substrate 40. The optical interconnect interposer can be obtained by thinning the semiconductor substrate of the photonic integrated circuit in the above embodiment. The carrier substrate may be, for example, a circuit board, such as a PCB board, or other substrate. The optical interconnect interposer has a first surface and a second surface opposite to the first surface. For example, a first chip and a second chip are disposed on the first surface of the optical interconnect interposer, and the second surface of the optical interconnect interposer faces the carrier substrate.
[0030] In some embodiments, the semiconductor package structure 100 includes a carrier substrate, the optical interconnect substrate having a first surface and a second surface opposite to the first surface. For example, a first chip and a second chip are mounted on the first surface of the optical interconnect substrate, the first surface of the optical interconnect substrate facing the carrier substrate. At this time, the first chip and the second chip are located between the optical interconnect substrate and the carrier substrate.
[0031] Optional, such as Figure 2 As shown, the first conversion unit 104 includes a first electro-optic converter 104a; the second conversion unit 105 includes a first photoelectric converter 105a; the first electro-optic converter 104a is configured to convert an electrical signal to an optical signal; the first photoelectric converter 105a is configured to convert an optical signal to an electrical signal; the first electro-optic converter 104a is electrically connected to the first conductive wiring unit 101 and coupled to the optical waveguide unit 103; the first electro-optic converter 104a receives a first electrical signal from the first chip 20 through the first conductive wiring unit 101 and encodes it to generate a first optical signal, which is transmitted in the optical waveguide unit 103; the first photoelectric converter is electrically connected to the second conductive wiring unit 102 and coupled to the optical waveguide unit 103; the first photoelectric converter 105a converts the first optical signal into a second electrical signal; the second chip 30 receives the second electrical signal through the second conductive wiring unit 102.
[0032] The aforementioned first electro-optic converter 104a can encode and generate a first optical signal based on the received first electrical signal.
[0033] In one specific structure, the first electro-optic converter 104a may include a first electro-optic modulator. The first electro-optic modulator may be one of a phase modulator, a polarization modulator, and an amplitude modulator. The first optical modulator modulates an initial optical signal according to a first electrical signal to obtain the first optical signal. In a specific example, the first optical modulator may be a capacitor-based modulator, a ring resonator modulator, an MZI modulator, etc.
[0034] In another specific configuration, the aforementioned first photoelectric converter 105a may include a first photodetector. The first photodetector can generate a second electrical signal based on the first optical signal.
[0035] Optional, such as Figure 2As shown, the first conversion unit 104 may include a second photoelectric converter 104b; the second conversion unit 105 may include a second electro-optical converter 105b; the second photoelectric converter 104b is configured to convert optical signals to electrical signals; the second electro-optical converter 105b is configured to convert electrical signals to optical signals; the second electro-optical converter 105b is electrically connected to the second conductive wiring unit 102 and coupled to the optical waveguide unit 103; the second electro-optical converter 105b receives a third electrical signal from the second chip 30 through the second conductive wiring unit 102 and encodes it to generate a second optical signal, which is transmitted in the optical waveguide unit 103; the second photoelectric converter 104b is electrically connected to the first conductive wiring unit 101 and coupled to the optical waveguide unit 103; the second photoelectric converter 104b converts the second optical signal into a fourth electrical signal; the first chip receives the fourth electrical signal through the first conductive wiring unit 101.
[0036] The aforementioned second electro-optic converter 105b can encode and generate a second optical signal based on the received third electrical signal.
[0037] In one specific configuration, the second electro-optic converter 105b may include a second optical modulator. The second optical modulator modulates the initial optical signal according to the first electrical signal to obtain the second optical signal. In a specific example, the second optical modulator may be a capacitor-based modulator, a ring resonator modulator, an MZI modulator, etc.
[0038] In another specific configuration, the second photoelectric converter 104b may include a second photodetector. The second photodetector can generate a fourth electrical signal based on the second optical signal.
[0039] Optionally, the first conversion unit 104 may include the first electro-optic converter 104a and the second photoelectric converter 104b; the second conversion unit 105 may include the first photoelectric converter 105a and the second electro-optic converter 105b. The first electro-optic converter 104a is configured to convert an electrical signal to an optical signal; the first photoelectric converter 105a is configured to convert an optical signal to an electrical signal; the first electro-optic converter 104a is electrically connected to and coupled to the first conductive wiring unit 101 and the optical waveguide unit 103; the first electro-optic converter 104a receives a first electrical signal from the first chip 20 through the first conductive wiring unit 101 and encodes it to generate a first optical signal, which is transmitted in the optical waveguide unit 103; the first photoelectric converter 105a is electrically connected to and coupled to the second conductive wiring unit 102 and the optical waveguide unit 103; the first photoelectric converter 105a converts the first optical signal into a second electrical signal. The second photoelectric converter 104b is configured to convert an optical signal into an electrical signal; the second electro-optical converter 105b is configured to convert an electrical signal into an optical signal; the second electro-optical converter 105b is electrically connected to and coupled to the second conductive wiring unit 102 and the optical waveguide unit 103; the second electro-optical converter 105b receives a third electrical signal from the second chip 30 through the second conductive wiring unit 102 and encodes it to generate a second optical signal, which is transmitted in the optical waveguide unit 103; the second photoelectric converter 104b is electrically connected to and coupled to the first conductive wiring unit 101 and the optical waveguide unit 103; the second photoelectric converter 104b converts the second optical signal into a fourth electrical signal.
[0040] In one instance, such as Figure 2 As shown, it illustrates two optical waveguides in the optical waveguide unit 103, namely a first optical waveguide 103a and a second optical waveguide 103b. A first electro-optic converter 104a and a first photoelectric converter 105a can be coupled to the first optical waveguide 103a; a second photoelectric converter 104b and a second electro-optic converter 105b can be coupled to the second optical waveguide 103b. In another example, as... Figure 3 As shown, the optical waveguide unit 103 includes an optical waveguide, and the first electro-optic converter 104a, the second photoelectric converter 104b, the first photoelectric converter 105a, and the second electro-optic converter 105b can be coupled to the same optical waveguide. In another example, as... Figure 4 As shown, the optical waveguide unit 103 has multiple optical waveguide branches 107, and the first electro-optic converter 104a, the second photoelectric converter 104b, the first photoelectric converter 105a and the second electro-optic converter 105b are respectively coupled to the first to fourth optical waveguide branches.
[0041] In practical applications, the aforementioned first conductive wiring unit 101 can be one or two. When there is one first conductive wiring unit 101, both the first electro-optical converter 104a and the second photoelectric converter 104b are electrically connected to the first conductive wiring unit 101. When there are two first conductive wiring units 101, the first electro-optical converter 104a is electrically connected to one of the first conductive wiring units 101, and the second photoelectric converter 104b is electrically connected to the other first conductive wiring unit 101. Similarly, the aforementioned second conductive wiring unit 102 can be one or two. When there is one second conductive wiring unit 102, both the second electro-optical converter 105b and the first photoelectric converter 105a are electrically connected to the second conductive wiring unit 102. When there are two second conductive wiring units 102, the second electro-optical converter 105b is electrically connected to one of the second conductive wiring units 102, and the first photoelectric converter 105a is electrically connected to the other second conductive wiring unit 102.
[0042] The technical solutions provided in this application can be applied to the packaging of multiple chiplets. That is, the first chip may include a first chiplet; the second chip may include a second chiplet.
[0043] The following section will introduce an information transmission method for the aforementioned semiconductor packaging structure. For example... Figure 1 As shown, the semiconductor package structure 100 includes: an optical interconnect substrate 10; the optical interconnect substrate 10 includes: a first conductive wiring unit 101, a second conductive wiring unit 102, an optical waveguide unit 103, and a first conversion unit 104 and a second conversion unit 105 for converting optical signals to electrical signals; the first conversion unit 104 and the second conversion unit 105 are respectively coupled to the optical waveguide unit 103; the first conductive wiring unit 101 is electrically connected to the first conversion unit 104; the second conductive wiring unit 102 is electrically connected to the second conversion unit 105; a first chip 20 and a second chip 30 are mounted on the optical interconnect substrate 10; wherein the first chip 20 is electrically connected to the first conductive wiring unit 101, and the second chip 30 is electrically connected to the second conductive wiring unit 102. Figure 5 As shown, the method includes: S501, the first chip transmits a first electrical signal carrying information to the first conductive wiring unit.
[0044] S502, the first conversion unit converts the first electrical signal into a first optical signal.
[0045] S503, the second conversion unit converts the first optical signal transmitted from the optical waveguide unit into a second electrical signal.
[0046] S504, the second chip receives the second electrical signal transmitted by the second conductive wiring unit.
[0047] In the above S502, the first conversion unit 104 can directly generate the first optical signal according to the first electrical signal, or modulate the initial optical signal according to the first electrical signal to obtain the first optical signal.
[0048] In one example, the first conversion unit 104 described above may include a first electro-optic converter, such as a first optical modulator.
[0049] In the above S504, after the second chip 30 receives the second electrical signal transmitted by the second conductive wiring unit 102, it can parse the information carried on the second electrical signal or transmit the second electrical signal to other chips for parsing.
[0050] Optionally, the above method may also include: S505, the second chip transmits a third electrical signal carrying information to the second conductive wiring unit.
[0051] S506, The second conversion unit converts the third electrical signal into a second optical signal.
[0052] S507, the first conversion unit converts the second optical signal transmitted from the optical waveguide unit into a fourth electrical signal.
[0053] S508, the first chip receives the fourth electrical signal transmitted from the first conductive wiring unit.
[0054] In the above S506, the second conversion unit 105 can directly generate the second optical signal according to the third electrical signal, or modulate the initial optical signal according to the third electrical signal to obtain the second optical signal.
[0055] In one example, the second conversion unit 105 may include a second electro-optic converter, such as a second optical modulator.
[0056] In the above S508, after the first chip 20 receives the fourth electrical signal transmitted by the first conductive wiring unit 101, it can parse the information carried on the fourth electrical signal or transmit the fourth electrical signal to other chips for parsing.
[0057] The following describes a method for manufacturing the aforementioned semiconductor package structure. For example... Figure 6 As shown, the method includes: S601, provides wafers.
[0058] S602, Multiple photonic integrated circuits are formed on the wafer.
[0059] Each of the plurality of photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals; the first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first conversion unit; and the second conductive wiring unit is electrically connected to the second conversion unit.
[0060] S603. A first chip and a second chip are mounted on each of the plurality of photonic integrated circuits, such that the first chip is electrically connected to the first conductive wiring unit, and the second chip is electrically connected to the second conductive wiring unit.
[0061] S604. The wafer is divided to obtain multiple independent semiconductor packaging structures.
[0062] Each of the semiconductor package structures includes the photonic integrated circuit and the first chip and the second chip mounted on the photonic integrated circuit. The first chip and the second chip are capable of communicating through the first conductive wiring unit, the first conversion unit, the optical waveguide unit, the second conversion unit, and the second conductive wiring unit. Specifically, each of the semiconductor package structures includes one photonic integrated circuit.
[0063] In S601 above, the wafer includes a semiconductor layer. In one example, the wafer may be a semiconductor-on-insulator (SOI) wafer, such as an SOI (Silicon-On-Insulator) wafer. Figure 7 As shown, a semiconductor-on-insulator wafer may include: an insulating layer 702, a semiconductor layer 703 formed on the insulating layer 702, and a backing substrate layer 701 located below the insulating layer 702.
[0064] In the above S602, a photonic integrated circuit can be formed by performing processes such as patterning, deposition, and doping on the semiconductor layer 703.
[0065] In one example of S603 described above, the first chip can be electrically connected to the first conductive wiring unit and the second chip can be electrically connected to the second conductive wiring unit by means of electrical connection such as bonding or soldering.
[0066] In a specific example, step S602 above, "forming multiple photonic integrated circuits on the wafer," can be implemented using the following steps: S21. The waveguide unit, the first conversion unit, and the second conversion unit are formed on the wafer.
[0067] S22. Deposit a dielectric layer on the wafer on which the waveguide unit, the first conversion unit and the second conversion unit are formed, to cover the waveguide unit, the first conversion unit and the second conversion unit and the wafer.
[0068] S23. A first opening and a second opening are formed in the dielectric layer.
[0069] S24. A first electrical connection structure is formed in the first opening and a second electrical connection structure is formed in the second opening.
[0070] The first conductive wiring unit includes the first electrical connection structure; the second conductive wiring unit includes the second electrical connection structure.
[0071] The above S21, such as Figure 7 and Figure 8 As shown, the semiconductor layer 703 of the wafer can be patterned to obtain the corresponding regions of the optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105. Specifically, photolithography and etching techniques are used to remove unwanted material in order to perform patterning. In some embodiments, the insulating layer described above can serve as an etch stop layer.
[0072] In S22 above, such as Figure 9 As shown, a dielectric layer 106 is deposited on a wafer on which the waveguide unit 103, the first conversion unit 104, and the second conversion unit 105 are formed, to cover the optical waveguide unit 103, the first conversion unit 104, the second conversion unit 105, and the wafer. Specifically, the dielectric layer 106 is formed by deposition on the optical waveguide unit 103, the first conversion unit 104, the second conversion unit 105, the insulating layer 702, and in the openings of the semiconductor layer 703 defining the optical waveguide unit 103, the first conversion unit 104, and the second conversion unit 105. The material of the dielectric layer can be the same as the material of the insulating layer.
[0073] In S23 above, such as Figure 9 As shown, a first opening and a second opening are formed in the dielectric layer 106. The first and second openings can be formed using etching technology, and the number of the first and second openings can be one or more depending on the connection requirements.
[0074] In some embodiments, the dielectric layer 106 is a multilayer structure formed by multiple sub-dielectric layers. The dielectric layer may include multiple conductive layers, which are connected by conductive material in vias. For example, a first sub-dielectric layer is deposited first, followed by a first conductive layer, then a second sub-dielectric layer, then a second conductive layer, then a third sub-dielectric layer, then a third conductive layer, and finally a fourth sub-dielectric layer. In the first to third conductive layers, different conductive layers are interconnected by conductive material in vias, and each conductive layer can be a patterned metal material layer.
[0075] In S24 above, such as Figure 9 As shown, a first electrical connection structure 101a of a first conductive wiring unit 101 and a second electrical connection structure 102a of a second conductive wiring unit 102 can be formed in the first opening by depositing conductive material.
[0076] After depositing the conductive material, excess conductive material can be removed along the mounting surface of the dielectric layer using a planarization process such as chemical mechanical polishing or mechanical grinding, thereby making the first and second electrical connection structures flush with the mounting surface of the dielectric layer. Alternatively, after depositing the conductive material, a first bonding structure 101b electrically connected to the first electrical connection structure 101a and a second bonding structure 102b electrically connected to the second electrical connection structure 102a can be formed on the mounting surface of the dielectric layer 106 in a patterned manner. The first bonding structure 101b and the second bonding structure 102b protrude from the mounting surface. The first conductive wiring unit further includes the first bonding structure 101b; the second conductive wiring unit further includes the second bonding structure 102b. Furthermore, a passivation film covering the first bonding structure 101b and the second bonding structure 102b can be formed on the mounting surface, and then the passivation film can be etched to form openings to expose the central portions of the first and second bonding structures.
[0077] Subsequently, a first chip and a second chip are mounted on each photonic integrated circuit on the wafer. Specifically, the first chip and the second chip are mounted on the mounting surface of the interface layer in the area corresponding to each photonic integrated circuit. That is, on the mounting surface of the interface layer in the area corresponding to each photonic integrated circuit, the first chip and the second chip are electrically connected to the first electrical connection structure and the second electrical connection structure in that area.
[0078] Subsequently, a sealant can be formed on the interface layer to bury or cover the first and second chips. The sealant can then be cured and planarized.
[0079] In some implementations, a process of thinning the backing substrate 701 may be included.
[0080] In some embodiments, S604 can be executed after S603, that is, the first chip and the second chip are assembled in batches before the photonic integrated circuit wafer is diced. This method allows the first chip and the second chip to be batch packaged in the wafer-level process. In this case, only the photonic integrated circuit wafer needs to be manufactured, and there is no need to form the photonic integrated circuit into a single chip.
[0081] Alternatively, a wafer dicing process can be performed first to form independent photonic integrated circuits, followed by further packaging to form multiple independent photonic integrated circuit chips. These photonic integrated circuit chips serve as optical interconnect chips. Then, a first chip and a second chip mounting process is performed, whereby the first chip and the second chip are mounted onto the independent photonic integrated circuit chips. Specifically, as shown... Figure 10 As shown, the method includes: S1001, provides wafers.
[0082] S1002, Multiple photonic integrated circuits are formed on the wafer.
[0083] Each of the plurality of photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for converting optical signals to electrical signals; the first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit; the first conductive wiring unit is electrically connected to the first conversion unit; and the second conductive wiring unit is electrically connected to the second conversion unit.
[0084] S1003. The wafer is divided to obtain multiple independent photonic integrated circuit chips.
[0085] Each of the photonic integrated circuit chips includes the photonic integrated circuit.
[0086] S1004. Install a first chip and a second chip on each of the plurality of independent photonic integrated circuit chips, such that the first chip is electrically connected to the first conductive wiring unit, and the second chip is electrically connected to the second conductive wiring unit.
[0087] The first chip and the second chip can communicate through the first conductive wiring unit, the first conversion unit, the optical waveguide unit, the second conversion unit, and the second conductive wiring unit.
[0088] The specific implementation of step S1002 can be found in the corresponding content of the above embodiments, and will not be repeated here.
[0089] It should be noted that any steps in the method provided in this application that are not described in detail can be found in the corresponding content of the above embodiments, and will not be repeated here. Furthermore, the method provided in this application may include other parts or all of the steps in the above embodiments in addition to the steps described above; for details, please refer to the corresponding content of the above embodiments, and will not be repeated here.
[0090] This application also provides a computing device. This computing device may include the semiconductor packaging structure described in the above embodiments.
[0091] The technical solutions and features in the above embodiments can be used individually or in combination if they conflict with this invention. As long as they do not exceed the knowledge of those skilled in the art, they are all equivalent embodiments within the scope of protection of this application.
[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A semiconductor manufacturing method, characterized in that, include: Provide wafers; Multiple photonic integrated circuits are formed on the wafer. Each of the multiple photonic integrated circuits includes a first conductive wiring unit, a second conductive wiring unit, an optical waveguide unit, and a first conversion unit and a second conversion unit for realizing the conversion between optical signals and electrical signals. The first conversion unit and the second conversion unit are respectively coupled to the optical waveguide unit, the first conductive wiring unit is electrically connected to the first conversion unit, and the second conductive wiring unit is electrically connected to the second conversion unit; A first chip and a second chip are mounted on each of the plurality of photonic integrated circuits, such that the first chip is electrically connected to the first conductive wiring unit and the second chip is electrically connected to the second conductive wiring unit. The first chip and the second chip can communicate through the first conductive wiring unit, the first conversion unit, the optical waveguide unit, the second conversion unit, and the second conductive wiring unit.
2. The manufacturing method according to claim 1, characterized in that, Also includes: After the first chip and the second chip are installed, the wafer is divided to obtain multiple independent semiconductor package structures.
3. The manufacturing method according to claim 1, characterized in that, Before installing the first chip and the second chip, the following is also included: The wafer is divided to obtain multiple independent photonic integrated circuit chips, each photonic integrated circuit chip including the photonic integrated circuit; The installation of the first chip and the second chip specifically includes: installing the first chip and the second chip on the independent photonic integrated circuit chip.
4. The manufacturing method according to claim 1, characterized in that, The formation of multiple photonic integrated circuits on the wafer includes: The optical waveguide unit, the first conversion unit, and the second conversion unit are formed on the wafer; A dielectric layer is deposited on the wafer on which the optical waveguide unit, the first conversion unit, and the second conversion unit are formed, to cover the optical waveguide unit, the first conversion unit, the second conversion unit, and the wafer; A first opening and a second opening are formed in the dielectric layer; A first electrical connection structure is formed in the first opening, and a second electrical connection structure is formed in the second opening; The first conductive wiring unit includes the first electrical connection structure, and the second conductive wiring unit includes the second electrical connection structure.
5. The manufacturing method according to claim 4, characterized in that, After forming the first electrical connection structure in the first opening and the second electrical connection structure in the second opening, the method further includes: A first bonding structure electrically connected to the first electrical connection structure is formed on the mounting surface of the dielectric layer, and a second bonding structure electrically connected to the second electrical connection structure is formed.
6. The manufacturing method according to claim 4, characterized in that, The dielectric layer is made of at least one of silicon oxide and silicon nitride.
7. The manufacturing method according to claim 1, characterized in that, The wafer is a semiconductor-on-insulator (SOI) wafer, comprising a back substrate, an insulating layer formed on the back substrate, and a semiconductor layer formed on the insulating layer.
8. The manufacturing method according to claim 7, characterized in that, The optical waveguide unit, the first conversion unit, and the second conversion unit are formed by patterning and doping the semiconductor layer.
9. The manufacturing method according to claim 7, characterized in that, Also includes: The backing substrate layer is thinned.
10. The manufacturing method according to claim 1, characterized in that, The first and second chips are electrically connected by bonding or soldering.
11. The manufacturing method according to claim 1, characterized in that, The first conversion unit includes a first electro-optic converter, and the second conversion unit includes a first photoelectric converter; The first electro-optic converter is used to convert the electrical signal received from the first chip into an optical signal and transmit it in the optical waveguide unit. The first photoelectric converter is used to convert the optical signal into an electrical signal and transmit it to the second chip.
12. The manufacturing method according to claim 11, characterized in that, The first conversion unit further includes a second photoelectric converter, and the second conversion unit further includes a second electro-optic converter; The second electro-optic converter is used to convert the electrical signal received from the second chip into an optical signal and transmit it in the optical waveguide unit. The second photoelectric converter is used to convert the optical signal into an electrical signal and transmit it to the first chip.