Intelligent relay high-speed response method and system based on FPGA direct control

Abstract

The invention discloses an intelligent relay high-speed response method and system based on FPGA direct control, and belongs to the technical field of relay response, and the method specifically comprises the steps: collecting coil current, magnetic flux change and contact motion signals of a relay in parallel, and generating an action pilot quantity which is used for reflecting the pre-action state of the relay; the time sequence offset between the target action and the electromagnetic lag of the relay is calculated based on the action pilot quantity, a variable time sequence combination driving waveform is generated according to the time sequence offset, the variable time sequence combination driving waveform is input to a relay coil circuit, and target magnetic flux distribution is maintained in the magnetic flux compensation stage. The magnetic energy is released at the slope controlled by the FPGA in the demagnetization stage, so that the actuation and release response time of the relay is shortened; according to the invention, dynamic regulation and control can be carried out according to the electromagnetic hysteresis characteristic and individual difference of the relay, the controllability and consistency of the action process of the relay are improved, and the method is suitable for a vehicle-mounted application scene with a high control time sequence requirement.

Description

Technical Field

[0001] This invention belongs to the field of relay response technology, specifically a high-speed response method and system for intelligent relays based on direct FPGA control. Background Technology

[0002] As widely used actuators in electrical control systems, relays are affected by various factors such as coil inductance characteristics, electromagnetic hysteresis, and contact mechanical movement during their activation and deactivation processes. The actual operating time often lags behind the control command. In automotive electrical systems, relays are typically controlled by microcontrollers, programmable logic controllers, or industrial control units via fixed voltage drive or pulse width modulation.

[0003] To improve the response performance of relays, some existing technologies have made improvements by increasing the driving voltage, introducing pre-excitation pulses, or optimizing drive circuit parameters. However, most of these methods focus on circuit-level or fixed strategy adjustments, lacking the ability to analyze and process the electromagnetic dynamic behavior of relays in real time. Furthermore, due to differences in manufacturing processes, operating environments, and aging levels, individual relays exhibit inconsistent electromagnetic hysteresis characteristics and contact movement patterns. In automotive applications, traditional control methods based on fixed parameters struggle to adapt to these differences, resulting in insufficient consistency and predictability of relay actions during long-term operation. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention proposes a high-speed response method and system for intelligent relays based on direct FPGA control. This method analyzes the precursors of relay operation using FPGA and dynamically generates the driving timing accordingly, thereby achieving refined management of the relay operation process.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A high-speed response method for intelligent relays based on direct FPGA control is applied in automotive electrical systems to perform high-speed on / off control of automotive load circuits. Specifically, it includes:

[0007] The relay's coil current, magnetic flux change, and contact movement signals are acquired in parallel, and an action pilot quantity is generated. The action pilot quantity is used to reflect the relay's pre-action state.

[0008] The timing offset between the relay target action and its electromagnetic hysteresis is calculated based on the action leader quantity, and a variable timing combination drive waveform is generated accordingly.

[0009] The variable timing combination driving waveform is input to the relay coil circuit to maintain the target magnetic flux distribution during the magnetic flux compensation stage and to release magnetic energy with an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay's engagement and disengagement response time.

[0010] Specifically, the parallel acquisition of relay coil current, magnetic flux changes, and contact movement signals, and the generation of action pilot quantities, include:

[0011] A sampling channel is established for the relay inside the FPGA, and the sampling start time of each sampling channel is uniformly indexed to form a synchronization reference;

[0012] Based on the synchronization benchmark, each sampling channel is time-sequentially segmented, and the sampling sequence in each period is divided into multiple discrete segments. A signal state set is then established in parallel for each discrete segment.

[0013] On-chip cross-correlation analysis is performed on the signal state set. The coil current change trend, magnetic flux increase / decrease mode and contact micro-displacement sequence are merged and calculated according to preset correlation weights to form an intermediate discrimination set for distinguishing different pre-action modes of the relay.

[0014] Based on the intermediate discrimination set, an action precursor sequence is constructed. The action precursor sequence is arranged by the FPGA according to the chronological order, so that different signal features form a prediction path before the actual action of the relay.

[0015] The FPGA performs regular extraction and timing compression on the action precursor sequence to generate action precursor quantities.

[0016] Specifically, constructing an action precursor sequence based on the intermediate discrimination set includes:

[0017] The discrimination units in the intermediate discrimination set are segmented and recombined according to their generation time, so that the discrimination units formed by different signal sources form time clusters in the same time segment;

[0018] The time clusters are serialized, and the discrimination units in adjacent time segments are connected into a continuous discrimination chain according to the segment order;

[0019] Path filtering is performed in the discrimination chain to remove discrimination units that do not meet the preset sequence association conditions, and the remaining discrimination units are formed into a path set according to the evolution relationship of signal changes;

[0020] Construct an action precursor sequence based on the set of paths.

[0021] Specifically, the step of using the FPGA to perform regular extraction and timing compression on the action precursor sequence to generate action precursor quantities includes:

[0022] The action precursor sequence is scanned in a pattern, and each precursor unit in the sequence is divided into multiple pattern segments according to a preset discrimination criterion.

[0023] The pattern segments are extracted by rules. Precursor units with continuous change relationships within the segments are grouped into rule groups, and precursor units that do not conform to the extraction rules are removed from the rule groups to form a candidate rule set.

[0024] The candidate rule set is time-series compressed by sequentially merging the precursor units that appear repeatedly or have overlapping time spans in the rule set, so that the FPGA obtains a compressed sequence.

[0025] Action leaders are extracted based on the compressed sequence.

[0026] Specifically, the step of calculating the timing offset between the relay target action and its electromagnetic hysteresis based on the action precursor, and generating a variable timing combination drive waveform accordingly, includes:

[0027] The timeline of the action leader is rearranged, and the time nodes within it are sorted sequentially according to the direction of relay action, so that the FPGA obtains a time series set.

[0028] The time series set is subjected to hysteresis mapping processing, and the reference time segments related to the inherent action delay of the relay are matched with the time series set to form a mapping group;

[0029] The offset derivation is performed on the mapping group, the time difference between each key node in the time series set and the corresponding segment in the mapping group is calculated, and the calculation results are combined into an offset sequence.

[0030] The offset sequence is decomposed into pulse structure, the preset driving mode is split into multiple pulse components with different time attributes, and each pulse component is rearranged according to the timing relationship in the offset sequence to generate a pulse combination framework with variable timing.

[0031] Based on the FPGA, the pulse combination framework is time-series synthesized, and the pulse components are combined in a rearranged order to form a variable timing combination drive waveform for driving the relay coil.

[0032] Specifically, the offset derivation is performed on the mapping group, the time difference between each key node in the time series set and the corresponding segment in the mapping group is calculated, and the calculation results are combined into an offset sequence, including:

[0033] In the time series set, key nodes are indexed. At least one key node is selected from each time series according to the preset node selection criteria, and the selected key node is assigned a corresponding node identifier.

[0034] The mapping group is segment aligned by aligning the reference segments corresponding to each node identifier according to the same time base, resulting in a set of aligned segments that correspond one-to-one with each key node.

[0035] Offset derivation is performed on the set of aligned segments. The time difference between each key node and the corresponding aligned segment is calculated. The time differences of different key nodes are then grouped according to the node identifier to form an offset entry set.

[0036] The offset entry set is serialized and arranged according to the chronological order of the key nodes, and the arrangement result is output as an offset sequence.

[0037] Specifically, the offset sequence is decomposed into pulse structures, the preset driving mode is split into multiple pulse components with different time attributes, and the pulse components are rearranged according to the temporal relationship in the offset sequence to generate a pulse combination framework with variable timing, including:

[0038] The offset sequence is divided into multiple offset intervals according to time order, and each offset interval is assigned an interval identifier to form an interval set.

[0039] The preset driving mode is decomposed into components, which are then divided into multiple pulse components. Each pulse component is assigned a component identifier and a time attribute label, which includes a start mark, a duration mark, and an interval mark.

[0040] Based on the set of intervals and the time attribute labels, component mapping is performed, and each pulse component is matched with its corresponding offset interval according to its time attribute label to generate a correspondence table between components and intervals.

[0041] The correspondence table between the components and intervals is rearranged, and the start mark, duration mark and interval mark of each pulse component are arranged in the order of interval identifier to form a pulse combination framework with variable timing.

[0042] Specifically, based on the FPGA, the pulse combination framework is time-synthesized, and the pulse components are combined in a rearranged order to form a variable timing combination drive waveform for driving the relay coil, including:

[0043] The pulse combination framework is instantiated sequentially, and each pulse component in the framework is parsed into an item to be synthesized according to its component identifier. A time-series description item corresponding to its time attribute label is established for each item to be synthesized.

[0044] The timing description items are conflict-normalized, and timing description items with overlapping times or contradictory intervals are adjusted according to a preset normalization criterion to generate a normalized timing set.

[0045] The regularized time series set is synthesized and arranged. Each item to be synthesized is spliced ​​together in the order determined by the regularized time series set, and the interval segment generated during the splicing process is written as an independent time series placeholder segment to form a synthesized time series table.

[0046] The FPGA performs waveform synthesis according to the synthesis timing table, and combines each item to be synthesized and the timing placeholders in sequence and outputs them as a variable timing combination drive waveform.

[0047] Specifically, the variable timing combination drive waveform is input to the relay coil circuit to maintain the target magnetic flux distribution during the magnetic flux compensation phase and to release magnetic energy at an FPGA-controlled slope during the demagnetization phase, thereby shortening the relay's engagement and disengagement response time. This includes:

[0048] The variable timing combination drive waveform is marked with stages and divided into a stage sequence including a pre-magnetization stage, a flux compensation stage and a demagnetization stage according to time order, and a stage identifier is written for each stage.

[0049] The waveform stack scheduling is performed on the stage sequence, and the waveform segments corresponding to each stage are loaded into the output sequence according to the stage identifier;

[0050] In the flux compensation stage, compensation parameters are written to the output sequence. The compensation control parameters associated with the action pilot and offset sequence are embedded into the timing description item of the corresponding waveform segment to form the output command set of the compensation stage.

[0051] During the demagnetization stage, the output sequence is sloped and arranged to convert the waveform segments of the demagnetization stage into timing expressions containing slope segments. The start and end marks of the slope segments are written into the synthesis timing table according to the preset slope arrangement criteria, so that the FPGA can output them to the relay coil circuit in sequence.

[0052] A high-speed response system for intelligent relays based on direct FPGA control is used to implement the aforementioned high-speed response method for intelligent relays based on direct FPGA control. The system includes: a signal acquisition module, a drive waveform generation module, and a response module.

[0053] The signal acquisition module is used to acquire the coil current, magnetic flux change and contact movement signals of the relay in parallel, and generate the action pilot quantity;

[0054] The drive waveform generation module calculates the timing offset between the relay target action and its electromagnetic hysteresis based on the action leader quantity, and generates a variable timing combination drive waveform accordingly.

[0055] The response module is used to input the variable timing combination drive waveform to the relay coil circuit, maintain the target magnetic flux distribution during the magnetic flux compensation stage, and release magnetic energy at an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay engagement and disengagement response time.

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] This invention proposes a high-speed response method and system for intelligent relays based on direct FPGA control. By using an FPGA as the core control unit, it performs parallel processing on multi-source information such as relay coil current, magnetic flux changes, and contact movement. This constructs a complete control flow including action precursor analysis, timing offset derivation, and variable timing drive waveform generation. The generated drive waveform is then directly applied to the relay coil, achieving full-process hardware-level timing control from action prediction to drive output. This frees the relay control process from the limitations of traditional fixed parameters and software scheduling, enabling dynamic adjustment based on the relay's electromagnetic hysteresis characteristics and individual differences. This improves the controllability and consistency of the relay's action process, making it suitable for automotive applications with high control timing requirements. Attached Figure Description

[0058] Figure 1 A flowchart of the high-speed response method for intelligent relays based on direct FPGA control provided by the present invention;

[0059] Figure 2 This is a schematic diagram of the variable timing combination drive waveform provided by the present invention;

[0060] Figure 3 This invention provides an architecture diagram of a high-speed response intelligent relay system based on direct FPGA control. Detailed Implementation

[0061] The present application will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present application, but do not limit the present application in any way. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application. These all fall within the protection scope of the present application.

[0062] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0063] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. In addition, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0064] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0065] Example 1

[0066] Please see Figures 1-2 The present invention provides an embodiment of a high-speed response method for intelligent relays based on direct FPGA control. This method is used in automotive electrical systems to perform high-speed on / off control of automotive load circuits, and includes the following specific steps:

[0067] Step S1: Parallel acquisition of relay coil current, magnetic flux change and contact movement signals, and generation of action pilot quantity, which is used to reflect the relay pre-action state.

[0068] The specific steps of step S1 are as follows:

[0069] Step S101: Establish sampling channels for relays inside the FPGA, and uniformly index the sampling start time of each sampling channel to form a synchronization reference.

[0070] In this embodiment, based on the technical understanding that multiple physical quantities have strict correlation in the time dimension during relay operation, specifically, although the changes in relay coil current, the evolution of magnetic flux state, and the contact movement process have different origins, they all revolve around the same electromagnetic excitation event. If the sampled signals lack a unified reference on the time axis, it will be difficult to perform subsequent correlation analysis and lead quantity derivation. Based on the above principle, independent sampling paths are allocated to different signals inside the FPGA, and a unified time stamp is set for each sampling path at the logic level, so that each sampling path establishes a sampling sequence with the same start time in the same control cycle, thereby forming an internally consistent time reference without relying on external clock synchronization.

[0071] Step S102: Based on the synchronization benchmark, perform time-series segmentation on each sampling channel, divide the sampling sequence in each period into multiple discrete segments, and establish a signal state set for each discrete segment in parallel.

[0072] In this embodiment, based on the technical understanding that the relay operation process has a phased evolution characteristic, specifically, the sampling sequence within the same control cycle usually includes the initial electromagnetic establishment stage, the transition change stage, and the micro-change stage before the contact response. If the complete sampling sequence is processed as a whole, it will be difficult to distinguish the inherent differences in signal changes within different stages. Based on this principle, using the synchronization reference formed in step S101, the sampling sequence in each sampling channel is divided according to a preset time span, dividing the continuous sampling data within each cycle into multiple discrete segments that are independent of each other in time, and making the discrete segments in the same time interval in different sampling channels logically correspond to each other. Specifically, by identifying and classifying each discrete segment inside the FPGA, the segments from different sampling channels in the same time interval are aggregated in parallel, thereby constructing a signal state set that reflects the multi-source signal state of the relay in that time interval.

[0073] Step S103: Perform on-chip cross-correlation analysis on the signal state set, and merge the coil current change trend, magnetic flux increase / decrease mode and contact micro-displacement sequence according to the preset correlation weight to form an intermediate discrimination set for distinguishing different pre-action modes of the relay.

[0074] In this embodiment, before the relay actually operates, its coil current, magnetic flux state, and contact micro-displacement do not change in isolation, but evolve together with a specific sequence and trend. Analyzing any single signal alone is insufficient to accurately depict the relay's pre-operation state. Based on this principle, cross-correlation analysis is performed on the signal state set obtained in step S102 on the FPGA chip. Specifically, firstly, the trends of the coil current change sequence, magnetic flux increase / decrease sequence, and contact micro-displacement sequence are extracted to make each sequence comparable within the same time segment. Then, based on pre-set correlation weights, the change trends of different signal sequences within the corresponding time segment are merged to logically form a unified discrimination vector for all types of signals. It should be noted that the correlation weights are used to reflect the relative influence of different signals in the relay's pre-operation stage. By weighted merging of multi-source signals, the results reflect the differences between different pre-operation states, ultimately forming an intermediate discrimination set for subsequent timing derivation.

[0075] The preset association weights are determined by those skilled in the art through routine experiments or based on actual circumstances.

[0076] Step S104: Construct an action precursor sequence based on the intermediate discrimination set. The action precursor sequence is arranged by the FPGA according to the chronological order, so that different signal features form a prediction path before the relay actually operates.

[0077] The specific steps of step S104 are as follows:

[0078] Step S1041: The discrimination units in the intermediate discrimination set are segmented and recombined according to their generation time, so that the discrimination units formed by different signal sources form a time cluster in the same time segment.

[0079] In this embodiment, the relay pre-action information exhibits a discrete distribution characteristic in the time dimension. Specifically, although different discrimination units in the intermediate discrimination set originate from different signal combinations, they all correspond to specific time points in the relay action evolution process. If the discrimination units are directly processed as a whole, it will be difficult to reveal the inherent correlation between the multi-source discrimination results within the same time stage. Based on this principle, each discrimination unit in the intermediate discrimination set is sorted according to its generation time, and the sorted discrimination units are segmented and reorganized according to the preset time slice width, so that discrimination units whose generation time is within the same time slice range are grouped into the same time cluster. It should be noted that the time cluster is not a simple data grouping, but rather a logically constructed set structure for carrying multi-source discrimination information at the same time, so that discrimination units from different signal sources form a corresponding relationship in the time dimension.

[0080] Step S1042: Perform serialization processing on the time cluster, and connect the discrimination units in adjacent time segments into a continuous discrimination chain according to the segment order.

[0081] In this embodiment, a single time cluster only reflects the judgment state of the relay within a certain instant or short time interval. The relay pre-action process is essentially the result of the continuous evolution of the judgment state along the time axis. Therefore, it is necessary to establish a sequential association between multiple time clusters in the time dimension. Based on this principle, the time clusters formed in step S1041 are arranged according to their corresponding time segment order, and the judgment units in adjacent time segments are serialized and connected, so that the judgment result in the previous time cluster is logically connected to the judgment result in the next time cluster. Specifically, by assigning a sequence identifier to each time cluster inside the FPGA, and connecting the judgment units in each time cluster segment by segment according to the sequence, a judgment chain reflecting the evolution of the judgment state over time is constructed.

[0082] Step S1043: Perform path filtering in the discrimination chain, remove discrimination units that do not meet the preset sequence association conditions, and form a path set for the remaining discrimination units according to the evolution relationship of signal changes.

[0083] In this embodiment, the relay pre-action process is directional and coherent. Specifically, although the discrimination chain reflects the continuous arrangement of discrimination units within different time segments, it includes discontinuous discrimination results introduced by noise fluctuations or local anomalies. If all of these are retained indiscriminately, it will interfere with the identification of the true pre-action evolution path. Based on this principle, a sequence association condition is introduced into the discrimination chain to check the time sequence, change direction, and association consistency between adjacent discrimination units item by item. Discrimination units that do not meet the association condition are eliminated. It should be noted that the association condition is used to constrain the continuity of discrimination units in the time dimension and change logic. By filtering the discrimination chain, the retained discrimination units are naturally connected according to the evolution relationship of signal changes, thereby logically constructing a set of paths that reflect the evolution trajectory of the relay pre-action.

[0084] Step S1044: Construct an action precursor sequence based on the path set.

[0085] In this embodiment, the implementation of step S1044 is based on the technical understanding that the path set completely reflects the evolution trajectory of the relay's pre-action. Specifically, each path in the path set is composed of discrimination units arranged in chronological order, and different paths correspond to the changes in the relay under different pre-action conditions. Based on this principle, each path in the path set is sorted according to its starting time, and the discrimination units within the path are connected in series according to their chronological order, so that each path forms a comparable evolution sequence under a unified time axis. It should be noted that during the construction process, by coordinating the temporal overlap and evolution order between paths, multiple paths are integrated into a single precursor expression sequence, so that the multi-stage change information of the relay before the actual action is expressed in a continuous and traceable form, ultimately obtaining an action precursor sequence for subsequent rule extraction and time-series compression.

[0086] Step S105: The FPGA performs regular extraction and timing compression on the action precursor sequence to generate action precursor quantities.

[0087] The specific steps of step S105 are as follows:

[0088] Step S1051: Perform pattern scanning on the action precursor sequence and divide each precursor unit in the sequence into multiple pattern segments according to a preset discrimination criterion.

[0089] In this embodiment, although the action precursor sequence presents the changes in the relay pre-action stage in chronological order, the sequence often contains multiple precursor forms with different evolutionary characteristics. If processed directly as a whole, it would be difficult to effectively distinguish between the different change forms. Based on this principle, a pattern scanning process is performed on the action precursor sequence. Specifically, each precursor unit is read sequentially along the sequence time axis, and the change relationship between adjacent precursor units is compared according to a preset discrimination criterion. When a change in the change characteristics between precursor units is detected, the corresponding precursor unit is classified into different pattern segments. It should be noted that the discrimination criterion is used to define the consistency of the change trend and temporal relationship of the precursor units. Through this scanning and division process, the action precursor sequence is decomposed into multiple logically relatively independent pattern segments.

[0090] Step S1052: Extract rules from the pattern fragments, combine precursor units with continuous change relationships within the fragments into rule groups, and remove precursor units that do not conform to the extraction rules from the rule groups to form a candidate rule set.

[0091] In this embodiment, each pattern segment obtained by step S1051 has precursor units that exhibit continuous evolution characteristics in terms of temporal sequence and direction of change. However, they still contain local anomalies or isolated changes, which, if not properly identified, will weaken the effectiveness of rule extraction. Based on this principle, rule extraction is performed on each pattern segment separately. The continuity relationship between adjacent precursor units is compared sequentially along the segment's time axis. Precursor units that meet the preset continuity conditions are grouped into rule groups, and precursor units that do not meet the continuity conditions are eliminated. It should be noted that by independently performing the above extraction process on each pattern segment, several rule groups are formed in different pattern segments, and then a candidate rule set reflecting different precursor evolution characteristics is obtained.

[0092] Step S1053: Perform time-series compression on the candidate rule set, and merge the precursor units that appear repeatedly or have overlapping time spans in the rule set in sequence so that the FPGA obtains a compressed sequence.

[0093] In this embodiment, based on the technical understanding that redundant temporal expressions exist in the candidate rule set, different rule groups contain precursor units pointing to the same precursor change process during their formation process, or have partially overlapping evolution segments on the time axis. If all of them are retained, the temporal expression will be lengthy and difficult to use for subsequent processing. Based on this principle, temporal compression processing is performed on the candidate rule set. Specifically, firstly, each precursor unit in the rule set is sorted according to its time position, and precursor units with the same or adjacent time markers are compared. Precursor units pointing to the same change meaning are regarded as merging objects. Then, precursor units with overlapping time spans are sequentially integrated to form a continuous expression on the time axis. It should be noted that through the above merging and integration process, redundant precursor units in the candidate rule set are eliminated, and finally a compressed sequence with a compact structure and clear temporal relationship is obtained.

[0094] Step S1054: Extract action leader based on the compressed sequence.

[0095] In this embodiment, based on the technical understanding that the compressed sequence reflects the key change nodes of the relay pre-action stage, specifically, in the time-compressed sequence, each precursor unit retains representative evolution information in chronological order, which is suitable as the basis for generating action precursor quantities. Based on this principle, the compressed sequence is analyzed item by item along the time axis to extract key information representing the starting point, duration, and transition nodes of precursor changes, and the key information is combined and organized according to a preset time arrangement rule. It should be noted that through this extraction and organization process, the scattered precursor expressions in the compressed sequence are transformed into a parameter set with clear time orientation, so that the obtained action precursor quantities can be used for subsequent derivation and control of the relay action timing.

[0096] Step S2: Calculate the timing offset between the relay target action and its electromagnetic hysteresis based on the action leader quantity, and generate a variable timing combination drive waveform accordingly.

[0097] The specific steps of step S2 are as follows:

[0098] Step S201: Rearrange the action leader on the time axis, and sort the time nodes inside it according to the direction of relay action, so that the FPGA can obtain a time series set.

[0099] In this embodiment, based on the technical understanding that each time node within the action leader quantity has different temporal orientation under different action directions of the relay, specifically, during the activation and deactivation process of the relay, the evolution sequence of its pre-action signal is not a simple temporal relationship, but is closely related to the action direction. If this distinction is not made, it will affect the accuracy of subsequent timing derivation. Based on this principle, each time node contained in the action leader quantity is analyzed. First, each time node is assigned a directional attribute identifier according to the current target action direction of the relay. Then, the time nodes are rearranged according to the directional attribute, so that the time nodes under the same action direction form a logically consistent evolution sequence. It should be noted that through this time axis rearrangement process, the originally scattered or intersecting time nodes are organized into a time sequence set that conforms to the relay action evolution logic.

[0100] Step S202: Perform hysteresis mapping processing on the time series set, and match the reference time segments related to the inherent action delay of the relay with the time series set to form a mapping group.

[0101] In this embodiment, based on the technical understanding that the inherent action delay of a relay is expressed through time segments, specifically, after receiving a drive command, there is a stable but non-instantaneous time lag between the electromagnetic establishment and contact movement of the relay. This lag characteristic is abstracted into several representative reference time segments. Based on this principle, the time series set obtained in step S201 is analyzed item by item, and each time node is matched with a pre-set reference time segment, so that each time node is logically associated with a time interval reflecting the inherent action delay characteristic of the relay. It should be noted that through this lag mapping process, each node in the time series set obtains a reference identifier corresponding to the relay action delay characteristic, thereby forming a mapping group between nodes and lag characteristics in the time dimension.

[0102] Step S203: Perform offset derivation on the mapping group, calculate the time difference between each key node in the time series set and the corresponding segment in the mapping group, and combine the calculation results into an offset sequence.

[0103] The specific steps of step S203 are as follows:

[0104] Step S2031: Index key nodes in the time series set, select at least one key node from each time series according to the preset node selection criteria, and assign the selected key node a corresponding node identifier.

[0105] In this embodiment, not all time nodes in the time series set have equal reference value for deducing the relay action timing. Some nodes more centrally reflect the turning points or boundary features in the pre-action evolution. Based on this principle, each time series in the time series set is scanned, and time nodes are filtered according to preset node selection criteria. The node selection criteria are used to define the representative position of the time node in the sequence, so that the selected nodes reflect the key change stages within the sequence. Specifically, under the condition of satisfying the node selection criteria, at least one time node is selected from each time series, and a unique node identifier is assigned to the selected time node to make it traceable in subsequent processing. It should be noted that through this key node indexing process, nodes with time sequence pointing significance in the time series set are distinguished from ordinary nodes, forming a key node set with clear identification.

[0106] Step S2032: Perform segment alignment on the mapping group. Align the reference segments corresponding to each node identifier with the same time base to obtain a set of aligned segments that correspond one-to-one with each key node.

[0107] In this embodiment, based on the technical understanding that a unified time reference is required between the reference time segments and key nodes, specifically, although each reference segment in the mapping group is related to the inherent action delay of the relay, their start and end time distributions are not consistent. If directly used for offset derivation, it will lead to difficulty in comparing time relationships. Based on this principle, the reference segments in the mapping group are retrieved according to the node identifier assigned in step S2031, and the reference segments are aligned using a unified time reference to ensure that the starting position and arrangement of each reference segment on the time axis are consistent. It should be noted that through this segment alignment process, each key node corresponds to a reference segment expressed under the same time reference, thereby forming a set of aligned segments that correspond one-to-one with the key nodes.

[0108] Step S2033: Perform offset derivation on the set of aligned segments, calculate the time difference between each key node and the corresponding aligned segment, and collect the time differences of different key nodes according to the node identifier to form an offset entry set.

[0109] In this embodiment, based on the technical understanding that there is a quantifiable time relationship between key nodes and their corresponding reference segments, specifically, key nodes represent the time pointing position in the action precursor quantity, while the alignment segment reflects the time interval of the inherent action delay of the relay. The relative position between the two is used to characterize the adjustment basis of the drive timing. Based on this principle, the alignment segment set obtained in step S2032 is analyzed item by item. For each key node, its position on the time axis is determined and compared with the start and end positions of the corresponding alignment segment to obtain the time difference between the key node and the reference segment. It should be noted that by performing the above time difference derivation on different key nodes respectively and aggregating the results according to the node identifier, each time difference logically forms a set of offset entries with a clear structure.

[0110] Step S2034: Serialize and arrange the offset entry set, arrange each offset entry according to the time sequence of the key nodes, and output the arrangement result as an offset sequence.

[0111] In this embodiment, based on the technical understanding that the offset entry set itself does not yet have a clear time evolution order, specifically, although each entry in the offset entry set corresponds to the time difference results of different key nodes, without a unified time arrangement rule, it will be difficult to directly use it for subsequent pulse structure rearrangement. Based on this principle, the node identifiers associated with each entry in the offset entry set are parsed, and the order of the corresponding key nodes in the time series set is used as the sorting basis to perform serialization arrangement processing on each offset entry. It should be noted that through this arrangement process, the originally discrete offset entries are arranged into a continuous and orderly arrangement structure on the time axis, and finally an offset sequence reflecting the offset evolution relationship of relay action is obtained.

[0112] Step S204: Perform pulse structure decomposition on the offset sequence, split the preset driving mode into multiple pulse components with different time attributes, and rearrange each pulse component according to the timing relationship in the offset sequence to generate a pulse combination framework with variable timing.

[0113] The specific steps of step S204 are as follows:

[0114] Step S2041: Perform interval processing on the offset sequence, divide the offset sequence into multiple offset intervals in chronological order, and assign an interval identifier to each offset interval to form an interval set.

[0115] In this embodiment, based on the technical understanding that the offset sequence exhibits segmented characteristics in the time dimension, specifically, although the offset sequence has been arranged according to the chronological order of key nodes, the offset change patterns reflected in different time periods within it are not consistent. If processed as a whole, it will be detrimental to the subsequent reconstruction of the driving mode. Based on this principle, the offset sequence is scanned along the time axis, and continuous offset entries are divided into several mutually distinguishable offset intervals according to a preset interval division criterion. Each offset interval is assigned a unique interval identifier to represent the position of the interval in the time series. It should be noted that through this intervalization process, the offset sequence is logically split into multiple time periods with clear boundaries, forming a set of intervals with a clear structure.

[0116] Step S2042: Decompose the preset driving mode into components, split the preset driving mode into multiple pulse components, and assign a component identifier and a time attribute label to each pulse component. The time attribute label includes a start mark, a duration mark and an interval mark.

[0117] In this embodiment, based on the technical understanding that the preset driving mode is abstracted into several independently scheduled time units, specifically, traditional driving modes usually exist in a holistic form, which is not conducive to flexible adjustment for different time periods. Based on this principle, the preset driving mode is analyzed along its time axis, and the continuous driving process is split into multiple time-independent pulse components. Each pulse component is assigned a unique component identifier for differentiation and retrieval in subsequent processing. It should be noted that, during the splitting process, time attribute tags are further written to each pulse component to describe the temporal position characteristics of the component in the driving mode. The start tag is used to indicate the starting position of the component in the overall driving sequence, the continuity tag is used to describe the time segment covered by the component, and the interval tag is used to characterize the time interval between the component and adjacent components, thereby forming a structured set of pulse components.

[0118] Step S2043: Based on the interval set and the time attribute label, perform component mapping, match each pulse component with its corresponding offset interval according to its time attribute label, and generate a correspondence table between components and intervals.

[0119] In this embodiment, based on the technical understanding of using offset intervals as reference coordinates for driving mode adjustment, specifically, the interval set formed in step S2041 characterizes different offset change segments in the time dimension, while the time attribute labels assigned to the pulse components in step S2042 describe the time position characteristics of each component in the original driving mode. Based on this principle, the interval set and pulse components are jointly analyzed, and the start mark, duration mark, and interval mark of each pulse component are compared with the time range of the offset interval, so that each pulse component is logically matched to at least one corresponding offset interval. It should be noted that through this component mapping process, a clear correspondence is formed between the pulse component and the offset interval, and a correspondence table between components and intervals is constructed accordingly.

[0120] Step S2044: The correspondence table between the components and the intervals is rearranged, and the start mark, duration mark and interval mark of each pulse component are arranged in the order of the interval identifier to form a pulse combination framework with variable timing.

[0121] In this embodiment, based on the technical understanding that the correspondence between components and intervals is used to drive timing reconstruction, specifically, the correspondence table between components and intervals has clearly defined the time assignment of each pulse component in different offset intervals, but has not yet formed an arrangement structure directly used for timing synthesis. Based on this principle, the correspondence table between components and intervals is parsed according to the interval identifiers of the offset intervals, and the start marker, duration marker, and interval marker of each pulse component are rearranged according to the order of the interval identifiers, so that the time attributes originally scattered in different intervals are integrated into a unified time arrangement logic. It should be noted that through this component rearrangement process, the relative positions of each pulse component on the time axis are adjusted according to the order of the offset intervals, and finally a variable timing pulse combination framework with clear time arrangement rules is formed.

[0122] Step S205: Based on the FPGA, the pulse combination framework is time-series synthesized, and the pulse components are combined in a rearranged order to form a variable timing combination driving waveform for driving the relay coil.

[0123] The specific steps of step S205 are as follows:

[0124] Step S2051: Instantiate the pulse combination framework into a sequence, parse each pulse component in the framework into an item to be synthesized according to its component identifier, and establish a timing description item corresponding to its timing attribute label for each item to be synthesized.

[0125] In this embodiment, based on the technical understanding that the pulse combination framework needs to be transformed into executable temporal units, specifically, the pulse combination framework only describes the relative temporal arrangement of pulse components and does not yet have a specific expression form that can be directly used for temporal synthesis. Based on this principle, the pulse combination framework is parsed, and the pulse components are extracted one by one according to the component identifier. Each pulse component is instantiated as an independent item to be synthesized, so that it has the logical attribute of a sequence unit to be processed separately. It should be noted that, during the instantiation process, a matching temporal description item is further established for each item to be synthesized based on the temporal attribute label corresponding to each pulse component. This item is used to clarify the starting position, duration segment and adjacent interval relationship of the item, thereby transforming the abstract combination framework into a set of synthesized objects with a clear structure and called in chronological order.

[0126] Step S2052: Perform conflict normalization on the time series description items, and adjust the time series description items with time overlap or interval contradiction according to the preset normalization criteria to generate a normalized time series set.

[0127] In this embodiment, based on the technical understanding that inconsistencies in timing arrangements occur after sequence instantiation, specifically, although the timing description items formed by instantiation of different pulse components each have clear time attributes, they may overlap in time, conflict in interval order, or have discontinuous connections after combination. If directly used for subsequent synthesis, they will disrupt the overall timing logic. Based on this principle, all timing description items are centrally analyzed according to their time attributes, and the start relationship, duration relationship, and interval relationship between adjacent timing description items are compared item by item. Conflicting timing description items are adjusted according to preset regularization criteria to coordinate conflicting relationships on the same time axis. It should be noted that through this conflict regularization process, each timing description item logically meets the continuity requirement of a single time sequence, ultimately forming a regularized timing set with consistent internal time relationships and a clear order.

[0128] Step S2053: Synthesize and arrange the regularized time series set, splice the items to be synthesized in the order determined by the regularized time series set, and write the interval segments generated during the splicing process as independent time series placeholder segments to form a synthesized time series table.

[0129] In this embodiment, based on the technical understanding that the regularized timing set already possesses unified time logic but still needs to be transformed into a complete execution order, specifically, although the time conflicts of each item to be synthesized in the regularized timing set have been eliminated, a continuous timing expression covering the entire control cycle has not yet been formed. Based on this principle, according to the order determined in the regularized timing set, each item to be synthesized is sequentially spliced ​​to form a continuous connection relationship between adjacent items on the time axis. During the splicing process, when there is an unoccupied time segment between adjacent items to be synthesized, the time segment is marked separately and written as a timing placeholder segment to maintain the integrity of the time axis. It should be noted that by incorporating the items to be synthesized and the timing placeholder segments into the orchestration process, a synthesized timing table covering the complete time axis is finally formed.

[0130] Step S2054: The FPGA performs waveform synthesis according to the synthesis timing table, and combines each item to be synthesized and the timing placeholders in sequence and outputs them as a variable timing combination drive waveform.

[0131] In this embodiment, based on the technical understanding that the synthesis timing table has fully described the timing structure of the driving waveform, specifically, the synthesis timing table not only includes the execution order of each item to be synthesized, but also clarifies the timing placeholders between each item, thus providing a continuous time frame for waveform generation. Based on this principle, the FPGA reads each item to be synthesized sequentially according to the synthesis timing table and generates waveform segments that match their timing descriptions within the corresponding time segments. For segments marked as timing placeholders, the corresponding unloaded timing expression is output according to their placeholder attributes. It should be noted that by sequentially combining each item to be synthesized with the timing placeholders on the same time axis, the final output driving waveform is consistent with the synthesis timing table in terms of timing structure.

[0132] Figure 2 The process of forming a variable timing combination drive waveform is illustrated, which, from left to right, reflects the preparation of pulse components, the establishment of the correspondence between components and offset intervals, and the timing synthesis result of the final drive waveform; specifically, Figure 2 The left side illustrates multiple pulse components obtained after the preset driving mode is decomposed into components, including pulse component A, pulse component B, pulse component C, pulse component D, pulse component E and pulse component F. Each pulse component participates in the subsequent timing reconstruction process as an independently schedulable time unit.

[0133] like Figure 2As shown in the middle section, after obtaining the offset sequence and completing the interval processing, a correspondence table between components and intervals is established based on the matching relationship between the time attribute labels of the components and the offset intervals. For example, pulse components A, B, and C are mapped to interval 1, pulse components D and E are mapped to interval 2, and pulse component F is mapped to interval 3. It should be noted that this correspondence does not limit the final output order of the components, but is used to determine the time segment to which the components should belong during the time reordering process.

[0134] like Figure 2 As shown on the right, after the component rearrangement and instantiation are completed, each pulse component is rearranged and synthesized into a variable timing combination drive waveform according to the order of the interval identifiers. Specifically, pulse components A and B belonging to interval 1 are arranged to the pre-magnetization stage, and a placeholder segment 1 is inserted afterward to maintain time continuity. Pulse components D and E belonging to interval 2 are arranged to the flux compensation stage, and a placeholder segment 2 is inserted afterward. The components belonging to interval 3 are used to form the demagnetization stage, which is expressed in the form of a slope descent segment, reflecting the timing characteristics of the demagnetization stage. Finally, each stage is arranged in order according to the time axis direction to form a complete variable timing combination drive waveform, which is then sequentially output by the FPGA to the relay coil circuit.

[0135] Step S3: Input the variable timing combination drive waveform to the relay coil circuit, maintain the target magnetic flux distribution during the magnetic flux compensation stage, and release magnetic energy with an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay's engagement and disengagement response time.

[0136] The specific steps of step S3 are as follows:

[0137] Step S301: Mark the variable timing combination drive waveform into stages and divide it into a stage sequence including a pre-magnetization stage, a flux compensation stage and a demagnetization stage according to time order, and write a stage identifier for each stage.

[0138] In this embodiment, based on the technical understanding that the variable timing combination drive waveform contains different control semantic segments in the time dimension, specifically, although the drive waveform has been constructed as a whole according to the synthetic timing table, the different time segments within it play different roles in the relay control process. If they are not distinguished, it will be detrimental to subsequent targeted processing. Based on this principle, the variable timing combination drive waveform is analyzed along the time axis, and stage labeling is performed on it according to the timing characteristics of the waveform in different time periods. The continuous waveform segments are divided into pre-magnetization stage, magnetic flux compensation stage and demagnetization stage according to the time sequence, and corresponding stage identifiers are written for each stage. It should be noted that through this stage labeling and division process, the drive waveform is logically organized into a stage sequence with clear stage attributes.

[0139] Step S302: Perform waveform stack scheduling on the stage sequence, and load the waveform segments corresponding to each stage into the output sequence according to the stage identifier.

[0140] In this embodiment, based on the technical understanding that the stage sequence needs to be transformed into a controllable output order, specifically, although the stage sequence formed in step S301 has clearly distinguished the time segments of different stages, the waveform segments corresponding to each stage still exist in the form of logical division and have not yet formed a scheduling structure for direct output. Based on this principle, each stage in the stage sequence is parsed according to its stage identifier, and the waveform segments belonging to the same stage are extracted and loaded according to the order of the stages on the time axis, so that each waveform segment logically enters a unified output management queue. It should be noted that, through the waveform stack scheduling process, the waveform segments of different stages are organized into a sequence to be output while maintaining the original time order.

[0141] Step S303: In the flux compensation stage, compensation parameters are written to the output sequence. The compensation control parameters associated with the action leader and offset sequence are embedded into the timing description item of the corresponding waveform segment to form the output command set of the compensation stage.

[0142] In this embodiment, based on the technical understanding that targeted control needs to be performed in conjunction with the results of the preceding analysis during the flux compensation stage, specifically, the flux compensation stage corresponds to the key transition section of the relay's electromagnetic state, and its control content should maintain a time correlation with the aforementioned action pilot quantity and offset sequence. Based on this principle, waveform segments belonging to the flux compensation stage are located in the output sequence, and the timing description items corresponding to these waveform segments are parsed. Compensation control parameters corresponding to the time nodes in the action pilot quantity and the offset entries in the offset sequence are written into the timing description items. It should be noted that through this compensation parameter writing process, each waveform segment in the flux compensation stage logically carries control information that matches the relay pre-action analysis results, thereby forming a structured set of output instructions for the compensation stage.

[0143] Step S304: In the demagnetization stage, the output sequence is sloped and arranged. The waveform segment in the demagnetization stage is converted into a timing expression containing a slope segment. The start and end marks of the slope segment are written into the synthesis timing table according to the preset slope arrangement criteria, so that the FPGA can output to the relay coil circuit in sequence.

[0144] In this embodiment, based on the technical understanding that the demagnetization stage has independent timing semantics in the relay control process, specifically, the demagnetization stage corresponds to the segment of the driving waveform that transitions from the excitation state to the release state, and its timing expression needs to be distinguished from the preceding stage for independent scheduling. Based on this principle, waveform segments belonging to the demagnetization stage are identified and extracted from the output sequence, and the timing structure of these waveform segments is re-analyzed, converting the original continuous expression into a timing expression form composed of at least one slope segment. Clear start and end markers are written for each slope segment according to a preset slope arrangement criterion. It should be noted that by writing the start and end markers into the synthesized timing table, the timing evolution relationship of the demagnetization stage has an independently identifiable expression unit in the synthesized timing table, thereby enabling the FPGA to sequentially retrieve the corresponding slope segments in a predetermined order and output them to the relay coil circuit in the subsequent output process, completing the timing arrangement of the demagnetization stage.

[0145] Example 2

[0146] Please see Figure 3 Another embodiment of the present invention provides: a high-speed response system for intelligent relays based on direct FPGA control, comprising: a signal acquisition module, a drive waveform generation module, and a response module;

[0147] The signal acquisition module is used to acquire the coil current, magnetic flux change and contact movement signals of the relay in parallel, and generate the action pilot quantity;

[0148] The drive waveform generation module calculates the timing offset between the relay target action and its electromagnetic hysteresis based on the action leader quantity, and generates a variable timing combination drive waveform accordingly.

[0149] The response module is used to input the variable timing combination drive waveform to the relay coil circuit, maintain the target magnetic flux distribution during the magnetic flux compensation stage, and release magnetic energy at an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay engagement and release response time.

[0150] In addition, the parts of the technical solutions provided in the embodiments of this application that are consistent with the implementation principles of the corresponding technical solutions in the prior art have not been described in detail, so as to avoid excessive elaboration.

[0151] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-speed response method for intelligent relays based on direct FPGA control, characterized in that, The method is used in vehicle electrical systems to perform high-speed on / off control of vehicle load circuits, specifically including: The relay's coil current, magnetic flux change, and contact movement signals are acquired in parallel, and an action pilot quantity is generated. The action pilot quantity is used to reflect the relay's pre-action state. The timing offset between the relay target action and its electromagnetic hysteresis is calculated based on the action leader quantity, and a variable timing combination drive waveform is generated accordingly. The variable timing combination driving waveform is input to the relay coil circuit to maintain the target magnetic flux distribution during the magnetic flux compensation stage and to release magnetic energy with an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay's engagement and disengagement response time.

2. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 1, characterized in that, The parallel acquisition of relay coil current, magnetic flux change, and contact movement signals, and the generation of action pilot quantities, including: A sampling channel is established for the relay inside the FPGA, and the sampling start time of each sampling channel is uniformly indexed to form a synchronization reference; Based on the synchronization benchmark, each sampling channel is time-sequentially segmented, and the sampling sequence in each period is divided into multiple discrete segments. A signal state set is then established in parallel for each discrete segment. On-chip cross-correlation analysis is performed on the signal state set. The coil current change trend, magnetic flux increase / decrease mode and contact micro-displacement sequence are merged and calculated according to preset correlation weights to form an intermediate discrimination set for distinguishing different pre-action modes of the relay. Based on the intermediate discrimination set, an action precursor sequence is constructed. The action precursor sequence is arranged by the FPGA according to the chronological order, so that different signal features form a prediction path before the actual action of the relay. The FPGA performs regular extraction and timing compression on the action precursor sequence to generate action precursor quantities.

3. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 2, characterized in that, Constructing an action precursor sequence based on the intermediate discrimination set includes: The discrimination units in the intermediate discrimination set are segmented and recombined according to their generation time, so that the discrimination units formed by different signal sources form time clusters in the same time segment; The time clusters are serialized, and the discrimination units in adjacent time segments are connected into a continuous discrimination chain according to the segment order; Path filtering is performed in the discrimination chain to remove discrimination units that do not meet the preset sequence association conditions, and the remaining discrimination units are formed into a path set according to the evolution relationship of signal changes; Construct an action precursor sequence based on the set of paths.

4. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 3, characterized in that, The step of using FPGA to perform regular extraction and timing compression of the action precursor sequence to generate action precursor quantities includes: The action precursor sequence is scanned in a pattern, and each precursor unit in the sequence is divided into multiple pattern segments according to a preset discrimination criterion. The pattern fragments are extracted by rules. Precursor units with continuous change relationships within the fragments are grouped into rule groups, and precursor units that do not conform to the extraction rules are removed from the rule groups to form a candidate rule set. The candidate rule set is time-series compressed by sequentially merging the precursor units that appear repeatedly or have overlapping time spans in the rule set, so that the FPGA obtains a compressed sequence. Action leaders are extracted based on the compressed sequence.

5. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 4, characterized in that, The step of calculating the timing offset between the relay target action and its electromagnetic hysteresis based on the action leader quantity, and generating a variable timing combination drive waveform accordingly, includes: The action leader is rearranged on the time axis, and its internal time nodes are sorted according to the direction of relay action, so that the FPGA obtains a time series set. The time series set is subjected to lag mapping processing, and the reference time segments related to the inherent action delay of the relay are matched with the time series set to form a mapping group; The offset derivation is performed on the mapping group, the time difference between each key node in the time series set and the corresponding segment in the mapping group is calculated, and the calculation results are combined into an offset sequence. The offset sequence is decomposed into pulse structure, the preset driving mode is split into multiple pulse components with different time attributes, and each pulse component is rearranged according to the timing relationship in the offset sequence to generate a pulse combination framework with variable timing. The pulse combination framework is time-series synthesized based on FPGA, and the pulse components are combined in a rearranged order to form a variable timing combination driving waveform for driving the relay coil.

6. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 5, characterized in that, The offset derivation is performed on the mapping group, the time difference between each key node in the time series set and the corresponding segment in the mapping group is calculated, and the calculation results are combined into an offset sequence, including: In the time series set, key nodes are indexed. At least one key node is selected from each time series according to the preset node selection criteria, and the selected key node is assigned a corresponding node identifier. The mapping group is segment aligned by aligning the reference segments corresponding to each node identifier according to the same time base, resulting in a set of aligned segments that correspond one-to-one with each key node. Offset derivation is performed on the set of aligned segments. The time difference between each key node and the corresponding aligned segment is calculated. The time differences of different key nodes are then grouped according to the node identifier to form an offset entry set. The offset entry set is serialized and arranged according to the chronological order of the key nodes, and the arrangement result is output as an offset sequence.

7. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 6, characterized in that, The offset sequence is decomposed into pulse structures, the preset driving mode is split into multiple pulse components with different time attributes, and the pulse components are rearranged according to the temporal relationship in the offset sequence to generate a pulse combination framework with variable timing, including: The offset sequence is divided into multiple offset intervals according to time order, and each offset interval is assigned an interval identifier to form an interval set. The preset driving mode is decomposed into components, which are then divided into multiple pulse components. Each pulse component is assigned a component identifier and a time attribute label, which includes a start mark, a duration mark, and an interval mark. Based on the set of intervals and the time attribute labels, component mapping is performed, and each pulse component is matched with its corresponding offset interval according to its time attribute label to generate a correspondence table between components and intervals. The correspondence table between the components and intervals is rearranged, and the start mark, duration mark and interval mark of each pulse component are arranged in the order of interval identifier to form a pulse combination framework with variable timing.

8. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 7, characterized in that, Based on FPGA, the pulse combination framework is time-synthesized, and the pulse components are combined in a rearranged order to form a variable timing combination drive waveform for driving the relay coil, including: The pulse combination framework is instantiated sequentially, and each pulse component in the framework is parsed into an item to be synthesized according to its component identifier. A time-series description item corresponding to its time attribute label is established for each item to be synthesized. The timing description items are conflict-normalized, and timing description items with overlapping times or contradictory intervals are adjusted according to a preset normalization criterion to generate a normalized timing set. The regularized time series set is synthesized and arranged. Each item to be synthesized is spliced ​​together in the order determined by the regularized time series set, and the interval segment generated during the splicing process is written as an independent time series placeholder segment to form a synthesized time series table. The FPGA performs waveform synthesis according to the synthesis timing table, and combines each item to be synthesized and the timing placeholders in sequence and outputs them as a variable timing combination drive waveform.

9. The high-speed response method for intelligent relays based on direct FPGA control as described in claim 8, characterized in that, The variable timing combination drive waveform is input to the relay coil circuit to maintain the target magnetic flux distribution during the magnetic flux compensation phase and to release magnetic energy at an FPGA-controlled slope during the demagnetization phase, thereby shortening the relay's engagement and disengagement response time. This includes: The variable timing combination drive waveform is marked with stages and divided into a stage sequence including a pre-magnetization stage, a flux compensation stage and a demagnetization stage according to time order, and a stage identifier is written for each stage. The waveform stack scheduling is performed on the stage sequence, and the waveform segments corresponding to each stage are loaded into the output sequence according to the stage identifier; In the flux compensation stage, compensation parameters are written to the output sequence. The compensation control parameters associated with the action pilot and offset sequence are embedded into the timing description item of the corresponding waveform segment to form the output command set of the compensation stage. During the demagnetization stage, the output sequence is sloped and arranged to convert the waveform segments of the demagnetization stage into timing expressions containing slope segments. The start and end marks of the slope segments are written into the synthesis timing table according to the preset slope arrangement criteria, so that the FPGA can output them to the relay coil circuit in sequence.

10. A high-speed response system for intelligent relays based on direct FPGA control, used to implement the high-speed response method for intelligent relays based on direct FPGA control as described in any one of claims 1-9, characterized in that, include: Signal acquisition module, drive waveform generation module, and response module; The signal acquisition module is used to acquire the coil current, magnetic flux change and contact movement signals of the relay in parallel, and generate the action pilot quantity; The drive waveform generation module calculates the timing offset between the relay target action and its electromagnetic hysteresis based on the action leader quantity, and generates a variable timing combination drive waveform accordingly. The response module is used to input the variable timing combination drive waveform to the relay coil circuit, maintain the target magnetic flux distribution during the magnetic flux compensation stage, and release magnetic energy at an FPGA-controlled slope during the demagnetization stage, thereby shortening the relay engagement and disengagement response time.

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