Method and apparatus for data protection control of memory devices with selective soft bit transmission

Abstract

Methods and apparatus are provided for data protection control of a memory device with aid of selective soft bit transfer. The memory device may include a memory controller and a non-volatile (NV) memory. The method may include transmitting at least one read command and a controller-side indication to the NV memory, the controller-side indication to selectively enable selective soft bit transfer in the NV memory for obtaining soft decoding information for a first page within a first block of the plurality of blocks, the first page being configured to store first data; and receiving the soft decoding information and a memory side indication from the NV memory, the memory side indication indicating whether the NV memory is to transmit at least one soft bit in a second period in a first period, and the second period is after the first period.

Description

Technical Field

[0001] This invention relates to memory control, and more particularly to a method for data protection control of a memory device by means of selective soft-bit transmission, and related apparatus. Background Technology

[0002] Memory devices may include flash memory for storing data, and access management of flash memory is complex. For example, a memory device can be a memory card, a solid-state drive (SSD), or an embedded storage device such as an embedded storage device conforming to the Universal Flash Storage (UFS) specification. This memory device can be used to store various files in the host's file system, such as system files, user files, etc. To ensure the integrity of data read from this flash memory, multiple types of data protection processes can be implemented. However, during data reading from this flash memory, when more than one type of data protection process is triggered, overall performance may degrade. Therefore, a novel method and related architecture are needed to address these problems without introducing side effects or in a way that is unlikely to introduce side effects. Summary of the Invention

[0003] The purpose of this invention is to provide a method and related apparatus for data protection control of a memory device by means of selective soft bit transfer, in order to solve the above-mentioned problems.

[0004] At least one embodiment of the present invention provides a method for data protection control of a memory device by means of selective soft bit transfer, wherein the method can be applied to a memory controller of the memory device. The memory device may include the memory controller and a non-volatile (NV) memory, the NV memory may include at least one NV memory element (e.g., one or more NV memory elements), and the at least one NV memory element may include multiple blocks. The method may include: transmitting at least one read command and a controller-side indication to the NV memory, the controller-side indication selectively enabling the selective soft-bit transfer in the NV memory to obtain soft-decoding information for a first page in a first block of a plurality of blocks, wherein the first page is used to store first data; and receiving the soft-decoding information and a memory-side indication from the NV memory to perform soft decoding based on the soft-decoding information to obtain the first data from the soft decoding, wherein the memory-side indication is used in a first cycle to indicate whether the NV memory will transfer at least one soft bit in a second cycle, and the second cycle is a cycle following the first cycle.

[0005] In addition to the methods described above, the present invention also provides a memory controller for data protection control of a memory device using selective soft bit transfer, wherein the memory device includes the memory controller and an NV memory. The NV memory may include at least one NV memory element (e.g., one or more NV memory elements), and the at least one NV memory element may include multiple blocks. Furthermore, the memory controller includes processing circuitry configured to control the memory controller according to multiple host commands from a host device, thereby allowing the host device to access the NV memory through the memory controller. More specifically, the memory controller is configured to transmit at least one read command and a controller-side indication to the NV memory, the controller-side indication being used to selectively enable the selective soft bit transfer in the NV memory to obtain soft decoding information for a first page in a first block of the plurality of blocks, wherein the first page is used to store first data; and the memory controller is configured to receive the soft decoding information and a memory-side indication from the NV memory to perform soft decoding based on the soft decoding information to obtain the first data from the soft decoding, wherein the memory-side indication is used in a first cycle to indicate whether the NV memory will transfer at least one soft bit in a second cycle, and the second cycle is a cycle following the first cycle.

[0006] In addition to the methods described above, the present invention also provides a memory device including the memory controller described above, wherein the memory device includes: the NV memory for storing information; and the memory controller coupled to the NV memory for controlling the operation of the memory device.

[0007] Furthermore, the present invention also provides an electronic device including the aforementioned memory device, wherein the electronic device further includes a host device coupled to the memory device. The host device may include: at least one processor for controlling the operation of the host device; and a power supply circuit coupled to the at least one processor for providing power to the at least one processor and the memory device. In addition, the memory device can provide storage space for the host device.

[0008] According to some embodiments, the device may include at least a portion (e.g., a portion or all) of the electronic device. For example, the device may include the memory controller in the memory device. As another example, the device may include the memory device. Yet another example, the device may include the electronic device.

[0009] The method and related apparatus of the present invention can ensure the normal operation of a memory device under various conditions. For example, a memory controller within the memory device can operate according to at least one control scheme (e.g., one or more control schemes) of the method to perform related operations. In particular, it controls the NV memory to selectively transfer a small subset of soft bits from a plurality of soft bits, rather than transferring all soft bits from the plurality of soft bits, and uses a predetermined indication signal (e.g., any signal from at least one predetermined signal between the memory controller and the NV memory) as a prompt for the selective soft bit transfer, thereby improving overall performance. Furthermore, the method and related apparatus of the present invention can solve the problems of related technologies without introducing side effects or in a manner unlikely to introduce side effects. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention, wherein... Figure 1 The architecture shown can be operated according to a method of data protection control of a memory device by means of selective soft bit transfer.

[0011] Figure 2 A schematic diagram illustrating a storage control scheme of the method according to an embodiment of the present invention is shown.

[0012] Figure 3 The following diagram illustrates the relevant operations in a software decoding control scheme according to an embodiment of the present invention.

[0013] Figure 4A schematic diagram illustrating an access control scheme of the method according to an embodiment of the present invention is shown.

[0014] Figure 5 A split control scheme of the method is illustrated according to an embodiment of the present invention.

[0015] Figure 6 A hybrid readout control scheme of the method is illustrated according to an embodiment of the present invention.

[0016] Figure 7 The following diagram illustrates the relevant operations in an enhanced soft decoding control scheme according to an embodiment of the present invention.

[0017] Figure 8 Illustration based on an embodiment of the present invention Figure 7 The enhanced soft decoding control scheme shown involves a set of data signals and a predetermined indication signal.

[0018] Figure 9 An embodiment of the present invention is illustrated, by means of Figure 7 The enhanced software decoding control scheme shown improves the overall throughput of the memory device.

[0019] Figure 10 Illustration based on an embodiment of the present invention Figure 7 The enhanced software decoding control scheme shown here relates to the relevant decoding performance.

[0020] Figure 11 Illustration based on an embodiment of the present invention Figure 7 The enhanced soft decoding control scheme shown here involves a series of histograms within a pre-established database.

[0021] Figure 12 Illustration based on an embodiment of the present invention Figure 7 The enhanced software decoding control scheme shown here involves relevant statistical data in the pre-established database.

[0022] Figure 13 Illustration based on an embodiment of the present invention Figure 7 The enhanced software decoding control scheme shown here involves more statistical data within the pre-established database.

[0023] Figure 14 An embodiment of the present invention is illustrated for... Figure 7 This diagram illustrates a scenario of the enhanced soft decoding control scheme and related implementation details.

[0024] [Symbol Explanation]

[0025] 10: Electronic devices

[0026] 50: Main unit

[0027] 52: Processor

[0028] 54: Power Supply Circuit

[0029] 58,118: Transmission interface circuit

[0030] 100: Memory device

[0031] 110: Flash memory controller

[0032] 112: Microprocessor

[0033] 112C: Program Code

[0034] 112M: Read-Only Memory (ROM)

[0035] 114: Control Logic Circuit

[0036] 116: Random Access Memory (RAM)

[0037] 120: Flash memory module

[0038] 122-1~122-N: Flash memory elements

[0039] 130: Data Protection (DP) Circuit

[0040] 130C: Data Protection Control (DPC) Circuit

[0041] NC: Noise Canceller

[0042] ENDEC: Encoder and Decoder Circuits

[0043] RNDRN: Randomizer and Derandomizer Circuits

[0044] DQ: Data signal

[0045] IND: Pre-set Indication Signal

[0046] VR1~VR15: Read voltage

[0047] PS0~PS15: Status

[0048] S10, S11, S12A, S12B, S13~S17, S24, S25: Steps

[0049] U0~U2,SIGN,L0~L2,U0_M1,SIGN_M1,L0_M1,U0_M0,SIGN_M0,L0_M0: Read the sensed voltage

[0050] Shift_M_to_M1: First distribution offset

[0051] Shift_M_to_M0: Second distribution offset

[0052] 611~618: Read operations

[0053] DBI: Data Bus Inversion (DBI) signal

[0054] 901: NAND flash memory throughput (abbreviated as "NAND throughput")

[0055] 902: Host throughput

[0056] 903: Hardware decoding throughput

[0057] 904: Fast N4 throughput

[0058] 1201, 1301, 1302: Trends

[0059] 1202: Reference Line

[0060] 1401: Read command

[0061] 1402: Direct Memory Access (DMA) command

[0062] 1403: Data Switching Operation

[0063] ALE: Address Latch Enable (ALE) signal

[0064] CLE: Command Latch Enable (CLE) signal

[0065] READ: Read operation command

[0066] Addr: address

[0067] R_stress: Read pressure

[0068] BZ: Busy signal

[0069] Polling: the signal for polling

[0070] Status: Status Detailed Implementation

[0071] Figure 1 This is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein... Figure 1 The architecture shown can operate according to a method for data protection control of a memory device, such as memory device 100, by means of selective soft bit transfer. For Figure 1As shown in the architecture, electronic device 10 may include a host device 50 and a memory device 100. The host device 50 may include at least one processor (e.g., one or more processors), collectively referred to as processor 52, and may further include a power supply circuit 54 coupled to processor 52. Processor 52 controls the operation of the host device 50, while the power supply circuit 54 provides power to processor 52 and memory device 100, and outputs one or more drive voltages to memory device 100. Memory device 100 can provide storage space to host device 50 and obtain the one or more drive voltages from host device 50 as power for memory device 100. Examples of host device 50 may include, but are not limited to, multifunction mobile phones, wearable devices, tablet computers, and personal computers such as desktop computers and laptop computers. Examples of memory device 100 may include, but are not limited to, solid-state drives (SSDs) and various embedded memory devices such as embedded memory devices conforming to the Peripheral Component Interconnect Express (PCIe) specification. According to this embodiment, the memory device 100 may include a memory controller, such as a flash memory controller 110, and may further include an NV memory, such as a flash memory, which may be implemented as a flash memory module 120. The flash memory controller 110 is used to control the operation of the memory device 100 and access the flash memory module 120, while the flash memory module 120 is used to store information. The NV memory, such as the flash memory module 120, may include at least one NV memory element, such as at least one flash memory element, particularly including a plurality of flash memory elements 122-1, 122-2, ... and 122-N, where "N" may represent a positive integer greater than 1. For example, these flash memory elements 122-1, 122-2, ... and 122-N may be implemented by means of flash memory chips, flash memory dies, etc. According to certain embodiments, these flash memory elements 122-1, 122-2, ... and 122-N can be implemented in the form of a plurality of flash memory dies, which can be packaged, stacked and / or integrated into at least one flash memory wafer (e.g., one or more flash memory wafers), wherein the at least one flash memory wafer may contain at least one of the plurality of flash memory dies.

[0072] like Figure 1As shown, the flash memory controller 110 may include a processing circuit, such as a microprocessor 112, a storage element, such as a read-only memory (ROM) 112M, a control logic circuit 114, a random-access memory (RAM) 116, and a transmission interface circuit 118, wherein the above elements can be coupled to each other via a bus. RAM 116 is implemented using static random-access memory (SRAM), but the invention is not limited thereto. RAM 116 can be used to provide internal storage space for the flash memory controller 110. For example, RAM 116 can be used as a buffer memory to buffer data. Furthermore, in this embodiment, ROM 112M is used to store program code 112C, and the microprocessor 112 is used to execute program code 112C to control access to the flash memory module 120. Note that in some embodiments, program code 112C may be stored in RAM 116 or any other type of memory. Furthermore, the control logic circuit 114 is used to control the flash memory module 120 and may include a data protection (DP) circuit 130 (denoted as "DP circuit" for simplicity) for performing data protection processing operations. The data protection circuit 130 may include multiple sub-circuits such as a noise canceller (NC), an encoder and decoder circuit (ENDEC), a randomizer and de-randomizer circuit (RNDRN), a data protection control (DPC) circuit 130C (denoted as "DPC circuit" for simplicity), and other circuits. For example, the encoder and decoder circuit ENDEC may have an encoder and a decoder, which are used to perform encoding and decoding operations respectively, while the randomizer and derandomizer circuit RNDRN may include a randomizer and a derandomizer, which are used to perform randomization and derandomization operations respectively, and the noise canceller NC may be used to perform noise cancellation operations, in particular, to cancel noise caused by cell-to-cell interference.The encoder and decoder operations within the encoder and decoder circuit ENDEC may include error correction code (ECC) encoding and decoding to protect data and / or correct errors in any of the multiple sub-storage units within a physical page, and may also include redundant array of independent disks (RAID) encoding and decoding to protect data and / or correct errors in a group of physical pages, such as a set of physical pages, wherein the multiple sub-storage units may have the same size, such as a predetermined size smaller than the size of a physical page, but the invention is not limited thereto. For example, the encoding / decoding of the encoder and decoder circuit ENDEC may include low-density parity-check (LDPC) code encoding / decoding. Furthermore, the data protection control circuit 130C may perform data protection control as overall control of the data protection processing operations to more securely protect data under one or more predetermined conditions. For example, the data protection control may include controlling the memory device 100 (or its flash memory controller 110) to operate according to at least one control scheme (e.g., one or more control schemes) of the method to perform related operations.

[0073] The transmission interface circuit 118 may conform to one or more communication standards (e.g., Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCIe, embedded Multi Media Card (eMMC), and Universal Flash Storage (UFS) standards), and may communicate with the host device 50 (or its corresponding transmission interface circuit 58) according to these standards. Similarly, the transmission interface circuit 58 may also conform to these standards and communicate with the memory device 100 (or its transmission interface circuit 118) according to these standards.

[0074] In this embodiment, the host device 50 can transmit host commands and corresponding logical addresses to the flash memory controller 110 to access the memory device 100. The flash memory controller 110 receives the host commands and logical addresses, converts the host commands into memory operation commands (hereinafter referred to as operation commands), and further uses the operation commands to control the flash memory module 120 to perform read, write / programming, and other operations on memory units (e.g., data pages) with physical addresses within the flash memory module 120, wherein these physical addresses can be associated with logical addresses. When the flash memory controller 110 performs an erase operation on any flash memory element 122-n (where “n” represents any integer in the range [1, N]) of the plurality of flash memory elements 122-1, 122-2, ..., and 122-N, at least one of the plurality of blocks in the flash memory element 122-n will be erased, wherein each of these blocks may contain multiple pages (e.g., data pages), and access operations such as read or write operations can be performed on one or more pages.

[0075] like Figure 1 As shown, the data protection circuit 130 may be illustrated as being integrated into the control logic circuit 114, but the invention is not limited thereto. According to some embodiments, the data protection circuit 130 may be implemented in a dedicated circuit outside the control logic circuit 114. For example, this dedicated circuit may be at least one digital signal processing (DSP) engine, such as a single DSP engine.

[0076] Certain implementation details of the internal control of the memory device 100 can be further described below. According to some embodiments, the flash memory controller 110 may record, maintain, and / or update management information in at least one table, such as at least one temporary table (e.g., one or more temporary tables) in the random access memory 116 and at least one non-temporary table (e.g., one or more non-temporary tables) in the flash memory module 120, wherein the at least one temporary table may be collectively referred to as a temporary table, and the at least one non-temporary table may be collectively referred to as a non-temporary table. A temporary table may contain a temporary version of at least a portion (e.g., a portion or all) of the non-temporary tables. For example, a non-temporary table may contain at least one logical-to-physical (L2P) address mapping table (e.g., one or more L2P address mapping tables) to record multiple logical addresses (e.g., logical block addresses (LBAs) indicating multiple logical blocks and logical page addresses (LPAs) indicating multiple logical pages within any of the multiple logical blocks) and multiple entity addresses (e.g., physical block addresses (PBAs) indicating multiple physical blocks and physical page addresses indicating multiple physical pages within any of the multiple physical blocks). The mapping relationship between address (PPA) and temporary table may contain a temporary version of at least one sub-table (e.g., one or more sub-tables) of at least one L2P address mapping table, wherein flash memory controller 110 (e.g., microprocessor 112) may perform bi-directional address translation between host-side storage space (e.g., logical address) of host device 50 and device-side storage space (e.g., physical address) of flash memory module 120 in memory device 100 to access data for host device 50.

[0077] In flash memory module 120, when a block of any one of flash memory elements 122-1, 122-2, ..., and 122-N is used as a single-level cell (SLC) block, each of the plurality of physical pages within the block can correspond to a logical page, and each of the plurality of memory cells within that page can be used to store only a single bit. Furthermore, when a block of any one of flash memory elements 122-1, 122-2, ..., and 122-N is used as a multiple-level cell (MLC) block, each of the plurality of physical pages within the block can correspond to at least two logical pages, and each of the plurality of memory cells within that page can be used to store at least two bits. In particular, when a block of any one of the flash memory elements 122-1, 122-2, ..., and 122-N is used as a triple-level cell (TLC) block, each of the plurality of physical pages within the block can correspond to three logical pages, and each of the plurality of memory cells of the page can be used to store three bits; when a block of any one of the flash memory elements 122-1, 122-2, ..., and 122-N is used as a quadruple-level cell (QLC) block, each of the plurality of physical pages within the block can correspond to four logical pages, and each of the plurality of memory cells of the page can be used to store four bits; and so on.

[0078] Figure 2 A schematic diagram illustrating a storage control scheme according to an embodiment of the present invention is provided, wherein multiple states (e.g., programming states) of a memory cell in a QLC block can be represented by curves for better understanding, but the invention is not limited thereto. The horizontal axis (labeled "Vth") may represent the read sensing voltage of the flash memory module 120 (e.g., a threshold voltage used to determine bit information during the reading of the flash memory module 120); for simplicity, the read sensing voltage may also be referred to as the read voltage. For example, the flash memory controller 110 may selectively set one or more of these read voltage settings {Vth = VR1, Vth = VR2, ..., Vth = VR15} to determine bit information during the reading of the flash memory module 120.

[0079] like Figure 2As shown, any memory cell in a QLC block can be configured to have any of 16 states, PS0, PS1… and PS15, for example, through programming, and these states can represent different combinations of four bits (named the top bit, upper bit, middle bit, and lower bit) in… Figure 2 In the illustrated embodiment, when the memory cell is configured to have state PS0, the highest, higher, middle, and lower bits stored in the memory cell are (1,1,1,1); when the memory cell is programmed to have state PS1, the highest, higher, middle, and lower bits stored in the memory cell are (1,1,1,0); and so on.

[0080] For example, when it is necessary to read the most significant bit by means of flash memory controller 110, flash memory controller 110 can control flash memory module 120 to apply four read voltages VR5, VR10, VR12 and VR15 to read the memory cell. If the memory cell is on when the read voltage VR5 is applied, the highest bit is determined to be "1"; if the memory cell is not on when the read voltage VR5 is applied and is on when the read voltage VR10 is applied, the highest bit is determined to be "0"; if the memory cell is not on when the read voltage VR10 is applied and is on when the read voltage VR12 is applied, the highest bit is determined to be "1"; if the memory cell is not on when the read voltage VR12 is applied and is on when the read voltage VR15 is applied, the highest bit is determined to be "0"; and if the memory cell is not on when the read voltage VR15 is applied, the highest bit is determined to be "1". For other cases where the flash memory controller 110 needs to read higher bits, middle bits, and lower bits separately, the relevant implementation details can be deduced similarly.

[0081] It is important to note that Figure 2 The gray code shown in the lower half is for illustrative purposes only and is not intended to limit the invention. In some instances, any suitable gray code can be applied to the memory device 100, and the read voltage used to determine the most significant bit, the higher significant bit, the middle significant bit, and the lower significant bit can be changed accordingly.

[0082] Bits read from memory cells using a portion of read voltages VR1, VR2, ..., and VR15 can be considered as a sign bit. For better understanding, the flash memory controller 110 can utilize data protection circuitry 130 to process the sign bit obtained from a set of memory cells (e.g., 4K memory cells). Specifically, it utilizes the derandomizer within the randomizer and derandomizer circuit RNDRN to perform derandomization operations and the decoder within the encoder and decoder circuit ENDEC to perform error correction operations (e.g., decoding to generate decoded data to correct errors). However, since the state interval of memory cells within a QLC block is typically very small, the state of memory cells can vary significantly due to one or more of the various problems that may occur in the flash memory module 120 (e.g., read disturbance, program disturbance, and data retention), and the error correction operation may be unsuccessful.

[0083] According to a soft-decoding control scheme of this method, the flash memory controller 110 can control the flash memory module 120 to apply additional read voltage to the memory cell to obtain multiple soft bits, thereby increasing the success rate of error correction operations. For example, if the decoder cannot decode the symbol bits obtained from the memory cell, the flash memory controller 110 can control the flash memory module 120 to use the additional read voltage to read the memory cell again to obtain the first set of soft bits. In particular, the decoder may include an LDPC decoder, such as a decoder capable of performing LDPC code-related decoding, for soft decoding. The decoder (e.g., an LDPC decoder) can use the first set of soft bits to decode the symbol bits. For example, when the flash memory controller 110 attempts to read the top page of a block (e.g., the most significant bit of a memory cell), the flash memory controller 110 can control the flash memory module 120 to acquire a first set of soft bits using additional read voltages (VR5-ΔV), (VR10-ΔV), (VR12-ΔV), and (VR15-ΔV), where the symbol "ΔV" can represent a predetermined voltage difference (e.g., one of a plurality of predetermined voltage differences, such as a first predetermined voltage difference selected from the plurality of predetermined voltage differences). If the decoder still fails, the flash memory controller 110 can control the flash memory module 120 to read the memory cell again using additional read voltages (VR5+ΔV), (VR10+ΔV), (VR12+ΔV), and (VR15+ΔV) to acquire a second set of soft bits, and the decoder (e.g., an LDPC decoder) can use the first and second sets of soft bits to decode the symbol bits. Assuming that an immediate response from memory device 100 to host device 50 is not required, if the decoder still fails, flash memory controller 110 can control flash memory module 120 to perform a similar operation using another predetermined voltage difference (e.g., another of the plurality of predetermined voltage differences), and so on. Thus, for a soft decoding control scheme, flash memory controller 110 can control flash memory module 120 to further read memory cells one or more times using one or more sets of additional read voltages to obtain one or more sets of soft bits for soft decoding, for example, using this set of soft bits to decode symbol bits, wherein the soft bit count of this set of soft bits and the associated number of retries can be limited.

[0084] Because the state of memory cells within a QLC block can change drastically, if the flash memory controller 110 needs to read data from a QLC block within the flash memory module 120, it may read the memory cell and decode the data multiple times to attempt error correction. Error correction may succeed in normal use cases of the memory device 100, but may fail in extreme access scenarios. While error correction may succeed in normal use cases of the memory device 100, each time the flash memory controller 110 reads a memory cell, a read command needs to be sent to the flash memory module 120, and the flash memory module 120 requires a read busy time to read the symbol bits or soft bits. Therefore, this may degrade the performance of accessing QLC blocks in high-density storage such as any of the aforementioned flash memory elements 122-n (e.g., flash memory elements 122-n implemented as three-dimensional (3D) inverse gate (NAND flash) memory elements based on a predetermined 3D structure). The method and related apparatus provided by the present invention can ensure that the memory device 100 can operate properly under various conditions, and in particular, can improve overall performance.

[0085] Figure 3 The relevant operations in the software decoding control scheme of the method are illustrated according to an embodiment of the present invention.

[0086] In step S10, the flash memory controller 110 (or microprocessor 112) can determine whether a host command (e.g., one of multiple host commands) has been received. If yes, proceed to step S11; otherwise, proceed to step S10.

[0087] In step S11, the flash memory controller 110 (or microprocessor 112) determines whether the host command (e.g., the newly received host command detected in step S10) is a host read command. If yes, proceed to step S12A; otherwise, proceed to step S12B. A host read command may instruct the reading of data DATA(r) at a logical address, where the symbol "r" may represent an index corresponding to (or equal to) the number of times step S12A is entered. For example, when a host read command, such as a first host read command, is received from the host device 50, step S12A is entered for the first time (e.g., r = 1); when a host read command, such as a second host read command, is received from the host device 50, step S12A is entered for the second time (e.g., r = 2); and so on. For better understanding, regardless of the entry... Figure 3The index r of any of the multiple subsequent partial loops from step S13 to step S17 can be regarded as a loop index that includes at least one main loop such as step S11, step S12A, step S13, etc., but the present invention is not limited thereto.

[0088] In step S12A, in response to a host read command (e.g., the newly received host read command detected in steps S10 and S11), the flash memory controller 110 (or microprocessor 112) may transmit a first read command to the NV memory, such as the flash memory module 120, to attempt to read data DATA(r) from a page PAGE(r) in one of the plurality of blocks according to a physical address associated with the logical address, wherein the physical address indicates the page PAGE(r) in this block.

[0089] For example, in response to a host read command, the flash memory controller 110 (or microprocessor 112) can perform address mapping on the logical address according to the aforementioned at least one L2P address mapping table to obtain the physical address associated with the logical address, wherein the logical address can be one of the plurality of logical addresses, and the physical address can be one of the plurality of physical addresses. Since the aforementioned at least one L2P address mapping table can contain the mapping relationship between the plurality of logical addresses and the plurality of physical addresses, the flash memory controller 110 (or microprocessor 112) can perform address mapping on the logical address to determine the physical address.

[0090] In step S12B, the flash memory controller 110 (or microprocessor 112) may perform other processing. For example, when the host command (e.g., the newly received host command detected in step S10) is a host write command, the flash memory controller 110 (or microprocessor 112) may write data to the flash memory module 120 (e.g., program data).

[0091] In step S13, the flash memory controller 110 (or microprocessor 112) can determine whether the data DATA(r) read from page PAGE(r) is successful. If yes, proceed to step S17; if no, proceed to step S14.

[0092] In step S14, in response to the failure to read data DATA(r) from page PAGE(r), the flash memory controller 110 may send a second read command to the NV memory, such as the flash memory module 120, to obtain the soft decoding information SDI(r) for page PAGE(r), and use the decoder, such as the LDPC decoder, to perform a first soft decoding operation based on the soft decoding information SDI(r) to attempt to obtain data DATA(r) from the first soft decoding operation.

[0093] In step S15, the flash memory controller 110 (or microprocessor 112) can determine whether the data DATA(r) obtained from the first soft decoding operation is successful. If yes, proceed to step S17; if no, proceed to step S16.

[0094] In step S16, in response to the failure to obtain data DATA(r) from the first soft decoding operation, the flash memory controller 110 may use the decoder (e.g., the LDPC decoder) to perform further soft decoding processing, such as a second soft decoding operation, to obtain data DATA(r) from the second soft decoding operation.

[0095] In step S17, the flash memory controller 110 can send the data DATA(r) back to the host device 50.

[0096] To better understand, this software decoding control scheme can be... Figure 3 The workflow shown is intended to illustrate the invention, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 3 Add, delete, or modify in the workflow shown.

[0097] Figure 4A schematic diagram illustrating an access control scheme according to an embodiment of the present invention is provided. For better understanding, it can be assumed that within any of the flash memory elements 122-n described above, there are at least two memory cell groups (e.g., at least two clusters of memory cells), such as a first memory cell group M1 and a second memory cell group M0. The first memory cell group M1 may represent a first cluster of memory cells with a first distribution, and the second memory cell group M0 may represent a second cluster of memory cells with a first distribution. However, the invention is not limited to this; for example, the number of memory cell groups may be varied. Furthermore, one of the at least two memory cell groups (e.g., the first memory cell group M1 and the second memory cell group M0) may have a distribution shift corresponding to a portion of the read sensing voltage distribution (relative to a read sensing voltage distribution of a superset M), where the superset M may include the at least two memory cell groups such as the first memory cell group M1 and the second memory cell group M0. However, the invention is not limited to this. For example, the parent set M may include any of the aforementioned flash memory elements 122-n, and the read sensing voltage distribution may be equal to a global read sensing voltage distribution of any of the aforementioned flash memory elements 122-n. As another example, the parent set M may include flash memory module 120, and the read sensing voltage distribution may be equal to the overall read sensing voltage distribution of flash memory module 120.

[0098] like Figure 4 As shown, the first memory cell group M1 may have a first partial read-sensing voltage distribution (e.g., a curve corresponding to the legend of "M1"), and in particular, a first distribution offset Shift_M_to_M1 of the first partial read-sensing voltage distribution corresponding to the first memory cell group M1 (relative to the read-sensing voltage distribution of the parent set M). Additionally, the second memory cell group M0 may have a second partial read-sensing voltage distribution (e.g., a curve corresponding to the legend of "M0"), and in particular, a second distribution offset Shift_M_to_M0 of the second partial read-sensing voltage distribution corresponding to the second memory cell group M0 (relative to the read-sensing voltage distribution of the parent set M).

[0099] For better understanding, the read sensing voltage SIGN can represent a read sensing voltage used to determine the symbol bit, and read sensing voltages greater than SIGN (e.g., read sensing voltages U0, U1, and U2) and less than SIGN (e.g., read sensing voltages L0, L1, and L2) can represent multiple read sensing voltages used to determine the soft bit, but the invention is not limited thereto. For example, the multiple read sensing voltages used to determine the soft bit and / or the number of these read sensing voltages can be varied.

[0100] Figure 5 A split control scheme of the method is illustrated according to an embodiment of the present invention. The flash memory controller 110 (or microprocessor 112) can control the flash memory module 120 to utilize... Figure 4 The right half shows read sensing voltages U0, U1, and U2 as read sensing voltages L0_M1, SIGN_M1, and U0_M1 corresponding to the second soft decoding operation for the first memory cell group M1, and controls the flash memory module 120 to utilize respectively Figure 4 The read sensing voltages L0, L1, and L2 shown in the left half are read sensing voltages U0_M0, SIGN_M0, and L0_M0 corresponding to the second memory cell group M0 in relation to the second soft decoding operation.

[0101] According to some embodiments, the soft decoding information corresponding to the parent set M may include 1H2S soft decoding information (i.e., one hard-information bit and two soft-information bits) for soft decoding. If soft decoding is performed without considering the aforementioned at least two memory cell groups (e.g., the first memory cell group M1 and the second memory cell group M2), many high-reliability errors (HREs) may occur, which significantly reduces the error correction capability of soft decoding. The flash memory controller 110 can classify the 1H2S soft decoding information into 1H1S soft decoding information (i.e., one hard-information bit and one soft-information bit) corresponding to the first portion of the read sensing voltage distribution and 1H1S soft decoding information corresponding to the second portion of the read sensing voltage distribution, for example by using a noise canceller NC, and then merge them back into complete 1H1S soft decoding. Since the number of HREs has been significantly reduced, the error correction capability can be greatly increased even though the soft-information bit count has been reduced. For example, the operation of the noise canceller (NC) in response to the group detection result (Group) can be designed according to the following pseudo code:

[0102] if(Group==M1){

[0103] SIGN_M1 = U1;

[0104] L0_M1 = U0;

[0105] U0_M1 = U2;

[0106] }

[0107] else if (Group == M0){

[0108] SIGN_M0 = L1;

[0109] L0_M0 = L2;

[0110] U0_M0 = L0;

[0111] }

[0112] In some examples, the soft information bit count corresponding to the soft decoding information of the parent set M can be increased, and the soft information bit count corresponding to any one of the partial read-sensing voltage distributions of the multiple partial read-sensing voltage distributions can be increased accordingly. Therefore, the error correction capability can be further increased.

[0113] Regardless of whether the data protection circuit 130 is integrated into the control logic circuit 114, Figure 1 As shown, or implemented within at least one of the above-described DSP engines, such as a single DSP engine, the flash memory controller 110 can operate / manage according to at least one of the above-described control schemes with the aid of the data protection circuit 130. In addition to Figures 2 to 5 In addition to the storage control scheme, the software decoding control scheme, the access control scheme, and the split control scheme shown respectively, the above-mentioned at least one control scheme may further include one or more other control schemes for a plurality of predetermined programs, and the flash memory controller 110 may perform any of the plurality of predetermined programs (such as a retention group scan program, a media scan program, and a read-disturbance scan program), in particular, it may find the optimal read point with the lowest error bit rate and perform noise cancellation, such as inter-cell interference cancellation, to reduce the error bit rate, thereby enabling stronger software decoding.

[0114] Figure 6A hybrid read control scheme of the method is illustrated according to an embodiment of the present invention. The memory device 100 (or its flash memory controller 110) can perform a series of read operations {611, 612, ..., 618} corresponding to a variety of predetermined read operation cases (hereinafter referred to as "read cases"), such as 4K read cases and 16K read cases. This series of read operations {611, 612, ..., 618} may include a set of read operations {611, 612, 614, 616, 617} corresponding to the 4K read case and a set of read operations {613, 615, 618} corresponding to the 16K read case. Over time, hybrid read behaviors may occur, such as normal reads, retry reads with hard bit decoding, and soft-reads with 1H1S soft-decoding (i.e., one hard information bit and one soft information bit). For example, when the data protection circuit 130 is implemented in at least one DSP engine (e.g., a single DSP engine) to achieve better overall performance, the above-mentioned mixed reading behavior may include mixed hard decoding and fast soft decoding operations in a single channel, and a single data transfer (e.g., data transfer of 1 to 4 sectors) will occupy one of the multiple page buffers in the single DSP engine.

[0115] In a re-decoding scenario, when reading data DATA(r) from page PAGE(r) fails, the operation of transmitting symbol bits (or hard bits) plus at least one soft bit (e.g., one or more soft bits) may be performed more than once. Assuming data transfer throughput is a critical metric, the soft bit transmission may become a performance bottleneck in some cases because the time required to transmit symbol bits plus the aforementioned at least one soft bit is longer than usual. The memory device 100 (or its flash memory controller 110) can operate according to an enhanced soft decoding control scheme of this method to improve overall performance.

[0116] Figure 7 The relevant operations in the enhanced soft decoding control scheme of the method are illustrated according to an embodiment of the present invention. Figure 7 The operations of steps S10 to S13 and step S17 shown can be compared with those of... Figure 3The operation is the same (or similar) in the illustrated embodiment. When it is determined that software decoding is required, the flash memory controller 110 can control the flash memory module 120 to selectively transmit a small subset of the multiple soft bits, instead of transmitting all of the multiple soft bits, and use a predetermined indication signal IND (e.g., any signal in at least one predetermined signal between the flash memory controller 110 and the flash memory module 120) as a prompt (or alert signal) for the selective soft bit transmission to improve overall performance. To better understand, suppose “Y” can represent a positive integer greater than 1 and “y” can be an integer in the interval [0, (Y-1)]. Then the state of a group of memory cells {PS(y)|y=0,…,(Y-1)} (e.g., states PS(0), PS(1), … and PS(15), such as the 16 states PS0, PS1, … and PS15 when Y=16) can be represented by Y corresponding curves along the horizontal axis. The curves of any two adjacent states {(PS(y), PS(y+1))|y≤(Y-2)} (e.g., the first two states PS(1) and PS(2)) may partially overlap due to Gaussian noise. Since the randomizer within the randomizer and derandomizer circuit RNDRN can be appropriately designed to perform randomization operations and make the randomization result as random as possible, the probability of obtaining the bit 1 and bit 0 corresponding to the two adjacent states {(PS(y), PS(y+1))} from the first transfer of the flash memory module 120 can be 50% each, which is equal to each other. In the second transfer of soft bits, taking the cases of "strong one (1)" and "weak zero (0)" as examples, the probability of obtaining bit 1 can be much greater than the probability of obtaining bit 0. The flash memory controller 110 can control the flash memory module 120 to perform this selective soft bit transfer, in particular, to transfer any soft byte that carries any bit 0, while avoiding the transfer of any soft byte that carries only eight bits 1 and does not contain any bit 0, thereby greatly reducing the number of extra byte transfers related to soft information transfer and thus improving overall performance.

[0117] In step S24, in response to the failure to read data DATA(r) from page PAGE(r), flash memory controller 110 may send a second read command to the NV memory, such as flash memory module 120, and a controller-side indicator IND_controller associated with the selective soft bit transfer, for example, to selectively enable the selective soft bit transfer, so as to obtain the soft decoding information SDI(r) for page PAGE(r), wherein page PAGE(r) may be configured to store data DATA(r). For example, the soft decoding information SDI(r) corresponding to any bit (i) of data DATA(r) may be called soft decoding information SDI(r,i), and may include a symbol bit and at least one soft bit (e.g., one or more soft bits).

[0118] In step S25, the flash memory controller 110 receives software decoding information SDI(r) and a memory-side indication IND_memory from the NV memory, such as the flash memory module 120, for software decoding (e.g., the first software decoding operation described in step S14) based on the software decoding information SDI(r) via the decoder (e.g., the LDPC decoder) to obtain data DATA(r) from the software decoding. The memory-side indication IND_memory is used in a first cycle to indicate whether the NV memory, such as the flash memory module 120, will transmit at least one soft bit in a second cycle, and the second cycle is the cycle following the first cycle. More specifically, the second cycle may represent the next cycle after the first cycle, and the next cycle is the cycle immediately following the first cycle.

[0119] The flash memory controller 110 can receive software decoding information SDI(r) and memory-side indication IND_memory from the flash memory module 120 via a set of data signals {DQ} and the predetermined indication signal IND, respectively, wherein the set of data signals {DQ} and the predetermined indication signal IND can be configured to carry the software decoding information SDI(r) and the memory-side indication IND_memory, respectively.

[0120] When needed, such as Figure 7As shown in the lower half, step S24 can be re-entered, where the dashed arrows from step S25 to step S24 indicate the relevant loop processing. For example, in response to the failure to obtain data DATA(r) from the first software decoding operation, the flash memory controller 110 (or microprocessor 112) can re-execute the loop including steps S24 and S25 to perform more software decoding operations (e.g., the aforementioned more software decoding processing, such as the second software decoding operation in step S16) to obtain data DATA(r) from the second software decoding operation. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0121] To better understand, this enhanced software decoding control scheme is available. Figure 7 The workflow shown is illustrated, but the invention is not limited thereto. According to some embodiments, one or more steps may be performed... Figure 7 The workflow shown can be added, deleted, or modified. For example, after the memory device 100 is powered on, the flash memory controller 110 can send a read command and a controller-side instruction IND_controller to the NV memory, such as the flash memory module 120, to determine whether to enable the selective soft bit transfer in the flash memory module 120. For the sake of simplicity, similar content in these embodiments will not be repeated here.

[0122] Figure 8 Illustration based on an embodiment of the present invention Figure 7The illustrated enhanced soft decoding control scheme involves some examples of the set of data signals {DQ} and the predetermined indication signal IND. The set of data signals {DQ} may include multiple data signals {DQ} on a data bus between the flash memory controller 110 and the flash memory module 120, such as multiple data signals {DQ} corresponding to at least one byte (e.g., one or more bytes) for simultaneous transmission of multiple bits in the at least one byte. For the case where the at least one byte represents a single byte, the multiple data signals {DQ} may be implemented as data signals DQ[7:0] such as data signals {DQ[7],DQ[6],…,DQ[0]}, but the invention is not limited thereto. Assuming that “CNT_byte” can be a positive integer, for the case where the at least one byte represents CNT_byte bytes, the multiple data signals {DQ} may be implemented as data signals DQ[((CNT_byte*8)-1):0]. Furthermore, the predetermined indication signal IND can represent an other-purpose signal that was originally intended for at least one purpose different from the selective soft bit transmission. When transmission for the aforementioned at least one other purpose is not required, this other-purpose signal can be used as the predetermined indication signal IND. For example, for the aforementioned at least one other purpose, this other-purpose signal can be a data-bus inversion (DBI) signal (also referred to as the "DBI signal"), used to indicate whether the data bits on the set of data signals {DQ} (e.g., data signals DQ[7:0]) have been inverted.

[0123] As shown in sub-Figure (a), when a transmission is required for at least one of the other purposes described above (e.g., the purpose of Data Bus Inversion (DBI)), the DBI signal can be configured to transition between multiple predetermined voltage levels corresponding to different logic values ​​(such as a high voltage level corresponding to logic value 1 and a low voltage level corresponding to logic value 0) to indicate whether data bits on the data signal DQ[7:0] have been inverted for power saving (e.g., by reducing the use of high voltage levels to save power, since high voltage levels are generally more power-consuming). In addition, the byte group {D(0),D(1),D(2),D(3),D(4),D(5),D(6),…} (or “byte group {D0,D1,D2,D3,D4,D5,D6,…}”) corresponding to the data DATA(r) can be transmitted from the flash memory module 120 to the flash memory controller 110 in multiple cycles #0, #1, #2, #3, #4, #5, #6, etc.

[0124] As shown in sub-figure (b), when transmission for at least one of the other purposes described above (e.g., the purpose of data bus inversion (DBI)) is not required, the DBI signal can be configured to switch between the plurality of predetermined voltage levels corresponding to different logic values ​​(such as the high voltage level corresponding to logic value 1 and the low voltage level corresponding to logic value 0) to indicate whether there is any soft bit immediately following a current data (or symbol) bit on any of the plurality of data signals {DQ} (e.g., data signals DQ[7:0]). Furthermore, a sequence of bytes corresponding to the soft-decoded information SDI(r) {D(0),S(0),D(1),D(2),D(3),S(3),D(4),D(5),D(6),…} (or referred to as “byte sequence {D0,S0,D1,D2,D3,S3,D4,D5,D6,…}” for brevity), such as data (or symbol) bytes {D0,D1,D2,D3,D4,D5,D6,…} interleaved with soft bytes {S0,S3,…} following the corresponding data bytes {D0,D3,…}, can be transmitted from the flash memory module 120 to the flash memory controller 110 in multiple cycles #0, #1, #2, #3, #4, #5, #6, #7, #8, etc. Assuming a chunk stored in flash memory module 120 can contain 4676 bytes (e.g., a combination of 4096 data bytes and 580 parity bytes corresponding to the data and parity within the chunk, referred to as "4K580B", where (4096+580)=4676), before transmitting the soft decoding information SDI(r), flash memory module 120 can prepare and buffer (or temporarily store) the data bytes {D0,D1,…,D4675} and the soft bytes {S0,S1,…,S4675} in a data byte buffer and a soft byte buffer within flash memory module 120, respectively. Figure 3 The software decoding control scheme shown compares all bytes in the data (or symbol) byte group {D0, D1, ..., D4675} with the soft byte group {S0, S1, ..., S4675}, according to... Figure 7 The enhanced soft decoding control scheme shown transmits a small portion of the data (or symbol) bytes {D0,D1,…,D4675} and the soft bytes {S0,S1,…,S4675}, which can significantly improve overall performance.

[0125] As shown in sub-figure (c), for the case where at least one soft bit in the soft decoding information SDI(r,i) contains multiple soft bits, the corresponding byte sequence of the soft decoding information SDI(r) is {D(0),S0(0),S1(0),D(1),D(2),D(3),S0(3),S1(3),D(4),…} (or “byte sequence {D0,S00,S10,D1,D2,D3,S03,S1…}). For example, data (or symbol) bytes {D0,D1,D2,D3,D4,…} are interspersed with soft bytes {{S00,S10},{S03,S13},…} following the corresponding data bytes {D0,D3,…}. They can be transferred from the flash memory module 120 to the flash memory controller 110 in multiple cycles #0, #1, #2, #3, #4, #5, #6, #7, #8, etc.

[0126] As shown in sub-figure (d), in the special case where at least one soft bit in the soft-decoded information SDI(r,i) contains only a single soft bit, for example, due to any soft-decoding limitations controlled by the flash memory controller 110 (or microprocessor 112), the pulses of the DBI signal can be individually reduced to single-cycle pulses, which may have the same pulse width equal to a single cycle. Generally, for better flexibility in most cases, it is best to avoid such soft-decoding limitations and it is not required that the pulse widths of all pulses of the DBI signal be equal to each other. Examples of memory-side indications of IND_memory may include, but are not limited to: the rising edge of the DBI signal, a high voltage level in a cycle starting from any of the rising edges of the DBI signal, and a pulse starting from any of the rising edges of the DBI signal, regardless of whether this pulse is within a single cycle (e.g., the cycle starting from this rising edge).

[0127] According to certain embodiments, the plurality of data signals {DQ}, such as data signal DQ[7:0], soft bytes and their associated byte arrangement on data signal DQ[7:0], the curve of the DBI signal, and / or the byte count per chunk in flash memory module 120, may be varied. Furthermore, in at least one scenario related to soft decoding using this selective soft byte transmission, a data byte on data signal DQ[7:0] (e.g., one of the data byte groups {D0,D1,D2,D3,D4,D5,D6,…} in the byte sequence {D(0),S(0),D(1),D(2),D(3),S(3),D(4),D(5),D(6),…}) can be used as a sign byte, and a data bit within this data byte can be used as a sign bit.

[0128] Figure 9 An embodiment of the present invention is illustrated, by means of Figure 7 The enhanced software decoding control scheme shown improves the overall throughput of the memory device 100. The horizontal axis represents the Raw Bit Error Rate (RBER), and the vertical axis represents throughput in appointed / predetermined units (au), such as megabytes per second (MB / s), but the invention is not limited thereto. For example, the memory device 100 (or its flash memory controller 110) may have various predetermined decoding modes, including a hard decode green mode (e.g., a hard decode mode with power-saving control), a hard decode regular mode (e.g., a hard decode mode without power-saving control), and N4 software decoding modes such as the fast N4 software decoding mode (labeled "Fast N4" for simplicity). Because the flash memory controller 110 can automatically switch between the hard decode green mode and the hard decode regular mode, the hard decoding throughput 903 of these hard decoding modes can vary smoothly with changes in RBER. Figure 9 As shown in the left half, when the hardware decoding throughput 903 is greater than the host throughput 902 (e.g., the direct memory access (DMA) throughput from flash memory module 120 to flash memory controller 110, where flash memory controller 110 is considered the host of flash memory module 120), the host throughput 902 can be considered the upper limit of the overall throughput. Figure 9 As shown in the middle section, with the increase of RBER, the hardware decoding throughput 903 can be reduced to below the host throughput 902, becoming the new upper limit of the overall throughput.

[0129] against Figure 9 In the right half, before the enhanced soft decoding control scheme is applied to the memory device 100, although the fast N4 throughput 904 in fast N4 soft decoding mode may be higher than the hard decoding throughput 903, switching to fast N4 soft decoding mode does not help improve the overall throughput. This is because the inverse gate NAND flash memory throughput (referred to as "NAND throughput") 901, which transmits two bits per soft-decoding symbol by the flash memory module 120, can become another upper limit on the overall throughput. Figure 9 The right half is shown. In particular, for any of the aforementioned bits (Bit(i)) in the data DATA(r), the flash memory module 120 can transmit a two-bit symbol, such as a combination of a symbol / hard bit and a soft bit (denoted as "1 symbol 1 soft" for simplicity), while the overall throughput may be limited by the NAND throughput 901. After this enhanced soft decoding control scheme is applied to the memory device 100, the overall throughput can be improved and approach the boundary formed by the fast N4 throughput 904 and the host throughput 902 (e.g., the boundary of the lower throughput of the fast N4 throughput 904 and the host throughput 902, depending on which one is closer to the NAND throughput 901 along the vertical axis). For simplicity, similar content will not be repeated here in this embodiment.

[0130] According to certain embodiments, the curves of NAND throughput 901, host throughput 902, hardware decoding throughput 903, and fast N4 throughput 904, the respective scales of the horizontal and vertical axes, and / or the associated decoding modes may be varied.

[0131] Figure 10 Illustration based on an embodiment of the present invention Figure 7The enhanced soft decoding control scheme shown relates to the relevant decoding performance, where the horizontal axis represents RBER and the vertical axis represents the Uncorrectable Bit Error Rate (UBER). The memory device 100 (or its flash memory controller 110) can dynamically switch between multiple predetermined decoding modes, which may include a hard-decode green mode, an N2 decoding mode, an N4 soft decoding mode, an N6 soft decoding mode, and an N8 soft decoding mode (labeled "green," "N2," "DN4," "N6," and "N8," respectively, for simplicity). Assuming a block stored in flash memory module 120 may contain 4676 bytes, such as the aforementioned 4K580B, memory device 100 (or flash memory controller 110 within it) may be designed to keep the UBER at the lowest possible level, in particular, to keep the UBER within a range not exceeding a target UBER, such as 0.000000001% (i.e., 1*10⁻¹¹, or written in E notation as “1E-11”). The curves for hard decoding green mode and N2 decoding mode indicate that these two decoding modes can guarantee successful decoding in narrower ranges of RBER, such as a first range [0, 0.007] and a second range [0, 0.0075] with relatively low upper limits, but if the RBER becomes higher, successful decoding cannot be guaranteed. Furthermore, for the same target UBER, such as 0.000000001%, the curves for N4, N6, and N8 soft decoding modes show that these three decoding modes can guarantee successful decoding within a wider range of RBER, such as the third interval [0, 0.015], the fourth interval [0, 0.0183], and the fifth interval [0, 0.0186], which respectively have relatively high upper limits. Since the N4 soft decoding mode offers significantly better capabilities than the previous two decoding modes, it can be used in environments unaffected by... Figure 9 The memory device 100 (or its flash memory controller 110) that dynamically switches to N4 soft decoding mode when the NAND throughput 901 shown is limited can significantly improve the overall decoding capability. For the sake of simplicity, similar content will not be repeated here in this embodiment.

[0132] According to certain embodiments, the curves, scales of the horizontal and vertical axes, and / or the byte counts in the flash memory module 120 for each block of the hard decoding green mode, N2 decoding mode, N4 soft decoding mode, N6 soft decoding mode, and N8 soft decoding mode can be varied.

[0133] Figure 11 Illustration based on an embodiment of the present invention Figure 7The enhanced soft decoding control scheme shown involves a series of histograms within a pre-established database (e.g., histograms corresponding to RBER = 0.8%, RBER = 0.9%, ..., and RBER = 1.6%, respectively). Based on this pre-established database, any one of these histograms (e.g., the histogram indexed by RBER) indicates a normal (or Gaussian) distribution of the zeros count for the second data transmission of soft bits in N4 soft decoding mode, where the horizontal axis can represent the zeros count, such as the bit 0 count, with each step size being ten (10), and the vertical axis can represent a percentage. Figure 8 Taking the byte sequence {D0,S0,D1,D2,D3,S3,D4,D5,D6,…} shown in subgraph (b) as an example, the transmission of any bit within a soft byte (e.g., the soft byte {S0,S3,…} that follows the corresponding data byte {D0,D3,…}) can be regarded as a second data transmission.

[0134] Given an RBER, any of the histograms in this series can indicate a corresponding zero count by the mean (or expected value) of its distribution. For example, assuming a block stored in flash memory module 120 may contain 4676 bytes, such as the 4K580B mentioned above, the histogram corresponding to RBER = 0.8% indicates that when RBER is 0.8%, the expected zero count is 1000, and these 1000 bits of 0 (e.g., zero-bits, all equal to zero) can randomly fall into (or be distributed among) some of the 4676 soft bytes {S0, S1, ..., S4675} buffered in the soft byte buffer of flash memory module 120, just as 1000 balls can randomly fall into some of the 4676 baskets. Since most bits in the 4676 buffered soft bytes {S0, S1, ..., S4675} are 1 (e.g., one-bits, all equal to 1), the flash memory controller 110 can carry a controller-side indication IND_controller in the second read command. Specifically, transmitting this second read command carrying the controller-side indication IND_controller enables the selective soft bit transfer in the flash memory module 120, allowing the flash memory module 120 to perform the selective soft bit transfer. During the selective soft bit transfer, the flash memory module 120 can detect or check whether any of the 4676 buffered soft bytes {S0, S1, ..., S4675} contains at least one 0 bit. If any of the soft bytes in the 4676 buffered soft bytes {S0, S1, ..., S4675} contains any bit 0, then the flash memory module 120 may transfer this soft byte (e.g., one of the soft bytes {S0, S3, ...}); otherwise, if any of the soft bytes in the 4676 buffered soft bytes {S0, S1, ..., S4675} does not contain bit 0, the flash memory module 120 may avoid transferring this soft byte.

[0135] Table 1

[0136] RBER Strong (1) weak(0) 0.8％ 97.377％ 2.623％ 0.9％ 97.113％ 2.887％ 1.0％ 96.855％ 3.145％ 1.1％ 96.597％ 3.403％ 1.2％ 96.349％ 3.651％ 1.3％ 96.108％ 3.892％ 1.4％ 95.872％ 4.128％ 1.5％ 95.640％ 4.360％ 1.6％ 95.412％ 4.588％

[0137] Table 1 shows examples of the percentages of strong one (or "strong (1)") and weak zero (or "weak (0)") relative to the change in BER within the pre-established database. Since most bits in the 4676-buffered soft byte {S0,S1,...,S4675} are bits 1, the flash memory controller 110 can control the flash memory module 120 to perform this selective soft byte transfer, for example, by transferring only a small subset of the aforementioned soft bytes in the soft byte {S0,S1,...,S4675}, such as the soft bytes {S0,S3,...} in the byte sequence {D0,S0,D1,D2,D3,S3,D4,D5,D6,...}, instead of transferring all the soft bytes in the soft byte {S0,S1,...,S4675}.

[0138] According to certain embodiments, the pre-established database, the histogram of the series, the respective percentages of strong (1) and weak (0) relative to BER, and / or the relevant range of RBER may be varied.

[0139] Figure 12 Illustration based on an embodiment of the present invention Figure 7 The enhanced soft decoding control scheme shown involves relevant statistical data within a pre-established database, which may include the number of additional bytes used for soft information and the additional-bytes to chunk-bytes ratio. For example, assuming a chunk stored in flash memory module 120 may contain 4676 bytes, such as the aforementioned 4K580B, then the number of additional bytes used for soft information may have a positive correlation with the zero count, as shown in trend 1201. For the case of RBER = 0.8%, when the zero count is 1000, the number of additional bytes used for soft information may be equal to 900, and the additional-bytes to chunk-bytes ratio is (900 / 4676) = 0.19247219846… (denoted as “0.192472198” for brevity), as shown in reference line 1202. Overall throughput can be significantly improved with RBER = 0.8%, especially from Figure 9 The NAND throughput 901 shown (e.g., 50% of the host throughput 902) increases to (1 / (1+0.19247219846…)) of the host throughput 902, which is approximately 83.86% of the host throughput 902.

[0140] According to some embodiments, the number of additional bytes used for soft information, the ratio of additional bytes to block bytes, the relevant range of zero counts, and / or the relevant range of RBER can be varied. Furthermore, at least a portion (e.g., some or all) of this pre-built database can be integrated into the memory device 100, particularly into any storage cell (or any memory) of the flash memory controller 110 or flash memory module 120, and the flash memory controller 110 can use this pre-built database as a reference to determine whether to enable the selective soft byte transfer in the flash memory module 120.

[0141] Figure 13 Illustration based on an embodiment of the present invention Figure 7 The enhanced software decoding control scheme illustrated involves further statistical data within the pre-established database, where the horizontal axis represents the percentage of zeros (0; e.g., zero bits) in the data (e.g., a data chunk containing 4676 bytes, such as the 4K580B mentioned above, i.e., a total of 37408 bits), expressed as a percentage (%), and the vertical axis represents the compression length, expressed in bits. For example, one or more conventional data compression control schemes for data compression, such as a bit-level run-length encoding (RLE) control scheme and a position-based control scheme, may require additional compression and decompression circuitry / engines to be implemented in the flash memory module 120 and flash memory controller 110, respectively, and may also require a new and complex communication protocol for transmitting the corresponding compressed data. The associated compression ratio can be obtained by dividing the compression length by the bit count of the data chunk (e.g., 37408), and for trend 1301 corresponding to conventional data compression control schemes, it can vary from 17% to 26.7%. Since trend 1302 corresponding to this enhanced soft decoding control scheme is very close to trend 1301 corresponding to the conventional data compression control scheme, and since this enhanced soft decoding control scheme does not require additional compression and decompression circuits / engines, new and complex communication protocols, etc., as in the conventional data compression control scheme, it is superior to the conventional data compression control scheme. Therefore, the method and related devices of the present invention, such as memory device 100 and flash memory controller 110, can indeed solve the problems of the related art without introducing side effects or in a way that is unlikely to introduce side effects.

[0142] Figure 14 An embodiment of the present invention is illustrated for... Figure 7The following is a scenario and related implementation details of the enhanced soft decoding control scheme. As shown in sub-Figure (a), taking the separate command and address format of this read command (CMD) 1401 (labeled as "Read CMD" for brevity) as an example, when reading data from the flash memory module 120, the flash memory controller 110 can transmit the read command 1401. In particular, using related control signals such as the Command Latch Enable (CLE) signal CLE (also referred to as the "CLE signal") and the Address Latch Enable (ALE) signal ALE (also referred to as the "ALE signal"), the read operation command READ and the address {Addr} to be latched on the input / output (I / O) terminals (e.g., I / O terminals used to transmit the plurality of data signals {DQ} such as data signals DQ[7:0] during data transmission). In addition to the original command elements such as the read operation command READ and the address {Addr} (e.g., block address Addr_BLK and page address Addr_PG), the read command 1401 may also include a new command element, such as read stress R_stress, to indicate any of the multiple stress levels for the read. For example, these stress levels may include low stress, medium stress, and high stress (or simply "low," "medium," and "high"), for fast reads with a first target RBER, such as high RBER; normal reads with a second target RBER, such as normal RBER; and combined soft reads based on the enhanced soft decoding control scheme (to obtain symbol bits and soft bits from the flash memory module 120). The read busy time (or "tR") can be normal or typical for medium stress conditions; while for low stress and high stress conditions, the read busy time can be shorter and longer, respectively. For ease of understanding, the read pressure R_stress can be represented as being latched on the I / O terminal when both the CLE and ALE signals are pulled high, but the invention is not limited thereto.According to some embodiments, another control signal, such as a Read-stress Latch Enable (RLE) signal dedicated to reading the pressure R_stress, can be illustrated as having a pulse in this cycle of the reading pressure R_stress, the pulse indicating that the reading pressure R_stress should be latched during the pulse, while the CLE and ALE signals can be illustrated as being preset to remain low during this cycle.

[0143] As shown in sub-figure (b), after the flash memory controller 110 transmits the read command 1401, the flash memory module 120 can enter a read busy state, as indicated by the busy signal BZ being at its high level. The flash memory controller 110 can poll the flash memory module 120 through the pulses of the polling signal to obtain the latest status of the flash memory module 120, such as any of the statuses of read completed and read in progress. The completion status can contain any of the multiple sub-states, such as: a pass status with a good reading result (labeled "Pass, w / Good result" for brevity), meaning no errors or only a few errors (e.g., errors that have been corrected); a pass status with a poor reading result (labeled "Pass, w / Poor result" for brevity), meaning a certain number of errors exist; and a failure status with a catastrophic reading result (labeled "Fail, Catastrophic" for brevity), meaning a large number of errors exist. Furthermore, after the busy signal BZ transitions to its low level, the flash memory controller 110 can begin DMA operations on the flash memory module 120 in a DMA phase.

[0144] As shown in sub-Figure (c), during the DMA phase, when the latest Status of flash memory module 120 is detected as complete, flash memory controller 110 can perform DMA operation on flash memory module 120 (specifically its internal buffers, which may include the data byte buffer and the soft byte buffer) by using DMA command 1402 plus Toggle Data operation 1403 (labeled as "DMA-CMD" and "Toggle Data" for brevity, respectively) to obtain data from flash memory module 120 through the plurality of data signals {DQ} (e.g., data signals DQ[7:0]) on the data bus. Furthermore, the plurality of command elements of DMA command 1402 may include a first command element, such as a Random Data Out (Random Out) operation command, a second command element, such as a Start Byte, and may also include a third command element, such as an index for a DMA type, to indicate any one of the plurality of predetermined DMA types. For example, the plurality of predetermined DMA types may include type #1 and type #2 corresponding to disabling the selective soft bit transfer in the NV memory, and type #3 corresponding to enabling the selective soft bit transfer in the NV memory, as follows:

[0145] (Type #1) Traditional DMA: DMA that does not enable data bus inversion, for example, does not use the DBI signal, and the data bits on the data signals DQ[7:0] are not inverted;

[0146] (Type #2) Data-Bus Inversion DMA (DBI-DMA): A DMA that enables data bus reversal, where the DBI signal is used to specify the byte group to be bitwise reversal so that this byte group has more zeros, and the data bits on the data signal DQ[7:0] can be selectively reversed as indicated by the DBI signal. For example, a high voltage level of the DBI signal indicates that the data bits on the data signal DQ[7:0] have been reversed, while a low voltage level of the DBI signal indicates that the data bits on the data signal DQ[7:0] have not been reversed; and

[0147] (Type #3) Data-Bus Inversion as Soft-Indicator / Indication DMA (abbreviated as "DBI as Soft-IND DMA"): The DBI signal is used as a soft-indicator DMA, where a predetermined indicator signal IND, such as the DBI signal, can be used to indicate whether any of the aforementioned soft bits immediately following the current data (or symbol) bit exists on any of the aforementioned data signals {DQ} (e.g., data signals DQ[7:0]), for example, as... Figure 8 As described in the illustrated embodiments;

[0148] The controller-side indication IND_controller can be implemented through the index carried by DMA command 1402.

[0149] When needed, after the memory device 100 is powered on, the flash memory controller 110 can send an after-power-up read command (or an immediate-after-power-up read command, i.e., a read command sent immediately after power-on) to the flash memory module 120, such as a read command 1401 carrying a read pressure R_stress, to determine whether to enable the selective soft bit transfer in the flash memory module 120. For example, the read pressure R_stress can be set to the high pressure, rather than the low pressure or the medium pressure. The flash memory controller 110 can perform at least one polling operation on the flash memory module 120 by at least one pulse of the polling signal to obtain the latest status of the flash memory module 120, and determine whether to enable the selective soft bit transfer in the flash memory module 120 based on the latest status. Regarding the index carried in DMA command 1402, if the latest state of flash memory module 120 is "good read result pass state", flash memory controller 110 can set the index to indicate type #1 or type #2 for conventional DMA or the DBI-DMA; and if the latest state of flash memory module 120 is "poor read result pass state", flash memory controller 110 can set the index to indicate type #3 for the DBI as Soft-IND DMA, specifying the DBI signal for soft bit transfer. During the DBI as Soft-IND DMA, flash memory controller 110 can apply 1-sign, 1-soft arrangement soft bit DMA, in particular, using DBI bits (e.g., bits indicated by the DBI signal) to specify that after a current data (or sign) byte on the data signal DQ[7:0], the next byte is its soft information (or soft byte), for example, as Figure 8 As shown. This still allows the byte count to be correctly known as the data transfer length. Assuming a block stored in flash memory module 120 may contain 4676 bytes, such as the 4K580B mentioned above, then flash memory controller 110 can count data (or symbol) bytes D0 to D4675.

[0150] According to some embodiments, the flash memory controller 110 may transmit at least one read command to the NV memory, such as the flash memory module 120, for example, the second read command mentioned in step S24 or the power-on read command, and a controller-side indication IND_controller for obtaining software decoding information SDI (e.g., software decoding information SDI(r) mentioned in step S24, or any software decoding information SDI for any page within any of the plurality of blocks), and receive software decoding information SDI and a memory-side indication IND_memory from the NV memory, such as the flash memory module 120, for software decoding based on the software decoding information SDI through the decoder (e.g., the LDPC decoder) to obtain data DATA from the software decoding (e.g., data DATA(r) mentioned in step S25, or any data DATA stored in any of the aforementioned pages). Furthermore, any of the above at least one read command may be implemented using read command 1401 to include the plurality of command elements such as a read operation command READ, at least one address Addr such as address {Addr}, and read pressure R_stress. For the sake of brevity, similar content in these embodiments will not be repeated here.

[0151] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. A method for data protection control of a memory device using selective soft-bit transmission, the method being adapted to a memory controller of the memory device, the memory device including the memory controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the method comprising: At least one read command and a controller-side indication are transmitted to the non-volatile memory. The controller-side indication selectively enables selective soft bit transfer in the non-volatile memory to obtain soft-decoding information for a first page within a first block of the plurality of blocks, wherein the first page stores first data. The software decoding information and a memory-side indication are received from the non-volatile memory for software decoding to obtain the first data based on the software decoding information. The memory-side indication is used in a first cycle to indicate whether the non-volatile memory will transmit at least one soft bit in a second cycle, and the second cycle is a cycle following the first cycle.

2. The method as described in claim 1, characterized in that, The at least one read command includes a second read command; and the method further includes: Receive a first host read command from a host device, wherein the first host read command instructs the reading of the first data at a first logical address; and In response to the first host read command, a first read command is transmitted to the non-volatile memory to attempt to read the first data from the first page according to a first physical address associated with the first logical address, wherein the first physical address points to the first page within the first block, and reading the first data from the first page is unsuccessful; In response to the failure to read the first data from the first page, the second read command is sent to the non-volatile memory.

3. The method as described in claim 2, characterized in that, Also includes: In response to the first host read command, the first logical address is mapped according to at least one logical-to-physical (L2P) address mapping table to obtain the first physical address associated with the first logical address. The at least one logical-to-physical address mapping table contains mapping relationships between multiple logical addresses and multiple physical addresses. The first logical address is one of the multiple logical addresses, and the first physical address is one of the multiple physical addresses.

4. The method as described in claim 1, characterized in that, The at least one read command is included in an after-power-up read command transmitted to the non-volatile memory after the memory device is powered on.

5. The method as described in claim 4, characterized in that, After the memory device is powered on, the memory controller is configured to send the power-on read command to the non-volatile memory to determine whether to enable the selective soft bit transfer in the non-volatile memory.

6. The method as described in claim 5, characterized in that, The power-on read command includes a read stress indicating any one of a plurality of stress levels for reading, which includes at least low stress and high stress, and the read stress is set to the high stress, rather than the low stress; and the memory controller is configured to perform at least one polling operation on the non-volatile memory to obtain the latest state of the non-volatile memory, and to determine whether to enable the selective soft bit transfer on the non-volatile memory based on the latest state.

7. The method as described in claim 1, characterized in that, Any of the at least one read command includes multiple command elements, and the multiple command elements include an operating command and at least one address, and further include a read stress to indicate any one of multiple stress levels for reading.

8. The method as described in claim 7, characterized in that, These multiple pressure levels include at least low pressure and high pressure.

9. The method as described in claim 1, characterized in that, The memory controller is configured to transmit a direct memory access (DMA) command, and the DMA command includes a plurality of command elements that include an index to indicate any one of a plurality of predetermined DMA types, wherein the controller-side indication is implemented through the index carried by the DMA command.

10. The method as described in claim 9, characterized in that, The plurality of predetermined direct memory access types include one or more types corresponding to disabling the selective soft bit transfer in the non-volatile memory, and further include another type corresponding to enabling the selective soft bit transfer in the non-volatile memory.

11. The method as described in claim 1, characterized in that, For any bit in the first data, the soft decoding information corresponding to that bit includes a sign bit and at least one soft bit.

12. The method as described in claim 1, characterized in that, The second cycle represents the next cycle after the first cycle, and the next cycle is the cycle that immediately follows the first cycle.

13. The method as described in claim 1, characterized in that, Receiving the software decoding information from the non-volatile memory and the memory-side indication further includes: The software decoding information and the memory-side indication are received from the non-volatile memory via a set of data signals and a predetermined indication signal, respectively, wherein the set of data signals and the predetermined indication signal are used to carry the software decoding information and the memory-side indication, respectively.

14. The method as described in claim 13, characterized in that, The data signal set includes multiple data signals corresponding to at least one byte group, for the simultaneous transmission of multiple bits in the at least one byte group.

15. The method as described in claim 13, characterized in that, The predetermined indication signal represents an other-purpose signal that was originally intended for at least one other purpose different from the purpose of the selective soft bit transmission; and when the transmission for the at least one other purpose is not required, the other-purpose signal is used as the predetermined indication signal.

16. The method as described in claim 15, characterized in that, For at least one other purpose, the signal is a data-bus inversion (DBI) signal used to indicate whether data bits on the set of data signals have been inverted.

17. A memory controller for performing data protection control of a memory device by means of selective soft-bit transmission, the memory device including the memory controller and a non-volatile (NV) memory, the non-volatile memory including at least one non-volatile memory element, the at least one non-volatile memory element including a plurality of blocks, the memory controller comprising: A processing circuit is used to control the memory controller according to a plurality of host commands from a host device, so as to allow the host device to access the non-volatile memory through the memory controller. in: The memory controller is configured to transmit at least one read command and a controller-side indication to the non-volatile memory, the controller-side indication being used to selectively enable the selective soft bit transfer in the non-volatile memory to obtain soft-decoding information for a first page in a first block of the plurality of blocks, wherein the first page is used to store first data; as well as The memory controller is configured to receive the soft decoding information and a memory-side indication from the non-volatile memory for soft decoding based on the soft decoding information to obtain the first data from the soft decoding, wherein the memory-side indication is used in a first cycle to indicate whether the non-volatile memory will transmit at least one soft bit in a second cycle, and the second cycle is a cycle following the first cycle.

18. A memory device comprising the memory controller of claim 17, wherein the memory device comprises: This non-volatile memory is used to store information; and The memory controller, coupled to the non-volatile memory, is used to control the operation of the memory device.

19. An electronic device comprising the memory device as claimed in claim 18, wherein the electronic device further comprises: The host device is coupled to the memory device, wherein the host device includes: At least one processor is used to control the operation of the host device; and A power supply circuit, coupled to the at least one processor, is used to provide power to the at least one processor and the memory device; The memory device provides storage space to the host device.

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