Multi-modal model fine-tuning EDA circuit block diagram analysis and evaluation method and system

Abstract

The invention relates to a circuit block diagram analysis technology in the field of electronic design automation (EDA), and provides an EDA circuit block diagram analysis and evaluation method and system for multi-modal model fine tuning aiming at the problems of text and visual information splitting, scarcity of professional data in the field of EDA, weak model generalization ability and lack of a standardized evaluation system in the prior art. By constructing a special topology and logic data set in the EDA field, adopting an LORA fine-tuning optimization Qwen2.5-VL-3B model and establishing a multi-dimensional quantitative evaluation system fusing IoU and F1 scores, accurate analysis of circuit block diagram component extraction, port identification and connection relation reasoning is realized, the analysis efficiency is improved by more than 300 times compared with manual analysis, and the method has the advantages that the method is simple and convenient to operate, and the method is suitable for large-scale popularization and application. And the structured JSON output is more beneficial to follow-up automatic adaptation of an EDA design tool, the follow-up application threshold is remarkably reduced, and efficient and accurate technical support is provided for EDA design iteration.

Description

Technical Field

[0001] This invention relates to the intersection of electronic design automation and artificial intelligence multimodal technology, specifically to an EDA circuit block diagram analysis and evaluation method and system based on a lightweight fine-tuning multimodal model. Background Technology

[0002] With the rapid development of EDA technology, circuit system block diagrams now account for more than 30% of academic papers, technical reports, and patent documents in the field of electronic engineering. These block diagrams are not simply auxiliary illustrations, but key carriers of core system-level information such as module interconnection relationships, timing control logic, and performance constraints. Their efficient and accurate analysis is of great significance for EDA design iteration and the reuse of technical documents.

[0003] Currently, parsing such multimodal documents mainly relies on two types of technologies: one is the large language model, which can only process text information and cannot recognize the visual logical relationships in the block diagram, making it difficult to understand the spatial location and connection structure of components; the other is the pure visual model, which can detect basic elements such as rectangles and lines in images, but lacks professional semantic understanding capabilities in the EDA field, cannot accurately identify the functions of professional components such as "processor core" and "DAC module", and cannot infer the signal flow connection relationship between components, resulting in a serious separation of text and image information.

[0004] Meanwhile, manual analysis remains an important method for EDA circuit block diagram analysis, but it has significant drawbacks: manual analysis of a single block diagram takes an average of 15-20 minutes, which is extremely inefficient; moreover, the professional threshold in the EDA field is high, and manual analysis is prone to subjective errors such as component naming deviations and misjudgments of connection relationships, making it difficult to meet the dual requirements of efficiency and accuracy for design iteration.

[0005] The shortcomings of existing technologies are mainly reflected in three aspects:

[0006] 1. Data level: Open-source multimodal documentation is scarce in the EDA field. There is an extreme lack of professional annotation data for component functions, port attributes, and connection relationships in circuit block diagrams. Manual annotation requires high-level domain knowledge, resulting in high annotation costs and low efficiency.

[0007] 2. Model level: Existing large-modal models have weak generalization ability. In specific scenarios in the EDA field (such as analog circuit block diagrams and signal flow analysis), the accuracy of component identification is low and the error rate of connection relationship inference is high, which cannot meet the needs of professional analysis.

[0008] 3. Evaluation level: There is a lack of quantitative evaluation system adapted to EDA block diagram analysis. Existing evaluation methods are difficult to accurately measure the comprehensive performance of multiple stages such as component positioning, function identification, and logical reasoning, and cannot provide effective guidance for model optimization.

[0009] Therefore, there is an urgent need for a technical solution that can solve the above-mentioned technical problems and achieve efficient and accurate analysis of EDA circuit block diagrams. Summary of the Invention

[0010] To address the above problems, this invention provides an EDA circuit block diagram analysis and evaluation method and system for multimodal model fine-tuning. It aims to solve the problems of fragmented textual and graphical information, scarcity of professional data, weak model generalization ability, and lack of evaluation system in existing EDA circuit block diagram analysis technology. It achieves efficient and accurate analysis of circuit block diagram component extraction, port identification, and connection relationship reasoning, and establishes a standardized performance evaluation system.

[0011] To achieve the above objectives, this invention provides a method and system for analytical evaluation of EDA circuit block diagrams for multimodal model fine-tuning, the specific technical solution of which is as follows:

[0012] 1. Construction of EDA-specific datasets

[0013] Topology Dataset Construction: 1000 circuit system block diagrams covering sub-scenarios such as communication circuits, analog circuits, and digital circuits were collected from academic papers, technical reports, and patent documents in the field of electronic engineering. Twenty block diagrams were selected for precise manual annotation, including component names, location coordinates, number of input / output ports, and connection relationships, serving as the test set. The remaining 980 unannotated block diagrams underwent preliminary pseudo-annotation generation using Qwen2.5-VL-3B, followed by manual refinement to improve the pseudo-annotation quality, serving as the training set. Considering the characteristic of the Qwen2.5-VL-3B model reading images in 28×28 patches, coordinate optimization was performed using a Python script. First, the model reset image logic was calculated, then the component coordinates were scaled proportionally to ensure the coordinate format adapted to the model input. Specifically, the calculation of the model reset image logic satisfies… , , , The original block diagram width and height, It is a rounding function. Set the target width of the image after model reset. The target height of the image after model reset; component coordinates are being proportionally transformed. The scaling factor is the width. The scaling factor in the height direction is calculated using the following formula: .

[0014] Logical Dataset Construction: Drawing inspiration from knowledge distillation methods, a question-and-answer dataset of over 300,000 characters in the EDA domain was constructed using large language models (such as chat-gpt and deepseek). The distilled dataset was cross-validated using multiple large models to ensure data accuracy. A dataset quality assessment mechanism was established to remove overly simplistic question-and-answer pairs and eliminate duplicate question types through fuzzy search. After cleaning, a logical training set that is image-related, of moderate difficulty, and diverse in question types was obtained to improve the model's semantic understanding capabilities.

[0015] 2. Lightweight model fine-tuning

[0016] LORA fine-tuning principle: Low-rank adaptation (LoRA) technique is used to introduce two smaller-dimensional matrices next to the original parameter matrix of the Qwen2.5-VL-3B basic model. and During training, the original matrix is ​​frozen, and only the matrix is ​​updated. and The parameters are then used to update the final model weights. (in (This is the original parameter matrix), which significantly reduces training overhead while ensuring model performance.

[0017] Fine-tuning parameter configuration: Freeze the parameters of the Qwen2.5-VL-3B base model, train only the LORA module, and set the rank of the low-rank matrix. Scaling factor Random inactivation rate .

[0018] Phased training strategy: A two-stage training approach is adopted to gradually improve the model's domain adaptability.

[0019] The first phase is the topology data training phase. Using labeled samples from the topology dataset as training data, a LoRA module is trained. The training objective is to improve the model's ability to extract circuit components and infer connectivity relationships. The training parameters are set as follows: epoch=8 (epoch refers to the training cycle that completes one traversal of the training dataset, used to measure the number of training iterations), and learning rate... Batch size = 16, and the optimizer used is AdamW;

[0020] The second stage is the logical data fusion training stage. The logical dataset is used as training data to train another LoRA module. The training objective is to improve the model's semantic understanding of EDA domain knowledge and strengthen the associative reasoning between component functions and connection logic. The training parameters are set as follows: epoch=3 (epoch is defined as before; different parameter values ​​are set for the two stages because the first stage requires more iterations to improve basic visual task capabilities, while the second stage only requires a small number of iterations to fuse semantic knowledge, avoiding overfitting), and learning rate. Batch size = 16, optimizer still uses AdamW.

[0021] In the first phase of training, an early stopping strategy is adopted, using the F1 score extracted from the test set components as the monitoring metric. When the metric does not improve for three consecutive epochs, training is stopped, and the optimal weights of the two LoRA modules are saved. When needed, the two LoRA modules are inserted separately into the base model.

[0022] 3. Multi-dimensional performance evaluation

[0023] Component extraction scoring Overall location matching score Name matching rating The calculation formula is: .in, For position matching F1 score, based on (Number of samples with an IoU ≥ 0.5 between the scaled component box and the truth box) and get, To improve location matching accuracy, For location-matched recall, The general formula for fractions is ; To match names to F1 scores, component name similarity is calculated using text edit distance or word vectors, based on the number of samples with similarity exceeding a threshold (set to 0.9 in this embodiment). calculate and get, To improve name matching accuracy, For name matching recall.

[0024] Port Quantity Identification Scoring The number of components based on whether both the input and output ports are correctly matched. ,calculate and Using the F1 score formula get ;in The total number of actual components in the labeled data is calculated by subtracting the number of components whose input and output ports both match correctly. The total number of components identified by the model is minus the number of components whose input and output ports are both correctly matched. To improve the accuracy of port number identification, Identify recall based on port count.

[0025] Connection relationship extraction scoring : Based on the connection relationship that is completely consistent with the truth value, the quantity ,calculate and Using the F1 score formula get ;in The total number of true connection pairs in the labeled data is minus the number of correctly matched connection pairs. Subtract the number of correctly matched connection pairs from the total number of connection pairs generated by the model. To improve the accuracy of connection relationship extraction, Extract recall for connection relationships.

[0026] To avoid confusion, the definitions of TP, FP, and FN for each dimension are clarified here:

[0027] Location matching dimension: (Number of component location samples with IoU ≥ 0.5) (The total number of component locations that actually exist in the labeled data but were not correctly identified by the model) (Total number of fake component locations generated by the model);

[0028] Name matching dimensions: (Number of samples with name similarity exceeding the threshold) (The total number of real component names in the labeled data minus the number of samples with correct name matches) (Total number of component names generated by the model minus the number of samples with correct name matches);

[0029] Port identification dimensions: (The number of input and output ports matches the correct number of components.) (The total number of actual components in the labeled data minus the number of components with correct port matching) (The total number of components identified by the model minus the number of components that correctly matched the port);

[0030] Connection relationship dimension: (The number of join pairs that are exactly the same as the truth value) (The total number of true connection pairs in the labeled data minus the number of correctly matched connection pairs) (The total number of connection pairs generated by the model minus the number of correctly matched relationship pairs).

[0031] Result normalization: Min-Max normalization was used to normalize the results. , , Mapping to the [0,1] interval, the normalization formula is: ,in The normalized value. The original fractions to be normalized, This is the original set of scores, which facilitates a comprehensive comparison of model performance.

[0032] 4. Structured Result Output

[0033] The model parsing results are converted into JSON format, which includes fields such as "Component" (component name), "Pos" (relative coordinates), "I_O" (number of input / output ports), and "Connection" (connection relationship between components). This facilitates adaptation to EDA design tools and makes subsequent design verification and reuse easier.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] 1. Significant Dataset Optimization Results: By employing a hybrid strategy of "manual annotation + pseudo-annotation correction," the utilization rate of model training data was increased by 49 times with only 20 precisely labeled datasets. After coordinate optimization, the component location IoU matching success rate increased from nearly 0 in the original dataset to 97.8%, effectively solving the problem of scarce labeled data in the EDA field.

[0036] 2. Excellent model analytical performance: After fine-tuning with LORA, the model performs outstandingly in EDA circuit block diagram analysis tasks, with high component extraction scores. (97.8% of samples were location-matched, and the name-matching accuracy was 99.5%), port recognition score. Connection relationship extraction scoring Its overall performance is significantly improved compared to the Qwen2.5-VL-3B basic version.

[0037] 3. Standardized Evaluation System: A multi-dimensional quantitative evaluation system integrating IoU and F1 score has been established, which can accurately measure the performance of each link such as component positioning, function identification, and logical reasoning, avoid subjective evaluation bias, and provide a unified performance comparison benchmark for circuit block diagram analysis models in the EDA field.

[0038] 4. Significantly improved efficiency: The model takes less than 30 seconds to parse a single circuit block diagram, which is more than 300 times more efficient than manual parsing (15-20 minutes / page); the JSON structured output can be directly adapted to EDA design tools, significantly reducing the time cost of subsequent design verification. Attached Figure Description

[0039] Figure 1 The EDA circuit block diagram analysis system's overall architecture diagram shows the composition and collaborative relationship of the dataset construction module, model fine-tuning module, performance evaluation module, and result output module.

[0040] Figure 2The dataset optimization flowchart clarifies the complete steps of topological dataset collection, annotation, pseudo-annotation generation, manual calibration, and coordinate optimization.

[0041] Figure 3 The diagram illustrates the IoU calculation, visually representing the intersection of the component's bounding box and the truth box, the area calculation logic, and the derivation of the IoU formula. , The coordinates of the top-left corner of the component's bounding box. , The coordinates of the bottom right corner of the component's bounding box. , The coordinates of the top left corner of the truth box. , The coordinates of the bottom right corner of the truth box;

[0042] Figure 4 The JSON output format example diagram illustrates the structured output specification that includes fields such as "Component", "Pos", "I_O", and "Connection".

[0043] Figure 5 : Output a JSON visualization, presenting the structured results in a visual form, making it easy to intuitively view the component distribution, port information, and connection relationships;

[0044] Figure 6 The diagram illustrates the principle of LORA fine-tuning, showing the introduction of a low-rank matrix alongside the original parameter matrix of the base model. and The fine-tuning principle and model weight update logic. Detailed Implementation

[0045] To enable those skilled in the art to better understand the technical solution, the present invention will be described in detail below with reference to embodiments. The description in this part is only exemplary and explanatory, and should not be used to limit the scope of protection of the present invention in any way.

[0046] (a) Data preprocessing implementation

[0047] 1. Data Collection: Obtain 1000 circuit block diagrams from academic papers, technical reports, and patent documents in the field of electronic engineering. Convert them to PNG format and adjust the image resolution to 784×784 or lower to balance image clarity and model training efficiency.

[0048] 2. Manual Annotation: Professionals with advanced EDA knowledge were organized to accurately annotate 20 block diagrams. Annotations included: component names (e.g., "processor core," "DAC module"), coordinates (using relative values ​​of left x, top y, right x, bottom y), number of input / output ports, and connection relationships between components. The annotation results underwent two rounds of cross-validation to ensure no annotation errors.

[0049] 3. Pseudo-label generation and calibration: The Qwen2.5-VL-3B model was used to generate preliminary pseudo-labels for the remaining 980 unlabeled bounding boxes. EDA engineers were invited to correct the pseudo-label results, focusing on correcting incorrect component names, coordinate deviations, and misjudgments of connection relationships. The corrected dataset was then merged with the 20 manually labeled test images to form a complete training set. The complete workflow for this step can be found in the appendix. Figure 2 (Dataset optimization flowchart), attached Figure 2 It clearly presents the entire chain logic of topological datasets, from collection, annotation, pseudo-annotation generation to manual calibration and subsequent coordinate optimization.

[0050] 4. Coordinate Optimization Execution: Coordinate optimization is implemented using a Python script, specifically by using the OpenCV library to read the width of the bounding box. and height Using the NumPy library to perform coordinate scaling calculations, first, according to the formula... , Calculate the target image size ( For target width, (Target height), then scale according to the scaling ratio. (width direction) (Height direction) Component coordinates are adjusted proportionally to ensure compatibility with the 28×28-patch reading logic of the model; component coordinate scaling is performed in batches using NumPy matrix multiplication operations to improve computational efficiency. For the position matching determination of component bounding boxes and truth boxes in this step, please refer to the appendix. Figure 3 (IoU calculation diagram), attached Figure 3 It intuitively presents the intersection region, area calculation logic, and IoU formula derivation process, which helps to judge the position matching accuracy after coordinate optimization.

[0051] (II) Implementation of Model Fine-tuning

[0052] 1. Environment configuration: Set up a training environment including GPU (≥16GB VRAM), Python 3.8+, PyTorch 1.18+, and install relevant dependency libraries such as Qwen-vl-utils, transformers, and peft.

[0053] 2. Model Loading and Parameter Setting: Load the Qwen2.5-VL-3B basic model and freeze all its parameters; configure LORA fine-tuning parameters: set the rank of the low-rank matrix. Scaling factor Random inactivation rate The optimizer chosen is AdamW. The principles behind LORA fine-tuning in this step can be found in the appendix. Figure 6 (LORA fine-tuning principle diagram), attached Figure 6 The original parameter matrix of the basic model is clearly displayed. Introducing a low-rank matrix and The core logic and model weights The update mechanism.

[0054] 3. Phased Training Execution: A two-stage training approach is adopted to gradually improve the model's domain adaptability.

[0055] 4. The first stage is the topology data training stage. Labeled samples from the topology dataset are used as training data to train a LoRA module. The training objective is to improve the model's ability to extract circuit components and infer connections. The training parameters are set as follows: epoch=8 (epoch refers to the training cycle of completing one full traversal of the training dataset), and learning rate... Batch size = 16, and the optimizer used is AdamW;

[0056] The second stage is the logical data fusion training stage. The logical dataset is used as training data to train another LoRA module. The training objective is to improve the model's semantic understanding of EDA domain knowledge and strengthen the correlation reasoning between component functions and connection logic. The training parameters are set as follows: epoch=3 (epoch definition is the same as before; the design basis for the parameter difference between the two stages is that the first stage needs to fully learn visual features, while the second stage avoids overfitting to semantic knowledge), and the learning rate... Batch size = 16, optimizer still uses AdamW.

[0057] In the first phase of training, an early stopping strategy is adopted, using the F1 score extracted from the test set components as the monitoring metric. When the metric does not improve for three consecutive epochs, training is stopped, and the optimal weights of the two LoRA modules are saved. When needed, the two LoRA modules are inserted separately into the base model.

[0058] (III) Implementation of Performance Evaluation

[0059] 1. Test set setup: Select 20 manually annotated block diagrams as the test set, covering typical application scenarios in the EDA field such as operational circuits, DAC circuits, and filter circuits, to ensure the universality and representativeness of the test results.

[0060] 2. Indicator Calculation:

[0061] 3. IoU Calculation: For the component bounding boxes and truth boxes output by the model, calculate the IoU value according to the following steps and perform statistical analysis. The number of samples with IoU ≥ 0.5 is used as the position matching TP value. For detailed calculation logic, please refer to the appendix. Figure 3 (IoU calculation diagram):

[0062] 4. Coordinates of the top left corner of the intersecting part: ,

[0063] 5. Coordinates of the lower right corner of the intersecting part: ,

[0064] 6. Intersection area:

[0065] 7. The areas of the two boxes: ,

[0066] 8. Union area:

[0067] 9. IoU Calculation:

[0068] in, , The coordinates of the top-left corner of the component's bounding box. , The coordinates of the bottom right corner of the component's bounding box. , The coordinates of the top left corner of the truth box. , The coordinates are the bottom right corner of the truth box.

[0069] Component extraction scoring Overall location matching score Name matching rating The calculation formula is: :

[0070] 1. Location matching ( (Score): First define the core parameters (Number of samples with IoU ≥ 0.5 between the scaled component box and the truth box) (The total number of component locations that actually exist in the labeled data but were not correctly identified by the model) (Total number of fake component locations generated by the model); then calculate the accuracy. Recall rate ;final .

[0071] 2. Name matching ( (Score): First define the core parameters (The number of samples with a similarity exceeding the threshold of 0.9 is calculated using text edit distance or word vectors.) (The total number of real component names in the labeled data minus the number of samples with correct name matches) (The total number of component names generated by the model minus the number of samples with correctly matched names); then calculate the accuracy. Recall rate ;final .

[0072] Port Quantity Identification Scoring (F1 score): Define core parameters (Both input and output ports match the correct number of components) (The total number of actual components in the labeled data minus the number of components with correct port matching) (Total number of components identified by the model minus the number of components with correct port matching); calculate accuracy. Recall rate ;final .

[0073] Connection relationship extraction scoring (F1 score): Define core parameters (The number of join pairs that are exactly the same as the truth value) (The total number of true connection pairs in the labeled data minus the number of correctly matched connection pairs) (Total number of connection pairs generated by the model minus the number of correctly matched relationship pairs); Calculate accuracy. Recall rate ;final .

[0074] Normalization: Collect data from 5 independent tests. , , Raw scores, normalized according to the Min-Max formula (in The normalized value. The original fractions to be normalized, The original score set is used to map the scores of each dimension to the interval [0,1], and the average value is taken as the final performance score. Normalization is performed using the min and max functions of the NumPy library to improve data processing efficiency.

[0075] Technical Performance Verification: To verify the superiority of this invention, 20 typical EDA circuit block diagrams were selected from the test set. The methods of this invention, manual analysis, and the Qwen2.5-VL-3B basic model (untuned) were used for comparative analysis. The core performance indicators are shown in the table below:

[0076]

[0077] Verification conclusion: As shown in the table above, the parsing efficiency of the method of the present invention is more than 300 times higher than that of manual methods, and the accuracy of component extraction and connection relationship reasoning is significantly better than that of the basic model.

[0078] (iv) Results Output and Adaptation

[0079] After model training, the input EDA circuit block diagram is parsed, and natural language results are output. A parsing script is written to extract the required fields in JSON format based on fixed tags, generating a structured file containing "Component", "Pos", "I_O", and "Connection". Specific specifications for the JSON format can be found in the appendix. Figure 4 (Example image of JSON output format), the generated structured result can be attached... Figure 5 (JSON output visualization) provides a visual representation, facilitating an intuitive view of component distribution, port information, and connection relationships. This structured file is highly automated and can be directly imported into mainstream EDA design tools (such as Cadence and Synopsys), enabling rapid reuse of the parsed results. The collaborative relationships between the various modules of this system can be found in the appendix. Figure 1 (EDA circuit block diagram analysis of the overall system architecture), attached. Figure 1 The composition and data interaction logic of the dataset construction module, model fine-tuning module, performance evaluation module, and result output module were clearly defined.

[0080] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the present invention. These examples are merely for the purpose of helping to understand the method and core ideas of the present invention. The above descriptions are only preferred embodiments of the present invention. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or variations without departing from the principles of the present invention, and can also combine the above technical features in an appropriate manner. These improvements, modifications, variations, or combinations, or the direct application of the concept and technical solution of the present invention to other situations without modification, should all be considered within the scope of protection of the present invention.

Claims

1. A method for analyzing the block diagram of an EDA circuit for fine-tuning of multimodal models, characterized in that, Includes the following steps: Step 1, Construct EDA domain topology dataset: Collect circuit system block diagrams covering communication circuits, analog circuits, and digital circuits. Select a portion for precise manual annotation as the test set, and generate pseudo-annotations using Qwen2.5-VL-3B and manually correct them as the training set. Perform coordinate optimization on all block diagrams to make the component coordinates adapt to the 28×28patch reading characteristics of the model. Step 2, construct the logical dataset for EDA domain: construct a question-and-answer set of 300,000+ characters using a large language model, and obtain the logical dataset for training semantic understanding of the model through cross-validation distillation, quality screening and deduplication cleaning. Step 3, perform lightweight LORA fine-tuning: freeze the 3B parameters of the Qwen2.5-VL-3B base model, train only the LORA module, and adopt a phased training strategy. In the first phase, train the component extraction and connection relationship reasoning ability based on topological data. In the second phase, introduce logical data to improve semantic understanding ability.

2. The method according to claim 1, characterized in that, The coordinate optimization described in step 1 includes two sub-steps: resetting the image logic of the computational model and proportionally transforming the component coordinates. Furthermore, the resetting the image logic of the computational model satisfies... , ,in , The original block diagram width and height, It is a rounding function; Set the target width of the image after model reset. The target height of the image after model reset; component coordinates are being proportionally transformed. The scaling factor is the width. This is the scaling factor in the height direction.

3. The method according to claim 2, characterized in that, The specific method for proportionally transforming the component coordinates is as follows: based on resizing the image according to the model. , The original absolute coordinates of the component Convert to coordinates of the model input The conversion formula is: , , , .

4. The method according to claim 1, characterized in that, The large language models mentioned in step 2 include chat-gpt and deepseek, and the constructed EDA domain question and answer set must meet the requirements of being related to circuit block diagram analysis, having moderate difficulty, and having diverse question types.

5. The method according to claim 1, characterized in that, The parameter configuration for lightweight LORA fine-tuning in step 3 is as follows: set the rank of the low-rank matrix. Scaling factor Random inactivation rate .

6. The method according to claim 1, characterized in that, The specific phased training strategy is as follows: The first phase is the topology data training phase. Using labeled samples from the topology dataset as training data, a LoRA module is trained. The training objective is to improve the model's ability to extract circuit components and infer connectivity relationships. The training parameters are set as follows: epoch=8, where epoch refers to the training cycle of completing one full traversal of the training dataset, and the learning rate... Batch size = 16, optimizer used is AdamW; The second stage is the logical data fusion training stage, where the logical dataset is used as training data to train another LoRA module. The training objective is to improve the model's semantic understanding of EDA domain knowledge and strengthen the correlation reasoning between component functions and connection logic. The training parameters are set as follows: epoch=3, learning rate... Batch size = 16, optimizer used is AdamW; In the first phase of training, an early stopping strategy is adopted, using the F1 score extracted from the test set components as the monitoring metric. When the metric does not improve for three consecutive epochs, training is stopped, and the optimal weights of the two LoRA modules are saved. When needed, the two LoRA modules are inserted separately into the base model.

7. A method for quantitatively evaluating the analytical performance of EDA block diagrams, used to evaluate the analytical performance of a model fine-tuned by the method described in any one of claims 1-6, characterized in that, Includes the following steps: Step A, calculate the component to extract the score ,in Match F1 scores to positions. Match the name to the F1 score; Step B: Calculate the port number identification score ; Step C: Calculate connection relationships and extract scores ; Step D, use Min-Max normalization to... , , Map to the interval [0,1].

8. The method according to claim 7, characterized in that, The position matches the F1 score. Through calculation and Received, among which This represents the number of samples where the IoU between the scaled component box and the truth box is ≥ 0.

5. This represents the total number of component locations in the labeled data that actually exist but were not correctly identified by the model. The total number of spurious component locations generated for the model, and the IoU is calculated by the ratio of the intersection area to the union area; For location matching accuracy, it represents the proportion of component locations identified by the model that match the ground truth. Location-matching recall represents the proportion of actual component locations that are correctly identified by the model.

9. The method according to claim 7, characterized in that, In step B, the number of components is calculated based on the fact that both input and output ports are correctly matched. and get ,in Ensure that the number of components matches the correct number for both input and output ports. The total number of actual components in the labeled data is calculated by subtracting the number of components whose input and output ports both match correctly. Subtract the number of components that are correctly matched at both input and output ports from the total number of components identified by the model; Port count identification accuracy represents the proportion of components identified by the model that correctly match the number of ports. Port count recall represents the proportion of ports in a real component that are correctly identified. In step C, the quantity is calculated based on the correctly matched connection relationships. and get ,in For the number of join pairs that are completely consistent with the truth value, The total number of true connection pairs in the labeled data is minus the number of correctly matched connection pairs. Subtract the number of correctly matched connection pairs from the total number of connection pairs generated for the model; The accuracy of connection relationship extraction represents the proportion of connection relationships identified by the model that match the ground truth. Recall is extracted for connections, representing the proportion of real connections that are correctly identified by the model.

10. An EDA circuit block diagram analysis system, applied to the method described in any one of claims 1-6, characterized in that, include: The system includes a dataset construction module, a model fine-tuning module, a performance evaluation module, and a results output module. The dataset construction module is used to collect circuit block diagrams in the EDA field and construct topology and logic datasets. Specifically, it includes: collecting circuit block diagrams, manually annotating some block diagrams to form a test set, generating pseudo-annotations for the remaining block diagrams using Qwen2.5-VL-3B and manually correcting them to form a training set, and performing coordinate optimization on all block diagrams by normalizing image size and scaling component coordinates proportionally. At the same time, it constructs an EDA domain question-answer set through a large language model, and obtains the logic dataset through cross-validation distillation, quality screening, and deduplication cleaning. The model fine-tuning module is used to implement lightweight LORA fine-tuning, specifically including: loading the Qwen2.5-VL-3B base model and freezing its original parameters, introducing a low-rank matrix and configuring the LORA module training parameters, and adopting a phased training strategy. The first phase is based on the topological dataset to train the component extraction and connection relationship reasoning capabilities, and the second phase introduces the logical dataset to improve the semantic understanding capabilities in the EDA domain. The performance evaluation module is used to achieve multi-dimensional quantitative evaluation, specifically including: calculating scores from the component. Port Quantity Identification and Scoring and connection relationship extraction scoring The position matching accuracy is calculated by IoU, the name matching accuracy is calculated by combining text edit distance or word vectors, the F1 score of each dimension is calculated based on Precision and Recall, and the Min-Max normalization is used to map each score to the [0,1] interval; The output module converts the model parsing results into JSON format, which is beneficial for adapting to secondary calls by EDA design tools.

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