Semiconductor device including back pattern

Abstract

A semiconductor device includes a memory cell on a front surface of a substrate, a first back pattern on a back surface of the substrate, and a second back pattern on the back surface of the substrate. The first back pattern includes first ground lines arranged in a first direction and extending in a second direction intersecting the first direction, and power lines extending in the second direction, where the first ground lines and the power lines are alternately arranged in the first direction, and the second back pattern includes back word lines arranged in the second direction and extending in the first direction.

Description

Technical Field

[0001] This application relates to semiconductor devices. Background Technology

[0002] As the integration of semiconductor devices increases, more complex wiring resources may be expected. Summary of the Invention

[0003] As semiconductor device design rules shrink and design complexity increases, securing wiring resources within limited physical space becomes increasingly difficult. Furthermore, as the path of a conductor increases, the resistance of the conductors can increase, the parasitic capacitance between conductors can increase, and the size of the semiconductor device can increase. Therefore, it may be desirable to efficiently arrange wiring resources.

[0004] Embodiments of this disclosure provide semiconductor devices capable of improving electrical characteristics.

[0005] Embodiments of this disclosure provide semiconductor devices capable of improving the stability of power supply or the stability of signal transmission.

[0006] One aspect of this disclosure provides a semiconductor device comprising: a plurality of memory cells located on a front surface of a substrate; a first back pattern located on a back surface of the substrate; and a second back pattern located on the back surface of the substrate. The first back pattern includes a plurality of first ground lines arranged in a first direction and extending in a second direction intersecting the first direction, and a plurality of power lines extending in the second direction. The plurality of first ground lines and the plurality of power lines are alternately arranged in the first direction. The second back pattern includes a plurality of back letter lines arranged in the second direction and extending in the first direction.

[0007] Another aspect of this disclosure provides a semiconductor device comprising: a plurality of memory cells located on a front surface of a substrate; a first back pattern located on a back surface of the substrate; and a second back pattern located on the back surface of the substrate. The first back pattern includes a plurality of first ground lines arranged in a first direction and extending in a second direction intersecting the first direction. The second back pattern includes a plurality of second ground lines arranged in the second direction and extending in the first direction. The plurality of second ground lines are connected to the plurality of first ground lines.

[0008] Another aspect of this disclosure provides a semiconductor device comprising: a plurality of memory cells on a substrate; a signal back pattern on a back surface of the substrate; a first front pattern on a front surface of the substrate; a second front pattern on the front surface of the first front pattern; and a plurality of first through-paths connecting the signal back pattern and the second front pattern. The signal back pattern includes a plurality of back letter lines extending in a first direction and arranged in a second direction intersecting the first direction. The first front pattern includes a plurality of first front letter lines arranged in the first direction and extending in the second direction. The second front pattern includes a plurality of second front letter lines extending in the first direction and perpendicularly overlapping the plurality of back letter lines. The plurality of second front letter lines are connected to the plurality of first front letter lines. The plurality of first through-paths connect a first end of the plurality of second front letter lines to a first end of the plurality of back letter lines, and connect a second end of the plurality of second front letter lines to a second end of the plurality of back letter lines. Attached Figure Description

[0009] Figure 1 This is a circuit diagram showing an example of a semiconductor device.

[0010] Figure 2 This is a view showing the layout of an example semiconductor device.

[0011] Figure 3 This is a view showing the layout of an example semiconductor device.

[0012] Figure 4 It is along Figure 2 The cross-sectional view taken from line I-I'.

[0013] Figure 5 It is along Figure 2 The cross-sectional view taken from line Ⅱ-Ⅱ'.

[0014] Figure 6 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0015] Figure 7 This is a view showing an example layout of the second back pattern.

[0016] Figure 8 This is a view showing the layout of an example of the first back pattern, an example of the second back pattern, and an example of the storage unit.

[0017] Figure 9 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0018] Figure 10This is a view showing the layout of an example of a first back pattern, an example of a second back pattern, an example of a storage cell, and an example of a first front pattern.

[0019] Figure 11 This is a view showing the layout of an example of the first back pattern, an example of the second back pattern, and an example of the storage unit.

[0020] Figure 12 This is a view showing the layout of an example of a first back pattern, an example of a second back pattern, an example of a storage cell, and an example of a first front pattern.

[0021] Figure 13 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0022] Figure 14 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0023] Figure 15 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0024] Figure 16 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0025] Figure 17 This is a view showing the layout of an example of the first back pattern, an example of the second back pattern, and an example of the storage unit.

[0026] Figure 18 This is a view showing the layout of examples of the first back pattern and examples of the second back pattern.

[0027] Figure 19 This is a view showing the layout of an example of the first back pattern, an example of the second back pattern, and an example of the storage unit.

[0028] Figure 20 This is a view showing the layout of an example of a first back pattern, an example of a second back pattern, an example of a storage cell, and an example of a second front pattern. Detailed Implementation

[0029] In the following, embodiments of the present disclosure will be described clearly and in detail with reference to the accompanying drawings.

[0030] Figure 1 This is a circuit diagram illustrating a semiconductor device according to some embodiments. Figure 1 The circuit diagram illustrates the equivalent circuit 20 corresponding to one memory cell MC included in a semiconductor device. In some embodiments, the remaining memory cells MC may have the same... Figure 1 The storage unit MC shown in the figure has the same structure.

[0031] refer to Figure 1 The semiconductor device may include: a memory cell array including memory cells MC, word lines connected to the memory cells MC, a first bit line BL1 and a second bit line BL2, wherein the first bit line BL1 and the second bit line BL2 may be connected to the memory cells MC. In some embodiments, the memory cell array may correspond to an embedded memory device, and the semiconductor device may also include any other components that input data to or output data to the memory cell array. For example, the semiconductor device may also include row drivers, column drivers, and control logic. Unlike the above description, in some embodiments, the memory cell array may correspond to a standalone memory device.

[0032] A memory cell array can receive commands, addresses, and data. For example, a memory cell array can receive commands, addresses, and data indicating input, and the received data can be stored in the memory cell MC corresponding to the address. Conversely, a memory cell array can receive commands and addresses indicating output, and can output data from the memory cell MC corresponding to the address.

[0033] A memory cell array may include memory cells (MCs) arranged in multiple rows and columns. That is, the memory cells (MCs) may be arranged in a matrix. The memory cells (MCs) included in the memory cell array may correspond to volatile memory cells (MCs) or non-volatile memory cells (MCs). For example, a memory cell (MC) may include static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. For example, a memory cell (MC) may include flash memory cells or resistive random access memory (RRAM) cells. For ease of description, memory cells (MCs) according to some embodiments will be described based on SRAM cells, but the technical concept of this disclosure is not limited thereto.

[0034] A memory cell (MC) can be connected to a word line (WL). Specifically, memory cells (MCs) arranged along a row can be connected together to a single word line (WL).

[0035] A memory cell MC can be connected to a first bit line BL1 and a second bit line BL2. That is, a memory cell MC can be connected to a pair of bit lines BL1 and BL2. One of the paired bit lines BL1 and BL2 can be referred to as "bit line BL1," and the other bit line can be referred to as "complementary bit line BL2." The first bit line BL1 and the second bit line BL2 can be arranged alternately along the memory cells MC arranged in the row direction.

[0036] Each memory cell MC may include two transistors PX1 and PX2 and a pair of inverters. For example, each memory cell MC may include a first pass transistor PX1, a second pass transistor PX2, a first inverter, and a second inverter.

[0037] The inputs of the first inverter and the outputs of the second inverter can be connected to each other, and the outputs of the first inverter and the inputs of the second inverter can be connected to each other. The inputs and outputs of the paired inverters can be cross-coupled, and the memory cell MC can store data in units of bits. The memory cell MC can be called a "bit cell".

[0038] The first channel transistor PX1 can be connected to the output of the first inverter and the input of the second inverter, and the second channel transistor PX2 can be connected to the output of the second inverter and the input of the first inverter. The first channel transistor PX1 can be referred to as "first channel gate transistor PX1", and the second channel transistor PX2 can be referred to as "second channel gate transistor PX2".

[0039] The first bit line BL1 can be connected to the source / drain of the first channel transistor PX1. The second bit line BL2 can be connected to the source / drain of the second channel transistor PX2. For example, the first bit line BL1 can be connected to the drain of the first channel transistor PX1, and the second bit line BL2 can be connected to the drain of the second channel transistor PX2.

[0040] The word line WL can be connected to the gate of the first channel transistor PX1 and the gate of the second channel transistor PX2. When the word line (WL) signal is applied to the gates of channel transistors PX1 and PX2, channel transistors PX1 and PX2 are turned on; in this case, the data bits stored in the memory cell MC are transmitted to the sense amplifier connected to the first end of the bit lines BL1 and BL2, and the sense amplifier amplifies and outputs the signal received through the bit lines BL1 and BL2.

[0041] The first inverter may include a first pull-up transistor PU1 and a first pull-down transistor PD1. The second inverter may include a second pull-up transistor PU2 and a second pull-down transistor PD2.

[0042] The first pull-up transistor PU1 and the second pull-up transistor PU2 can be P-type field-effect transistors (PFETs), and the first pull-down transistor PD1 and the second pull-down transistor PD2 can be N-type field-effect transistors (NFETs). In some embodiments, a pull-up transistor and a pull-down transistor can constitute an inverter.

[0043] The sources of the first pull-up transistor PU1 and the second pull-up transistor PU2 can be connected to the power supply line VDD. The sources of the first pull-down transistor PD1 and the second pull-down transistor PD2 can be connected to the ground line VSS.

[0044] The drain of the first pull-up transistor PU1 and the drain of the first pull-down transistor PD1 can be connected. The source / drain of the first channel transistor PX1 can be connected to the drain of the first pull-up transistor PU1 and the drain of the first pull-down transistor PD1 at the first node N1. For example, the drain of the first channel transistor PX1 can be connected to the drain of the first pull-up transistor PU1 and the drain of the first pull-down transistor PD1 at the first node N1. The first node N1 can be connected to the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2.

[0045] The drain of the second pull-up transistor PU2 and the drain of the second pull-down transistor PD2 can be connected. The source / drain of the second channel transistor PX2 can be connected to the drain of the second pull-up transistor PU2 and the drain of the second pull-down transistor PD2 at the second node N2. For example, the drain of the second channel transistor PX2 can be connected to the drain of the second pull-up transistor PU2 and the drain of the second pull-down transistor PD2 at the second node N2. The second node N2 can be connected to the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1.

[0046] Figure 2 This is a view showing the layout of a semiconductor device according to some embodiments. Figure 3 This is a view showing the layout of a semiconductor device according to some embodiments. Figure 4 It is along Figure 2 The cross-sectional view taken from line I-I'. Figure 5 It is along Figure 2 The cross-sectional view taken from line Ⅱ-Ⅱ'.

[0047] refer to Figures 2 to 5 The semiconductor device may include a substrate SUB, a transistor located on the front surface of the substrate SUB, a first front pattern FP1, a second front pattern FP2, a first back pattern BP1, and a second back pattern BP2. The first front pattern FP1 and the second front pattern FP2 may be located on the front surface of the substrate SUB, and the first back pattern BP1 and the second back pattern BP2 may be located on the back surface of the substrate SUB.

[0048] The substrate SUB may include active patterns defined by a shallow device isolation pattern (STI). The shallow device isolation pattern (STI) may fill shallow trenches formed in the substrate SUB. Specifically, the substrate SUB may include a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4 defined by the shallow device isolation pattern (STI). The substrate SUB may include at least one of silicon, germanium, or silicon-germanium.

[0049] The transistors may include a first pull-up transistor PU1 located on a first active pattern AP1, a first pull-down transistor PD1 and a first channel transistor PX1 located on a second active pattern AP2, a second pull-up transistor PU2 located on a third active pattern AP3, and a second pull-down transistor PD2 and a second channel transistor PX2 located on a fourth active pattern AP4. Transistors PU1, PU2, PD1, PD2, PX1, and PX2 may be formed on active patterns AP1 to AP4.

[0050] The gate electrode can be disposed on the front surface of the substrate SUB. The gate electrode can extend in a first direction DR1. The gate electrodes can be arranged to be spaced apart from each other in a second direction DR2.

[0051] Specifically, the first gate electrode G1 and the second gate electrode G2 may extend along the first direction DR1 and may be spaced apart from each other along the second direction DR2. The second direction DR2 may intersect the first direction DR1. For example, the second direction DR2 may be orthogonal to the first direction DR1.

[0052] Specifically, the first gate electrode G1 can be disposed on the first active pattern AP1 and the second active pattern AP2. The first gate electrode G1 can extend along the first direction DR1 on the first active pattern AP1 and the second active pattern AP2. In this way, the first pull-up transistor PU1 and the first pull-down transistor PD1 can share the first gate electrode G1.

[0053] The second gate electrode G2 can be disposed on the third active pattern AP3 and the fourth active pattern AP4. The second gate electrode G2 can extend along the first direction DR1 on the third active pattern AP3 and the fourth active pattern AP4. In this way, the second pull-up transistor PU2 and the second pull-down transistor PD2 can share the second gate electrode G2.

[0054] The third gate electrode G3 can be disposed on the second active pattern AP2. The third gate electrode G3 can extend along the first direction DR1 on the second active pattern AP2. The first channel transistor PX1 may include the third gate electrode G3. The third gate electrode G3 can be disposed next to the second gate electrode G2. That is, the third gate electrode G3 can be configured to be aligned with the second gate electrode G2. In addition, the third gate electrode G3 can be configured to be parallel to the first gate electrode G1.

[0055] A fourth gate electrode G4 may be disposed on a fourth active pattern AP4. The fourth gate electrode G4 may extend along a first direction DR1 on the fourth active pattern AP4. The second channel transistor PX2 may include the fourth gate electrode G4. The fourth gate electrode G4 may be disposed adjacent to the first gate electrode G1. That is, the fourth gate electrode G4 may be configured to be aligned with the first gate electrode G1. Furthermore, the fourth gate electrode G4 may be configured to be parallel to the second gate electrode G2.

[0056] The source / drain contact can be disposed on the front surface of the substrate SUB. The source / drain contact can extend in the first direction DR1. The source / drain contact can be arranged parallel to the gate electrode.

[0057] The first source / drain contact SDC1 can be disposed on the first active pattern AP1 and the second active pattern AP2. The first source / drain contact SDC1 can extend along a first direction DR1 on the first active pattern AP1 and the second active pattern AP2. The first source / drain contact SDC1 can be disposed between the first gate electrode G1 and the third gate electrode G3. Furthermore, the first source / drain contact SDC1 can also be disposed between the first gate electrode G1 and the second gate electrode G2.

[0058] The first source / drain contact SDC1 can be electrically connected to the first active pattern AP1 and the second active pattern AP2. For example, the first source / drain contact SDC1 can be electrically connected to the drain region PSD2 of the first pull-up transistor PU1 on the first active pattern AP1 and the drain region NSD2 of the first pull-down transistor PD1 on the second active pattern AP2.

[0059] The second source / drain contact SDC2 can be disposed on the third active pattern AP3 and the fourth active pattern AP4. The second source / drain contact SDC2 can extend along the first direction DR1 on the third active pattern AP3 and the fourth active pattern AP4. The second source / drain contact SDC2 can be disposed between the second gate electrode G2 and the fourth gate electrode G4. Furthermore, the second source / drain contact SDC2 can be disposed between the second gate electrode G2 and the first gate electrode G1. The second source / drain contact SDC2 can be spaced apart from the first source / drain contact SDC1.

[0060] The second source / drain contact SDC2 can electrically connect the third active pattern AP3 and the fourth active pattern AP4. For example, the second source / drain contact SDC2 can electrically connect the drain region of the second pull-up transistor PU2 on the third active pattern AP3 and the drain region of the second pull-down transistor PD2 on the fourth active pattern AP4.

[0061] The third source / drain contact SDC3 can be disposed on the second active pattern AP2. The third source / drain contact SDC3 can extend along the first direction DR1 on the second active pattern AP2. The third gate electrode G3 can be located between the first source / drain contact SDC1 and the third source / drain contact SDC3. The third source / drain contact SDC3 can be electrically connected to the first front pattern FP1 and the first bit line BL1. For example, the drain region NSD3 of the first channel transistor PX1 can be electrically connected to the first bit line BL1 through the third source / drain contact SDC3.

[0062] A fourth source / drain contact SDC4 can be disposed on a fourth active pattern AP4. The fourth source / drain contact SDC4 can extend along a first direction DR1 on the fourth active pattern AP4. A fourth gate electrode G4 can be located between the second source / drain contact SDC2 and the fourth source / drain contact SDC4. The fourth source / drain contact SDC4 can be electrically connected to the first front pattern FP1 and the second bit line BL2. For example, the drain region of the second channel transistor PX2 can be electrically connected to the second bit line BL2 through the fourth source / drain contact SDC4.

[0063] The semiconductor device may further include a first node contact NC1 connecting the second gate electrode G2 and the first source / drain contact SDC1. The first node contact NC1 may be disposed on the second gate electrode G2 and the first source / drain contact SDC1. The first node contact NC1 may extend in the second direction DR2. The first node contact NC1 and the first source / drain contact SDC1 may form the first node N1 of the equivalent circuit 20.

[0064] The semiconductor device may further include a second node contact NC2 connecting the first gate electrode G1 and the second source / drain contact SDC2. The second node contact NC2 may be disposed on the first gate electrode G1 and the second source / drain contact SDC2. The second node contact NC2 may extend in a second direction DR2. The second node contact NC2 may be spaced apart from the first node contact NC1 in a first direction DR1. The second node contact NC2 and the second source / drain contact SDC2 may form the second node N2 of the equivalent circuit 20.

[0065] The first front pattern FP1 can be disposed on the front surface of the substrate SUB. The first front pattern FP1 may include a pair of first front word lines FWL1 and a pair of bit lines BL1 and BL2. The pair of bit lines BL1 and BL2 may include a first bit line BL1 and a second bit line BL2. Since the ground line VSS and the power line VDD are disposed on the back surface of the substrate SUB, the wiring resources in the first front pattern FP1 can be increased. This can refer to a reduction in the parasitic capacitance of the first front pattern FP1.

[0066] The semiconductor device may further include a second front pattern FP2. The second front pattern FP2 may be disposed on the front surface of the first front pattern FP1. The second front pattern FP2 may include a second front word line FWL2. The second front word line FWL2 may extend in a first direction DR1. The second front word line FWL2 may be arranged in a second direction DR2. The second front word line FWL2 may be electrically connected to the first front word line FWL1.

[0067] The first back pattern BP1 can be disposed on the back surface of the substrate SUB. The first back pattern BP1 may include a first ground line VSS1 and a power line VDD.

[0068] The second back pattern BP2 can be disposed on the back surface of the substrate SUB. The second back pattern BP2 can be disposed on the back surface of the first back pattern BP1. That is, the first back pattern BP1 can be located between the back surface of the substrate SUB and the second back pattern BP2. The second back pattern BP2 may include a second ground line VSS2 and a back letter line BWL. The second front letter line FWL2 may perpendicularly overlap with the back letter line BWL.

[0069] Since the first back pattern BP1 and the second back pattern BP2 are disposed on the back surface of the substrate SUB, the wiring resources on the front surface of the substrate SUB can be increased. That is, since the wiring resources of the semiconductor device are distributed on the front and back surfaces of the substrate SUB, the complexity of the wiring resources can be reduced and the wiring path can be shortened.

[0070] In addition, semiconductor devices that can reduce the resistance of wires and the parasitic capacitance between wires can be provided.

[0071] In addition, the size of semiconductor devices can be reduced.

[0072] refer to Figure 4 The first source / drain contact SDC1 can be disposed on the drain region PSD2 of the first pull-up transistor PU1. In this way, the first source / drain contact SDC1 can be electrically connected to the drain region PSD2 of the first pull-up transistor PU1.

[0073] The first node contact NC1 can be disposed on the first source / drain contact SDC1 and can be electrically connected to the first source / drain contact SDC1. Furthermore, the first node contact NC1 can be disposed on the second gate electrode G2 and can be electrically connected to the second gate electrode G2.

[0074] The semiconductor device may include a direct contact that penetrates the substrate SUB. The direct contact may include a first direct contact BDC1, which connects the power line VDD and the source region PSD1 of the first pull-up transistor PU1. The first direct contact BDC1 may be disposed on the front surface of a first back pattern BP1. Specifically, the first direct contact BDC1 may be disposed on the front surface of the power line VDD. The first direct contact BDC1 may penetrate the back surface of the substrate SUB and may be connected to the source region PSD1 of the first pull-up transistor PU1 located on the front surface of the substrate SUB.

[0075] As described above, the power line VDD can be directly connected to the pull-up transistors PU1 and PU2 on the substrate SUB via the first direct contact BDC1.

[0076] Furthermore, the length of the connection between the power line VDD and the pull-up transistors PU1 and PU2 can be shortened, which means that the resistance is reduced.

[0077] In addition, semiconductor devices that can improve voltage drop and enhance stability can be provided.

[0078] refer to Figure 5 The first source / drain contact SDC1 can be set on the drain region NSD2 of the first pull-down transistor PD1. In this way, the first source / drain contact SDC1 can be electrically connected to the drain region NSD2 of the first pull-down transistor PD1.

[0079] The third source / drain contact SDC3 can be disposed on the source / drain region NSD3 of the first channel transistor PX1. For example, the third source / drain contact SDC3 can be disposed on the drain region NSD3 of the first channel transistor PX1. In this way, the third source / drain contact SDC3 can be electrically connected to the drain region NSD3 of the first channel transistor PX1.

[0080] The semiconductor device may include a path VA electrically connecting a first front pattern FP1 and a second front pattern FP2. Specifically, the path VA may be electrically connected to a first front word line FWL1 and a second front word line FWL2. The path VA may be disposed on the first front word line FWL1.

[0081] The direct contact may include a second direct contact BDC2 connecting the first ground line VSS1 and the source region NSD1 of the first pull-down transistor PD1. The second direct contact BDC2 may be disposed on the front surface of the first back pattern BP1. Specifically, the second direct contact BDC2 may be disposed on the front surface of the first ground line VSS1. The second direct contact BDC2 may penetrate the back surface of the substrate SUB and may be connected to the source region NSD1 of the first pull-down transistor PD1 located on the front surface of the substrate SUB.

[0082] As described above, the ground wire VSS can be directly connected to the pull-down transistors PD1 and PD2 located on the substrate SUB via the second direct contact BDC2.

[0083] Furthermore, the length of the connection between the ground wire VSS and the pull-down transistors PD1 and PD2 can be shortened, which means that the resistance is reduced.

[0084] In addition, semiconductor devices that can improve voltage drop and enhance stability can be provided.

[0085] The semiconductor device may further include a back contact BC disposed between the first back pattern BP1 and the second back pattern BP2. Specifically, the back contact BC may be disposed between the first ground line VSS1 and the second ground line VSS2. In this way, the back contact BC can electrically connect the first ground line VSS1 and the second ground line VSS2.

[0086] Figure 6 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments. Figure 7 This is a view showing the layout of the second back pattern BP2 according to some embodiments.

[0087] refer to Figure 6 and Figure 7 The second back pattern BP2 may include an elongated second grounding line VSS2 and a back letter line BWL. For ease of description, Figure 6 and Figure 7 The diagram only shows one second ground line VSS2 and one back word line BWL on the back surface of any one memory cell MC. However, it is clear that multiple second ground lines VSS2 and back word lines BWL are provided to correspond to multiple memory cells MC.

[0088] Each second ground wire VSS2 can extend along the first direction DR1. The second ground wire VSS2 can be arranged along the second direction DR2. For example, each second ground wire VSS2 can overlap with the first long side of any memory cell MC.

[0089] The back word line (BWL) can extend along the first direction DR1. Each back word line (BWL) can be positioned on the back surface of any memory cell (MC). That is, each back word line (BWL) can overlap with any memory cell (MC). The back word line (BWL) can cross with any memory cell (MC). The back word line (BWL) can be spaced apart from the second ground line (VSS2) along the second direction DR2.

[0090] The back contact BC can be disposed on the second ground wire VSS2. Specifically, the back contact BC can be disposed on the front surface of the second ground wire VSS2. The back contact BC can overlap with the corner of any memory cell MC.

[0091] A first back pattern BP1 can be disposed on the front surface of a second back pattern BP2. Specifically, a first grounding wire VSS1 can be disposed on the back contact BC. As described above, the first grounding wire VSS1 can be electrically connected to the second grounding wire VSS2 via the back contact BC.

[0092] This could mean that the resistance of the ground wire VSS has decreased.

[0093] In addition, the performance of semiconductor devices can be improved. For example, the read performance of memory cells can be improved.

[0094] The first ground wire VSS1 may extend along the second direction DR2. The first ground wire VSS1 may be arranged along the first direction DR1. The first ground wires VSS1 may be spaced apart from each other. Each memory cell MC may include a first end and a second end that are opposite to each other along the first direction DR1, and each first ground wire VSS1 may overlap with the first end or the second end of the memory cell MC arranged along the second direction DR2. For example, each first ground wire VSS1 may overlap with the first short side or the second short side of any memory cell MC, and the first short side and the second short side may be opposite each other.

[0095] Each power line VDD can be positioned between adjacent first ground lines VSS1. Specifically, the power lines VDD and the first ground lines VSS1 can be arranged alternately along the first direction DR1. Each power line VDD can overlap with a memory cell MC arranged along the second direction DR2. Each power line VDD can cross with a memory cell MC arranged along the second direction DR2. Specifically, each power line VDD can overlap with the center portion of a memory cell MC arranged along the second direction DR2.

[0096] Figure 8 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, and a storage cell MC according to some embodiments. Figure 9This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments.

[0097] refer to Figures 2 to 5 , Figure 8 and Figure 9 The first direct contact BDC1 can be positioned on the power line VDD. The pair of first direct contacts BDC1 can be connected to any one of the memory cells MC. In a top view, one of the pair of first direct contacts BDC1 can overlap with the first pull-up transistor PU1, and the other of the pair of first direct contacts BDC1 can overlap with the second pull-up transistor PU2. More specifically, one of the pair of first direct contacts BDC1 can overlap with the source region of the first pull-up transistor PU1, and the other of the pair of first direct contacts BDC1 can overlap with the source region of the second pull-up transistor PU2.

[0098] The second direct contact BDC2 can be disposed on the first ground line VSS1. The paired second direct contacts BDC2 can be connected to any one of the memory cells MC. In a top view, one of the paired second direct contacts BDC2 can overlap with the first pull-down transistor PD1, and the other of the paired second direct contacts BDC2 can overlap with the second pull-down transistor PD2. Specifically, one of the paired second direct contacts BDC2 can overlap with the source region of the first pull-down transistor PD1, and the other of the paired second direct contacts BDC2 can overlap with the source region of the second pull-down transistor.

[0099] Figure 10 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, a storage cell MC, and a first front pattern FP1 according to some embodiments. Figure 11 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, and a storage cell MC according to some embodiments.

[0100] refer to Figure 10 and Figure 11 The first front pattern FP1 may include a first front word line FWL1, a first bit line BL1, and a second bit line BL2. The first front word line FWL1 may be arranged in a first direction DR1 and a second direction DR2. The first front word line FWL1 may extend in the second direction DR2. Specifically, the first front word line FWL1 may overlap with one side and the opposite side of any memory cell MC. Specifically, a pair of first front word lines FWL1 may overlap with the first short side and the second short side of any memory cell MC. The first front word line FWL1 may overlap perpendicularly with the first ground line VSS1.

[0101] The first bit line BL1 and the second bit line BL2 can extend along the second direction DR2. The first bit line BL1 and the second bit line BL2 can be arranged alternately along the first direction DR1. The first bit line BL1 and the second bit line BL2 can intersect with the memory cell MC arranged along the second direction DR2. A first bit line BL1 and a second bit line BL2 can be positioned between a pair of first front word lines FWL1.

[0102] The semiconductor device may further include a first pass pattern VP1, which connects the drain regions of channel transistors PX1 and PX2 to bit lines BL1 and BL2. Specifically, the first pass pattern VP1 may be disposed on the drain regions of the first channel transistor PX1 and the second channel transistor PX2. More specifically, some first pass patterns VP1 may be disposed on a third source / drain contact SDC3, which is located on the drain region of the first channel transistor PX1. Other first pass patterns VP1 may be disposed on a fourth source / drain contact SDC4, which is located on the drain region of the second channel transistor PX2.

[0103] The first bit line BL1 and the second bit line BL2 of the first front pattern FP1 can be set on the first pass pattern VP1. Specifically, some first pass patterns VP1 can connect the drain region of the first channel transistor PX1 and the first bit line BL1. In addition, other first pass patterns VP1 can connect the drain region of the second channel transistor PX2 and the second bit line BL2.

[0104] The semiconductor device may include a second path pattern VP2 disposed on the gate electrodes of channel transistors PX1 and PX2. Specifically, some second path patterns VP2 may be disposed on a third gate electrode G3, and other second path patterns VP2 may be disposed on a fourth gate electrode G4. According to the above description, the gates of the first channel transistor PX1 and the second channel transistor PX2 can be electrically connected to the first front word line FWL1 through the second path pattern VP2.

[0105] Figure 12 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, a storage cell MC, and a first front pattern FP1 according to some embodiments.

[0106] refer to Figure 12The semiconductor device may further include a first through-path STC1, which electrically connects the back word line BWL and the second front word line FWL2. The first through-path STC1 can penetrate the substrate SUB. The second front word line FWL2 may perpendicularly overlap with the back word line BWL, and the first through-path STC1 may be disposed between the second front word line FWL2 and the back word line BWL. The first through-path STC1 may perpendicularly overlap with the second front word line FWL2 and the back word line BWL. The first through-path STC1 may not overlap with the memory cell MC. That is, in a top view, the first through-path STC1 may be located outside the memory cell MC.

[0107] Specifically, the first through-path STC1 can be disposed on the end of the back word line BWL. For example, some first through-paths STC1 can connect the first end of the back word line BWL and the first end of the second front word line FWL2, and other first through-paths STC1 can connect the second end of the back word line BWL and the second end of the second front word line FWL2. According to the above description, finally, the gates of channel transistors PX1 and PX2 can be electrically connected to the back word line BWL of the second back pattern BP2.

[0108] Therefore, the back letter line (BWL) can be set on the back surface of the substrate (SUB).

[0109] The passage VA can be positioned on the first front digit line FWL1. The passage VA can be positioned between the first front digit line FWL1 and the second front digit line FWL2. In a top view, the passage VA can overlap with the first front digit line FWL1 and the second front digit line FWL2.

[0110] Figure 13 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments. Figure 14 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments. Figure 15 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments.

[0111] refer to Figures 13 to 15 The second grounding wire VSS2 can be arranged on the second direction DR2. The second grounding wires VSS2 can be spaced apart from each other.

[0112] Each second grounding wire VSS2 can be set at every 2 arranged along the second direction DR2. nAt each of the two memory cells MC. Here, "n" can include "0" and any natural number. For example, a second grounding wire VSS2 can overlap with the first memory cell MC arranged in the second direction DR2, and other second grounding wires VSS2 can be arranged sequentially at each of the two memory cells MC arranged in the second direction DR2. n At each storage unit MC.

[0113] The back-character line BWL can be positioned between the second grounding lines VSS2. More specifically, the back-character line BWL can be positioned between pairs of adjacent second grounding lines VSS2. Even more specifically, 2 n Two back word lines (BWL) can be periodically arranged between adjacent pairs of second ground lines (VSS2). The back word lines (BWL) can be arranged to be spaced apart from each other in the second direction (DR2). For example, the pairs of second ground lines (VSS2) can be arranged to intersect perpendicularly with two memory cells (MC) arranged in the second direction (DR2), and the two back word lines (BWL) can be positioned between the pairs of second ground lines (VSS2). In this case, the two back word lines (BWL) can intersect with two memory cells (MC) arranged in the second direction (DR2), respectively.

[0114] In some implementations, reference Figure 14 The paired second ground wires VSS2 can be arranged to perpendicularly overlap with the outermost memory cell MC of the four memory cells MC arranged on the second direction DR2, and the four back word lines BWL can be arranged between the paired second ground wires VSS2. In this case, the four back word lines BWL can overlap with the four memory cells MC arranged on the second direction DR2 respectively.

[0115] In some implementations, reference Figure 15 The paired second ground wires VSS2 can be arranged to perpendicularly overlap with the outermost memory cell MC among the eight memory cells MC arranged on the second direction DR2, and the eight back word lines BWL can be arranged between the paired second ground wires VSS2. In this case, the eight back word lines BWL can overlap with the eight memory cells MC arranged on the second direction DR2, respectively.

[0116] Figure 16 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments. Figure 17 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, and a storage cell MC according to some embodiments.

[0117] refer to Figure 16 and Figure 17Each power line VDD may further include a protruding terminal 120, which overlaps with the first pull-up transistor PU1 and / or the second pull-up transistor PU2. The protruding terminal 120 may extend in a direction parallel to the first direction DR1. For example, the protruding terminal 120 may extend in a direction parallel to the first direction DR1 and may perpendicularly overlap with the source region of the first pull-up transistor PU1 and the source region of the second pull-up transistor PU2.

[0118] Based on the above description, the distance between the power line VDD and the pull-up transistors PU1 and PU2 can be shortened.

[0119] Furthermore, by reducing the resistance between the power line VDD and the pull-up transistors PU1 and PU2, a semiconductor device with improved voltage drop can be provided.

[0120] In addition, as the width of each power line VDD decreases, the space between the power line VDD and the first ground line VSS1 can be further increased.

[0121] In addition, the parasitic capacitance of the first back pattern BP1 can be reduced.

[0122] Furthermore, as the width of each power line VDD decreases, the width of each first ground line VSS1 can be increased.

[0123] Figure 18 This is a view showing the layout of the first back pattern BP1 and the second back pattern BP2 according to some embodiments.

[0124] refer to Figure 18 Each power line VDD can be wavy. That is, each power line VDD can extend in the second direction DR2 and can be repeatedly bent along the extension direction in the first direction DR1 and in a direction opposite to the first direction DR1. In this way, each power line VDD can perpendicularly overlap with the first pull-up transistor PU1 and the second pull-up transistor PU2. Specifically, each power line VDD can perpendicularly overlap with the source region of the first pull-up transistor PU1 and the source region of the second pull-up transistor PU2.

[0125] Based on the above description, the distance between the power line VDD and the pull-up transistors PU1 and PU2 can be shortened.

[0126] Furthermore, by reducing the resistance between the power line VDD and the pull-up transistors PU1 and PU2, a semiconductor device with improved voltage drop can be provided.

[0127] In addition, as the width of each power line VDD decreases, the space between the power line VDD and the first ground line VSS1 can be further increased.

[0128] In addition, the parasitic capacitance of the first back pattern BP1 can be reduced.

[0129] Furthermore, as the width of each power line VDD decreases, the width of each first ground line VSS1 can be increased.

[0130] Therefore, the distance between the power supply line VDD and the source regions of pull-up transistors PU1 and PU2 can be shortened, and the resistance of the wires connecting the power supply line VDD and the source regions of pull-up transistors PU1 and PU2 can be reduced.

[0131] Figure 19 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, and a storage cell MC according to some embodiments. Figure 20 This is a view showing the layout of a first back pattern BP1, a second back pattern BP2, a storage cell MC, and a second front pattern FP2 according to some embodiments.

[0132] refer to Figure 19 and Figure 20 The semiconductor device may further include a second through-path STC2 disposed on the back word line BWL. The second through-path STC2 can penetrate the substrate SUB. In a top view, the second through-path STC2 can be disposed between memory cells MC. Some memory cells MC arranged on the first direction DR1 can be spaced apart from other memory cells MC on the first direction DR1, and the separation space can be defined between some memory cells MC and other memory cells MC. The second through-path STC2 can penetrate the substrate SUB so as to be disposed in the separation space.

[0133] The second through passage STC2 can connect the back letter line BWL and the second front letter line FWL2. The second through passage STC2 can be located on the center portion of the back letter line BWL. The second through passage STC2 can be arranged in the first direction DR1 between the first through passage STC1 located at the end of the back letter line BWL.

[0134] In the semiconductor device according to embodiments of the present disclosure, the wiring resources of the integrated circuit can be increased, and the parasitic capacitance of the wires can be reduced. Therefore, the stability of the voltage supply or the stability of signal transmission can be improved.

[0135] Furthermore, electrical characteristics can be improved in semiconductor devices according to embodiments of the present disclosure.

[0136] The effects obtained from the embodiments of this disclosure are not limited to the effects described above, and those skilled in the art to which the embodiments of this disclosure pertain can clearly derive and understand other unmentioned effects from the following description.

[0137] Although this disclosure has been described with reference to embodiments thereof, those skilled in the art will understand that various changes and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Multiple memory cells, the multiple memory cells being located on the front surface of the substrate; A first back pattern is located on the back surface of the substrate; as well as The second back pattern is located on the back surface of the substrate. The first back pattern includes: A plurality of first grounding wires, the plurality of first grounding wires being arranged in a first direction and extending in a second direction intersecting the first direction; and Multiple power lines extending in the second direction. The plurality of first grounding wires and the plurality of power lines are arranged alternately in the first direction, and The second back pattern includes multiple back letter lines, which are arranged in the second direction and extend in the first direction.

2. The semiconductor device according to claim 1, wherein, The first back pattern is located between the back surface of the substrate and the second back pattern.

3. The semiconductor device according to claim 1, wherein, The second back pattern also includes: Multiple second grounding wires are arranged in the second direction and extend in the first direction. Among them, the multiple back-character lines are located between two adjacent second grounding lines among the multiple second grounding lines.

4. The semiconductor device according to claim 1, wherein, Each of the plurality of power lines overlaps with the central portion of one of the plurality of storage cells arranged along the second direction. Each of the plurality of storage cells includes a first end and a second end that are opposite to each other in the first direction, and Each of the plurality of first grounding wires overlaps with the first end or the second end of the storage cell arranged along the second direction.

5. The semiconductor device according to claim 1, wherein, Each of the plurality of storage units includes: A first pull-up transistor and a first pull-down transistor, the first pull-up transistor and the first pull-down transistor sharing a first gate electrode extending in the first direction; and The second pull-up transistor and the second pull-down transistor share a second gate electrode, and The second gate electrode extends in the first direction and is spaced apart from the first gate electrode in the second direction.

6. The semiconductor device according to claim 5, wherein, Each of the plurality of power lines includes a protruding terminal that overlaps with the first pull-up transistor and the second pull-up transistor.

7. The semiconductor device according to claim 5, wherein, Each of the multiple power lines is wavy and overlaps with the first pull-up transistor and the second pull-up transistor.

8. The semiconductor device according to claim 5, further comprising: Multiple first direct contacts extend to multiple source regions of the first pull-up transistor and the second pull-up transistor and are connected to the multiple power lines. Each of the plurality of storage units is connected to the plurality of power lines.

9. The semiconductor device according to claim 5, further comprising: Multiple second direct contacts extend into the source regions of the first pull-down transistor and the second pull-down transistor and are connected to the multiple first ground lines. Each of the storage cells is electrically connected to the plurality of first grounding wires.

10. The semiconductor device according to claim 1, further comprising: A first front pattern is located on the front surface of the substrate. The first front pattern includes: Multiple first front letter lines, said multiple first front letter lines being arranged in the first direction and extending in the second direction; and The first and second lines extend in the second direction and are located between two adjacent first front characters of the plurality of first front characters.

11. The semiconductor device according to claim 10, wherein, The plurality of first front letter lines intersect perpendicularly with the plurality of first ground lines.

12. The semiconductor device of claim 10, further comprising: The second front pattern is located on top of the first front pattern. The second front pattern includes multiple second front letter lines, which are arranged in the second direction and extend in the first direction. Among them, the multiple second front character lines intersect perpendicularly with the multiple back character lines.

13. The semiconductor device according to claim 12, further comprising: Multiple first through-paths connect the first ends of the multiple second front characters and the first ends of the multiple back characters, and also connect the second ends of the multiple second front characters and the second ends of the multiple back characters.

14. The semiconductor device according to claim 13, wherein, A subset of the storage cells in the plurality of storage cells are arranged in the first direction. Wherein, the first storage cell in the subset of the storage cells is spaced apart from the second storage cell in the subset of the storage cells, and The semiconductor device further includes: Multiple second through-paths are located between the first storage unit and the second storage unit, and connect the multiple second front letter lines and the multiple back letter lines.

15. The semiconductor device according to claim 1, wherein, Each of the plurality of storage units includes a static random access memory unit.

16. A semiconductor device, the semiconductor device comprising: Multiple memory cells, the multiple memory cells being located on the front surface of the substrate; A first back pattern is located on the back surface of the substrate; as well as The second back pattern is located on the back surface of the substrate. The first back pattern includes multiple first grounding wires, which are arranged in a first direction and extend in a second direction intersecting the first direction. The second back pattern includes multiple second grounding wires, which are arranged in the second direction and extend in the first direction. The plurality of second grounding wires are connected to the plurality of first grounding wires.

17. The semiconductor device of claim 16, wherein, Each of the plurality of second grounding wires is located in every 2 units of the plurality of storage cells arranged in the second direction. n Between the storage units, n is a natural number.

18. The semiconductor device according to claim 16, wherein, The second back pattern also includes a plurality of back letter lines arranged in the second direction and extending in the first direction, and Among them, 2 of the multiple back characters n The back-character line is located between two adjacent second grounding lines among the plurality of second grounding lines, where n is a natural number.

19. A semiconductor device, the semiconductor device comprising: Multiple memory cells, the multiple memory cells being located on a substrate; Signal back pattern, the signal back pattern being located on the back surface of the substrate; A first front pattern is located on the front surface of the substrate; A second front pattern, the second front pattern being located on the front surface of the first front pattern; and Multiple first through-paths, the multiple first through-paths connecting the signal back pattern and the second front pattern, The signal back pattern includes multiple back letter lines, which extend in a first direction and are arranged in a second direction intersecting the first direction. The first front pattern includes multiple first front letter lines, which are arranged in the first direction and extend in the second direction. The second front pattern includes multiple second front letter lines, which extend in the first direction and intersect the multiple back letter lines perpendicularly. The plurality of second front letter lines are connected to the plurality of first front letter lines, and The plurality of first through-paths connect the first ends of the plurality of second front characters and the first ends of the plurality of back characters, and also connect the second ends of the plurality of second front characters and the second ends of the plurality of back characters.

20. The semiconductor device of claim 19, wherein, A subset of the storage cells in the plurality of storage cells are arranged in the first direction. Wherein, the first storage cell in the subset of the storage cells is spaced apart from the second storage cell in the subset of the storage cells, and The semiconductor device further includes: Multiple second through-paths are located between the first storage unit and the second storage unit, and connect the multiple second front letter lines and the multiple back letter lines.

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