Pulse neural network acceleration method and device, equipment, storage medium and product
By sorting the presynaptic neurons in descending order of weights and comparing thresholds, and prioritizing the accumulation of important weights, the problems of low computational efficiency and high energy consumption of spiking neural networks are solved, thus achieving efficient neural network acceleration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-11-21
- Publication Date
- 2026-04-24
AI Technical Summary
Existing spiking neural network accelerators suffer from computational efficiency issues such as high overhead in binary adder search trees and neglect of weight importance, leading to redundant computations and high energy consumption.
By sorting presynaptic neurons in descending order of weight and using a threshold comparison mechanism during the stepwise accumulation process, important weights are accumulated first, and pulses are output only when the membrane potential exceeds the excitation threshold, thus reducing invalid computation.
It improves the signal propagation efficiency of neural networks, shortens network convergence time, reduces energy consumption, and significantly enhances computational efficiency and response capability.
Smart Images
Figure CN121920443A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of neural network technology, and for example to a method, apparatus, device, storage medium, and product for accelerating spiking neural networks. Background Technology
[0002] Deep artificial neural networks (ANNs) perform exceptionally well in image and speech processing, but they are extremely energy-intensive and difficult to deploy on edge devices. Spiking neural networks (SNNs), inspired by biology, use an event-driven model to simulate synaptic neurons, combining high prediction accuracy with low energy consumption. They represent an important direction for efficient computing, with their core mechanisms being "integration-firing of spiking neurons" and "spatiotemporal information encoding of spiking sequences."
[0003] While existing SNN accelerators (such as SATO) reduce the repeated accumulation of weights through time-parallel data streams, they suffer from the problem of "large overhead of binary adder search tree" and ignore the importance of weights (large weights contribute more significantly to membrane potential), resulting in redundant weight accumulation and threshold comparison, which leads to low computational efficiency.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.
[0006] This disclosure provides a method, apparatus, device, storage medium, and product for accelerating spiking neural networks. The method effectively solves the technical problem of computational efficiency in existing spiking neural networks by constructing an approximate computational model and a time-driven accelerator.
[0007] In some embodiments, a method for accelerating a spiking neural network is provided, comprising: The presynaptic neurons are sorted in descending order according to their weights; The weights of the activated presynaptic neurons are gradually accumulated into the membrane potential of the postsynaptic neurons according to the sorting order. During the gradual accumulation process, when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential, the postsynaptic neuron outputs a pulse.
[0008] In some embodiments, a spiking neural network acceleration device is provided, comprising: The reordering engine is used to sort presynaptic neurons in descending order according to their weights. The adder is used to progressively accumulate the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order. A comparator is used to cause the postsynaptic neuron to output a pulse when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential during a stepwise accumulation process.
[0009] In some embodiments, a computer device is provided, including: a processor and a memory storing program instructions, the processor being configured to execute the above-described spiking neural network acceleration method when running the program instructions.
[0010] In another aspect, a computer-readable storage medium is provided, on which program instructions are stored, which, when executed, perform the above-described spiking neural network acceleration method.
[0011] In another aspect, a computer program product is provided, which, when run by the processor of a computer device, executes the above-described spiking neural network acceleration method.
[0012] The spiking neural network acceleration method, apparatus, device, storage medium, and product provided in this disclosure can achieve the following technical effects: Presynaptic neurons are sorted in descending order of weight, allowing neurons with larger weights to be activated preferentially, thereby reducing unnecessary computation. The weights of the activated presynaptic neurons are gradually accumulated in the membrane potential of the postsynaptic neurons. Only when the membrane potential exceeds the activation threshold can the postsynaptic neuron output a pulse, avoiding the occurrence of invalid pulses. This method improves the signal propagation efficiency of the neural network by reducing invalid computation, shortens the network convergence time, thereby accelerating the operating speed and response capability of the neural network, reducing energy consumption, and significantly improving overall computational efficiency.
[0013] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description
[0014] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein: Figure 1 This is a schematic diagram of a spiking neural network acceleration method provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the process by which the weights of the activated presynaptic neurons are gradually accumulated into the membrane potential of the postsynaptic neurons, according to an embodiment of this disclosure. Figure 3 This is a schematic diagram of the spiking neural network activation process provided in an embodiment of this disclosure; Figure 4 This is another schematic diagram of the spiking neural network activation process provided in the embodiments of this disclosure; Figure 5 This is a hardware module diagram of the spiking neural network provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the postsynaptic neuron output pulse provided in an embodiment of this disclosure; Figure 7 This is another schematic diagram of a spiking neural network acceleration method provided in this embodiment of the present disclosure; Figure 8 This is a schematic diagram of a spiking neural network acceleration device provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of a spiking neural network acceleration device provided in an embodiment of this disclosure. Attached image description: 100: Reordering engine; 200: Adder; 300: Comparator. Detailed Implementation
[0016] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.
[0017] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.
[0018] Unless otherwise stated, the term "multiple" means two or more.
[0019] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.
[0020] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.
[0021] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.
[0022] Combination Figure 1 As shown, this disclosure provides a method for accelerating a spiking neural network, including: S101: Sort the presynaptic neurons in descending order according to their weights; S102: According to the sorting order, the weights of the activated presynaptic neurons are gradually accumulated into the membrane potential of the postsynaptic neurons. S103: During the gradual accumulation process, when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential, the postsynaptic neuron outputs a pulse.
[0023] To reduce the weight accumulation cycle of activated postsynaptic neurons, the method in this application adopts an early activation strategy based on weight importance awareness. It uses a fast sorting algorithm to sort the weights of presynaptic neurons offline in descending order, thereby obtaining the sorted weights and their corresponding indices.
[0024] The weights are reordered in descending order. When accumulating the weights, the weights are accumulated from largest to smallest. Then, the accumulated weights are compared with the activation threshold potential to determine whether activation is needed, thereby realizing the perception of the importance of the weights.
[0025] Among them, combined Figure 2 As shown, the stepwise accumulation of the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order includes: S201: When a presynaptic neuron receives an input pulse, the presynaptic neuron is activated; S202: Select the first presynaptic neuron in the sorting order as the current presynaptic neuron; S203: Determine whether the current presynaptic neuron is activated; S204: If so, the weight of the current presynaptic neuron is accumulated into the membrane potential of the postsynaptic neuron, and the next presynaptic neuron in the sorting order is updated to the current presynaptic neuron; S205: If not, update the next presynaptic neuron in the sorting order to the current presynaptic neuron; S206: Repeat the above process of determining whether the current presynaptic neuron is activated.
[0026] like Figure 3As shown, during the execution of a spiking neural network (SNN), the input pulse sequence at point t1 is first input into the presynaptic neuron u. i When the input pulse is "1", it indicates that the corresponding presynaptic neuron is activated. Further, based on steps S201 to S206, the weights of the currently activated presynaptic neurons are accumulated to the postsynaptic neuron u according to the weight sorting order. j membrane potential V mem middle.
[0027] like Figure 6 As shown, during the gradual accumulation process, when the membrane potential of the postsynaptic neuron is greater than the activation threshold potential, the postsynaptic neuron outputs a pulse, specifically including: S301: Accumulate the weight of the current presynaptic neuron into the membrane potential of the postsynaptic neuron, and determine whether the membrane potential is greater than the excitation threshold potential; S302: If the membrane potential is greater than the excitation threshold potential, the loop stops to determine whether the current presynaptic neuron is activated, and the postsynaptic neuron outputs a pulse; S303: If the membrane potential is not greater than the excitation threshold potential, continue the loop to determine whether the current presynaptic neuron is activated.
[0028] When it is determined in step S204 that the current presynaptic neuron is activated, the gradual accumulation process begins, and steps S301 to S303 are executed. Specifically, after each accumulation of the weight of the current presynaptic neuron into the membrane potential of the postsynaptic neuron, it is necessary to determine whether the membrane potential is greater than the activation threshold potential. The membrane potential V... mem With the excitation threshold potential V th Compare, if V mem Greater than V th The output pulse is 1, and the membrane potential of the postsynaptic neuron is reset to V. reset Conversely, the output pulse is 0. After t1 completes the calculation, the pulse sequence of t2 is processed in the same way, where the reset value V... reset It can be set according to actual needs.
[0029] After the input pulse sequence at time t1 is input, the input pulse sequence is rearranged according to the index of the sorted weights. Then, based on the rearranged input pulse sequence, the more important weights are preferentially accumulated on the membrane potential of the neuron, and the membrane potential V is set... mem With threshold potential V th Compare, if V mem Exceeding V ahead of time th This will generate non-zero pulses, eliminating the need to accumulate other weights, reducing the amount of computation and computational steps, and improving the calculation speed.
[0030] like Figure 3 As shown, at point t1, after the weights are reordered and the important weights W4 and W2 are accumulated, the membrane potential V... mem (1.05) has exceeded the threshold potential V. th (Assuming it is 1.0), the corresponding neurons can be activated in advance, without having to accumulate all the weights and then compare them to determine whether to activate them.
[0031] In this embodiment of the application, the step of accumulating the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order further includes: When the membrane potential of the postsynaptic neuron is lower than the premature termination threshold potential, the process of gradually accumulating the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neuron according to the sorting order stops.
[0032] like Figure 7 As shown, according to the sorting order, the weights of the activated presynaptic neurons are gradually accumulated to the membrane potential of the postsynaptic neurons, specifically as follows: S401: When the weighted number of the accumulated membrane potential of the postsynaptic neuron is the number of spikes, determine whether the membrane potential of the postsynaptic neuron is less than the premature termination threshold potential. S402: If so, then stop the process of gradually accumulating the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neurons according to the sorting order. S403: If not, continue with the process of gradually accumulating the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neurons according to the sorting order.
[0033] To address the problem of wasted computation cycles due to weight accumulation on neurons that are unlikely to be activated, the method in this application uses weight importance-aware early dismissal processing with a threshold comparison mechanism to adjust the membrane potential V. mem With early retirement threshold potential V sth The comparison showed that the premature withdrawal threshold potential was less than the excitation threshold potential (V0). sth <V th ).
[0034] The method in this embodiment prioritizes the accumulation and the number of spikes N. th A corresponding important weight, where the number of spikes can be set according to actual needs and the properties of the spiking neural network, and the current V... mem With V sth Compare, if V mem <V sth If this happens, the subsequent weight accumulation will be terminated early, because continuing to accumulate weights is ineffective for neuron firing.
[0035] like Figure 4 As shown, at time t2, two spikes (N) are accumulated. th After assigning weights (W2 and W5) to the values of =2, V mem (0.53) is still less than V sth (Assuming a value of 0.76), the subsequent weight accumulation is terminated and the process exits, saving two computation cycles. This significantly improves the computational efficiency and performance of the spiking neural network by reducing redundant computation, lowering energy consumption, and optimizing the neuron activation process.
[0036] In the field of speech processing, the spiking neural network acceleration method based on the embodiments of this application can realize speech signal processing and recognition, and improve the efficiency and accuracy of speech recognition.
[0037] The following is one implementation method used in speech processing: In speech signal processing, presynaptic neurons represent features in the speech signal, while postsynaptic neurons represent speech discrimination events. The system performs discrimination and classification based on speech features. First, speech features (such as MFCC features, intonation features, etc.) are extracted for each frame. These features include feature values and weights, where feature values represent key information, and weights indicate their importance in speech recognition. For example, features containing phoneme or intonation information are usually more important than background noise features. These speech features are arranged in descending order of importance, allowing more important features to be processed first.
[0038] In speech recognition, activated presynaptic neurons represent speech features in the processed audio frames. When a speech feature is activated, its weight gradually accumulates to the membrane potential of the postsynaptic neuron, at which point the postsynaptic neuron represents the speech discrimination event. For example, when processing a speech signal, important intonation changes are accumulated first, increasing the membrane potential and ensuring that key features can be quickly identified.
[0039] When the membrane potential gradually increases and exceeds the activation threshold, the postsynaptic neuron outputs a pulse to determine the category of the speech signal. This indicates that the speech signal has been recognized and passed to the next layer of the neural network. This process is equivalent to the recognition and classification of the speech signal's features. During speech processing, certain features (such as changes in intonation or the pronunciation of specific syllables) may quickly cause the membrane potential to exceed the threshold, thereby triggering pulse output and completing feature recognition.
[0040] In practical applications, the Spiking Neural Network (SNN) method can be used to rapidly identify important features in speech signals. SNNs operate, learn, and process information by mimicking the pulse transmission mechanism of neurons in the biological brain, making them particularly suitable for processing temporal signals such as speech. They reduce the interconnections between neurons, lowering model complexity and computational resource requirements, while simultaneously improving the temporal awareness of the neural network. Therefore, SNNs can efficiently classify and recognize speech based on the comparison of progressively accumulated weights and membrane potentials. By controlling the weight ranking and dynamic adjustment of membrane potentials, the speech recognition process not only improves computational efficiency but also reduces computational resource consumption and accelerates response speed by prematurely excluding the processing of less important features.
[0041] In speech recognition tasks, presynaptic neurons represent speech features (e.g., MFCC, pitch, speech frequency, etc.). When these features are activated and accumulate in postsynaptic neurons, the membrane potential increases. This process is similar to the processing of speech signals in neural networks: when a certain number of features (e.g., two spikes, i.e., syllables or key speech features) are input, the membrane potential begins to accumulate and is evaluated. If the membrane potential is less than the premature termination threshold, the speech feature is considered not to meet the expected discrimination criteria and may be noise or irrelevant information.
[0042] In speech processing, if the membrane potential is lower than the early termination threshold potential in certain parts of the speech signal (such as non-speech segments or background noise segments), it means that this part of the information does not contribute to the recognition result. Therefore, processing of the features in this part is stopped, and the remaining feature weights are no longer accumulated to avoid unnecessary calculations.
[0043] In the process of processing speech signals, suppose we are processing a speech signal with background noise. First, the system divides the speech signal into frames and extracts features, such as MFCC values. Each frame of feature values corresponds to a presynaptic neuron. The system sorts the features according to their weights (e.g., phoneme weights, intonation weights), prioritizing the processing of important features.
[0044] As features are activated one by one and accumulate to postsynaptic neurons, the membrane potential rises. If, during processing, two presynaptic neurons (corresponding to two important features, such as syllables) are activated, but the membrane potential has not yet reached the activation threshold potential, but has reached the premature termination threshold potential, the system will determine that the signal has no effect on the recognition result and will stop accumulating other irrelevant features.
[0045] The advantage of this approach is that it avoids influencing the recognition results with too many irrelevant features or noise information, reduces unnecessary computation and energy consumption, and thus improves the efficiency of the speech recognition system. Especially when processing large-scale data, it improves response speed and recognition accuracy by prematurely excluding unnecessary computations.
[0046] This process, through weighted sorting, membrane potential comparison, and early termination mechanism, ensures that only speech features that have a significant impact on the recognition results are processed, reducing the waste of computing resources and improving the efficiency and accuracy of recognition, especially when faced with speech signals containing noise or irrelevant information.
[0047] In summary, the acceleration method based on the above-mentioned spiking neural network can optimize the calculation steps, improve recognition efficiency, and reduce unnecessary calculation and energy consumption in speech processing, thereby improving the overall performance and speed of the speech recognition system.
[0048] In the field of image processing, the aforementioned spiking neural network acceleration method can be applied to image feature extraction and classification tasks.
[0049] The following is one implementation method used in image processing: In image processing tasks, presynaptic neurons represent image features, while postsynaptic neurons represent image discrimination events. Based on these features, images are classified and categorized. First, image features (such as edges, textures, and color histograms) are extracted. These features reflect important information from different parts of the image; for example, edge features are often more critical than background information. Therefore, in this step, these image features are sorted in descending order of their importance in the image classification task. Prominent features such as edges or corners are processed first, while less important features such as background noise are processed later.
[0050] In image recognition, each activated presynaptic neuron represents an extracted feature from the image (e.g., an edge or texture pattern). The weights of these features are progressively accumulated in the membrane potential of the postsynaptic neuron, indicating the importance of that feature in image classification. For example, when processing an image, the most crucial edge information is accumulated first, increasing the membrane potential of the postsynaptic neuron, thus ensuring that important features can be quickly identified.
[0051] When the membrane potential accumulates to a certain level and exceeds the activation threshold, the postsynaptic neuron outputs a pulse, indicating that an important feature in the image has been identified. This is similar to the identification of specific features in image classification. For example, in facial recognition technology, when the system effectively extracts and accumulates key facial features (such as eyes and nose) to a certain extent through a deep learning model, it outputs a pulse signal, which indicates that the image has been identified as a "face".
[0052] In image processing, by applying spiking neural networks (SNNs) to accelerate image processing, key features can be quickly identified, and classification can be performed efficiently based on progressively accumulated weights and comparisons of membrane potentials. By prioritizing important features and accumulating weights, the system can complete image classification tasks in a shorter time. By prematurely terminating the processing of unimportant features, the system reduces unnecessary computation, lowers computational resource consumption, and improves response speed. Using this method, image processing systems can significantly improve processing efficiency and reduce energy consumption when handling large-scale image data.
[0053] In summary, by employing spiking neural network acceleration technology, the computational steps in image processing tasks are optimized, significantly improving the efficiency of image recognition. This technology reduces unnecessary computation and energy consumption, thereby enhancing the overall performance and processing speed of the image classification system.
[0054] Combination Figure 8 Based on the above-described spiking neural network acceleration method, this disclosure provides a spiking neural network acceleration device, comprising: Reordering Engine 100 is used to sort presynaptic neurons in descending order according to their weights. Adder 200 is used to progressively accumulate the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order. Comparator 300 is used to enable the postsynaptic neuron to output a pulse when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential during the stepwise accumulation process.
[0055] The spiking neural network acceleration device provided in this disclosure sorts presynaptic neurons in descending order of weight, prioritizing the activation of neurons with larger weights and thus reducing unnecessary computation. The weights of the activated presynaptic neurons gradually accumulate in the membrane potential of the postsynaptic neurons. Only when the membrane potential exceeds the activation threshold does the postsynaptic neuron output a pulse, avoiding the occurrence of invalid pulses. This method improves the signal propagation efficiency of the neural network by reducing invalid computation, shortens the network convergence time, thereby accelerating the operation speed of the neural network, enhancing its responsiveness, and reducing energy consumption, significantly improving the overall computational efficiency.
[0056] To ensure the accuracy of data analysis and the scientific nature of decision-making, this application designs a dedicated processing unit (PE). This unit integrates an adder, a comparator, and a weight reordering engine to achieve efficient weight accumulation and threshold comparison. Figure 5 As shown, these components work together to ensure the correct access to and accumulation of effective weights, thereby triggering and deactivating weight importance awareness in advance.
[0057] The global buffer stores the input pulse sequences of all layers in the spiking neural network, the sorted weights, and the indices of these sorted weights.
[0058] Each processing unit (PE) in the system is responsible for performing weight accumulation and comparing the neuron membrane potential with the threshold potential.
[0059] The reordering engine prioritizes the accumulation of important weights. It strategically retrieves input pulses based on the indices of already sorted weights, and these pulses are then stored sequentially in the reordered input buffer. To reduce reordering latency, the reordering engine includes multiple comparators and allocators, enabling simultaneous reordering of multiple weight indices and input pulses.
[0060] An early exit mechanism is implemented using two comparators (① and ②) and a counter. The counter tracks the number of spikes (N) processed, and exits once N reaches a predefined threshold N0. th The comparator (②) will then be activated, and this comparator is responsible for converting the current membrane potential V... mem With predefined threshold V sth Compare, if V mem Below V sth This indicates that continuing to accumulate weights is unlikely to cause the neuron to fire, thus triggering premature exit.
[0061] The input pulse sequence is reorganized by the reordering engine and stored in the reordering input buffer. Subsequently, the weights corresponding to the reordered pulse sequence are retrieved from the weight buffer and accumulated in the adder to generate the membrane potential V. mem V mem It is simultaneously transmitted to two comparators (③ and ②), which are responsible for converting V... mem respectively with V th and V sth The comparison is performed. Once the comparator (③) outputs a positive signal, the output pulse is 1, and V... mem It will be reset to V reset Conversely, the output pulse is 0.
[0062] The input pulse sequence, sorted weights, and their indices are loaded from DRAM into a global buffer. Each processing unit retrieves its corresponding weights and indices from the global buffer and performs one layer of inference. After a processing unit completes its task, the output pulse sequence moves to the next column, thus beginning the next layer of inference. Inference at all time steps is pipelined, and the final inference results are collected and stored in the output buffer.
[0063] Given that the solutions and methods for solving the problem are similar, the specific implementation of the device in the embodiments of this specification can be referred to the foregoing method embodiments, and will not be repeated here.
[0064] Combination Figure 9 As shown, this disclosure provides a spiking neural network acceleration device, including a processor 904 and a memory 901. Optionally, the device may further include a communication interface 902 and a bus 903. The processor 904, communication interface 902, and memory 901 can communicate with each other via the bus 903. The communication interface 902 can be used for information transmission. The processor 904 can call logical instructions in the memory 901 to execute the spiking neural network acceleration method of the above embodiment.
[0065] Furthermore, the logic instructions in the aforementioned memory 901 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.
[0066] The memory 901, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 904 executes functional applications and data processing by running the program instructions / modules stored in the memory 901, thereby implementing the spiking neural network acceleration method in the above embodiments.
[0067] The memory 901 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 901 may include high-speed random access memory and may also include non-volatile memory.
[0068] This disclosure provides a computer program product, which is a software product that mainly implements the methods described in this specification through a computer program.
[0069] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute the above-described spiking neural network acceleration method.
[0070] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.
[0071] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.
[0072] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.
[0073] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0074] The methods and products disclosed in the embodiments herein (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. In addition, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0075] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks, and the operations or steps corresponding to different blocks in the flowchart and block diagram descriptions, may occur in a different order than indicated in the drawings or descriptions. For example, two consecutive blocks or operation steps may actually be executed substantially in parallel, or sometimes in reverse order, depending on the functions involved. Sometimes there is no specific order between different operations or steps. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.
Claims
1. A method for accelerating spiking neural networks, characterized in that, include: The presynaptic neurons are sorted in descending order according to their weights; The weights of the activated presynaptic neurons are gradually accumulated into the membrane potential of the postsynaptic neurons according to the sorting order. During the gradual accumulation process, when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential, the postsynaptic neuron outputs a pulse.
2. The method according to claim 1, characterized in that, The step of progressively accumulating the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order includes: When a presynaptic neuron receives an input pulse, the presynaptic neuron is activated; The first presynaptic neuron in the sorting order is taken as the current presynaptic neuron; Determine whether the current presynaptic neuron is activated; If so, the weight of the current presynaptic neuron is accumulated into the membrane potential of the postsynaptic neuron, and the next presynaptic neuron in the sorting order is updated to the current presynaptic neuron; If not, then update the next presynaptic neuron in the sorting order to the current presynaptic neuron; Repeat the above process of determining whether the current presynaptic neuron is activated.
3. The method according to claim 2, characterized in that, During the gradual accumulation process, when the membrane potential of the postsynaptic neuron is greater than the activation threshold potential, the postsynaptic neuron outputs a pulse, specifically including: The weight of the current presynaptic neuron is accumulated into the membrane potential of the postsynaptic neuron, and it is determined whether the membrane potential is greater than the excitation threshold potential. If the membrane potential is greater than the excitation threshold potential, the loop stops to determine whether the current presynaptic neuron is activated, and the postsynaptic neuron outputs a pulse. If the membrane potential is not greater than the activation threshold potential, the loop continues to determine whether the current presynaptic neuron is activated.
4. The method according to any one of claims 1-3, characterized in that, The postsynaptic neuron outputs a pulse, which then includes: The membrane potential of the postsynaptic neuron is reset.
5. The method according to claim 1, characterized in that, The step of accumulating the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order further includes: When the membrane potential of the postsynaptic neuron is less than the premature termination threshold potential, the process of gradually accumulating the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neuron according to the sorting order is stopped.
6. The method according to claim 5, characterized in that, The process of stopping the gradual accumulation of the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neurons according to the sorting order when the membrane potential of the postsynaptic neuron is less than the early termination threshold potential includes: When the weighted number of the accumulated membrane potential of the postsynaptic neuron is equal to the number of spikes, it is determined whether the membrane potential of the postsynaptic neuron is less than the premature termination threshold potential. If so, then the process of gradually accumulating the weights of the activated presynaptic neurons to the membrane potential of the postsynaptic neurons according to the sorting order is stopped.
7. A spiking neural network acceleration device, characterized in that, include: The reordering engine is used to sort presynaptic neurons in descending order according to their weights. The adder is used to progressively accumulate the weights of the activated presynaptic neurons into the membrane potential of the postsynaptic neurons according to the sorting order. A comparator is used to cause the postsynaptic neuron to output a pulse when the membrane potential of the postsynaptic neuron is greater than the excitation threshold potential during a stepwise accumulation process.
8. A spiking neural network acceleration device, characterized in that, The device includes a processor and a memory storing program instructions, characterized in that the processor is configured to execute the spiking neural network acceleration method as described in any one of claims 1 to 6 when running the program instructions.
9. A computer-readable storage medium storing program instructions, characterized in that, When the program instructions are executed, they perform the spiking neural network acceleration method as described in any one of claims 1 to 6.
10. A computer program product, characterized in that, When the computer program product is run by the processor of a computer device, it executes the spiking neural network acceleration method according to any one of claims 1-6.