Display panel, driving method thereof and display device

Abstract

The embodiment of the invention provides a display panel, a driving method thereof and a display device, relates to the technical field of display, and aims to improve the display effect. The display panel comprises a pixel circuit, the pixel circuit comprises a driving module, a light emitting control module and a reset module, and the driving module is coupled with a first node, a second node and a third node. The first node is coupled to a first power signal end, the second node is coupled to a light emitting device, and the third node is coupled to a data signal end. The light-emitting control module is coupled with the first node, the first power supply signal end and the light-emitting control signal end. The reset module is coupled with the second node, a reset signal end and an initialization signal end. Wherein the driving module and the light-emitting control module are configured to control the first power supply signal end to be conducted with the second node in a reset stage. And the reset stage of one row of pixel circuits and the light emitting stage of at least one row of pixel circuits adjacent to the row of pixel circuits are staggered. The display panel is used for the display device.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the rapid development of display technology, display devices have gradually become ubiquitous in people's lives. Among them, organic light-emitting diodes (OLEDs) are widely used in smart products such as mobile phones, televisions, laptops, virtual reality (VR), and augmented reality (AR) due to their advantages such as self-illumination, low power consumption, wide viewing angle, fast response speed, high contrast, and flexible display.

[0003] In related technologies, the pixels of a display device include OLEDs and pixel circuits connected to the OLEDs. The output current of the driving transistors in the pixel circuits is used to drive the corresponding OLED to emit light, determining the brightness of the OLED. However, during the display process, the displayed image exhibits flickering. Summary of the Invention

[0004] The purpose of the embodiments disclosed herein is to provide a display panel and its driving method and display device, for reducing the flicker value of the display panel and improving the problem of flickering in the display screen.

[0005] On one hand, a display panel is provided. The display panel includes multiple pixel circuits arranged in multiple rows and columns. Each pixel circuit includes a light-emitting stage and a reset stage, with the light-emitting stage following the reset stage. The pixel circuit also includes a driving module, a light-emitting control module, and a reset module.

[0006] The driving module is coupled to a first node, a second node, and a third node. The first node is coupled to a first power signal terminal, the second node is coupled to a light-emitting device, and the third node is coupled to a data signal terminal. The driving module is configured to generate a driving current signal in response to the voltages of the first node and the third node during the light-emitting phase.

[0007] The light-emitting control module is coupled to the first node, the first power signal terminal, and the light-emitting control signal terminal. The light-emitting control module is configured to, during the light-emitting phase, control the transmission of the drive current signal to the second node in response to the light-emitting control signal at the light-emitting control signal terminal.

[0008] The reset module is coupled to the second node, a reset signal terminal, and an initialization signal terminal. The reset module is configured to, during the reset phase, transmit an initialization signal from the initialization signal terminal to the second node in response to a reset signal from the reset signal terminal.

[0009] The driving module and the light-emitting control module are further configured to, during the reset phase, control the first power supply signal terminal to be connected to the second node in response to the voltage of the third node and the light-emitting control signal of the light-emitting control signal terminal. Furthermore, the reset phase of a row of pixel circuits is staggered from the light-emitting phase of at least one row of pixel circuits adjacent to that row.

[0010] In the display panel provided by the embodiments of this disclosure, when a row of pixel circuits is in the reset phase, the light-emitting devices of at least one adjacent row of pixel circuits do not emit light, and fluctuations in the first power signal do not affect the light emission of the light-emitting devices of at least one adjacent row of pixel circuits. In other words, when the light-emitting devices of at least one row of pixel circuits adjacent to the target row emit light, since the pixel circuits of the target row are not in the reset phase, the first power signal will not be affected by the reset phase of the target row and will not fluctuate. This can reduce the fluctuation in the brightness of the light-emitting devices of at least one row of pixel circuits adjacent to the target row, reduce the flicker value of the display panel, and improve the problem of flickering in the displayed image.

[0011] In some embodiments, there are at least two adjacent rows of pixel circuits, and the reset phase of the bottommost row of pixel circuits is staggered from the light-emitting phase of the other rows of pixel circuits.

[0012] In some embodiments, the pixel circuit further includes a data writing stage located between the light-emitting stage and the reset stage. The pixel circuit also includes a data writing module coupled to the third node, the data signal terminal, and the scan signal terminal. The data writing module is configured to, during the data writing stage, transmit a data signal from the data signal terminal to the third node in response to a control signal from the scan signal terminal. During the reset stage, it transmits a data signal from the data signal terminal to the third node in response to a control signal from the scan signal terminal. At least two adjacent rows of the pixel circuits exist, with the reset stage of the bottommost row of pixel circuits located between the data writing stage and the light-emitting stage of the other rows.

[0013] In some embodiments, in at least two adjacent rows of pixel circuits, the uppermost row of pixel circuits has its light-emitting phase staggered from that of the other rows of pixel circuits.

[0014] In some embodiments, the pixel circuit further includes a black insertion phase, which is located before the reset phase. The light-emitting control module is further configured to, during the black insertion phase, control the drive current signal not to be transmitted to the light-emitting device in response to a light-emitting control signal at the light-emitting control signal terminal. Specifically, there are at least two adjacent rows of the pixel circuits, with the reset phase of the topmost row of pixel circuits occurring within the black insertion phases of the other rows.

[0015] In some embodiments, the reset module is further configured to, during the black-out insertion phase, transmit the initialization signal of the initialization signal terminal to the second node in response to the reset signal of the reset signal terminal.

[0016] On the other hand, a driving method is provided. The driving method is applied to the display panel described in any of the above embodiments, and the driving method includes:

[0017] During the light-emitting phase, the driving module generates a driving current signal in response to the voltages of the first node and the third node. The light-emitting control module, in response to the light-emitting control signal at the light-emitting control signal terminal, controls the transmission of the driving current signal to the second node.

[0018] During the reset phase, the driving module responds to the voltage of the third node, and the light-emitting control module responds to the light-emitting control signal at the light-emitting control signal terminal, controlling the first power signal terminal to conduct with the second node. The reset module responds to the reset signal at the reset signal terminal and transmits the initialization signal at the initialization signal terminal to the second node. The reset phase of one row of pixel circuits is staggered from the light-emitting phase of at least one row of pixel circuits adjacent to that row.

[0019] In some embodiments, the pixel circuit further includes a data writing stage located between the light-emitting stage and the reset stage. The pixel circuit also includes a data writing module coupled to the third node, the data signal terminal, and the scan signal terminal.

[0020] The driving method further includes: during the data writing phase, the data writing module, in response to the control signal at the scanning signal terminal, transmits the data signal at the data signal terminal to the third node. During the reset phase, the data writing module, in response to the control signal at the scanning signal terminal, transmits the data signal at the data signal terminal to the third node. There are at least two adjacent rows of pixel circuits, and the reset phase of the bottommost row of pixel circuits is located between the data writing phase and the light emission phase of the other rows.

[0021] In some embodiments, the pixel circuit further includes a black-insertion phase, which is located before the reset phase. The driving method further includes: during the black-insertion phase, the light-emitting control module, in response to a light-emitting control signal at the light-emitting control signal terminal, controls the driving current signal not to be transmitted to the light-emitting device. The reset module, in response to a reset signal at the reset signal terminal, transmits an initialization signal from the initialization signal terminal to the second node. Wherein, there are at least two adjacent rows of the pixel circuits, and the reset phase of the topmost row of the pixel circuits is located within the black-insertion phases of the other rows.

[0022] In another aspect, a display device is provided. The display device includes the display panel described in any of the above embodiments.

[0023] The driving method and display device of the above-described display panel have the same structure and beneficial technical effects as the display panels provided in some of the above embodiments, and will not be described again here. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams.

[0025] Figure 1 This is a schematic diagram of the structure of a display device according to some embodiments;

[0026] Figure 2 This is a schematic diagram of the structure of another display device according to some embodiments;

[0027] Figure 3 This is a block diagram of a display device according to some embodiments;

[0028] Figure 4 This is a schematic diagram of the structure of a display panel according to some embodiments;

[0029] Figure 5 A circuit diagram of a sub-pixel according to some embodiments;

[0030] Figure 6 A timing diagram of a pixel circuit according to some embodiments;

[0031] Figure 7 A timing diagram of another pixel circuit according to some embodiments;

[0032] Figure 8 A timing diagram of another pixel circuit according to some embodiments;

[0033] Figure 9 This is a timing diagram of yet another pixel circuit according to some embodiments;

[0034] Figure 10 This is a timing diagram of yet another pixel circuit according to some embodiments. Detailed Implementation

[0035] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0036] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0037] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0038] The terms "coupled" and "connected," and their derivatives, may be used in describing some embodiments. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0039] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0040] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0041] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0042] As used herein, “equal” includes the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “equal” includes absolute equality and approximate equality, wherein an acceptable range of deviation for approximate equality may be, for example, a difference between the two equal entities being less than or equal to 5% of either one.

[0043] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0044] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0045] This document describes exemplary embodiments with reference to plan views as idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0046] In this disclosure, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0047] In the circuits provided in the embodiments of this disclosure, the first node, the second node, and the third node do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0048] The transistors used in the circuits provided in the embodiments of this disclosure can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors) or other switching devices with the same characteristics. The embodiments of this disclosure are all described using thin-film transistors as an example.

[0049] In some embodiments, the control terminal of each transistor used in the shift register is the gate of the transistor, the first terminal is one of the source and drain of the transistor, and the second terminal is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable; that is, the first and second terminals of the transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal is the source and the second terminal is the drain; for example, when the transistor is an N-type transistor, the first terminal is the drain and the second terminal is the source.

[0050] In the circuits provided in the embodiments of this disclosure, P-type transistors are used as an example for illustration. It should be noted that the embodiments of this disclosure include, but are not limited to, this. For example, one or more transistors in the circuits provided in the embodiments of this disclosure can also be N-type transistors, simply by connecting the terminals of the selected type of transistor in accordance with the terminals of the corresponding transistors in the embodiments of this disclosure, and providing the corresponding high or low voltage at the corresponding voltage terminals.

[0051] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which can be any device that displays images, whether moving (e.g., video) or fixed (e.g., still images) and whether it is text or images.

[0052] For example, see Figure 1 and Figure 2The display device 1000 can be any product or component with display function, such as portable display products, wearable devices, televisions, computers, flight displays, in-vehicle displays, clocks, virtual reality (VR) devices, augmented reality (AR) devices, signs, and billboards.

[0053] For example, such as Figure 1 As shown, the display device 1000 can be Figure 1 The mobile phone shown. For example, see [link to relevant documentation]. Figure 2 The display device 1000 can be Figure 2 The VR device shown.

[0054] It should be noted that, depending on the application scenario, the display device 1000 can be a flat display device, a curved display device, or a foldable display device, etc., and the shape of the display surface of the display device 1000 can be any of a circle, an ellipse, a polygon, or an irregular shape. The embodiments disclosed herein are not limited to these.

[0055] In some embodiments, see Figure 2 and Figure 3 The display device 1000 may include one or more display panels 100. For example, such as... Figure 3 As shown, the display device 1000 includes two display panels 100. It should be noted that... Figure 3 Taking two display panels 100 as an example, the number of display panels included in the display device 1000 is not limited to this, nor is their position limited. Figure 3 For example, when the display device 1000 consists of four display panels 100, the four display panels 100 can form a two-row, two-column display panel array.

[0056] The display panel 100 described above includes various types, which can be selected and configured according to actual needs. For example, the display panel 100 can be: an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a micro light-emitting diode (Micro LED) display panel, a silicon-based Micro OLED display panel, a sub-millimeter light-emitting diode (Mini Light Emitting Diode) display panel, etc., and the embodiments disclosed herein are not limited to these.

[0057] The following description uses a silicon-based Micro OLED display panel as an example to illustrate some embodiments of this disclosure. The embodiments of this disclosure are not limited thereto, and any other display panel can be considered as long as the same technical concept is applied.

[0058] In some embodiments, see Figure 3 The display device 1000 may further include a host 200, with the display panel 100 connected to the host 200. The host 200 controls the display panel 100 to transmit display signals to both display panels 100 and controls the images displayed on both display panels 100. The host 200 may be a separate circuit board, or it may be an electronic device such as a TV box, server, mobile phone, or tablet. The embodiments disclosed herein are not limited to these.

[0059] The host 200 can, for example, control the display panel 100 to display different images to match the left and right eyes of a person, so that the human eye can obtain this information with differences and generate a sense of three-dimensionality in the mind, thus realizing VR / AR display.

[0060] In some embodiments, see Figure 4 The display panel 100 has a display area A, which is an area for displaying images. The display area A is configured to set multiple sub-pixels P, which can be understood as the smallest light-emitting unit in the display panel 100.

[0061] For example, such as Figure 4 As shown, display area A is provided with multiple sub-pixels P, which are arranged in multiple rows and columns. Each row includes at least two sub-pixels P arranged along the first direction X, and each column includes at least two sub-pixels P arranged along the second direction Y.

[0062] It should be noted that the first direction X is the row direction of the arrangement of multiple sub-pixels P, and the second direction Y is the column direction of the arrangement of multiple sub-pixels P. The first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular.

[0063] Among them, see Figure 4 Multiple sub-pixels P can include various sub-pixels P with different emission colors to achieve full-color display. For example, multiple sub-pixels P include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B, where the emission colors of the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are the three primary colors; for example, the emission color of the first sub-pixel R is red, the emission color of the second sub-pixel G is green, and the emission color of the third sub-pixel B is blue.

[0064] In some embodiments, see Figure 4 The display panel 100 also includes a peripheral area B, which is disposed on at least one side of the display area A. Figure 4 The diagram illustrates the arrangement of the surrounding area B around the display area A.

[0065] The peripheral area B is an area where no image is displayed. It is configured to set up driving circuits and circuit traces, such as gate driving circuit 101 and source driving circuit 102.

[0066] For example, such as Figure 4 As shown, the display panel 100 also includes a gate driving circuit 101, a source driving circuit 102, multiple gate lines GL, and multiple data lines DL.

[0067] The gate line GL extends along the first direction X, and the same control signal terminals (such as the light emission control signal terminal DS, reset signal terminal AZ, and scan signal terminal WS mentioned below) in the same row of sub-pixels P can be electrically connected to a gate line GL. The data line DL extends along the second direction Y, and the data signal terminals in the same row of sub-pixels P can be connected to the same data line DL to scan each row of sub-pixels P row by row.

[0068] In some embodiments, see Figure 4 and Figure 5 The sub-pixel P includes a pixel circuit 10 and a light-emitting device 20. The pixel circuit 10 is connected to the light-emitting device 20 to drive the light-emitting device 20 to emit light. The light-emitting device can be, for example, an OLED.

[0069] In some examples, see Figure 5 and Figure 6 The pixel circuit 10 may include a driving module 11, a light-emitting control module 12, and a reset module 13. The pixel circuit 10 includes a light-emitting stage P1 and a reset stage P2, with the reset stage P2 preceding the light-emitting stage P1.

[0070] like Figure 5 and Figure 6 As shown, the driving module 11 is coupled to a first node N1, a second node N2, and a third node N3. The first node N1 is coupled to a first power signal terminal VDD, the second node N2 is coupled to the anode of the light-emitting device 20, the cathode of the light-emitting device 20 can be connected to a second power signal terminal VSS, and the third node N3 is coupled to a data signal terminal D. The driving module 11 is configured to generate a driving current signal in response to the voltages of the first node N1 and the third node N3 during the light-emitting phase P1.

[0071] For example, such as Figure 5 As shown, the driving module 11 may include a first transistor T1, the first electrode of the first transistor T1 is connected to the first node N1, the second electrode is connected to the second node N2, and the control electrode is connected to the third node N3.

[0072] like Figure 5 and Figure 6 As shown, the light-emitting control module 12 is coupled to the first node N1, the first power supply signal terminal VDD, and the light-emitting control signal terminal DS. The light-emitting control module 12 is configured to, in the light-emitting phase P1, control the transmission of the drive current signal to the second node N2 in response to the light-emitting control signal at the light-emitting control signal terminal DS.

[0073] For example, such as Figure 5 As shown, the light emission control module 12 may include a second transistor T2. The first terminal of the second transistor T2 is connected to the first power supply signal terminal VDD, the second terminal is connected to the first node N1, and the control terminal is connected to the light emission control signal terminal DS.

[0074] like Figure 5 and Figure 6 As shown, the reset module 13 is coupled to the second node N2, the reset signal terminal AZ, and the initialization signal terminal Vinit. The reset module 13 is configured to, in the reset phase P2, in response to the reset signal of the reset signal terminal AZ, transmit the initialization signal of the initialization signal terminal Vinit to the second node N2 to reset the second node N2 and eliminate the voltage influence of the previous frame.

[0075] For example, such as Figure 5 As shown, the reset module 13 may include a third transistor T3. The first terminal of the third transistor T3 is connected to the initialization signal terminal Vinit, the second terminal is connected to the second node N2, and the control terminal is connected to the reset signal terminal AZ.

[0076] Furthermore, the driving module 11 and the light-emitting control module 12 are configured to, during the reset phase P2, control the first power supply signal terminal VDD to conduct with the second node N2 in response to the voltage of the third node N3 and the light-emitting control signal of the light-emitting control signal terminal DS. At this time, since the initialization signal terminal Vinit is conducted with the second node N2 during the reset phase P2, the first power supply signal terminal VDD is also conducted with the initialization signal terminal Vinit.

[0077] In some examples, see Figure 5 The pixel circuit 10 may include a data writing module 14 and a storage module 15. The pixel circuit 10 also includes a data writing stage P3 and a self-discharge stage P4. The data writing stage P3 is located between the reset stage P2 and the light-emitting stage P1, and the self-discharge stage P4 is located between the reset stage P2 and the data writing stage P3.

[0078] like Figure 5 and Figure 6As shown, the data writing module 14 is coupled to the data signal terminal D, the third node N3, and the scan signal terminal WS. The data writing module 14 is configured to, in the data writing phase P3, respond to the scan signal of the scan signal terminal WS, control the data signal of the data signal terminal D to write to the third node N3 to generate a drive current; and in the reset phase P2, respond to the scan signal of the scan signal terminal WS, control the data signal of the data signal terminal D to write to the third node N3 to reset the third node N3. The data writing phase P3 is located between the reset phase P2 and the light emission phase P1.

[0079] For example, such as Figure 5 As shown, the data writing module 14 may include a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the data signal terminal D, the second terminal is connected to the third node N3, and the control terminal is connected to the scan signal terminal WS.

[0080] like Figure 5 and Figure 6 As shown, the storage module 15 is coupled to the first power signal terminal VDD, the first node N1, and the third node N3. The storage module 15 is configured to, during the self-discharge phase P4, adjust the voltage difference between the first node N1 and the third node N3 until the voltage difference between the first node N1 and the third node N3 is equal to the threshold voltage of the first transistor T1 of the drive module 11, so as to compensate for the threshold voltage of the first transistor T1 and eliminate the substrate bias effect of the first transistor T1.

[0081] For example, such as Figure 5 As shown, the storage module 15 may include a first capacitor C1 and a second capacitor C2. The first plate of the first capacitor C1 is connected to the first power signal terminal VDD, and the second plate is connected to the first node N1. The first plate of the second capacitor C2 is connected to the first node N1, and the second plate is connected to the third node N3.

[0082] The following uses the structure of pixel circuit 10 as an example. Figure 5 Taking the "4T2C" example shown, and combining it with Figure 6 The timing diagrams provided illustrate the various stages of the pixel circuit 10 described above, but the embodiments disclosed herein are not limited thereto.

[0083] During the reset phase P2, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned on to reset the first node N1, the second node N2, and the third node N3.

[0084] During the self-discharge phase P4, the second transistor T2 and the fourth transistor T4 are turned off, while the first transistor T1 and the third transistor T3 are turned on. The first node N1 continues to discharge until the voltage difference between the third node N and the first node N1 equals the threshold voltage of the first transistor T1, in order to compensate for the threshold voltage of the first transistor T1.

[0085] During the data writing phase P3, the first transistor T1 and the second transistor T2 are turned off, while the third transistor T3 and the fourth transistor T4 are turned on, writing the data signal to the third node N.

[0086] During the light-emitting stage P1, the third transistor T3 and the fourth transistor T4 are turned off, while the first transistor T1 and the second transistor T2 are turned on. Under the control of the voltages of the first node N1 and the third node N3, the first transistor T1 generates a driving current, which is transmitted to the light-emitting device 20 to drive the light-emitting device 20 to emit light.

[0087] The inventors discovered that in the related display panel, during the reset phase of the pixel circuits in a row of sub-pixels, the pixel circuits of adjacent rows of sub-pixels are in the light-emitting phase. At this time, because the first power signal terminal and the initialization signal terminal are connected during the reset phase, the first power signal transmitted by the first power signal terminal fluctuates. Simultaneously, since the first power signal terminals of all pixel circuits are connected to the same power line, the first power signal transmitted by the first power signal terminals of adjacent rows of sub-pixels in the light-emitting phase also fluctuates, causing fluctuations in the brightness of that row of sub-pixels and resulting in a flickering display.

[0088] Based on this, see Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 In some embodiments of the present disclosure, the display panel 100 has at least one reset phase P2 of a row of pixel circuits 10 that is offset from the light emission phase P1 of the adjacent at least one row of pixel circuits 10.

[0089] In this scenario, when a row of pixel circuits 10 is in reset phase P2, the light-emitting devices 20 of at least one adjacent row of pixel circuits 10 do not emit light. The fluctuations in the first power signal do not affect the light emission of the light-emitting devices 20 of the adjacent row of pixel circuits 10. In other words, when the light-emitting devices 20 of at least one row of pixel circuits 10 adjacent to the target row emit light, since the pixel circuits 10 of that target row are not in reset phase P2, the first power signal will not be affected by the reset phase P2 of that target row and thus will not fluctuate. This reduces the fluctuation in the brightness of the light-emitting devices 20 of the at least one row of pixel circuits 10 adjacent to the target row, lowers the flicker value of the display panel 100, and improves the problem of flickering in the displayed image.

[0090] It should be noted that the target row mentioned above refers to a row of pixel circuits 10 whose reset phase P2 is offset from the light emission phase P1 of at least one adjacent row of pixel circuits 10.

[0091] In some embodiments, see Figure 5 , Figure 6 and Figure 7 There are at least two adjacent rows of pixel circuits 10, where the reset phase P2 of the bottommost row of pixel circuits 10 is staggered from the light-emitting phase P1 of the other rows of pixel circuits 10. In this case, when the bottommost row of pixel circuits 10 is in reset phase P2, the light-emitting devices 20 of the other rows of pixel circuits 10 do not emit light. That is, the fluctuation in the first power signal caused by the bottommost row of pixel circuits 10 in reset phase P2 will not affect the light emission of the light-emitting devices 20 of the other rows of pixel circuits 10. Since the bottommost row of pixel circuits 10 is not in reset phase P2, the first power signal will not fluctuate due to the reset phase P2 of the bottommost row of pixel circuits 10, which can reduce the fluctuation of the light emission brightness of the light-emitting devices 20 of the other rows of pixel circuits 10, reduce the flicker value of the display panel 100, and improve the problem of flickering in the display screen.

[0092] It should be noted that the other rows mentioned above refer to the other rows of pixel circuits 10, excluding the bottommost row of pixel circuits 10, which are at least two adjacent rows of pixel circuits 10.

[0093] For example, see Figure 5 , Figure 6 and Figure 7There are at least two adjacent rows of pixel circuits 10, with the reset phase P2 of the bottommost row of pixel circuits 10 located between the data writing phase P3 and the light emission phase P1 of the other rows. At this time, there are at least two adjacent rows of pixel circuits 10, with the reset phase P2 of the bottommost row of pixel circuits 10 located between the data writing phase P3 and the light emission phase P1 of the other rows, so that the reset phase P2 of the bottommost row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10.

[0094] For example, see Figure 5 and Figure 6 In each pair of adjacent pixel circuits 10, the reset phase P2 of the lower row of pixel circuits 10 is between the data writing phase P3 and the light emission phase P1 of the upper row of pixel circuits 10. In this case, the pixel circuits 10 in the same column can be connected to the same data line DL, and interference can be avoided between the lower row of pixel circuits 10 resetting the third node N3 using a data signal (carrying the initial data voltage for reset) in the reset phase P2 and the upper row of pixel circuits 10 writing a data signal (carrying the grayscale data voltage for light emission) to the third node N3 in the data writing phase P3. Here, the other rows are the upper row of pixel circuits 10 in each pair of adjacent pixel circuits 10.

[0095] For example, in each of three adjacent rows of pixel circuits 10, the reset phase P2 of the bottom row of pixel circuits 10 is between the data writing phase P3 and the light emission phase P1 of the two rows of pixel circuits 10 above. In this case, the pixel circuits 10 in the same column can be connected to the same data line DL, and interference can be avoided between the reset of the third node N3 by the bottom row of pixel circuits 10 using data signals (carrying the initial data voltage for reset) in the reset phase P2 and the writing of data signals (carrying the grayscale data voltage for light emission) to the third node N3 by the two rows of pixel circuits above in the data writing phase P3. Here, the other rows are the two rows of pixel circuits 10 located at the top of the three adjacent rows of pixel circuits 10.

[0096] In some examples, such as Figure 5 and Figure 6 As shown, the display panel 100 has a plurality of L rows of pixel circuits 10. In each pair of adjacent rows of pixel circuits 10, the reset phase P2 of the lower row of pixel circuits 10 is staggered from the light-emitting phase P1 of the upper row of pixel circuits 10.

[0097] in, Figure 6The diagram uses a three-row pixel circuit as an example. DS-1 represents the waveform of the light emission control signal of the first row pixel circuit 10, DS-2 represents the waveform of the light emission control signal of the second row pixel circuit 10, and DS-3 represents the waveform of the light emission control signal of the third row pixel circuit 10. WS-1 represents the waveform of the scan signal of the first row pixel circuit 10, WS-2 represents the waveform of the scan signal of the second row pixel circuit 10, and WS-3 represents the waveform of the scan signal of the third row pixel circuit 10. AZ-1 represents the waveform of the reset signal of the first row pixel circuit 10, AZ-2 represents the waveform of the reset signal of the second row pixel circuit 10, and AZ-3 represents the waveform of the reset signal of the third row pixel circuit 10.

[0098] In this situation, in every two adjacent rows of pixel circuits 10, during the reset phase P2, the light-emitting device 20 of the upper row of pixel circuits 10 does not emit light. That is, the fluctuation of the first power supply signal caused by the lower row of pixel circuits 10 during the reset phase P2 will not affect the light emission of the light-emitting device 20 of the upper row of pixel circuits 10.

[0099] In other words, when the light-emitting device 20 of the upper row of pixel circuits 10 emits light in each of the two adjacent rows of pixel circuits 10, the first power signal will not fluctuate due to the reset phase P2 of the lower row of pixel circuits 10 since the lower row of pixel circuits 10 is not in the reset phase P2. This can reduce the fluctuation of the light-emitting device 20 of the upper row of pixel circuits 10, reduce the flicker value of the display panel 100, and improve the problem of flickering in the display screen.

[0100] In some examples, see Figure 5 and Figure 7 The display panel 100 has L rows of pixel circuits 10. In the L rows of pixel circuits 10, the reset phase P2 of some rows of pixel circuits 10 is staggered from the light-emitting phase P1 of the row of pixel circuits 10 adjacent to it above; the reset phase P2 of other rows of pixel circuits 10 is not changed. For example, the reset phase P2 of other rows of pixel circuits 10 can at least partially overlap with the light-emitting phase P1 of the row of pixel circuits 10 adjacent to it above.

[0101] in, Figure 7The diagram uses a three-row pixel circuit 10 as an example. DS-1 represents the waveform of the light emission control signal of the first row pixel circuit 10, DS-2 represents the waveform of the light emission control signal of the second row pixel circuit 10, and DS-3 represents the waveform of the light emission control signal of the third row pixel circuit 10. WS-1 represents the waveform of the scan signal of the first row pixel circuit 10, WS-2 represents the waveform of the scan signal of the second row pixel circuit 10, and WS-3 represents the waveform of the scan signal of the third row pixel circuit 10. AZ-1 represents the waveform of the reset signal of the first row pixel circuit 10, AZ-2 represents the waveform of the reset signal of the second row pixel circuit 10, and AZ-3 represents the waveform of the reset signal of the third row pixel circuit 10.

[0102] For example, such as Figure 5 and Figure 7 As shown, the reset phase P2 of the pixel circuits 10 in the 2nd row, 5th row, 8th row, ..., (2+3X)th row is offset from the light-emitting phase P1 of the adjacent row of pixel circuits 10 above it. Here, 2+3X is less than or equal to L, X is greater than or equal to 0, and X is an integer. At this time, the reset phase P2 of the pixel circuits 10 in the 3rd row, 6th row, ..., (3+3X)th row can at least partially overlap with the light-emitting phase P1 of the adjacent row of pixel circuits 10 above it.

[0103] It should be noted that there are at least two adjacent rows of pixel circuits 10. The reset phase P2 of the bottom row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10. This design is not limited to this and may include other examples. The embodiments disclosed herein will not be illustrated one by one.

[0104] In some embodiments, see Figure 5 , Figure 8 and Figure 9 There are at least two adjacent rows of pixel circuits 10, where the reset phase P2 of the topmost row of pixel circuits 10 is staggered from the light-emitting phase P1 of the other rows of pixel circuits 10. In this case, when the topmost row of pixel circuits 10 is in reset phase P2, the light-emitting devices 20 of the other rows of pixel circuits 10 do not emit light. That is, the fluctuation in the first power signal caused by the topmost row of pixel circuits 10 in reset phase P2 will not affect the light emission of the light-emitting devices 20 of the other rows of pixel circuits 10. Since the topmost row of pixel circuits 10 is not in reset phase P2, the first power signal will not fluctuate due to the reset phase P2 of the topmost row of pixel circuits 10, which can reduce the fluctuation of the light emission brightness of the light-emitting devices 20 of the other rows of pixel circuits 10, reduce the flicker value of the display panel 100, and improve the problem of flickering in the display screen.

[0105] It should be noted that the other rows mentioned above refer to the other rows of pixel circuits 10 that are present in at least two adjacent rows of pixel circuits 10, excluding the topmost row of pixel circuits 10.

[0106] For example, see Figure 5 , Figure 8 and Figure 9 The pixel circuit 10 also includes a black insertion phase P5, which is located before the reset phase P2. The light emission control module 12 is further configured to, during the black insertion phase P5, control the drive current signal not to be transmitted to the light emission device 20 in response to the light emission control signal at the light emission control signal terminal DS. At this time, in at least two adjacent rows of pixel circuits 10, the reset phase P2 of the topmost row of pixel circuits is located within the black insertion phase P5 of the other rows, so that the reset phase P2 of the topmost row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10.

[0107] For example, see Figure 5 and Figure 8 In each pair of adjacent pixel circuits 10, the reset phase P2 of the upper row of pixel circuits 10 is within the black insertion phase P5 of the lower row of pixel circuits 10. In this case, the fluctuation in the first power signal caused by the upper row of pixel circuits 10 during the reset phase P2 will not affect the light emission of the light-emitting device 20 of the lower row of pixel circuits 10. Here, the other rows refer to the lower row of pixel circuits 10 in each pair of adjacent pixel circuits 10.

[0108] For example, in each of three adjacent rows of pixel circuits 10, the reset phase P2 of the top row of pixel circuits 10 is within the black insertion phase P5 of the two rows of pixel circuits below. In this case, the fluctuation of the first power supply signal caused by the top row of pixel circuits 10 during the reset phase P2 will not affect the light emission of the light-emitting devices 20 of the two rows of pixel circuits below. Here, the other rows are the two rows of pixel circuits 10 located below in the three adjacent rows of pixel circuits 10.

[0109] It should be noted that the reset module 13 is also configured to, in response to the reset signal of the reset signal terminal AZ during the black insertion phase P5, transmit the initialization signal of the initialization signal terminal Vinit to the second node N2, so as to keep the light-emitting device 20 from emitting light during the black insertion phase P5.

[0110] In some examples, such as Figure 5 and Figure 8As shown, the display panel 100 has L rows of pixel circuits 10. In each pair of adjacent rows of pixel circuits 10, the reset phase P2 of the upper row of pixel circuits 10 is staggered from the light-emitting phase P1 of the lower row of pixel circuits 10.

[0111] in, Figure 8 The diagram uses a three-row pixel circuit 10 as an example. DS-1 represents the waveform of the light emission control signal of the first row pixel circuit 10, DS-2 represents the waveform of the light emission control signal of the second row pixel circuit 10, and DS-3 represents the waveform of the light emission control signal of the third row pixel circuit 10. WS-1 represents the waveform of the scan signal of the first row pixel circuit 10, WS-2 represents the waveform of the scan signal of the second row pixel circuit 10, and WS-3 represents the waveform of the scan signal of the third row pixel circuit 10. AZ-1 represents the waveform of the reset signal of the first row pixel circuit 10, AZ-2 represents the waveform of the reset signal of the second row pixel circuit 10, and AZ-3 represents the waveform of the reset signal of the third row pixel circuit 10.

[0112] In this situation, in every two adjacent rows of pixel circuits 10, during the reset phase P2, the light-emitting device 20 of the lower row of pixel circuits 10 does not emit light. That is, the fluctuation of the first power supply signal caused by the upper row of pixel circuits 10 during the reset phase P2 will not affect the light emission of the light-emitting device 20 of the lower row of pixel circuits 10.

[0113] In other words, when the light-emitting device 20 of the lower row of pixel circuits 10 emits light in each of the two adjacent rows of pixel circuits 10, the first power signal will not fluctuate due to the reset phase P2 of the upper row of pixel circuits 10 since the upper row of pixel circuits 10 is not in the reset phase P2. This can reduce the fluctuation of the light-emitting device 20 of the lower row of pixel circuits 10, reduce the flicker value of the display panel 100, and improve the problem of flickering in the display screen.

[0114] In some examples, such as Figure 5 and Figure 9 As shown, the display panel 100 has L rows of pixel circuits 10. In the L rows of pixel circuits 10, the reset phase P2 of some rows of pixel circuits 10 is staggered from the light-emitting phase P1 of the row of pixel circuits 10 adjacent to its lower side; the reset phase P2 of other rows of pixel circuits 10 is not changed. For example, the reset phase P2 of other rows of pixel circuits 10 can at least partially overlap with the light-emitting phase P1 of the row of pixel circuits 10 adjacent to its lower side.

[0115] in, Figure 9The diagram uses a three-row pixel circuit 10 as an example. DS-1 represents the waveform of the light emission control signal of the first row pixel circuit 10, DS-2 represents the waveform of the light emission control signal of the second row pixel circuit 10, and DS-3 represents the waveform of the light emission control signal of the third row pixel circuit 10. WS-1 represents the waveform of the scan signal of the first row pixel circuit 10, WS-2 represents the waveform of the scan signal of the second row pixel circuit 10, and WS-3 represents the waveform of the scan signal of the third row pixel circuit 10. AZ-1 represents the waveform of the reset signal of the first row pixel circuit 10, AZ-2 represents the waveform of the reset signal of the second row pixel circuit 10, and AZ-3 represents the waveform of the reset signal of the third row pixel circuit 10.

[0116] For example, such as Figure 5 and Figure 9 As shown, the reset phase P2 of the pixel circuits 10 in the 1st row, 4th row, 7th row, ..., (1+3X)th row is offset from the light-emitting phase P1 of the adjacent row of pixel circuits 10 below it. Here, 1+3X is less than or equal to L, X is greater than or equal to 0, and X is an integer. At this time, the reset phase P2 of the pixel circuits 10 in the 2nd row, 5th row, 8th row, ..., (2+3X)th row overlaps at least partially with the light-emitting phase P1 of the adjacent row of pixel circuits below it.

[0117] It should be noted that there are at least two adjacent rows of pixel circuits 10. The reset phase P2 of the top row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10. This design is not limited to this and may include other examples. The embodiments disclosed herein will not be illustrated one by one.

[0118] In some embodiments, see Figure 5 and Figure 10 There are at least two adjacent rows of pixel circuits 10, and the reset phase P2 of the bottom row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10; and the reset phase P2 of the top row of pixel circuits 10 is staggered from the light emission phase P1 of the other rows of pixel circuits 10.

[0119] in, Figure 10The diagram uses a three-row pixel circuit 10 as an example. DS-1 represents the waveform of the light emission control signal of the first row pixel circuit 10, DS-2 represents the waveform of the light emission control signal of the second row pixel circuit 10, and DS-3 represents the waveform of the light emission control signal of the third row pixel circuit 10. WS-1 represents the waveform of the scan signal of the first row pixel circuit 10, WS-2 represents the waveform of the scan signal of the second row pixel circuit 10, and WS-3 represents the waveform of the scan signal of the third row pixel circuit 10. AZ-1 represents the waveform of the reset signal of the first row pixel circuit 10, AZ-2 represents the waveform of the reset signal of the second row pixel circuit 10, and AZ-3 represents the waveform of the reset signal of the third row pixel circuit 10.

[0120] For example, see Figure 5 and Figure 10 In each pair of adjacent pixel circuits 10, the reset phase P2 of the lower row of pixel circuits 10 is located between the data writing phase P3 and the light emission phase P1 of the upper row of pixel circuits 10. Furthermore, the reset phase P2 of the upper row of pixel circuits 10 is located within the black insertion phase P5 of the lower row of pixel circuits 10.

[0121] In this scenario, during the reset phase P2, the light-emitting device 20 of the other row of pixel circuits 10 does not emit light in any of the two adjacent rows of pixel circuits 10. That is, fluctuations in the first power supply signal caused by the reset phase P2 of any row of pixel circuits 10 will not affect the light emission of the light-emitting device 20 of the adjacent row of pixel circuits 10.

[0122] In other words, when the light-emitting device 20 of one row of pixel circuits 10 emits light, the other row of pixel circuits 10 is not in the reset phase P2. The first power signal will not be affected by the reset phase P2 of the adjacent row of pixel circuits 10 above and below, and will not fluctuate. This can further reduce the fluctuation of the light-emitting device 20 of the pixel circuit 10, reduce the flicker value of the display panel 100, and improve the problem of flickering in the display screen.

[0123] Embodiments of this disclosure also provide a driving method for a display panel 100, applicable to the display panel 100 of any of the above embodiments, the driving method comprising:

[0124] Combination Figure 5 and Figure 6 During the light-emitting phase P1, the driving module 11 generates a driving current signal in response to the voltages of the first node N1 and the third node N3. The light-emitting control module 12 controls the transmission of the driving current signal to the second node N2 in response to the light-emitting control signal at the light-emitting control signal terminal DS.

[0125] Combination Figure 5 and Figure 6 During the reset phase P2, the driving module 11 responds to the voltage of the third node N3, and the light-emitting control module 12 responds to the light-emitting control signal at the light-emitting control signal terminal DS, controlling the first power supply signal terminal VDD to conduct with the second node N2. Furthermore, the reset module 13 responds to the reset signal at the reset signal terminal AZ, transmitting the initialization signal at the initialization signal terminal Vinit to the second node N2.

[0126] The reset phase P2 of a row of pixel circuits 10 is staggered from the light emission phase P1 of at least one row of pixel circuits 10 adjacent to that row of pixel circuits 10.

[0127] The driving method for the display panel 100 provided in this embodiment has the same structure and beneficial technical effects as the display panel 100 provided in some of the above embodiments, and will not be described again here.

[0128] In some embodiments, see Figure 5 and Figure 6 The pixel circuit 10 also includes a data writing stage P3, which is located between the reset stage P2 and the light emission stage P1.

[0129] Specifically, during the data writing phase P3, the data writing module 14, in response to the control signal from the scan signal terminal WS, transmits the data signal from the data signal terminal D to the third node N3. Furthermore, during the reset phase P2, the data writing module 14, in response to the control signal from the scan signal terminal WS, transmits the data signal from the data signal terminal D to the third node N3.

[0130] Based on this, there are at least two adjacent rows of pixel circuits 10. The reset phase P2 of the bottom row of pixel circuits 10 is located between the data writing phase P3 and the light emission phase P1 of the other rows, so as to avoid interference between the reset of the second node N2 by the bottom row of pixel circuits 10 using data signals (carrying the initial data voltage for reset) in the reset phase P2 and the writing of data signals (carrying the grayscale data voltage for light emission) to the third node N3 by the top row of pixel circuits 10 in the data writing phase P3.

[0131] In some embodiments, see Figure 5 , Figure 7 and Figure 8 The pixel circuit 10 also includes a black insertion stage P5, which is located before the reset stage P2.

[0132] During the black insertion phase P5, the light emission control module 12 responds to the light emission control signal at the light emission control signal terminal DS and controls the drive current signal not to be transmitted to the light emission device 20. The reset module 13 responds to the reset signal at the reset signal terminal AZ and transmits the initialization signal at the initialization signal terminal Vinit to the second node N2.

[0133] There are at least two adjacent rows of pixel circuits 10. The reset phase P2 of the top row of pixel circuits 10 is located within the black insertion phase P5 of other rows, so that the fluctuation of the first power supply signal caused by the reset phase P2 of any row of pixel circuits 10 will not affect the light emission of the light-emitting device 20 of the adjacent row of pixel circuits 10 (including the row of pixel circuits 10 adjacent to the top and bottom).

[0134] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0135] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, It includes multiple pixel circuits, which are arranged in multiple rows and columns; The pixel circuit includes a light-emitting stage and a reset stage, wherein the light-emitting stage is located after the reset stage; The pixel circuit also includes: A driving module is coupled to a first node, a second node, and a third node; the first node is coupled to a first power signal terminal, the second node is coupled to a light-emitting device, and the third node is coupled to a data signal terminal; the driving module is configured to generate a driving current signal in response to the voltage of the first node and the third node during the light-emitting phase. A light-emitting control module is coupled to the first node, the first power signal terminal, and the light-emitting control signal terminal; the light-emitting control module is configured to, during the light-emitting phase, control the transmission of the drive current signal to the second node in response to the light-emitting control signal at the light-emitting control signal terminal. A reset module is coupled to the second node, a reset signal terminal, and an initialization signal terminal; the reset module is configured to, during the reset phase, transmit the initialization signal of the initialization signal terminal to the second node in response to the reset signal of the reset signal terminal. The driving module and the light emission control module are further configured to, during the reset phase, control the first power supply signal terminal to be connected to the second node in response to the voltage of the third node and the light emission control signal of the light emission control signal terminal; and the reset phase of a row of pixel circuits is staggered from the light emission phase of at least one row of pixel circuits adjacent to the row of pixel circuits.

2. The display panel according to claim 1, characterized in that, There are at least two adjacent rows of the pixel circuits, and the reset phase of the pixel circuit in the bottom row is staggered from the light-emitting phase of the pixel circuits in the other rows.

3. The display panel according to claim 2, characterized in that, The pixel circuit further includes a data writing stage, which is located between the light emission stage and the reset stage; The pixel circuit also includes: A data writing module is coupled to the third node, the data signal terminal, and the scan signal terminal; the data writing module is configured to, during the data writing phase, transmit the data signal of the data signal terminal to the third node in response to the control signal of the scan signal terminal; and during the reset phase, transmit the data signal of the data signal terminal to the third node in response to the control signal of the scan signal terminal. There are at least two adjacent rows of pixel circuits, with the reset phase of the bottom row of pixel circuits located between the data writing phase and the light emission phase of the other rows.

4. The display panel according to any one of claims 1 to 3, characterized in that, There are at least two adjacent rows of the pixel circuits, and the reset phase of the pixel circuit in the topmost row is staggered from the light-emitting phase of the pixel circuits in the other rows.

5. The display panel according to claim 4, characterized in that, The pixel circuit further includes a black insertion stage, which is located before the reset stage; the light emission control module is further configured to, in response to the light emission control signal at the light emission control signal terminal, control the drive current signal not to be transmitted to the light emission device during the black insertion stage. Among them, there are at least two adjacent rows of pixel circuits, the reset phase of the pixel circuit in the top row, and the black insertion phase in the other rows.

6. The display panel according to claim 5, characterized in that, The reset module is also configured to, in response to the reset signal at the reset signal terminal during the blackout phase, transmit the initialization signal at the initialization signal terminal to the second node.

7. A driving method for a display panel, characterized in that, Applied to a display panel as described in any one of claims 1 to 6, the driving method comprises: During the light-emitting phase, the driving module generates a driving current signal in response to the voltage of the first node and the third node; the light-emitting control module controls the transmission of the driving current signal to the second node in response to the light-emitting control signal at the light-emitting control signal terminal. During the reset phase, the driving module responds to the voltage of the third node, and the light-emitting control module responds to the light-emitting control signal of the light-emitting control signal terminal to control the first power signal terminal to conduct with the second node; the reset module responds to the reset signal of the reset signal terminal to transmit the initialization signal of the initialization signal terminal to the second node. The reset phase of a row of pixel circuits is staggered from the light emission phase of at least one row of pixel circuits adjacent to the row of pixel circuits.

8. The driving method for a display panel according to claim 7, characterized in that, The pixel circuit further includes a data writing stage, which is located between the light emission stage and the reset stage; the pixel circuit further includes a data writing module, which is coupled to the third node, the data signal terminal and the scan signal terminal. The driving method further includes: During the data writing phase, the data writing module responds to the control signal at the scanning signal terminal and transmits the data signal at the data signal terminal to the third node; During the reset phase, the data writing module responds to the control signal at the scan signal terminal and transmits the data signal at the data signal terminal to the third node; There are at least two adjacent rows of pixel circuits, with the reset phase of the bottom row of pixel circuits located between the data writing phase and the light emission phase of the other rows.

9. The driving method for a display panel according to claim 7, characterized in that, The pixel circuit further includes a black pixel insertion stage, which is located before the reset stage; the driving method further includes: During the black insertion phase, the light emission control module responds to the light emission control signal at the light emission control signal terminal and controls the drive current signal not to be transmitted to the light emission device; the reset module responds to the reset signal at the reset signal terminal and transmits the initialization signal at the initialization signal terminal to the second node; wherein, there are at least two adjacent rows of pixel circuits, the reset phase of the top row of pixel circuits is within the black insertion phase of the other rows.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 6.

Images