Copper electrode thermistor chip adaptive to spinel ceramic substrate and preparation process of copper electrode thermistor chip

Abstract

The copper electrode thermistor chip comprises a copper electrode layer, a composite barrier layer, a silver seed layer and the spinel ceramic substrate which are sequentially arranged from top to bottom, the composite barrier layer comprises a Ti layer, a Ta-W alloy layer and a TiN layer, and the Ti layer, the Ta-W alloy layer and the TiN layer are sequentially and continuously sputtered through a magnetron sputtering technology. The invention has the advantages that the three-function composite layer is used as a composite barrier layer, the Ti layer realizes ohmic contact, the alloy layer inhibits atomic diffusion, and the TiN layer provides initial anti-oxidation protection, so that the contact resistance can be effectively reduced, the diffusion of copper atoms and the migration of transition metal atoms are prevented, and the initial anti-oxidation protection is provided for the copper electrode. The high temperature resistance and surge resistance of the copper electrode thermistor are effectively improved, and the service life of the copper electrode is prolonged. And direct large-scale mass production can be realized, equipment transformation is not needed, and large-scale production and use are facilitated. And the production cost is effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of NTC thermistor technology, and relates to the application of power-type NTC thermistor blocking layers. Specifically, it relates to a copper electrode thermistor chip adapted to a spinel ceramic substrate and its fabrication process. Background Technology

[0002] The interface problem between the copper electrode and spinel ceramic in power NTC thermistor chips is the core bottleneck for replacing silver paste with copper paste. Existing single-function or dual-function barrier layers cannot simultaneously solve the three core problems of "ohmic contact + bidirectional atomic diffusion suppression + copper electrode oxidation resistance": On the one hand, the interface reaction between copper and ceramic is prone to forming a high-resistivity layer, leading to ohmic contact failure; on the other hand, copper atoms diffuse into ceramic and transition metal atoms migrate into the electrode, causing electrode failure and NTC characteristic drift; in addition, the surface of copper electrode is prone to oxidation, affecting long-term reliability.

[0003] In extreme surge (>2500A / ms) and high-temperature operating scenarios, the overall performance of existing barrier layers is insufficient to meet the stringent application requirements. Therefore, developing a composite barrier layer with three functions and adaptable to extreme scenarios has become a key technological breakthrough for replacing silver electrodes with copper electrodes. Summary of the Invention

[0004] To address the aforementioned problems, the main objective of this invention is to design a thermistor chip with a composite barrier layer that combines three functions and is adaptable to extreme scenarios.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A copper electrode thermistor chip adapted to a spinel ceramic substrate includes a spinel ceramic substrate. A composite barrier layer, a silver seed layer, and a copper electrode layer are sequentially disposed on the upper and lower surfaces of the spinel ceramic substrate. The composite barrier layer is disposed between the silver seed layer and the spinel ceramic substrate and includes a Ti layer, a Ta-W alloy layer, and a TiN layer. The Ti layer covers the upper and lower surfaces of the spinel ceramic substrate, respectively; the Ta-W alloy layer covers the surface of the Ti layer; the TiN layer covers the surface of the Ta-W alloy layer; and the silver seed layer covers the surface of the TiN layer.

[0006] As a further description of the present invention, the thickness of the Ti layer is 20-30 nm, the thickness of the Ta-W alloy layer is 30-50 nm, and the thickness of the TiN layer is 5-10 nm.

[0007] As a further description of the present invention, the Ta-W alloy layer in the composite barrier layer can also be configured as a Ta-Nb alloy layer.

[0008] As a further description of the present invention, the weight ratio of Ta to W in the Ta-W alloy is 7:3; the weight ratio of Ta to Nb in the Ta-Nb alloy is 8:2.

[0009] Based on the fabrication process of the copper electrode thermistor chip adapted to spinel ceramic substrates in this application, the Ti layer, Ta-W alloy layer and TiN layer are sequentially sputtered using a magnetron sputtering process.

[0010] As a further description of the present invention, the sputtering process parameters for the Ti layer are: argon pressure 0.5-0.8 Pa, sputtering power 200-250 W, target-substrate distance 80-100 mm, and sputtering temperature <150 °C.

[0011] As a further description of the present invention, the sputtering process parameters for the Ti-Nb alloy layer or Ta-W alloy layer are: argon pressure 0.6-0.9 Pa, sputtering power 220-260 W, and sputtering temperature <150℃.

[0012] As a further description of the present invention, the sputtering process parameters for the TiN layer are: pressure 0.4-0.6 Pa, sputtering power 180-210 W, sputtering temperature <150℃, and sputtering atmosphere is a mixture of argon and nitrogen gas.

[0013] Compared with the prior art, the technical advantages of the present invention are as follows: This invention provides a copper electrode thermistor chip adapted to spinel ceramic substrates and its fabrication process, which has the following main advantages: 1. This invention employs a three-functional composite layer as a composite barrier layer. The Ti layer achieves ohmic contact, the alloy layer inhibits atomic diffusion, and the TiN layer provides initial oxidation protection. This effectively reduces contact resistance, prevents copper atom diffusion and excessive metal atom migration, and provides initial oxidation protection for the copper electrode. It effectively improves the high-temperature resistance and surge resistance of the copper electrode thermistor, while also extending the service life of the copper electrode.

[0014] 2. It is fully compatible with magnetron sputtering, thick film printing and reduction sintering processes, and can be directly mass-produced without equipment modification, making it convenient for large-scale production.

[0015] 3. When used in conjunction with copper electrodes to replace silver electrodes, it effectively reduces production costs. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall structure of the present invention; Figure 2 yes Figure 1 A magnified view of position AA in the image; Figure 3 This is a data table showing the results of the welding heat resistance test; Figure 4 This is a data table showing the results of a constant temperature and humidity experiment; Figure 5 This is a data table showing the results of high and low temperature impact tests; Figure 6 This is a data table showing the results of a high-temperature storage test; Figure 7 This is a data table showing the results of the maximum steady-state current test; Figure 8 This is a data table showing the results of the maximum capacitance test.

[0017] In the figure, 1. spinel ceramic substrate, 2. copper electrode, 3. composite barrier layer, 31. Ti layer, 32. Ta-W alloy layer, 33. TiN layer, 4. silver seed layer, 5. oxide protection layer. Detailed Implementation

[0018] The present invention will now be described in detail with reference to the accompanying drawings: To address the aforementioned problems, the main objective of this invention is to design a thermistor chip with a composite barrier layer that combines three functions and is adaptable to extreme scenarios, as well as its fabrication process.

[0019] To achieve the above objectives, the present invention adopts the following technical solution: A copper electrode thermistor chip adapted to a spinel ceramic substrate mainly consists of a spinel ceramic substrate 1, a composite barrier layer 3, a silver seed layer 4, a copper electrode layer 2, and an oxide protection layer 5.

[0020] The upper and lower surfaces of the spinel ceramic substrate are sequentially covered with a composite barrier layer 3, a silver seed layer 4, a copper electrode layer 2, and an oxide protection layer 5, as shown below. Figure 1 As shown.

[0021] The composite barrier layer 3 is disposed between the silver seed layer 4 and the spinel ceramic substrate 1, and is mainly composed of Ti layer 31, Ta-W alloy layer 32 and TiN layer 33. Ti layer 31, Ta-W alloy layer 32 and TiN layer 33 are prepared by sequential sputtering using magnetron sputtering process.

[0022] Ti layer 31 covers the surface of spinel ceramic substrate 1; Ta-W alloy layer 32 covers the surface of Ti layer 31; TiN layer 33 covers the surface of Ta-W alloy layer 32, and a silver seed layer 4 is covered on the surface of TiN layer 33. The thickness of Ti layer 31 is 20-30 nm, the thickness of Ta-W alloy layer 32 is 30-50 nm, and the thickness of TiN layer 33 is 5-10 nm. Figure 2 As shown.

[0023] The Ta-W alloy layer 32 in this application can also be configured as a Ta-Nb alloy layer. In the Ta-W alloy, the weight ratio of Ta to W is 7:3; in the Ta-Nb alloy, the weight ratio of Ta to Nb is 8:2.

[0024] During the preparation process, the sputtering parameters for the Ti layer 31 are: argon pressure 0.5-0.8 Pa, sputtering power 200-250 W, target-substrate distance 80-100 mm, and sputtering temperature <150℃.

[0025] The sputtering process parameters for Ti-Nb alloy layers or Ta-W alloy layers are: argon pressure 0.6-0.9 Pa, sputtering power 220-260 W, and sputtering temperature <150℃.

[0026] The sputtering process parameters for TiN layer 33 are: pressure 0.4-0.6 Pa, sputtering power 180-210 W, sputtering temperature <150℃, and sputtering atmosphere is a mixture of argon and nitrogen gas. Example 1

[0027] The copper electrode thermistor was prepared by selecting Ta-W as the alloy layer, wherein the thickness of the Ti layer was 25 nm, the thickness of the Ta-Nb alloy layer was 35 nm, and the thickness of the TiN layer was 8 nm. The weight ratio of Ta to W in the Ta-W alloy was 7:3.

[0028] The composite barrier layer was prepared by electromagnetic sputtering, and the specific steps are as follows. Step 1: Sputter a Ti layer on the surface of a spinel ceramic substrate. The sputtering parameters are: argon pressure 0.6 Pa, sputtering power 220 W, target-substrate distance 85 mm, and sputtering temperature 130 °C. Step 2: After the Ti layer sputtering is completed, the Ta-W alloy layer is continuously sputtered without atmospheric exposure. The sputtering parameters are: argon pressure 0.7 Pa, sputtering power 240 W, sputtering rate 5 nm / min, and sputtering temperature 140 °C. Step 3: After the Ta-W layer sputtering is completed, the TiN layer is sputtered without atmospheric exposure. The sputtering parameters are: pressure 0.5 Pa, sputtering power 200 W, sputtering temperature 140 °C, and sputtering atmosphere is a mixture of argon and nitrogen gas with a volume ratio of 9:1.

[0029] The Ti layer porosity is <1.5%, the Ta-W layer porosity is <0.8%, and the thickness uniformity deviation is <±3%.

[0030] After the composite barrier layer is prepared, a silver seed layer, a copper electrode, and an anti-oxidation protective layer are sequentially prepared on the TiN layer to complete the preparation of the entire thermistor.

[0031] The test results for the copper electrodes are as follows: The contact resistance is 3.8 mΩ; It withstood a 2800A / ms surge current 25 times without cracking; After 1000 hours of operation, the copper atom diffusion rate is <5×10⁻⁶. -11 cm² / s, transition metal atom migration < 2 × 10⁻⁶ -10 cm² / s; steady-state current density ≥ 6.5 A / mm²; It conforms to the copper electrode parameter standards in power-type NTC thermistor chips. Example 2

[0032] The copper electrode thermistor was prepared by selecting Ta-Nb as the alloy layer, wherein the thickness of the Ti layer was 25 nm, the thickness of the Ta-Nb alloy layer was 35 nm, and the thickness of the TiN layer was 8 nm. The weight ratio of Ta to Nb in the Ta-Nb alloy was 8:2.

[0033] The composite barrier layer was prepared by electromagnetic sputtering, and the specific steps are as follows. Step 1: Sputter a Ti layer on the surface of a spinel ceramic substrate with an argon pressure of 0.7 Pa, a sputtering power of 230 W, a target-substrate distance of 90 mm, and a sputtering temperature of 120 °C. Step 2: After the Ti layer sputtering is completed, the Ta-Nb alloy layer is continuously sputtered without atmospheric exposure. The argon pressure is 0.8 Pa, the sputtering power is 240 W, the sputtering rate is 5 nm / min, and the sputtering temperature is 140 °C. Step 3: After the Ta-Nb layer is sputtered, the TiN layer is sputtered without atmospheric exposure. The sputtering parameters are: pressure 0.5 Pa, sputtering power 200 W, sputtering temperature 140 °C, and sputtering atmosphere is a mixture of argon and nitrogen gas with a volume ratio of 9:1.

[0034] The Ti layer porosity is <1.2%, the Ta-Nb layer porosity is <0.8%, and the thickness uniformity deviation is <±3%.

[0035] After the composite barrier layer is prepared, a silver seed layer, a copper electrode, and an optional anti-oxidation layer are sequentially prepared on the TiN layer to complete the preparation of the entire copper electrode.

[0036] The test results for the copper electrodes are as follows: The contact resistance is 4.2 mΩ; It withstood a 2800A / ms surge current 25 times without cracking; After 1000 hours of operation, the copper atom diffusion rate is <8×10⁻⁶. -10 cm² / s, transition metal atom migration < 3 × 10⁻⁶ -10 cm² / s; steady-state current density ≥ 5.8 A / mm²; It conforms to the parameter standards for copper electrodes in power-type NTC thermistor chips. Example 3

[0037] Copper electrodes were prepared using Ta-W and Ta-Nb as alloy layers in Examples 1 and 2, respectively, to fabricate thermistors. The resistance changes of existing silver electrode thermistors under different conditions were compared.

[0038] The experimental temperature was 25℃. Figures 3-8 |ΔR 25 / R 25 |, where R 25 The resistance before the experiment is ΔR. 25 The difference between the resistance after the experiment and the resistance before the experiment is |ΔR|. 25 / R 25 | represents the rate of change of resistance.

[0039] Experimental product carrier: 5Ω power NTC thermistor Experiment 1: Welding Heat Resistance Test Experimental conditions and methods: temperature 260±5℃, immersion depth 6mm from the resistive element, time 10±1s; Experimental results: such as Figure 3 .

[0040] After replacing silver with copper or aluminum as the electrode material and conducting welding heat resistance tests, the resistance change rate of the silver electrode was approximately 1.48%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was approximately 1.51%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was approximately 1.55%. The resistance change rates of the copper electrodes with Ta-W and Ta-Nb as the alloy layers were close to those of the existing silver electrodes, and both met the technical requirement of less than 20% in actual use.

[0041] Experiment 2: Constant Temperature and Humidity Experiment Experimental conditions and methods: Temperature 40±2℃, humidity 93±2%, time 1000h; Experimental results: such as Figure 4 .

[0042] After replacing silver with copper or aluminum as the electrode material in the constant temperature and humidity test, the resistance change rate of the silver electrode was about 5.95%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was about 6.63%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was about 6.30%. The resistance change rate of the copper electrode with Ta-W and Ta-Nb as the alloy layer is close to that of the existing silver electrode, and both meet the technical requirement of less than 20% in actual use.

[0043] Experiment 3: High and Low Temperature Impact Test Experimental conditions and methods: -40℃ / 30min to 170℃ / 30min for 1000 cycles; Experimental results: such as Figure 5 .

[0044] After replacing silver with copper or aluminum as the electrode material in high and low temperature impact tests, the resistance change rate of the silver electrode was about 3.67%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was about 3.52%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was about 3.61%. The resistance change rate of the copper electrode with Ta-W and Ta-Nb as the alloy layer is close to that of the existing silver electrode, and both meet the technical requirement of less than 20% in actual use.

[0045] Experiment 4: High-Temperature Storage Experiment Experimental conditions and methods: Temperature 170±5℃, time 1000h; Experimental results: such as Figure 6 .

[0046] After high-temperature storage experiments using copper or aluminum instead of silver as electrode materials, the resistance change rate of the silver electrode was approximately 8.58%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was approximately 8.90%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was approximately 9.22%. The resistance change rates of the copper electrodes with Ta-W and Ta-Nb as the alloy layers are close to those of the existing silver electrodes, and both meet the technical requirement of less than 20% in practical use.

[0047] Experiment 5: Maximum Steady-State Current Experiment Experimental conditions and methods: The maximum steady-state current was continuously applied at room temperature for 1000±24h; Experimental results: such as Figure 7 .

[0048] After replacing silver with copper or aluminum as the electrode material in the maximum steady-state current experiment, the resistance change rate of the silver electrode was about 12.82%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was about 12.41%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was about 12.88%. The resistance change rate of the copper electrode with Ta-W and Ta-Nb as the alloy layer is close to that of the existing silver electrode, and both meet the technical requirement of less than 20% in actual use.

[0049] Experiment 6: Maximum Capacitance Experiment Experimental conditions and methods: Apply the maximum allowable capacitance, intermittently close for 50ms, and open for 5 times the thermal time constant as one cycle, continue for 1000 cycles; Experimental results: such as Figure 8 .

[0050] After replacing silver with copper or aluminum as the electrode material in the maximum steady-state current experiment, the resistance change rate of the silver electrode was about 2.31%, the resistance change rate of the copper electrode with Ta-W as the alloy layer was about 2.99%, and the resistance change rate of the aluminum electrode with Ta-Nb as the alloy layer was about 2.50%. The resistance change rate of the copper electrode with Ta-W and Ta-Nb as the alloy layer is close to that of the existing silver electrode, and both meet the technical requirement of less than 20% in actual use.

[0051] Experiments 1-6 show that, under different experimental conditions, the resistance change rates of the thermistors prepared with Ta-W and Ta-Nb alloy layers as copper electrodes are close to those of existing silver electrodes, and both meet the technical requirements and can satisfy practical application needs. Therefore, in this application, it is entirely feasible to use copper electrodes prepared with Ta-W and Ta-Nb alloy layers as replacement materials for silver in the thermistor electrodes.

[0052] The above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Any other modifications or equivalent substitutions made by those skilled in the art to the technical solutions of the present invention, as long as they do not depart from the direction and scope of the technical solutions of the present invention, should be covered within the scope of the claims of the present invention.

Claims

1. A copper electrode thermistor chip adapted to a spinel ceramic substrate, characterized in that: The invention includes a spinel ceramic substrate. A composite barrier layer, a silver seed layer, and a copper electrode layer are sequentially disposed on the upper and lower surfaces of the spinel ceramic substrate. The composite barrier layer is disposed between the silver seed layer and the spinel ceramic substrate and includes a Ti layer, a Ta-W alloy layer, and a TiN layer. The Ti layer covers the upper and lower surfaces of the spinel ceramic substrate, respectively. The Ta-W alloy layer covers the surface of the Ti layer. The TiN layer covers the surface of the Ta-W alloy layer, and the silver seed layer covers the surface of the TiN layer.

2. The copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 1, characterized in that: The thickness of the Ti layer is 20-30 nm, the thickness of the Ta-W alloy layer is 30-50 nm, and the thickness of the TiN layer is 5-10 nm.

3. The copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 1, characterized in that: The Ta-W alloy layer in the composite barrier layer can also be set as a Ta-Nb alloy layer.

4. A copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 1 or 3, characterized in that: The weight ratio of Ta to W in the Ta-W alloy is 7:3; the weight ratio of Ta to Nb in the Ta-Nb alloy is 8:

2.

5. The fabrication process of a copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 1, characterized in that: The Ti layer, Ta-W alloy layer and TiN layer are sequentially sputtered using a magnetron sputtering process.

6. The fabrication process of a copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 5, characterized in that: The sputtering process parameters for the Ti layer are: argon pressure 0.5-0.8 Pa, sputtering power 200-250 W, target-substrate distance 80-100 mm, and sputtering temperature <150℃.

7. The fabrication process of a copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 5, characterized in that: The sputtering process parameters for the Ti-Nb alloy layer or Ta-W alloy layer are: argon pressure 0.6-0.9 Pa, sputtering power 220-260 W, and sputtering temperature <150℃.

8. The fabrication process of a copper electrode thermistor chip adapted to a spinel ceramic substrate according to claim 5, characterized in that: The sputtering process parameters for the TiN layer are: pressure 0.4-0.6 Pa, sputtering power 180-210 W, sputtering temperature <150℃, and sputtering atmosphere is a mixture of argon and nitrogen.

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