Deep ultraviolet led chip with enhanced optical output power and method of manufacturing the same
By introducing a reflective current blocking layer into the deep ultraviolet LED chip, the problems of low light extraction efficiency and current concentration effect are solved, thereby improving the light output power and enhancing reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN UNIV
- Filing Date
- 2023-12-21
- Publication Date
- 2026-06-09
AI Technical Summary
In existing AlGaN-based deep ultraviolet LED chips, the absorption of deep ultraviolet light by the ITO transparent conductive film or NiAu electrode leads to low light extraction efficiency, and the current concentration effect results in large local heat generation, which affects device performance.
A reflective current blocking layer is set between the P-type ohmic contact layer and the P-type semiconductor layer, partially covering the P-type semiconductor layer. The reflective current blocking layer is a periodically stacked structure of aluminum, rhodium or oxide to form a DBR, which enhances light reflection and forces the current to diffuse laterally.
It significantly improves light extraction efficiency, reduces the absorption of deep ultraviolet light by the P-type ohmic contact layer, reduces local heat generation, and enhances light output power and reliability.
Smart Images
Figure CN117712255B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor light-emitting devices, and more specifically to a deep ultraviolet LED chip with enhanced light output power and its manufacturing method. Background Technology
[0002] In recent years, due to the significant advantages of high-aluminum AlGaN-based semiconductor devices in terms of energy saving, environmental protection, and portability, as well as their important applications in sterilization, secure communication, and especially their inactivation effect on the novel coronavirus, research on high-aluminum AlGaN-based diodes and transistors has attracted much attention.
[0003] Currently, in AlGaN-based deep ultraviolet LED chips (light-emitting diodes), due to the special characteristics of their low emission wavelength, light cannot pass through or is reflected, resulting in extremely low light extraction efficiency and thus low photoelectric conversion efficiency, which affects their application.
[0004] In related technologies, the ohmic contact materials often use ITO transparent conductive film or NiAu electrode. Although ITO transparent conductive film or NiAu electrode can form a good ohmic contact with the P-type GaN or AlGaN layer in the deep ultraviolet LED chip, ITO transparent conductive film or NiAu electrode has extremely high absorption loss for deep ultraviolet light, which seriously affects the extraction efficiency of deep ultraviolet light.
[0005] Furthermore, in AlGaN-based deep ultraviolet LEDs, the conductivity of the P-side is very small, making it easier for current to accumulate near the electrodes, resulting in a current accumulation effect. This leads to excessive local heat generation, affecting the application performance of semiconductor devices. Summary of the Invention
[0006] This application provides a deep ultraviolet LED chip with enhanced light output power and its manufacturing method, which can solve the technical problems in related technologies, such as low extraction efficiency of deep ultraviolet light caused by the absorption of deep ultraviolet light by ITO transparent conductive film or NiAu electrode and large local heat generation caused by current concentration effect.
[0007] In a first aspect, embodiments of this application provide a deep ultraviolet LED chip with enhanced light output power, the deep ultraviolet LED chip comprising:
[0008] The epitaxial layer includes a buffer layer, an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer stacked sequentially, wherein the P-type semiconductor layer is a P-AlGaN layer or a P-GaN layer.
[0009] An N-type ohmic contact layer is provided, which covers the N-type semiconductor layer and forms an ohmic contact with the N-type semiconductor layer.
[0010] A current-reflecting barrier layer, wherein the current-reflecting barrier layer partially covers the P-type semiconductor layer;
[0011] A P-type ohmic contact layer is provided, which covers the reflective current blocking layer and forms an ohmic contact with the P-type semiconductor layer.
[0012] An insulating layer, wherein the insulating layer covers the N-type ohmic contact layer and the P-type ohmic contact layer respectively;
[0013] A metal pad layer covers the insulating layer to connect the N-type ohmic contact layer and the P-type ohmic contact layer, respectively.
[0014] In conjunction with the first aspect, in one embodiment, the P-type ohmic contact layer fully covers the reflective current blocking layer.
[0015] In conjunction with the first aspect, in one embodiment, the duty cycle of the reflective current blocking layer is 10%-90%.
[0016] In conjunction with the first aspect, in one embodiment, the reflective current blocking layer comprises one or more of aluminum, rhodium, oxides, or a combination film layer formed by periodically stacking different oxides, wherein the oxides include one or more of silicon dioxide, titanium pentoxide, and hafnium oxide.
[0017] In conjunction with the first aspect, in one embodiment, the reflected current blocking layer is any one of a strip, a circle, or a square pattern.
[0018] In conjunction with the first aspect, in one embodiment, when the reflected current blocking layer is a strip pattern, its width d is 1. ≤d≤50 When the reflected current blocking layer is a circular pattern, its radius r is 2. ≤r≤25 When the reflected current blocking layer is a square pattern, its width d is 1. ≤d≤50 .
[0019] In conjunction with the first aspect, in one embodiment, the epitaxial layer further includes a nitride heterostructure layer located between the buffer layer and the N-type semiconductor layer.
[0020] In conjunction with the first aspect, in one embodiment, the deep ultraviolet LED chip further includes a metal thickening layer located between the P-type ohmic contact layer and the insulating layer, and / or located between the N-type ohmic contact layer and the insulating layer.
[0021] Secondly, embodiments of this application provide a method for manufacturing a deep ultraviolet LED chip with enhanced light output power, comprising the following steps:
[0022] An epitaxial layer is formed on a substrate, the epitaxial layer comprising a buffer layer, an N-type semiconductor layer, a quantum well layer, and a P-type semiconductor layer sequentially stacked on the substrate;
[0023] Etch a portion of the epitaxial layer to expose the N-type semiconductor layer;
[0024] An N-type ohmic contact layer is fabricated, which covers the N-type semiconductor layer located in the etched region and forms an ohmic contact with the N-type semiconductor layer;
[0025] A reflective current blocking layer is deposited in the non-etched area, and the reflective current blocking layer partially covers the P-type semiconductor layer;
[0026] A P-type ohmic contact layer is fabricated, which covers the reflective current blocking layer and forms an ohmic contact with the P-type semiconductor layer;
[0027] An insulating layer is fabricated, which covers the N-type ohmic contact layer and the P-type ohmic contact layer respectively;
[0028] A metal pad layer is fabricated to cover the insulating layer, thereby connecting the N-type ohmic contact layer and the P-type ohmic contact layer, respectively.
[0029] In conjunction with the second aspect, in one embodiment, the deposition of a reflective current blocking layer in a non-etched region, wherein the reflective current blocking layer partially covers the P-type semiconductor layer, comprises:
[0030] Photolithography is performed on the P-type semiconductor layer to form a photoresist mask layer with different patterns on the surface of the P-type semiconductor layer;
[0031] A reflective current blocking layer is deposited on the photoresist mask layer;
[0032] Part of the photoresist mask layer is removed to form reflective current blocking layers of different shapes or with different duty cycles.
[0033] The beneficial effects of the technical solutions provided in this application include:
[0034] This application provides a deep ultraviolet (DUV) LED chip that enhances light output power. A reflective current blocking layer is disposed between a P-type ohmic contact layer and a P-type semiconductor layer, and the reflective current blocking layer partially covers the P-type semiconductor layer. On the one hand, the partial coverage maintains a good ohmic contact between the P-type ohmic contact layer and the P-type semiconductor layer, thereby ensuring its electrical performance. On this basis, the reflective current blocking layer reflects light, significantly increasing the light extraction effect and significantly reducing the absorption effect of deep ultraviolet light by the P-type ohmic contact layer, effectively improving the light extraction efficiency and thus increasing the light output power of the DUV LED chip. On the other hand, the reflective current blocking layer and the P-type semiconductor layer cannot form an ohmic contact, forcing the accumulated current to diffuse laterally, further promoting current expansion, reducing excessive local heat generation caused by the current accumulation effect, thereby improving the light power and reliability of the DUV LED chip. Attached Figure Description
[0035] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0036] Figure 1 This is a schematic diagram of the structure of a deep ultraviolet LED chip in one embodiment of the present invention.
[0037] Figure 2 This is a schematic diagram of the photolithography process for manufacturing a deep ultraviolet LED chip in one embodiment of the present invention.
[0038] Figure 3 This is a flowchart illustrating the steps of a method for manufacturing a deep ultraviolet LED chip according to an embodiment of the present invention.
[0039] Figure 4 This is a schematic diagram comparing the optical power / current curves of a deep ultraviolet LED chip in one embodiment of the present invention.
[0040] In the figure: 1. Substrate; 2. Epitaxial layer; 21. Buffer layer; 22. N-type semiconductor layer; 23. Quantum well layer; 24. P-type semiconductor layer; 3. N-type ohmic contact layer; 4. Reflective current blocking layer; 5. P-type ohmic contact layer; 6. Metal thickening layer; 7. Insulating layer; 8. Metal pad layer. Detailed Implementation
[0041] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0042] This application provides a deep ultraviolet LED chip that enhances light output power, which can solve the technical problems in related technologies such as low extraction efficiency of deep ultraviolet light due to absorption of deep ultraviolet light by ITO transparent conductive film or NiAu electrode and large local heat generation due to current concentration effect.
[0043] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a deep ultraviolet LED chip in one embodiment of the present invention.
[0044] This embodiment provides a deep ultraviolet LED chip to enhance light output power. The deep ultraviolet LED chip includes:
[0045] Epitaxial layer 2 includes a buffer layer 21, an N-type semiconductor layer 22, a quantum well layer 23, and a P-type semiconductor layer 24 stacked sequentially, wherein the P-type semiconductor layer 24 is a P-AlGaN layer or a P-GaN layer.
[0046] N-type ohmic contact layer 3 covers N-type semiconductor layer 22 and forms an ohmic contact with N-type semiconductor layer 22;
[0047] A current-reflecting barrier layer 4 is provided, which partially covers a P-type semiconductor layer 24.
[0048] P-type ohmic contact layer 5 covers the reflective current blocking layer 4 and forms an ohmic contact with the P-type semiconductor layer 24;
[0049] Insulating layer 7 covers N-type ohmic contact layer 3 and P-type ohmic contact layer 5 respectively;
[0050] Metal pad layer 8, which covers insulating layer 7, to connect N-type ohmic contact layer 3 and P-type ohmic contact layer 5 respectively.
[0051] This embodiment provides a deep ultraviolet (DUV) LED chip with enhanced light output power. A reflective current blocking layer is disposed between a P-type ohmic contact layer and a P-type semiconductor layer, and the reflective current blocking layer partially covers the P-type semiconductor layer. On the one hand, the partial coverage maintains a good ohmic contact between the P-type ohmic contact layer and the P-type semiconductor layer, thereby ensuring its electrical performance. On this basis, the reflective current blocking layer reflects light, significantly increasing the light extraction effect and significantly reducing the absorption effect of deep ultraviolet light by the P-type ohmic contact layer, effectively improving the light extraction efficiency and thus increasing the light output power of the DUV LED chip. On the other hand, the reflective current blocking layer and the P-type semiconductor layer cannot form an ohmic contact, forcing the accumulated current to diffuse laterally, further promoting current expansion and reducing excessive local heat generation caused by the current accumulation effect, thereby improving the light power and reliability of the DUV LED chip.
[0052] Epitaxial layer 2 is grown on substrate 1, and buffer layer 21, N-type semiconductor layer 22, quantum well layer 23 and P-type semiconductor layer 24 are stacked sequentially on substrate 1.
[0053] In one embodiment, the substrate 1 comprises a semiconductor structure formed of sapphire (Al2O3), aluminum nitride (AlN), or other III / V compounds, exhibiting high transmittance in the deep ultraviolet band and meeting the requirements for LED epitaxial structure growth. The substrate 1 is specifically determined based on the type of light-emitting diode formed and the epitaxial layer 2 on the substrate 1. For example, in this embodiment, the light-emitting diode is specifically a deep ultraviolet-emitting diode, and the substrate 1 is sapphire (Al2O3).
[0054] In the epitaxial layer 2, the buffer layer 21 is an AlN layer formed on the substrate 1, the N-type semiconductor layer 22 is an N-AlGaN layer, and the P-type semiconductor layer 24 is a P-AlGaN layer or a P-GaN layer.
[0055] The buffer layer 21 reduces the dislocation density caused by stress release during the growth of the epitaxial layer 2, thereby obtaining a high-quality crystal. Specifically, a 10-50 nm layer of aluminum nitride (AlN) is deposited on the substrate 1 using physical vapor deposition (PVD), and then grown at high and low temperatures using metal-organic chemical vapor deposition (MOCVD) to obtain the buffer layer 21.
[0056] In one embodiment, the epitaxial layer 2 further includes a nitride heterostructure layer located between the buffer layer 21 and the N-type semiconductor layer 22.
[0057] A nitride heterostructure layer is deposited on the buffer layer 21. The nitride heterostructure layer is a superlattice layer. The refractive index difference of the superlattice is used to improve the reflection of photons in the ultraviolet band, thereby improving the light output power and reliability of the deep ultraviolet LED chip, so as to promote the application of gallium nitride aluminum (AlGaN) based semiconductor devices.
[0058] In one embodiment, the nitride heterostructure layer is a group III nitride heterostructure layer, such as an AlN / AlGaN layer; further, the thickness of the nitride heterostructure layer is preferably 20-2000 nm.
[0059] The N-type ohmic contact layer 3 covers the N-type semiconductor layer 22 and forms an ohmic contact with the N-type semiconductor layer 22.
[0060] like Figure 2 As shown, Figure 2 This is a schematic diagram of the photolithography process for manufacturing a deep ultraviolet LED chip in one embodiment of the present invention.
[0061] Specifically, such as Figure 2 ① The substrate 1 with epitaxial layer 2 is patterned according to the mask pattern. ICP (Inductively Coupled Plasma) etching equipment is used to etch a part of the epitaxial layer 2 (i.e., P-type semiconductor layer 24, quantum well layer 23, and part of the N-type semiconductor layer 22 of a predetermined thickness) to form a mesa (MESA) structure and expose the N-type semiconductor layer 22.
[0062] In one embodiment, the ICP etching process controls the etching parameters to create a mesa etching angle on the mesa structure. θ And the etched angle θ The etching angle is preferably 30°-90°, and the etching depth is preferably 0.2μm-1.5μm. The first type of gas is preferably a mixture of chlorine (Cl2) and boron trichloride (BCl3). The flow rate of Cl2 is preferably 120-300 sccm, and the flow rate of BCl3 is preferably 10-50 sccm. The etching chamber pressure is preferably 4-10 mT, the upper electrode RF power is preferably 200-500 W, and the lower electrode RF power is preferably 30-60 W.
[0063] like Figure 2② After etching, an N-type ohmic contact layer 3 is fabricated in the etched area of the epitaxial layer 2. The N-type ohmic contact layer 3 is preferably one or more of titanium, aluminum, nickel, gold, chromium, platinum, and tungsten or their alloys, and is fabricated by one or a combination of electron beam evaporation and sputtering. Then, it is annealed at high temperature in an N2 atmosphere. The annealing temperature is preferably 800-1100℃, the annealing time is preferably 30-300s, the annealing atmosphere gas is preferably O2, N2 or a mixture of O2 and N2, and the flow rate is preferably 10-50sccm. After annealing, the N-type ohmic contact layer 3 is formed.
[0064] The fabricated N-type ohmic contact layer 3 serves as an N-type metal electrode covering the N-type semiconductor layer 22 located in the etched region, forming an ohmic contact with the N-type semiconductor layer 22 in the etched region.
[0065] like Figure 2 ③ A reflective current blocking layer 4 is deposited in the non-etched area of epitaxial layer 2 (i.e., the surface of P-type semiconductor layer 24). The reflective current blocking layer is uniformly distributed and partially covers P-type semiconductor layer 24, forming an effective duty cycle.
[0066] In one embodiment, the duty cycle of the reflective current blocking layer 4 is 10%-90%.
[0067] By employing the above scheme, different reflection and current blocking effects can be achieved based on the different duty cycles of the reflective current blocking layer 4. The reflective current blocking layer 4 provides partial coverage, and the duty cycle (coverage rate) can be understood as the ratio of the areas of the orthographic projections of the two structural layers.
[0068] In one embodiment, the reflective current blocking layer 4 comprises one or more of aluminum, rhodium, oxides, or different oxides formed by periodic stacking, wherein the oxides include one or more of silicon dioxide, titanium pentoxide, and hafnium oxide.
[0069] When the reflective current blocking layer 4 is made of aluminum or rhodium, it has high reflectivity in the deep ultraviolet band, which increases the reflection and allows more light emitted from the quantum well layer 23 to be emitted from the substrate 1 through reflection, thereby effectively increasing the light extraction efficiency and ultimately improving the light output power of the deep ultraviolet LED chip. It also has strong stability and good repeatability.
[0070] When the reflective current blocking layer 4 is a composite film layer formed by periodically stacking oxides or different oxides (i.e., DBR, distributed Bragg reflector, thin films with different refractive indices are periodically stacked together), the corresponding emission band involved has high reflectivity, with a reflectivity of not less than 70%.
[0071] Through the above scheme, the reflective current blocking layer 4 is partially covered, which can increase the reflection effect without affecting the formation of ohmic contact. At the same time, since the DBR itself is insulated, even if the current is concentrated directly below the electrode, the presence of the reflective current blocking layer 4 forces the concentrated current to diffuse laterally on the P-side, improving current accumulation and reducing excessive local heat generation caused by the current accumulation effect, thereby improving the light power and reliability of the deep ultraviolet LED chip.
[0072] In one embodiment, the reflective current blocking layer 4 is any one of a strip, a circle, or a square pattern.
[0073] In one embodiment, when the reflected current blocking layer 4 is a strip pattern, its width d is 1. ≤d≤50 When the reflected current blocking layer is a circular pattern, its radius r is 2. ≤r≤25 When the reflected current blocking layer is a square pattern, its width d is 1. ≤d≤50 .
[0074] Size and shape affect the reflection effect and ohmic contact effect. The above scheme uses patterns of different sizes and shapes to balance the reflection effect and ohmic contact effect. The reflective current blocking layer 4 can be set at uniform intervals or distributed non-uniformly. It can be a single pattern or multiple patterns. There are no specific limitations on the arrangement, method, and spacing of the patterns.
[0075] The specific process of depositing and forming the reflective current blocking layer 4 in the non-etched region of epitaxial layer 2 (i.e., the surface of P-type semiconductor layer 24) includes:
[0076] Photolithography is performed on the P-type semiconductor layer 24 to form a photoresist mask layer with different patterns on the surface of the P-type semiconductor layer 24;
[0077] A reflective current blocking layer 4 is deposited on the photoresist mask layer;
[0078] Part of the photoresist mask layer is removed to form reflective current blocking layers 4 with different shapes or different duty cycles.
[0079] In the above process, the deposition of the reflective current blocking layer 4 can be made by one or a combination of electron beam evaporation and sputtering, or by other processes.
[0080] like Figure 2④ After the reflection current blocking layer 4 is deposited, a P-type ohmic contact layer 5 is fabricated in the non-etched area of the epitaxial layer 2. The P-type ohmic contact layer 5 is preferably one or more of nickel, gold, titanium, aluminum, platinum, rhodium or their alloys, as well as metal oxides such as indium tin oxide (ITO), and is fabricated using one or a combination of electron beam evaporation and sputtering. Annealing treatment is required depending on the material properties. The annealing process conditions are as follows: the annealing temperature is preferably 500–750℃, the annealing time is preferably 50–300s, the annealing atmosphere gas is preferably O2, N2 or a mixture of O2 and N2, and the flow rate is preferably 10–50 sccm. After annealing, the P-type ohmic contact layer 5 is formed.
[0081] The fabricated P-type ohmic contact layer 5 serves as a P-type metal electrode covering the P-type semiconductor layer 24 and the reflective current blocking layer 4 located in the non-etched area. The P-type ohmic contact layer 5 forms an ohmic contact with the P-type semiconductor layer 24 in the non-etched area.
[0082] In one embodiment, the P-type ohmic contact layer 5 fully covers the reflective current blocking layer 4.
[0083] With the above scheme, taking the P-type ohmic contact layer 5 preferably being nickel-gold as an example, since both nickel and gold have high absorption loss for deep ultraviolet light, compared to the scheme in which deep ultraviolet light is absorbed by nickel-gold and then reflected, in the scheme provided in this embodiment, the deep ultraviolet light is directly reflected by the reflective current blocking layer 4, and its reflectivity is higher; the reflective current blocking layer 4 partially covers the device, which also avoids abnormal problems such as high device voltage and easy burnout caused by the inability to form an effective ohmic contact when the reflective current blocking layer 4 is fully covered.
[0084] Moreover, the P-type ohmic contact layer 5 fully covers the reflective current blocking layer 4, which also protects the reflective current blocking layer 4 and suppresses reflectivity degradation caused by diffusion clusters and oxidation of aluminum during chip fabrication and use.
[0085] In one embodiment, the deep ultraviolet LED chip further includes a metal thickening layer 6, which is located between the P-type ohmic contact layer 5 and the insulating layer 7, covering the P-type ohmic contact layer 5; and / or located between the N-type ohmic contact layer 3 and the insulating layer 7, covering the N-type ohmic contact layer 3.
[0086] like Figure 2 ⑤ The metal thickening layer 6 serves as the second metal electrode and is deposited using one or a combination of electron beam evaporation and sputtering. The metal thickening layer 6 is preferably one or more of titanium, aluminum, nickel, gold, chromium, platinum, and tungsten, or an alloy thereof.
[0087] The insulating layer 7 is preferably one or a combination of silicon dioxide (SiO2), silicon nitride (Si3N4), titanium pentoxide (Ti3O5), and tantalum oxide (Ta2O5); the thickness of the insulating layer 7 is preferably 300nm-5000nm, and it is preferably deposited by plasma enhanced chemical vapor deposition (PECVD).
[0088] like Figure 2 ⑥ In one embodiment, the insulating layer 7 covers a portion of the metal thickened layer 6. After the insulating layer 7 is deposited, dry etching or wet etching is used to etch a portion of the metal thickened layer 6 covering the N-type ohmic contact layer 3 and the metal thickened layer 6 covering the P-type ohmic contact layer 5 to expose the metal thickened layer 6, i.e., to create an opening.
[0089] like Figure 2 ⑦ The metal pad layer 8 serves as the third metal electrode layer. The pads are vapor-deposited to fully cover the openings of the insulating layer 7, enabling them to conduct electricity and connect to the metal thickened layer 6 on the N-type ohmic contact layer 3 and the metal thickened layer 6 on the P-type ohmic contact layer 5, respectively.
[0090] like Figure 3 As shown, Figure 3 This is a flowchart illustrating the steps of a method for manufacturing a deep ultraviolet LED chip according to an embodiment of the present invention.
[0091] Secondly, embodiments of this application provide a method for manufacturing a deep ultraviolet LED chip with enhanced light output power, comprising the following steps:
[0092] Step S1: An epitaxial layer 2 is formed on the substrate 1. The epitaxial layer 2 includes a buffer layer 21, an N-type semiconductor layer 22, a quantum well layer 23, and a P-type semiconductor layer 24 that are sequentially stacked on the substrate 1.
[0093] Step S2: Etch a portion of the epitaxial layer 2 to expose the N-type semiconductor layer 22;
[0094] Step S3: Fabricate an N-type ohmic contact layer 3. The N-type ohmic contact layer 3 covers the N-type semiconductor layer 22 located in the etched area and forms an ohmic contact with the N-type semiconductor layer 22.
[0095] Step S4: Deposit a reflective current blocking layer 4 in the non-etched area, wherein the reflective current blocking layer 4 partially covers the P-type semiconductor layer 24;
[0096] Step S5: Fabricate a P-type ohmic contact layer 5. The P-type ohmic contact layer 5 covers the reflective current blocking layer 4 and forms an ohmic contact with the P-type semiconductor layer 24.
[0097] Step S6: Fabricate insulating layer 7, which covers N-type ohmic contact layer 3 and P-type ohmic contact layer 5 respectively;
[0098] Step S7: Fabricate a metal pad layer 8, which covers an insulating layer 7 to connect the N-type ohmic contact layer 3 and the P-type ohmic contact layer 5 respectively.
[0099] Through the above scheme, a reflective current blocking layer is deposited between the P-type ohmic contact layer and the P-type semiconductor layer, and the reflective current blocking layer partially covers the P-type semiconductor layer. On the one hand, the partial coverage maintains a good ohmic contact between the P-type ohmic contact layer and the P-type semiconductor layer, thereby ensuring its electrical performance. On this basis, the reflective current blocking layer reflects light, greatly increasing the light extraction effect and significantly reducing the absorption effect of the P-type ohmic contact layer on deep ultraviolet light, effectively improving the light extraction efficiency and thus increasing the light output power of the deep ultraviolet LED chip. On the other hand, the reflective current blocking layer and the P-type semiconductor layer cannot form an ohmic contact, forcing the accumulated current to diffuse laterally, further promoting current expansion, reducing excessive local heat generation caused by the current accumulation effect, thereby improving the light power and reliability of the deep ultraviolet LED chip.
[0100] In one embodiment, step S4, depositing a reflective current blocking layer 4 in the non-etched area, wherein the reflective current blocking layer 4 partially covers the P-type semiconductor layer 24, includes:
[0101] Step S41: Perform photolithography on the P-type semiconductor layer 24 to form a photoresist mask layer with different patterns on the surface of the P-type semiconductor layer 24;
[0102] Step S42: Deposit a reflective current blocking layer 4 on the photoresist mask layer;
[0103] Step S43: Remove part of the photoresist mask layer to form a reflective current blocking layer 4 with different shapes or different duty cycles.
[0104] In one embodiment, a method for manufacturing a deep ultraviolet LED chip includes the following steps:
[0105] Step S1: An epitaxial layer 2 is formed on the substrate 1. The epitaxial layer 2 includes a buffer layer 21, an N-type semiconductor layer 22, a quantum well layer 23, and a P-type semiconductor layer 24 that are sequentially stacked on the substrate 1.
[0106] Step S2: Etch a portion of the epitaxial layer 2 to expose the N-type semiconductor layer 22;
[0107] Step S3: Fabricate an N-type ohmic contact layer 3. The N-type ohmic contact layer 3 covers the N-type semiconductor layer 22 located in the etched area and forms an ohmic contact with the N-type semiconductor layer 22.
[0108] Step S4: Deposit a reflective current blocking layer 4 in the non-etched area, wherein the reflective current blocking layer 4 partially covers the P-type semiconductor layer 24;
[0109] Step S5: Fabricate a P-type ohmic contact layer 5. The P-type ohmic contact layer 5 covers the reflective current blocking layer 4 and forms an ohmic contact with the P-type semiconductor layer 24.
[0110] Step S6: Fabricate a metal thickening layer 6, which covers the N-type ohmic contact layer 3 and the P-type ohmic contact layer 5 respectively;
[0111] Step S7: Fabricate insulating layer 7, which covers the metal thickening layer 6 on the N-type ohmic contact layer 3 and the metal thickening layer 6 on the P-type ohmic contact layer 5 respectively.
[0112] Step S8: Fabricate a metal pad layer 8, which covers an insulating layer 7 to connect the metal thickened layer 6 on the N-type ohmic contact layer 3 and the metal thickened layer 6 on the P-type ohmic contact layer 5, respectively.
[0113] The steps described above have been explained in detail above and will not be repeated here.
[0114] like Figure 4 As shown, Figure 4 This is a schematic diagram comparing the optical power / current curves of a deep ultraviolet LED chip in one embodiment of the present invention.
[0115] A deep ultraviolet LED chip (with a reflective current blocking layer being an aluminum layer obtained by electron beam evaporation) manufactured by the manufacturing method provided in this application, and a deep ultraviolet LED chip without a reflective current blocking layer manufactured by the same method are provided, and the optical power / current curves of the two are compared.
[0116] Depend on Figure 4 It is known that at 100mA, the brightness of the deep ultraviolet LED chip with added reflective current blocking layer provided in this application is increased by more than 5%, indicating that the deep ultraviolet LED chip provided in this application effectively improves light extraction efficiency and enhances light output power. It can be applied in many fields and made into a variety of electronic devices, such as disinfection and sterilization modules, light curing equipment, etc.
[0117] In the description of this application, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.
[0118] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0119] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.
Claims
1. A deep ultraviolet LED chip with enhanced light output power, characterized in that, The deep ultraviolet LED chip includes: Epitaxial layer (2), the epitaxial layer (2) includes a buffer layer (21), an N-type semiconductor layer (22), a quantum well layer (23) and a P-type semiconductor layer (24) stacked in sequence, the P-type semiconductor layer (24) being a P-AlGaN layer or a P-GaN layer; An N-type ohmic contact layer (3) is formed, which covers the N-type semiconductor layer (22) and forms an ohmic contact with the N-type semiconductor layer (22). A reflective current blocking layer (4) partially covers the P-type semiconductor layer (24). A P-type ohmic contact layer (5) is formed, which covers the reflective current blocking layer (4) and forms an ohmic contact with the P-type semiconductor layer (24). An insulating layer (7) covers the N-type ohmic contact layer (3) and the P-type ohmic contact layer (5) respectively. A metal pad layer (8) covers the insulating layer (7) to connect the N-type ohmic contact layer (3) and the P-type ohmic contact layer (5), respectively.
2. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The P-type ohmic contact layer (5) fully covers the reflective current blocking layer (4).
3. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The duty cycle of the reflective current blocking layer (4) is 10%-90%.
4. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The reflective current blocking layer (4) includes one or more of aluminum, rhodium, oxides or different oxides formed by periodic stacking of combined film layers, wherein the oxides include one or more of silicon dioxide, titanium pentoxide, and hafnium oxide.
5. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The reflected current blocking layer (4) can be any one of the strip, circular, or square patterns.
6. The deep ultraviolet LED chip with enhanced light output power as described in claim 5, characterized in that, When the reflective current blocking layer (4) is a strip pattern, its width d 1 ≤ d ≤50 When the reflected current blocking layer (4) is a circular pattern, its radius is... r 2 ≤ r ≤25 When the reflected current blocking layer (4) is a square pattern, its width d 1 ≤ d ≤50 .
7. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The epitaxial layer (2) also includes a nitride heterostructure layer located between the buffer layer (21) and the N-type semiconductor layer (22).
8. The deep ultraviolet LED chip with enhanced light output power as described in claim 1, characterized in that, The deep ultraviolet LED chip also includes a metal thickening layer (6), which is located between the P-type ohmic contact layer (5) and the insulating layer (7), and / or between the N-type ohmic contact layer (3) and the insulating layer (7).
9. A method for manufacturing a deep ultraviolet LED chip with enhanced light output power, characterized in that, Includes the following steps: An epitaxial layer (2) is formed on a substrate (1). The epitaxial layer (2) includes a buffer layer (21), an N-type semiconductor layer (22), a quantum well layer (23), and a P-type semiconductor layer (24) that are stacked sequentially on the substrate (1). Etch a portion of the epitaxial layer (2) to expose the N-type semiconductor layer (22); An N-type ohmic contact layer (3) is fabricated, which covers the N-type semiconductor layer (22) located in the etched region and forms an ohmic contact with the N-type semiconductor layer (22); A reflective current blocking layer (4) is deposited in the non-etched area, and the reflective current blocking layer (4) partially covers the P-type semiconductor layer (24). A P-type ohmic contact layer (5) is fabricated, which covers the reflective current blocking layer (4) and forms an ohmic contact with the P-type semiconductor layer (24); An insulating layer (7) is fabricated, which covers the N-type ohmic contact layer (3) and the P-type ohmic contact layer (5) respectively. A metal pad layer (8) is fabricated, which covers the insulating layer (7) to connect the N-type ohmic contact layer (3) and the P-type ohmic contact layer (5) respectively.
10. The method for manufacturing a deep ultraviolet LED chip with enhanced light output power as described in claim 9, characterized in that, The deposition of a reflective current blocking layer (4) in the non-etched area, wherein the reflective current blocking layer (4) partially covers the P-type semiconductor layer (24), includes: Photolithography is performed on the P-type semiconductor layer (24) to form a photoresist mask layer with different patterns on the surface of the P-type semiconductor layer (24); A reflective current blocking layer (4) is deposited on the photoresist mask layer. Remove part of the photoresist mask layer to form reflective current blocking layers of different shapes or different duty cycles (4).