Intelligent power management and repeated restart prevention method for gateway machine

Abstract

The invention discloses an intelligent power management and repeated restart prevention method for a gateway machine. An independent battery power supply control circuit and an external resistance voltage division type power state detection circuit are arranged on a main board of the gateway machine. The battery power supply control circuit adopts two implementation modes: one implementation mode is based on a switch relay J5 and is suitable for a large current scene; and the second method is based on a P-channel enhanced MOS tube, and is suitable for a low-current and low-power-consumption scene. The resistance voltage division type power supply state detection circuit detects the state of a main power supply through a P02 pin. Meanwhile, virtual sensor data points and guarding tasks are configured, the power supply state is monitored in real time, seamless battery power supply switching when the main power supply is abnormal is achieved, repeated restarting is avoided, and the system has the battery electric quantity calculation and low-voltage protection functions. According to the invention, the problems of power failure alarm delay, repeated restart, battery over-discharge and the like of the main power supply of the gateway machine are solved, the system stability and reliability are improved, the service life is prolonged, and the method is suitable for gateway scenes with different current requirements.

Description

Technical Field

[0001] This invention relates to a method for intelligent power management and prevention of repeated restarts of a gateway device, belonging to the field of intelligent control technology for power distribution substations. Background Technology

[0002] In IoT, edge computing, and industrial automation systems, gateways serve as the core hub connecting terminal devices and upper-layer cloud platforms, and their continuous and stable operation is crucial. Power supply stability is one of the fundamental conditions for ensuring their normal operation. However, in real-world deployment environments, gateways may experience unexpected power outages due to various reasons, such as accidental unplugging of the power cord, power line faults, or circuit breaker tripping. Currently, there are two main technical solutions for power outage monitoring and alarms for gateways: 1. Indirect judgment scheme based on network heartbeat packets This is currently the most common solution. During normal operation, the gateway sends "heartbeat" packets to a remote monitoring server at fixed intervals (e.g., every minute). If the monitoring server does not receive a heartbeat packet from a specific gateway for several consecutive periods, it determines that the gateway may be offline and generates a "device disconnected" alarm. This solution has the following inherent drawbacks: (1) Large alarm delay: The alarm triggering depends on the timeout of multiple heartbeat cycles, which means that it may take several minutes or even longer from the power outage to the generation of the alarm, making it impossible to achieve an instant response at the second level or even faster.

[0003] (2) Poor accuracy: Network congestion, packet loss, and gateway main system software crash (rather than power failure) can all cause heartbeat packet interruption. The monitoring platform cannot distinguish whether the device is "powered down", "network interrupted" or "system crashed", resulting in a high false alarm rate and an inability to provide accurate fault causes, which is not conducive to the operation and maintenance personnel to quickly locate problems.

[0004] (3) Dependence on the main system: This solution requires the gateway's main operating system and network protocol stack to be running normally. If a power outage occurs during the system startup phase or causes the system to crash instantly, the heartbeat mechanism will be completely ineffective.

[0005] 2. Scheme based on different external power supplies This solution requires equipping the gateway with a large external UPS (without power interruption) to continue supplying power when the mains power fails. The UPS management system typically sends alarms to the monitoring system via network protocols (such as SNMP). This solution has the following limitations: (1) High cost: Deploying large UPS equipment increases additional hardware costs and space requirements.

[0006] (2) System complexity: Additional configuration and management of the UPS system are required, which increases the complexity of operation and maintenance.

[0007] (3) Non-integrated: The power failure detection and alarm functions rely on external devices rather than the gateway's own capabilities, resulting in low system coupling.

[0008] Meanwhile, both of these solutions lack effective real-time power outage detection capabilities. Once the external power supply is disconnected, the gateway typically stops working immediately, failing to capture and issue a final alarm signal at the moment of power failure. Maintenance personnel often have to wait until service interruption or through the aforementioned delayed heartbeat timeout mechanism to discover the problem, which greatly affects fault recovery time and system reliability.

[0009] In addition, some gateways are designed with built-in backup batteries, which can maintain short-term operation during power outages. However, existing solutions typically only focus on alarm triggering at the moment of power failure, lacking fine-grained management of backup batteries. This leads to a common problem: after the battery is depleted, the gateway completely shuts down; if the main power supply has not yet been restored, the gateway cannot restart. Furthermore, if the battery level is critical, the gateway may repeatedly attempt to start and shut down under low voltage. This "repeated power-on / off" phenomenon can severely damage the gateway's hardware (such as memory) and file system, shortening the device's lifespan.

[0010] In summary, existing technologies have failed to resolve the contradiction between "power outage alarms" and "battery life management" at the system level. Simple power outage detection and battery switching solutions, while providing temporary battery life, cannot intelligently determine the duration of the external power outage and make proactive power-off decisions at critical moments to protect the battery and the device itself. This leads to a dilemma: either the battery runs out and the device becomes unusable, or repeated power cycles damage the device. Therefore, there is an urgent need in the field for a solution that can not only detect power outages and issue alarms in real time, but also intelligently manage backup batteries to prevent the device from entering abnormal operating states due to insufficient power. Summary of the Invention

[0011] Purpose of the invention: In order to overcome the problems of long delay, poor accuracy and dependence on external systems in the power failure alarm of the gateway in the prior art, the present invention provides a method and system for intelligent power management and anti-repeated restart of the gateway. It is a power failure real-time detection and alarm technology that is integrated into the gateway and has a fast response and is accurate and reliable.

[0012] Technical solution: To achieve the above objectives, the technical solution adopted by this invention is as follows: A method for intelligent power management and anti-repeated restart of a gateway device is provided by setting up an independent battery power supply control circuit and an external resistor voltage divider power status detection circuit on the gateway device motherboard. The battery power supply control circuit has its signal input terminal connected to a general-purpose input / output pin on the gateway motherboard, denoted as pin P00. Its signal output terminal controls a switching device connected to an internal battery to power the gateway by switching the internal battery on or off. The control logic of the battery power supply control circuit is as follows: when pin P00 outputs a low level (logic 0), the internal battery power supply is turned on; when pin P00 outputs a high level (logic 1), the internal battery power supply is turned off. The resistor divider power status detection circuit has its power input terminal connected to the main power supply (e.g., +12V) and its signal output terminal connected to another general-purpose input / output pin on the gateway motherboard, which is designated as pin P02. The control logic of the resistor divider power status detection circuit is as follows: when the main power supply is working normally, pin P02 is pulled to a high level (logic 1); when the main power supply is off, pin P02 is pulled to a low level (logic 0).

[0013] In this case, an independent battery power supply control circuit and an external resistor-divider power status detection circuit are set up on the gateway motherboard. The battery power supply control circuit controls the switching device to turn on and off the power supply to the built-in battery through the P00 pin, and the power status detection circuit detects the main power supply level through the P02 pin (high level indicates normal main power supply, low level indicates main power supply is off). This solution, through a dual-circuit collaborative architecture (battery power supply control + resistor-divider power detection) and functional definitions of GPIO pins (P00 / P02), can solve problems such as repeated restarts and untimely main power status detection caused by disordered power management of the gateway.

[0014] Specifically, the battery power supply control circuit is designed based on a switching relay J5, which includes five ports: ports 1 and 5 are connected to the two ends of the coil, port 2 serves as a common contact, port 3 as a normally open contact, and port 4 as a normally closed contact; port 1 is connected to the power supply (e.g., +12V); port 2 is connected to the positive terminal of the built-in battery and is the power input node of the battery power supply control circuit; port 3 serves as the control node of the battery power supply control circuit, used to detect the real-time voltage of the built-in battery to realize power calculation and low voltage protection functions, and also used to draw charging current from the outside to charge the built-in battery; when port 5 is connected to a low level, ports 2 and 3 are connected, and the built-in battery supplies power to the gateway motherboard; port 4 is left floating, and when port 5 is connected to a high level, ports 2 and 4 are connected, disconnecting the built-in battery; port 5 is connected to the P00 pin to receive the control signal for the built-in battery power supply.

[0015] In this design, the battery power supply control circuit is based on a five-port switching relay J5. Ports 1 and 5 are coil terminals (port 1 connects to the power supply), port 2 is a common contact (connected to the positive terminal of the built-in battery), port 3 is a normally open contact (battery power supply control node), and port 4 is a normally closed contact. The connection between ports 2 and 3 (built-in battery power supply) or port 4 (floating) is controlled by the P00 pin level. When the P00 pin outputs a low level, port 5 is triggered to a low level, connecting ports 2 and 3, and powering the built-in battery. When the P00 pin outputs a high level, port 5 is triggered to a high level, connecting ports 2 and 4, and disconnecting the built-in battery. This solution, through the five-port structure of the switching relay J5 (coil + common / normally open / normally closed contacts) and the level-driven power switching logic, can solve the problems of insufficient reliability in power switching under high current scenarios in gateway devices (such as the tendency of traditional electronic switches to overheat and be damaged).

[0016] Specifically, the battery power supply control circuit is based on a switching MOSFET design. The switching MOSFET design adopts a P-channel enhancement-type MOSFET, whose gate is connected to the P00 pin through a 1KΩ current-limiting resistor, the source is connected to the positive terminal of the built-in battery, and the drain is connected to the power supply circuit of the gateway motherboard through a reverse connection protection diode.

[0017] In this design, the battery power supply control circuit is based on a P-channel enhancement-mode MOSFET. The gate is connected to the P00 pin via a 1KΩ current-limiting resistor, the source is connected to the positive terminal of the internal battery, and the drain is connected to the motherboard power supply circuit via a reverse-connection protection diode. A low level on P00 turns the MOSFET on (battery power supply) and a high level on P00 turns it off (disconnects battery power supply). The conduction logic of the P-channel enhancement-mode MOSFET is as follows: it conducts when the gate voltage is lower than the source voltage (i.e., when the P00 pin outputs a low level, the gate voltage < the source (positive terminal of the internal battery) voltage → the MOSFET conducts → the internal battery powers); it is turned off when the gate voltage is higher than the source voltage (i.e., when the P00 pin outputs a high level, the gate voltage > the source voltage → the MOSFET is turned off → the internal battery power supply is disconnected). This solution, through the selection of the P-channel MOSFET, the external design of the gate current-limiting resistor + drain reverse-connection protection diode, and the level control logic, can solve the problems of slow response speed and high power consumption (such as the large delay and high power consumption of traditional relay switching) in low-current scenarios of gateway devices.

[0018] Specifically, the resistor divider power status detection circuit is designed based on two fixed resistors, R32 and R30. The two ends of resistor R32 are connected to the main power supply (e.g., +12V) and the P02 pin, respectively, while the two ends of resistor R30 are connected to the P02 pin and system ground (GND), respectively. Specifically, resistor R32 is a 1KΩ fixed resistor with an accuracy class of ±5%, and resistor R30 is a 270Ω fixed resistor with an accuracy class of ±5%.

[0019] In this case, the resistor-divider power status detection circuit uses a 270Ω fixed resistor R30 with an accuracy of ±5%, in conjunction with other voltage divider resistors to achieve precise voltage division of the main power supply, ensuring that the P02 pin level (high / low) accurately reflects whether the main power supply is normal. This solution, through the precision and resistance value selection of the key resistor R30, ensures the accuracy of the voltage divider signal, and can solve problems such as misjudgment of the main power supply status due to inaccurate resistor parameters, which could lead to gateway power management errors.

[0020] Specifically, the alarm state of main power failure is virtualized as a sensor data point, and the following steps are performed: S1. Pre-set a gateway power failure alarm model in the gateway device, and add a gateway power failure alarm status model data point to indicate the gateway power failure alarm status. The data point data type is bool, and the remote signaling type is remote signaling. S2. Define a GPIO communication management node within the gateway device; S3. Configure a gateway power failure alarm sensor under the GPIO communication management node according to the gateway power failure alarm model, and add gateway power failure alarm status sensor data points; S4. Configure the alarm threshold for the gateway power failure alarm status sensor data points or gateway power failure alarm status model data points. The data type is remote signaling change alarm, and the alarm threshold is 0. When the collected data value of the gateway power failure alarm status is 0, an alarm is prompted; when the collected data value of the gateway power failure alarm status is 1, a normal status is prompted.

[0021] This solution configures virtual sensor data points in the gateway system, including data collection points for parameters such as power status and battery level, for real-time digital monitoring of the power system's operating status. This approach, through the types of virtual sensor data points (power status, battery level) and the acquisition logic, addresses the problem of delayed fault detection caused by the lack of real-time monitoring methods in gateway power systems.

[0022] Specifically, the method includes the following steps: S1. Load software configuration, including GPIO communication management node, gateway power failure alarm sensor configuration, gateway power failure alarm status sensor data points and alarm thresholds; S2. In the operating system of the gateway device, a power failure alarm monitoring and protection task (task one) is run. During this task, the power failure alarm status sensor data points of the gateway device are continuously monitored: when the data value of the data point changes from 0 to 1, it indicates that the gateway device motherboard has changed from a power failure state to a normal power-on state, and an alarm recovery message is sent; when the data value of the data point changes from 1 to 0, it indicates that the gateway device motherboard has changed from a normal power-on state to a power failure state, and an alarm generation message is sent; the alarm generation message and alarm recovery message are used to notify other tasks or processes in the system to start or terminate the corresponding emergency data backup and processing procedures; S3. In the operating system of the gateway, run a power failure status monitoring and protection task (task two). During this task, read the level status of pin P02 at preset periodic time intervals (e.g., every second), and update the read level status of pin P02 and the reading time to the power failure alarm status sensor data point of the gateway. When the level status of pin P02 is read as 0, if the timer has not been started, start the timer and write control signal 0 to pin P00 after the timer expires. When the level status of pin P02 is read as 1, write control signal 1 to pin P00. If the timer has already been started, stop the timer.

[0023] In this case, a guardian task is set up in the gateway to periodically check the status of virtual sensor data points and GPIO pins. When a power abnormality is detected (such as main power failure or low battery), a protection mechanism (such as power supply switching or alarm) is triggered. This solution, with its periodic detection mechanism, multi-dimensional status detection (sensors + GPIO), and abnormal trigger protection logic, can solve the problems of repeated restarts or hardware damage caused by the lack of an automatic protection mechanism when the gateway experiences power abnormalities.

[0024] Specifically, the built-in battery is a 12V / 5Ah lithium polymer battery, equipped with an independent charging management module. When the main power supply is normal, the built-in battery is in a float charging state, and automatically switches to a discharging state when the main power supply is disconnected. The built-in battery and the main power supply circuit are isolated by diodes to avoid power conflicts.

[0025] This solution utilizes a voltage detection node in the battery power control circuit to calculate the built-in battery level in real time and trigger low-voltage protection (such as cutting off unnecessary loads or triggering an alarm) when the level falls below a threshold. This approach, through real-time battery level calculation and the setting and execution logic of low-voltage protection thresholds, addresses issues such as inadequate management of the gateway's built-in battery level, leading to battery over-discharge damage or sudden power outages.

[0026] This solution, through the aforementioned power management methods, enables seamless battery power switching for the gateway when the main power supply is abnormal, while avoiding repeated restarts and improving system stability and lifespan. Furthermore, the synergistic effect of the overall solution (seamless switching, prevention of repeated restarts), the improvement in system stability and lifespan, can solve problems such as poor system stability and short lifespan caused by power management defects in gateways.

[0027] Beneficial Effects: The intelligent power management and anti-repeated restart method for gateways provided by this invention has the following advantages compared to existing technologies: 1. Seamless switching and instant alarm: Through hardware level detection, detection, battery switching, and alarm can be completed within seconds of the main power being disconnected, ensuring the short-term continuity of services and the instant reporting of faults; 2. Introduction of intelligent battery life management: Through a timer mechanism, a deterministic and controlled operating window (e.g., 20 minutes) is provided for the gateway after a power outage, allowing the system to complete critical operations such as data saving and safe exit; 3. Fundamentally eliminate the harm of "repeated power on and off": Through the "active power off" mechanism, the gateway is safely shut down before the battery is about to run out of power; this effectively prevents repeated system restarts caused by the decrease in battery load capacity under low voltage, greatly protecting the gateway's hardware (especially storage devices) and software file system, and extending the overall lifespan of the device; 4. Automatic power supply recovery: When the main power is restored, the system can automatically identify and switch back to the main power supply, while allowing the backup battery to exit the power supply circuit and enter charging or standby mode, realizing a complete power management closed loop. Attached Figure Description

[0028] Figure 1 A schematic diagram of the battery-powered control circuit structure based on the J5 switching relay; Figure 2 This is a schematic diagram of a resistor-divider power supply status detection circuit. Figure 3 This is a port diagram of the gateway's motherboard; Figure 4 This is a schematic diagram illustrating the implementation process of the method of the present invention. Detailed Implementation

[0029] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0030] The core objective of this project is to provide an intelligent battery power management method that integrates with power outage detection. By introducing a delayed power-off mechanism, it ensures that critical services have sufficient time to safely exit the system while proactively preventing repeated power-on and power-off of the gateway after the battery is depleted, thus protecting the hardware and extending battery life. Specifically, this project aims to achieve the following objectives: 1. An alarm mechanism that can be triggered the instant (within seconds) the gateway's main power is disconnected, reducing alarm latency; 2. A design that does not rely on the gateway's main operating system or network heartbeat, but only on direct detection based on hardware voltage levels, improving the accuracy and reliability of alarms; 3. A low-cost, easily integrated built-in power outage detection solution that does not rely on expensive and complex external devices; 4. An intelligent battery management mechanism that integrates with power outage alarms. By introducing a configurable delayed power-off strategy, it ensures that critical tasks have sufficient time to safely exit after a power outage while proactively and completely cutting off battery power, effectively preventing repeated power-on and power-off of the device due to battery depletion, protecting the hardware, and extending battery life.

[0031] Based on the above product requirements, the intelligent power management and anti-repeated restart method for the gateway is designed as follows.

[0032] I. Hardware Configuration An independent battery power supply control circuit and an external resistor divider power status detection circuit are set on the gateway motherboard. The battery power supply control circuit has its signal input connected to a general-purpose input / output pin on the gateway motherboard, designated P00. Its signal output controls a switching device connected to an internal battery to power the gateway by switching the internal battery on or off. The control logic of the battery power supply control circuit is as follows: when the P00 pin outputs a low level (logic 0), the internal battery power is connected; when the P00 pin outputs a high level (logic 1), the internal battery power is disconnected. The resistor divider power status detection circuit has its power input connected to the main power supply (e.g., +12V), and its signal output connected to another general-purpose input / output pin on the gateway motherboard, designated P02. The control logic of the resistor divider power status detection circuit is as follows: when the main power supply is normal, the P02 pin is pulled high (logic 1); when the main power supply is off, the P02 pin is pulled low (logic 0).

[0033] like Figure 1The diagram illustrates a design scheme for a battery-powered control circuit. This scheme is based on a switching relay J5, which includes five ports: ports 1 and 5 are connected to the two ends of the coil, port 2 serves as a common contact, port 3 as a normally open contact, and port 4 as a normally closed contact. Port 1 is connected to the power supply (e.g., +12V); port 2 is connected to the positive terminal of the built-in battery and is the power input node for the battery-powered control circuit; port 3 serves as the control node for the battery-powered control circuit, used to detect the real-time voltage of the built-in battery for power calculation and low-voltage protection, and also to receive charging current from the outside to charge the built-in battery. When port 5 is low, ports 2 and 3 are connected, supplying power to the gateway motherboard through the built-in battery; port 4 is left floating, and when port 5 is high, ports 2 and 4 are connected, disconnecting the built-in battery; port 5 is connected to the P00 pin to receive control signals for the built-in battery power supply.

[0034] The battery power supply control circuit can also be based on a switching MOSFET design. The switching MOSFET design adopts a P-channel enhancement-type MOSFET, whose gate is connected to the P00 pin through a 1KΩ current-limiting resistor, whose source is connected to the positive terminal of the built-in battery, and whose drain is connected to the power supply circuit of the gateway motherboard through a reverse connection protection diode.

[0035] like Figure 2 The diagram shows a design scheme for a resistor-divided power supply status detection circuit. This scheme is based on two series-connected fixed resistors R32 and R30. The two ends of resistor R32 are connected to the main power supply (e.g., +12V) and the P02 pin, respectively, while the two ends of resistor R30 are connected to the P02 pin and the system ground (GND), respectively. In this scheme, resistor R32 is a 1KΩ fixed resistor with an accuracy class of ±5%, and resistor R30 is a 270Ω fixed resistor with an accuracy class of ±5%.

[0036] II. Software Configuration To simulate a main power failure alarm state as a sensor data point, perform the following steps: S1. Pre-configure a gateway power failure alarm model in the gateway device, and add a gateway power failure alarm status model data point to indicate the gateway power failure alarm status. The data point data type is bool, and the remote signaling type is remote signaling.

[0037] S2. Define a GPIO communication management node within the gateway device.

[0038] S3. Configure a gateway power failure alarm sensor under the GPIO communication management node according to the gateway power failure alarm model, and add gateway power failure alarm status sensor data points.

[0039] S4. Configure the alarm threshold for the gateway power failure alarm status sensor data points or gateway power failure alarm status model data points. The data type is remote signaling change alarm, and the alarm threshold is 0. When the collected data value of the gateway power failure alarm status is 0, an alarm is prompted; when the collected data value of the gateway power failure alarm status is 1, a normal status is prompted.

[0040] III. Status Monitoring S1. Load software configuration, including GPIO communication management node, gateway power failure alarm sensor configuration, gateway power failure alarm status sensor data points and alarm thresholds.

[0041] S2. In the operating system of the gateway machine, a power failure alarm monitoring and protection task (task one) is run. In this task, the power failure alarm status sensor data points of the gateway machine are continuously monitored. When the data value of the data point meets the preset alarm triggering conditions, an alarm generation message is triggered and issued. When the data value of the data point meets the preset alarm recovery conditions, an alarm recovery message is triggered and issued. The alarm generation message and the alarm recovery message are used to notify other tasks or processes in the system to start or terminate the corresponding emergency data backup and processing procedures.

[0042] like Figure 4 As shown, when Task 1 detects a change in the data value of the gateway power failure alarm status sensor data point, it issues a corresponding message: when the data value changes from 0 to 1, it indicates that the gateway motherboard has changed from a power failure state to a normal power-on state, and an alarm recovery message is sent; when the data value changes from 1 to 0, it indicates that the gateway motherboard has changed from a normal power-on state to a power failure state, and an alarm generation message is sent.

[0043] S3. Initialize and run an independent power failure status monitoring guardian task (task two); this task reads the level status of the P02 pin at preset, periodic time intervals (e.g., every second); when the level status of the P02 pin is read as 1, it indicates that the main power supply is connected normally; when the level status of the P02 pin is read as 0, it indicates that the gateway is powered off; update the level status of the P02 pin and the reading time to the gateway power failure alarm status sensor data point.

[0044] like Figure 4As shown, when Task 2 detects a change in the level of the P02 pin, it executes the corresponding battery power supply path control: (1) When the level of the P02 pin changes from 0 to 1, it indicates that the main power supply has been restored. Then, a control signal 1 is written to the P00 pin to disconnect the built-in battery power supply circuit from the gateway motherboard. At the same time, it monitors whether the timer has been started. If the timer has been started, it stops the timer. (2) When the level of the P02 pin changes from 1 to 0, it indicates that the main power supply has been disconnected. A timer with a configurable duration (e.g., 20 minutes) is started. When the timer expires, a control signal 1 is written to the P00 pin to cut off the built-in battery power supply circuit, preventing the built-in battery from running out of power or causing the gateway to restart repeatedly when the built-in battery is low.

[0045] IV. Effect Analysis 1. The overall operational mechanism of this case This case adopts a dual power supply switching mechanism: when the main power supply is normal, it is powered by the main power supply and the built-in battery is in standby or charging state; when the main power supply fails, the battery power supply control circuit immediately switches to battery power supply and the gateway continues to operate.

[0046] This case adopts a hardware and software collaborative mechanism: at the hardware level, the power path is quickly switched through MOSFETs; at the software level, a complete closed loop of status awareness, decision execution, and alarm reporting is achieved through GPIO status monitoring, timed tasks, alarm protection tasks, etc.

[0047] This solution can work with the task design mechanism to ensure continuous system operation. During battery power, the gateway can complete tasks such as unfinished data transmission, cache data persistence, sending the last alarm information, safely shutting down non-core processes, and extending battery life.

[0048] The above mechanism design can solve the following problems: ① Traditional power outage alarms have long delays and high false alarm rates: direct hardware detection enables second-level response; ② Inefficient battery management leads to repeated restarts or complete shutdowns: an intelligent timed power outage mechanism is introduced to protect the equipment; ③ The system relies on external UPS or network heartbeats, resulting in high costs and poor reliability: built-in detection and control reduce costs and improve reliability.

[0049] Typical application scenarios for this case include: ① power distribution stations and industrial IoT gateways: scenarios that require continuous operation and are sensitive to power outages; ② edge computing nodes: need to complete local data processing and uploading after a power outage; ③ unattended equipment: need to automatically alarm and safely shut down after a power outage to avoid hardware damage.

[0050] 2. Rapid response and accurate monitoring in this case This design employs direct hardware-level detection using a resistor-divider power status detection circuit, directly connected to the main power supply and pin P02. When the main power supply is normal, pin P02 is high; when the main power supply is off, pin P02 is low, enabling a rapid power-off response. This design allows the detection process to be independent of the operating system or application, completing status identification within seconds. Furthermore, this design avoids the latency (typically several minutes) and network dependency issues of traditional "heartbeat" solutions.

[0051] This design utilizes software virtualization and an alarm mechanism to map the voltage level of the P02 pin to a virtual sensor data point. This data point is monitored in real-time via a GPIO communication management node and a guardian task. An alarm is generated when the P02 pin state changes from 1 to 0, and an alarm is recovered when it changes from 0 to 1. This design provides clear alarm triggering conditions and a low false alarm rate. Furthermore, it can be integrated with other system tasks (such as data backup and process management) to achieve closed-loop alarm processing.

[0052] 3. Battery intelligent management in this case The P00 pin controls the MOSFET, enabling seamless switching between on and off the built-in battery to ensure continued operation of the gateway after a power outage. When the P02 pin detects a mains power disconnection (1→0), a configurable timer (e.g., 20 minutes) is started. After the timer expires, battery power is actively cut off. This design provides a safe operating window for the system. After the mains power is disconnected, critical operations such as data saving and process exit can be performed using the built-in battery, preventing the gateway from repeatedly restarting under low voltage after the battery is depleted, thus protecting hardware (such as memory) and the file system. When the P02 pin detects a mains power restoration (0→1), the timer is immediately stopped, and the system switches back to mains power, disconnecting the battery power supply circuit, and the battery enters charging or standby mode.

[0053] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any way, and all technical solutions obtained by equivalent substitution or equivalent transformation fall within the protection scope of the present invention.

Claims

1. A method for intelligent power management and preventing repeated restarts of a gateway, characterized in that: Set up an independent battery power control circuit and an external resistor divider power status detection circuit on the gateway motherboard. The battery power supply control circuit has its signal input terminal connected to a general-purpose input / output pin on the gateway motherboard, denoted as pin P00. Its signal output terminal controls a switching device connected to an internal battery to power the gateway by switching the internal battery on or off. The control logic of the battery power supply control circuit is as follows: when pin P00 outputs a low level, the internal battery power is turned on; when pin P00 outputs a high level, the internal battery power is turned off. The resistor divider power status detection circuit has its power input terminal connected to the main power supply and its signal output terminal connected to another general-purpose input / output pin on the gateway motherboard, which is designated as pin P02. The control logic of the resistor divider power status detection circuit is as follows: when the main power supply is working normally, pin P02 is pulled to a high level; when the main power supply is off, pin P02 is pulled to a low level.

2. The intelligent power management and anti-repeated restart method for a gateway device according to claim 1, characterized in that: The battery power supply control circuit is designed based on a switching relay J5, which includes five ports: ports 1 and 5 are connected to the two ends of the coil, port 2 serves as a common contact, port 3 as a normally open contact, and port 4 as a normally closed contact; port 1 is connected to the power supply; port 2 is connected to the positive terminal of the built-in battery and is the power input node for the battery power supply control circuit; port 3 serves as the control node for the battery power supply control circuit, used to detect the real-time voltage of the built-in battery for power calculation and low-voltage protection, and also to receive charging current from the outside to charge the built-in battery; when port 5 is low, ports 2 and 3 are connected, supplying power to the gateway motherboard through the built-in battery; port 4 is left floating; when port 5 is high, ports 2 and 4 are connected, disconnecting the built-in battery; port 5 is connected to the P00 pin to receive control signals for the built-in battery power supply.

3. The intelligent power management and anti-repeated restart method for a gateway device according to claim 1, characterized in that: The battery power supply control circuit is based on a switching MOSFET design. The switching MOSFET design adopts a P-channel enhancement-mode MOSFET, whose gate is connected to the P00 pin through a 1KΩ current-limiting resistor, the source is connected to the positive terminal of the built-in battery, and the drain is connected to the power supply circuit of the gateway motherboard through a reverse connection protection diode.

4. The intelligent power management and anti-repeated restart method for a gateway device according to claim 1, characterized in that: The resistor-divider power status detection circuit is designed based on two fixed resistors R32 and R30. The two ends of resistor R32 are connected to the main power supply and the P02 pin, respectively, and the two ends of resistor R30 are connected to the P02 pin and the system ground, respectively.

5. The intelligent power management and anti-repeated restart method for a gateway device according to claim 4, characterized in that: In the resistor-divider power supply status detection circuit, resistor R32 is a 1KΩ fixed resistor with an accuracy class of ±5%, and resistor R30 is a 270Ω fixed resistor with an accuracy class of ±5%.

6. The intelligent power management and anti-repeated restart method for a gateway device according to claim 1, characterized in that: To simulate a main power failure alarm state as a sensor data point, perform the following steps: S1. Pre-set a gateway power failure alarm model in the gateway device, and add a gateway power failure alarm status model data point to indicate the gateway power failure alarm status. The data point data type is bool, and the remote signaling type is remote signaling. S2. Define a GPIO communication management node within the gateway device; S3. Configure a gateway power failure alarm sensor under the GPIO communication management node according to the gateway power failure alarm model, and add gateway power failure alarm status sensor data points; S4. Configure the alarm threshold for the gateway power failure alarm status sensor data points or gateway power failure alarm status model data points. The data type is remote signaling change alarm, and the alarm threshold is 0. When the collected data value of the gateway power failure alarm status is 0, an alarm is prompted; when the collected data value of the gateway power failure alarm status is 1, a normal status is prompted.

7. The intelligent power management and anti-repeated restart method for a gateway device according to claim 5, characterized in that: The method includes the following steps: S1. Load software configuration, including GPIO communication management node, gateway power failure alarm sensor configuration, gateway power failure alarm status sensor data points and alarm thresholds; S2. In the operating system of the gateway machine, a power failure alarm monitoring and protection task is run. During the task, the power failure alarm status sensor data points of the gateway machine are continuously monitored: when the data value of the data point changes from 0 to 1, it indicates that the gateway machine motherboard has changed from a power failure state to a normal power-on state, and an alarm recovery message is sent; when the data value of the data point changes from 1 to 0, it indicates that the gateway machine motherboard has changed from a normal power-on state to a power failure state, and an alarm generation message is sent. S3. In the operating system of the gateway, run a power failure status monitoring and protection task. During the task, read the level status of the P02 pin at preset periodic time intervals, and update the read level status of the P02 pin and the reading time to the power failure alarm status sensor data point of the gateway. When the level of pin P02 is read as 0, if the timer has not been started, the timer will start counting down. After the timer expires, a control signal 0 will be written to pin P00. When the level of pin P02 is read as 1, a control signal 1 will be written to pin P00. If the timer has already been started, the timer will be stopped.

8. The intelligent power management and anti-repeated restart method for a gateway device according to claim 5, characterized in that: The built-in battery is a 12V / 5Ah lithium polymer battery, equipped with an independent charging management module. When the main power supply is normal, the built-in battery is in a float charging state, and automatically switches to a discharging state when the main power supply is disconnected. The built-in battery is isolated from the main power supply circuit through a diode.

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