Load switching circuit, integrated circuit chip and electronic system

Abstract

The present disclosure provides a load switch circuit, an integrated circuit chip and an electronic system, the load switch circuit comprising: a power transistor for converting an input voltage into an output voltage; the reference voltage generator is used for generating reference voltage changing along with the input voltage; the error amplifier is used for acquiring a feedback signal of the output voltage and an error signal of the reference voltage; the driver is used for generating a grid driving signal according to the error signal, the reference voltage generator samples the input voltage to generate reference voltage, so that the output voltage changes along with the input voltage, and the voltage difference between the output voltage and the input voltage is maintained within a preset range; therefore, the load switch circuit has high efficiency and also has the ripple suppression capability of the structure of the low dropout regulator.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a load switching circuit, an integrated circuit chip, and an electronic system. Background Technology

[0002] Load switch ICs, as key power management devices, are widely used in consumer electronics, industrial control, and automotive electronics. Their core function is to achieve rapid response and precise management of the power supply at the load end by controlling the on / off state of power transistors. Traditional load switch ICs typically operate in the linear region. Although they have high conversion efficiency, they lack ripple suppression capabilities, requiring external filtering components. These additional filtering components increase the bill of materials (BOM) cost and PCB area during the design, manufacturing, or procurement of printed circuit boards (PCBs).

[0003] Therefore, it is hoped that the circuit of the existing load switch chip can be improved so that the circuit can also have ripple suppression capability while meeting the high efficiency requirements of the load switch chip. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a load switching circuit that achieves a balance between high efficiency and ripple suppression capability.

[0005] According to a first aspect of the present disclosure, a load switching circuit is provided, comprising:

[0006] Power transistors are used to convert input voltage into output voltage.

[0007] A reference voltage generator is used to generate a reference voltage that follows changes in the input voltage;

[0008] An error amplifier is used to acquire the error signal between the feedback signal of the output voltage and the reference voltage; and

[0009] A driver is configured to generate a gate drive signal based on the error signal.

[0010] The reference voltage generator samples the input voltage to generate the reference voltage, so that the output voltage follows the changes in the input voltage and maintains the voltage difference between the output voltage and the input voltage within a preset range.

[0011] Optionally, the reference voltage generator includes:

[0012] An analog-to-digital converter (ADC) is used to sample and convert the input voltage into a digital value; and

[0013] A digital-to-analog converter is used to convert the digital value into the reference voltage.

[0014] The voltage difference between the output voltage and the input voltage corresponds to the conversion error of the analog-to-digital converter and the digital-to-analog converter.

[0015] Optionally, the resolution of the analog-to-digital converter and the digital-to-analog converter corresponds to the conversion error.

[0016] Optionally, the reference voltage generator further includes:

[0017] A filtering network is used to filter the reference voltage to obtain a smooth voltage signal.

[0018] Optionally, the reference voltage generator further includes:

[0019] A comparator is used to compare a sampled signal of the input voltage with a reference voltage; and

[0020] The selection module is used to provide a selection signal to the analog-to-digital converter based on the comparison result of the comparator.

[0021] The selection signal is used to switch the sampling rate of the analog-to-digital converter according to the establishment state of the reference voltage, so as to use a high sampling rate in the initial stage and reduce the sampling rate in the stable stage.

[0022] Optionally, the reference voltage generator further includes:

[0023] A resistor divider network is used to sample the analog signal of the input voltage.

[0024] Optionally, the reference voltage generator further includes:

[0025] A clock unit is used to provide a synchronization clock signal to the analog-to-digital converter and the digital-to-analog converter.

[0026] Optionally, it also includes:

[0027] A charge pump is used to generate a charge pump voltage that boosts the input voltage to a level higher than the output voltage, in order to provide the control voltage required by the error amplifier and driver.

[0028] According to a second aspect of the present disclosure, an integrated circuit chip is provided, including the load switching circuit described above.

[0029] According to a third aspect of the present disclosure, an electronic system is provided, including the load switching circuit described above.

[0030] One of the above technical solutions has the following beneficial effects:

[0031] The load switching circuit provided in this disclosure uses an error amplifier, a driver, and a power transistor to form a negative feedback loop. This negative feedback loop employs a low-dropout linear regulator (LDO) structure, thereby enabling the load switching circuit to inherently possess ripple suppression capabilities. Furthermore, by providing a sample-and-hold function for the input voltage Vin of the reference voltage generator, the output voltage Vout dynamically follows the input voltage Vin, while strictly controlling the voltage difference between the output and input within a preset range (e.g., 0.2V), thus achieving high-efficiency switching of the load switch. Compared to existing solutions that require external filtering components on the load switching chip, the load switching circuit of this disclosure achieves high efficiency while also possessing the ripple suppression capabilities of an LDO, and can save PCB area and cost.

[0032] It should be noted that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this disclosure. Attached Figure Description

[0033] Figure 1 A schematic diagram of the load switching circuit according to an embodiment of the present disclosure is shown.

[0034] Figure 2 It shows Figure 1 A schematic diagram of the circuit structure of the first embodiment of the reference voltage generator.

[0035] Figure 3 It shows Figure 1 A schematic diagram of the circuit structure of the second embodiment of the reference voltage generator.

[0036] Figure 4 It shows Figure 1 A schematic diagram of the circuit structure of the third embodiment of the reference voltage generator.

[0037] Figure 5 It shows Figure 1 A schematic diagram of the circuit structure of the intermediate error amplifier and driver.

[0038] Figure 6 The dynamic response characteristic curve of the load switching circuit in an embodiment of this disclosure is shown. Detailed Implementation

[0039] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure.

[0040] Figure 1A schematic diagram of the load switching circuit according to an embodiment of the present disclosure is shown.

[0041] like Figure 1 As shown, the load switching circuit 100 of this embodiment includes: a power transistor M0, a reference voltage generator 110, an error amplifier 120, and a driver 130. The power transistor M0 is used to convert the input voltage Vin received at the second terminal into an output voltage Vout at the first terminal, thereby supplying power to the load. Figure 1 In this embodiment, the load is represented by a load network consisting of resistor R1 and capacitor C1. A reference voltage generator 110 samples the input voltage Vin to generate a reference voltage Vref that follows the changes in the input voltage Vin. An error amplifier 120 acquires the feedback signal Vfb of the output voltage Vout and the error signal Verr of the reference voltage Vref. The non-inverting input of the error amplifier 120 receives the reference voltage Vref, the inverting input receives the feedback signal Vfb, and the output provides the error signal Verr. A driver 130 generates a gate drive signal Vg based on the error signal Verr and provides it to the control terminal of the power transistor M0. In this embodiment, the power transistor M0 is an N-type power transistor with its first terminal as the source, its second terminal as the drain, and its control terminal as the gate. In this embodiment, the inverting input of the error amplifier 120 is connected to the first terminal of the power transistor M0, so the feedback signal Vfb can be directly the same as the output voltage Vout. In some other embodiments, the feedback signal Vfb can also be a voltage divider signal of the output voltage Vout, and correspondingly, the reference voltage Vref can also be scaled by a certain proportion.

[0042] In some preferred embodiments, the load switching circuit 100 further includes a charge pump 140. The circuit design of the charge pump 140, for example, employs a multi-stage voltage multiplier structure, and the input voltage is boosted through the coordinated control of the capacitor array and the switching matrix. Optionally, in this embodiment, by adjusting the relevant parameters in the charge pump, it can be ensured that the charge pump voltage Vcp is always higher than the output voltage Vout by at least 4V, thereby providing a stable high-voltage drive capability for the error amplifier 120 and the driver 130, thus meeting the drive requirements of the N-type power transistor M0. Especially when the voltage difference between the input voltage Vin and the output voltage Vout is small (e.g., 0.2V, which is used as an example below, but other settings can be made according to the actual application), the 4V margin can meet the large current drive requirements of the N-type power transistor M0. However, the embodiments disclosed herein are not limited to this. Those skilled in the art can, according to the needs of the actual application, specifically set the margin of the charge pump voltage Vcp (e.g., it can also be greater than or less than 4V) based on the ability to drive the power transistor M0.

[0043] In this embodiment, the error amplifier 120, driver 130, and power transistor M0 constitute a negative feedback loop, which employs a low-dropout linear regulator (LDO) structure. The error amplifier 120 compares the difference between the feedback signal Vfb of the output voltage Vout and the reference voltage Vref. The driver 130 generates a gate drive signal Vg based on the error signal Verr to control the conduction state of the power transistor M0. This negative feedback loop ensures that the output voltage Vout follows the reference voltage Vref.

[0044] The reference voltage generator 110 dynamically samples the input voltage Vin to generate a reference voltage Vref that matches the input voltage Vin. This reference voltage Vref serves as the reference input for the error amplifier 120. Since the output voltage Vout follows the reference voltage Vref, and the reference voltage Vref follows changes in the input voltage Vin, dynamic tracking of the input voltage Vin by the output voltage Vout can be achieved. Furthermore, the efficiency of the load switching circuit 100 can be approximated as the ratio of the output voltage Vout to the input voltage Vin. When the Vin-Vout voltage difference is stable within a preset range, for example, when the input voltage Vin is 12V, the output voltage Vout is 11.8V, and the Vin-Vout voltage difference is a low difference of 0.2V, the conversion efficiency of the load switching circuit 100 can be very high (reaching over 98%). Even if the input voltage Vin changes, the Vin-Vout voltage difference remains at 0.2V, staying in the dropout region of the LDO. Since the output voltage Vout follows the reference voltage Vref, the voltage difference between Vin and Vref needs to be stabilized at 0.2V. The reference voltage generator 110 will be described in detail below.

[0045] Figure 2 It shows Figure 1 A schematic diagram of the circuit structure of the first embodiment of the reference voltage generator.

[0046] like Figure 2 As shown, the reference voltage generator 110 in this embodiment includes an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a clock unit CLK. In the reference voltage generator 110, the ADC first periodically samples the input voltage Vin, converting the sampling result into an n-bit digital code. This digital code is then converted back into an analog voltage signal by the DAC to form the reference voltage Vref. The clock unit CLK provides a synchronous clock signal for the ADC and DAC, ensuring timing consistency during the sampling and conversion processes.

[0047] In this embodiment, the voltage difference between the reference voltage Vref and the input voltage Vin corresponds to the conversion error of the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC), and this conversion error corresponds to the resolution of the ADC and the DAC. For example, when the resolution is set to 3 bits, the voltage difference between the reference voltage Vref and the input voltage Vin is 0.2V. Accordingly, if other settings are required for the voltage difference between the reference voltage Vref and the input voltage Vin, the resolution needs to be adjusted accordingly. The reference voltage generator 110 can stabilize the Vin-Vref voltage difference at 0.2V, thereby ensuring that the Vin-Vout voltage difference of the load switching circuit 100 remains stable at 0.2V when the input voltage Vin changes or remains constant, thus achieving high conversion efficiency of the load switching circuit 100.

[0048] Figure 3 It shows Figure 1 A schematic diagram of the circuit structure of the second embodiment of the reference voltage generator.

[0049] like Figure 3 As shown, the difference from the first embodiment is that, in this embodiment, the reference voltage generator 110 further includes a filter network 111 composed of resistor R2 and capacitor C2, used to filter the reference voltage Vref to obtain a smooth voltage signal. Resistor R2 and capacitor C2 are connected in series between the output terminal of the digital-to-analog converter (DAC) and ground, and the reference voltage Vref is obtained at the series connection node of resistor R2 and capacitor C2.

[0050] Since the negative feedback loop formed by the error amplifier 120, driver 130 and power transistor M0 in the load switch circuit 100 has ripple suppression function, and the filter network 111 of the reference voltage generator 110 also has ripple suppression function, the load switch circuit 100 in this embodiment can have a dual ripple suppression effect on the input voltage Vin.

[0051] In some preferred embodiments, the reference voltage generator 110 further includes a comparator 112 and a selection module 113, which can achieve rapid establishment and stable maintenance of the reference voltage Vref by dynamically adjusting the sampling rate. For example, the non-inverting input of the comparator 112 is connected to the input voltage Vin, and the inverting input is connected to the reference voltage Vref. Its output provides a comparison result signal to the selection module 113. The selection module 113 sends a sampling rate selection signal Vsel to the analog-to-digital converter (ADC) based on the comparison result of the comparator 112. When the system starts, since the initial value of the reference voltage Vref is much lower than the input voltage Vin, the selection module 113 controls the ADC to quickly capture the fluctuations of the input voltage Vin in a high-speed sampling mode and generate corresponding digital codes. The digital-to-analog converter (DAC) then outputs a rapidly rising reference voltage Vref. When the reference voltage Vref approaches the target value of Vin-0.2V, the selection module 113 switches the ADC to a low-speed sampling mode, reducing dynamic power consumption by lowering the sampling frequency, while maintaining a small adjustment of the reference voltage Vref to adapt to changes in Vin. This design effectively controls the overall heat dissipation of the load switching circuit 100 while ensuring system response speed through an intelligent rate adjustment mechanism, making it particularly suitable for portable device scenarios with strict requirements for startup time and standby power consumption.

[0052] Figure 4 It shows Figure 1 A schematic diagram of the circuit structure of the third embodiment of the reference voltage generator.

[0053] like Figure 4 As shown, the difference from the first embodiment is that, in this embodiment, the reference voltage generator 110 further includes a resistor divider network 114. The resistor divider network 114 is composed of resistors R3 and R4 connected in series, and the voltage divider signal at its series node serves as the input voltage sampling voltage for the analog-to-digital converter (ADC). This design uses the voltage divider network to scale the input voltage Vin, adapting the sampling range of the ADC to the voltage processing capability of the chip's internal circuitry. Simultaneously, through precise control of the voltage division ratio, it ensures that the correspondence between the reference voltage Vref and the input voltage Vin meets the preset voltage difference requirement. For example, when Vin = 12V, by designing the resistance ratio of resistors R3 and R4, the voltage after voltage division (e.g., 0 to 5V) can be adjusted to the input dynamic range of the ADC, thereby improving sampling accuracy and reducing circuit power consumption. The coordinated operation of this voltage divider network with the ADC / DAC ensures that the establishment process of the reference voltage Vref maintains high resolution while avoiding excessive input signal interference to the chip.

[0054] In addition, although Figure 4 Although not illustrated, the reference voltage Vref input to comparator 112 is amplified by a certain ratio.

[0055] In some other embodiments, the input voltage Vin, the reference voltage Vref, and the feedback voltage Vfb can all be reduced by a certain proportion. In this case, the two input terminals of comparator 112 receive the reduced input voltage Vin and the reference voltage Vref, respectively.

[0056] Figure 5 This illustration shows one embodiment of the cooperative control circuit structure of the error amplifier 120 and the driver 130. Those skilled in the art can use other circuit structures as needed, and are not limited to this embodiment. Figure 5 The circuit structure shown is shown.

[0057] In this embodiment, the error amplifier 120 serves as the first-stage driving structure and includes transistors M1 to M4, resistor R5, capacitor C3, and current source I1.

[0058] Transistors M1 and M2 are connected at their first terminals and receive the charge pump voltage Vcp. The control terminals of transistors M1 and M2 are connected. The second terminal of transistor M1 is connected to the control terminal. Transistors M3 and M4 are connected at their first terminals. The control terminal of transistor M3 receives the feedback signal Vfb of the output voltage Vout. The control terminal of transistor M4 receives the reference voltage Vref. Transistors M3 and M1 are connected at their second terminals. Transistors M4 and M2 are connected at their second terminals and provide the error signal Verr. A current source I1 is connected in series between the first terminal of transistor M3 and ground. A resistor R5 and a capacitor C3 are connected in series between the first and second terminals of transistor M2.

[0059] In this embodiment, transistors M1 and M2 are P-type transistors, and transistors M3 and M4 are N-type transistors. The first terminal of transistors M1 to M4 is the source, the second terminal is the drain, and the control terminal is the gate. Transistors M3 and M4 are the input pair of the error amplifier 120. Transistors M1 and M2 form a current mirror structure, and the connection of their control terminals ensures that the current from the current source I1 is dynamically distributed between the input pair M3 and M4. When there is a difference between the feedback signal Vfb and the reference voltage Vref, the conduction state of the input pair M3 and M4 changes accordingly, causing an imbalance in the source current ratio of transistors M1 and M2, thereby generating an error signal Verr at the output of the error amplifier 120. Resistor R5 and capacitor C3 form a compensation network used to compensate for the error signal Verr.

[0060] In this embodiment, the driver 130 serves as a second-stage driving structure, including transistors M5 and M6 and resistor R6.

[0061] Transistor M5's first terminal receives the charge pump voltage Vcp, its control terminal receives the error signal Verr, and its second terminal is connected to the second terminal of transistor M6. Transistor M6 is connected to the control terminal of power transistor M0. Transistor M6's second terminal is connected to the control terminal, and transistor M6 is also connected to the first terminal of power transistor M0. Resistor R6 is connected in series between the control terminal and the first terminal of transistor M6.

[0062] In this embodiment, transistor M5 is a P-type transistor, and transistor M6 is an N-type transistor. The first terminal of transistors M5 and M6 is the source, the second terminal is the drain, and the control terminal is the gate. Transistor M5 serves as the input stage of the second-stage source follower circuit, and transistor M6 serves as the driving mirror stage of power transistor M0. Under the coordinated control of error amplifier 120 and driver 130, the gate drive signal Vg of power transistor M0 is dynamically adjusted through the conduction state of transistor M6. When the error signal Verr reflects the deviation between the output voltage Vout and the reference voltage Vref, driver 130 adjusts the gate voltage of transistor M6 through the change in the source current of transistor M5, thereby precisely controlling the conduction level of power transistor M0. Since the charge pump voltage Vcp provided by charge pump 140 is always at least 4V higher than the output voltage Vout, driver 130 can output a sufficient gate drive voltage (Vg = Vout + 4V) to ensure that the N-type power transistor M0 can still achieve stable conduction with a large current (e.g., 1A) under low voltage drop (Vin - Vout = 0.2V). Meanwhile, resistor R6 acts as a pull-down resistor, quickly pulling down the gate voltage of power transistor M0 when the system is turned off, achieving fast turn-off and zero leakage current characteristics. This two-stage drive structure, combined with the boost capability of the charge pump, not only solves the problem of insufficient drive capability of the load switch at low voltage drop, but also achieves dynamic stability of the output voltage through the internal negative feedback loop.

[0063] Those skilled in the art can integrate the circuits described above into the same chip, or they can choose not to integrate them into the same chip.

[0064] Figure 6 The dynamic response characteristic curves of the load switching circuit in the embodiment of this disclosure are shown. Curve 10 represents the process of the input voltage Vin changing with time, and curve 20 represents the process of the output voltage Vout changing with time. In this figure, Vin is 12V, the voltage difference between Vin and Vout is 0.2V, and the resolution is 3 bits for illustration.

[0065] When the input voltage Vin is superimposed with a ripple signal of a certain frequency, the output voltage Vout completes its initial adjustment within a 2.5ms settling time, and then maintains a constant voltage difference of Vin-Vout=0.2V within the Vin fluctuation range. Through the sample-and-hold mechanism of the reference voltage generator 110, the reference voltage Vref initially approaches the Vin-0.2V target value at a fast conversion rate of 3 bits (e.g., 100ksps). When the reference voltage Vref approaches the Vin-0.2V target value, the system automatically switches to a low-speed sampling mode (e.g., 10ksps). At this time, the reference voltage Vref output by the digital-to-analog converter DAC is processed by the RC filter network 111, and its ripple amplitude is suppressed. The error amplifier 120 drives the conduction degree of the power transistor M0 by comparing the difference between the feedback signal Vfb and the reference voltage Vref, so that the output voltage Vout always follows the change of Vin and maintains a voltage difference of 0.2V.

[0066] This disclosure also provides an integrated circuit chip, including the load switch circuit 100 as described above.

[0067] This disclosure also provides an electronic system including the load switching circuit 100 as described above.

[0068] The load switch circuit 100 provided in this embodiment forms a negative feedback loop through an error amplifier 120, a driver 130, and a power transistor M0. This negative feedback loop employs an LDO structure, thereby enabling the load switch circuit 100 to inherently possess ripple suppression capabilities. Furthermore, by providing a sample-and-hold function for the input voltage Vin to the reference voltage generator 110, the output voltage Vout dynamically follows the input voltage Vin, while strictly controlling the voltage difference between the output and input within a preset range (e.g., 0.2V), thus achieving high-efficiency switching of the load switch 100. Compared to existing solutions that require external filtering components on the load switch chip, the load switch circuit 100 of this disclosure achieves high efficiency while also possessing the ripple suppression capabilities of an LDO, and can save PCB area and cost.

[0069] It should be noted that the numerical values ​​in this article are for illustrative purposes only. In other embodiments of this disclosure, other numerical values ​​may be sampled to implement this solution. The specific values ​​should be reasonably set according to the actual situation, and this disclosure does not limit them.

[0070] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this disclosure and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of this disclosure.

[0071] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A load switching circuit, characterized in that, include: Power transistors are used to convert input voltage into output voltage. A reference voltage generator is used to generate a reference voltage that follows changes in the input voltage; An error amplifier is used to acquire the error signal between the feedback signal of the output voltage and the reference voltage; as well as A driver is configured to generate a gate drive signal based on the error signal. The reference voltage generator samples the input voltage to generate the reference voltage, so that the output voltage follows the changes in the input voltage and maintains the voltage difference between the output voltage and the input voltage within a preset range.

2. The load switching circuit according to claim 1, characterized in that, The reference voltage generator includes: An analog-to-digital converter (ADC) is used to sample and convert the input voltage into a digital value; and A digital-to-analog converter is used to convert the digital value into the reference voltage. The voltage difference between the output voltage and the input voltage corresponds to the conversion error of the analog-to-digital converter and the digital-to-analog converter.

3. The load switching circuit according to claim 2, characterized in that, The resolution of the analog-to-digital converter and the digital-to-analog converter correspond to the conversion error.

4. The load switching circuit according to claim 2, characterized in that, The reference voltage generator also includes: A filtering network is used to filter the reference voltage to obtain a smooth voltage signal.

5. The load switching circuit according to claim 2, characterized in that, The reference voltage generator also includes: A comparator is used to compare a sampled signal of the input voltage with a reference voltage; and The selection module is used to provide a selection signal to the analog-to-digital converter based on the comparison result of the comparator. The selection signal is used to switch the sampling rate of the analog-to-digital converter according to the establishment state of the reference voltage, so as to use a high sampling rate in the initial stage and reduce the sampling rate in the stable stage.

6. The load switching circuit according to claim 2, characterized in that, The reference voltage generator also includes: A resistor divider network is used to sample the analog signal of the input voltage.

7. The load switching circuit according to claim 2, characterized in that, The reference voltage generator also includes: A clock unit is used to provide a synchronization clock signal to the analog-to-digital converter and the digital-to-analog converter.

8. The load switching circuit according to claim 1, characterized in that, Also includes: A charge pump is used to generate a charge pump voltage that boosts the input voltage to a level higher than the output voltage, in order to provide the control voltage required by the error amplifier and driver.

9. An integrated circuit chip, characterized in that, Includes the load switching circuit as described in any one of claims 1 to 8.

10. An electronic system, characterized in that, Includes the load switching circuit as described in any one of claims 1 to 8.

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