Chip, temperature measuring method and electronic equipment

Abstract

The invention provides a chip, a temperature measurement method and electronic equipment, and relates to the technical field of semiconductors, and the actual resistance value of a grid electrode in a conduction transistor can be calculated through values measured by a voltage end and a current end, so that the actual temperature of the conduction transistor is obtained. The chip comprises a plurality of voltage ends, a plurality of current ends and a plurality of same transistors. The distance between every two adjacent transistors in the row direction is nx, the distance between every two adjacent transistors in the column direction is ny, n is a positive integer, and x and y are positive numbers. Each transistor comprises a grid electrode, and the voltage ends are electrically connected with the two ends of a branch circuit where the grid electrodes arranged in the column direction are located. The grid electrodes of the plurality of transistors are electrically connected in a snake-shaped line shape, and the current ends are electrically connected with the grid electrodes at the two ends of the snake-shaped line respectively; and / or, the grids arranged in the column direction are electrically connected, the grids arranged in the row direction are electrically isolated, and the current ends are electrically connected with the two ends of the branches where the grids arranged in the column direction are located respectively.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a chip, a temperature measurement method, and an electronic device. Background Technology

[0002] As integrated circuit density increases, heat dissipation in transistors has become a critical factor affecting transistor performance. Vertical transistors, considered one of the next-generation advanced process options, have vertical channels encased in a large amount of silicon oxide dielectric. Silicon oxides have extremely low thermal conductivity; for example, silicon dioxide has a thermal conductivity only 1 / 100th that of silicon. This extremely low thermal conductivity easily leads to the continuous accumulation of heat on the transistor, i.e., a self-heating effect. This temperature accumulation not only causes a difference between the transistor's operating temperature and the ambient temperature but also results in various problems such as transistor performance drift and decreased reliability. Therefore, accurate characterization of the self-heating effect is crucial in transistor modeling. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a chip, a temperature measurement method, and an electronic device. By measuring the values ​​at the voltage and current terminals, the actual resistance value of the gate in a conducting transistor can be calculated, thereby obtaining the actual temperature of the conducting transistor.

[0004] In a first aspect, this application provides a chip including multiple voltage terminals, multiple current terminals, and multiple identical transistors. The spacing between two adjacent transistors in the row direction is nx, and the spacing between two adjacent transistors in the column direction is ny, where n is a positive integer, and x and y are positive numbers.

[0005] Multiple transistors each include a gate, and voltage terminals are electrically connected to the two ends of the branch containing the gates arranged along the column direction. The gates of the multiple transistors are electrically connected in a serpentine pattern, and current terminals are electrically connected to the gates located at both ends of the serpentine pattern; and / or, the gates arranged along the column direction are electrically connected to each other, and the gates arranged along the row direction are electrically isolated from each other, with current terminals electrically connected to the two ends of the branch containing the gates arranged along the column direction.

[0006] In this application, based on the aforementioned connection relationship, all transistors can be turned off first. A first voltage is detected across at least one branch containing a gate using a voltage terminal, and a first current is applied to the gates of multiple transistors using a current terminal. Based on the first voltage and the first current, the gate resistance value under transistor off-state conditions can be calculated. Simultaneously, by changing the ambient temperature of the multiple transistors and performing traversal measurements of multiple transistor temperatures, multiple sets of relationships between transistor temperature and gate resistance can be obtained. By establishing a functional relationship between transistor temperature and each gate resistance, under consistent ambient temperature conditions, the temperature rise of the gate can be calculated from the change in gate resistance.

[0007] It is also possible to turn on at least one transistor, detect the second voltage across the branch where the gate is electrically connected using the voltage terminal, and apply a second current to the gates of multiple transistors using the current terminal. Replace the turned-on transistor and repeat the above steps twice, obtaining a total of three sets of second voltages and second currents. Using these three sets of second voltages and second currents, and the gate resistance value when the transistor is turned off, calculate the gate resistance value *r'* caused by the turn-on of any transistor, and the temperature effect of the transistor adjacent to the turned-on transistor in the row direction on that transistor. The temperature effect of the transistor adjacent to the conducting transistor in the row direction on the transistor. This allows for the accurate determination of the actual gate resistance of the conducting transistor. Furthermore, based on the functional relationship between transistor temperature and gate resistance calculated when all transistors are off, the temperature rise of the conducting transistor can be calculated by examining the actual gate resistance. The temperature rise of the conducting transistor is influenced not only by its own conduction but also by the temperature of the surrounding transistors. Moreover, the temperature rise of the conducting transistor calculated through resistance is unaffected by the transistor's fabrication process.

[0008] In some possible implementations, multiple voltage terminals are used to: detect a first voltage across the branch containing each column of gates when all transistors are off; and detect a second voltage across the branch containing the electrically connected gates when at least one transistor is on. Multiple current terminals are used to: supply a first current to the gates of the multiple transistors when all transistors are off; and supply a second current to the gates of the multiple transistors when at least one transistor is on.

[0009] Measuring the first voltage and first current across a row of gates can save the number of pads in the chip compared to measuring the voltage and current across a single gate or fewer than a row of gates.

[0010] In some possible implementations, the gates of multiple transistors are electrically connected in a serpentine pattern, with the gates at both ends of the serpentine pattern being a first gate and a second gate, respectively. Multiple voltage terminals include a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal is electrically connected to the first gate, the second voltage terminal is electrically connected to the second gate, and two adjacent rows of gates are electrically connected to the third voltage terminal. Multiple current terminals include a first current terminal and a second current terminal. The first current terminal is electrically connected to the first gate, and the second current terminal is electrically connected to the second gate.

[0011] In other possible implementations, gates arranged along the column direction are electrically connected, while gates arranged along the row direction are electrically isolated; the gates located at both ends of the branch containing each column gate are respectively the first gate and the second gate. Multiple voltage terminals include multiple first voltage terminals and multiple second voltage terminals, with the first voltage terminals electrically connected to the first gate and the second voltage terminals electrically connected to the second gate. Multiple current terminals include multiple first current terminals and multiple second current terminals, with the first current terminals electrically connected to the first gate and the second current terminals electrically connected to the second gate.

[0012] Compared to the scheme where gates are electrically isolated in a row-oriented arrangement, the scheme where the gates of multiple transistors are electrically connected in a serpentine pattern has fewer voltage and current terminals, thus saving the number of pads in the chip.

[0013] In some possible implementations, multiple first voltage terminals are electrically connected as a common voltage terminal, and / or multiple first current terminals are electrically connected as a common current terminal. During measurement, only the voltage at the common voltage terminal and the voltages at the multiple second voltage terminals need to be detected, simplifying the measurement and calculation process. Taking the multiple first current terminals electrically connected as a common current terminal as an example, the current flowing through the multiple current terminals electrically connected to the common current terminal is the same, further simplifying the measurement process.

[0014] In some possible implementations, multiple transistors are arranged in an array, with the spacing between adjacent transistors in the row direction being x and the spacing between adjacent transistors in the column direction being y. Compared to some schemes where the spacing between adjacent transistors is nx or ny, and n is greater than 1, the case where the spacing between adjacent transistors in the row direction is x and the spacing between adjacent transistors in the column direction is y results in more uniform temperature distribution among the transistors, and it is easier to calculate the temperature influence of any transistor on the other transistors.

[0015] In some possible implementations, multiple gates are electrically connected in the same layer as the gates; or, the chip may also include a conductive structure disposed on a different layer from the gates, with the multiple gates electrically connected through the conductive structure.

[0016] Compared to multiple gates being electrically connected through conductive structures arranged in different layers, connecting multiple gates within the same gate layer can reduce the number of chip layers. Furthermore, connecting multiple gates through conductive structures arranged in different layers can save chip area in the planar direction.

[0017] In some possible implementations, the gates of multiple transistors are electrically connected in the same layer as the gates, and all transistors are vertical ring gate transistors, thereby enabling chip miniaturization.

[0018] Secondly, this application provides a temperature measurement method applied to a chip, the chip including multiple voltage terminals, multiple current terminals, and multiple identical transistors. The spacing between two adjacent transistors in the row direction is nx, and the spacing between two adjacent transistors in the column direction is ny. Each transistor includes a gate, and at least the gates arranged along the column direction are electrically connected. Wherein, n is a positive integer, and x and y are positive numbers;

[0019] When multiple transistors are off, the ambient temperature of the transistors is adjusted. A first current is applied to the gates of the transistors through multiple current terminals, and a first voltage is detected across the branch containing each gate at different ambient temperatures through multiple voltage terminals. Based on the first current, first voltage, and ambient temperature, the temperature-resistance relationship between the transistor temperature and the gate resistance is obtained. When different transistors are on, a second current is applied to the gates of the transistors through multiple current terminals three times, and a second voltage is detected across the branch containing the electrically connected gates through multiple voltage terminals. Based on the first current, first voltage, second current, and second voltage, the actual resistance of the gate in the transistor in the on state is obtained. Based on the actual resistance and the temperature-resistance relationship, the temperature of the transistor in the on state is obtained.

[0020] In some possible implementations, multiple transistors are arranged in an array, with the spacing between two adjacent transistors in the row direction being x and the spacing between two adjacent transistors in the column direction being y.

[0021] In some possible implementations, the gates of multiple transistors are electrically connected in a serpentine pattern, with the gates at both ends of the serpentine pattern being a first gate and a second gate, respectively. Multiple voltage terminals include a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal is electrically connected to the first gate, the second voltage terminal is electrically connected to the second gate, and two adjacent rows of gates are electrically connected to the third voltage terminal. Multiple current terminals include a first current terminal and a second current terminal. The first current terminal is electrically connected to the first gate, and the second current terminal is electrically connected to the second gate.

[0022] In some possible implementations, gates arranged along the column direction are electrically connected to each other, and gates arranged along the row direction are electrically isolated from each other; the gates located at both ends of the branch containing each column gate are respectively the first gate and the second gate. Multiple voltage terminals include multiple first voltage terminals and multiple second voltage terminals, with the first voltage terminals electrically connected to the first gate and the second voltage terminals electrically connected to the second gate. Multiple current terminals include multiple first current terminals and multiple second current terminals, with the first current terminals electrically connected to the first gate and the second current terminals electrically connected to the second gate.

[0023] In some possible implementations, when different transistors are turned on, the process of repeatedly applying a second current to the gates of multiple transistors through multiple current terminals and detecting a second voltage across the branches containing the electrically connected gates through multiple voltage terminals includes: when all transistors are turned on, applying a first sub-current to the gates of multiple transistors through current terminals and detecting a first sub-voltage across the branches containing the electrically connected gates through multiple voltage terminals; when all transistors in a row are turned on and the other transistors are turned off, applying a second sub-current to the gates of multiple transistors through current terminals and detecting a second sub-voltage across the branches containing the electrically connected gates through multiple voltage terminals; and when all transistors in a row are turned on and the other transistors are turned off, applying a third sub-current to the gates of multiple transistors through current terminals and detecting a third sub-voltage across the branches containing the electrically connected gates through multiple voltage terminals.

[0024] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0025] Thirdly, this application provides an electronic device, including a circuit board and the chip described in the first aspect, wherein the chip is disposed on the circuit board.

[0026] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0027] Figure 1a A block diagram of an electronic device provided in an embodiment of this application;

[0028] Figure 1b An interaction diagram of the various modules in the memory provided in the embodiments of this application;

[0029] Figure 2a A diagram showing the arrangement of multiple transistors provided in an embodiment of this application;

[0030] Figure 2b A diagram showing the arrangement of multiple transistors provided in an embodiment of this application;

[0031] Figure 3a A connection structure diagram of multiple transistors with voltage terminals and current terminals provided in the embodiments of this application;

[0032] Figure 3b for Figure 3a Top view;

[0033] Figure 3c A structural diagram showing the electrical connection of multiple gates through a conductive structure, provided in an embodiment of this application;

[0034] Figure 4a A connection structure diagram of multiple transistors with voltage terminals and current terminals provided in the embodiments of this application;

[0035] Figure 4b for Figure 4a Top view;

[0036] Figure 5a A connection structure diagram of multiple transistors with voltage terminals and current terminals provided in the embodiments of this application;

[0037] Figure 5b A connection structure diagram of multiple transistors with voltage terminals and current terminals provided in the embodiments of this application;

[0038] Figure 6 A flowchart for measuring temperature provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0041] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0042] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0043] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0044] This application provides an electronic device, which may be a device containing transistors, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product.

[0045] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other communication equipment containing transistors.

[0046] Take the memory in electronic devices as an example. Figure 1a This application provides a schematic diagram of the structure of a memory in an electronic device. The electronic device includes a circuit board, a memory, and other chips or independent devices. The other chips or independent devices may include a processor. The memory and other chips or independent devices are disposed on the circuit board. Figure 1b As shown, the memory includes a storage array, a controller, row decoders, column decoders, etc. The processor can send the address of the selected storage cell to the row decoders and column decoders through the controller. After decoding the received address, the row decoders and column decoders determine the storage cell in the storage array as the selected storage cell, and then perform read and write operations on the selected storage cell. The storage cell includes a transistor and a capacitor. Of course, the transistors in this embodiment are not limited to transistors in memory; they can also be transistors in other circuit structures in electronic devices.

[0047] As mentioned in the background section, with the increasing density of integrated circuits, heat dissipation in transistors has become a significant factor affecting transistor performance. Vertical transistors, considered one of the next-generation advanced process options, have vertical channels encased in a large amount of silicon oxide dielectric. Silicon oxides have extremely low thermal conductivity; for example, silicon dioxide has a thermal conductivity only 1 / 100th that of silicon. This extremely low thermal conductivity easily leads to the continuous accumulation of heat on the transistor, i.e., a self-heating effect. This temperature accumulation not only causes a difference between the transistor's operating temperature and the ambient temperature but also results in various problems such as transistor performance drift and decreased reliability. Therefore, accurate characterization of the self-heating effect is crucial in transistor modeling; in other words, accurate monitoring of the transistor's temperature is necessary.

[0048] Of course, the transistors in the embodiments of this application are not limited to vertical transistors, but can also be transistors of other structures, as long as they are encased in a dielectric, causing heat accumulation and resulting in a self-heating effect.

[0049] To address the above problems, the relevant technologies propose the following two solutions:

[0050] First, the gate of the transistor is led out through four terminals. The voltage and current of the transistor gate are measured. The resistance of the gate is obtained based on the voltage and current. The relationship between the transistor gate resistance and the ambient temperature is obtained through the gate resistance method. Then, by observing the change in the transistor gate resistance under the transistor's operating state, the actual temperature rise of the transistor can be deduced.

[0051] However, the temperature in a transistor channel originates from two sources: 1. heat accumulation caused by the dielectric layer; and 2. heat diffusion from other transistors around the transistor. This necessitates that the endpoints for measuring gate voltage and current be close to the channel. The problem with the thermal clamping test method is that the gate resistance of the transistor is limited by process design rules, and its measurement endpoints typically cannot be close to the channel boundary. This leads to inconsistencies between the measured transistor temperature rise and the actual temperature rise, thus failing to accurately characterize the impact of transistor temperature rise on transistor performance.

[0052] Second, the surrounding transistors are driven by two heated polysilicon channels on the left and right. Since the transistors generate a temperature rise during operation, this temperature rise is used to control the local ambient temperature. A detection transistor is located at the center of this local area. Because there is an approximately linear relationship between the subthreshold swing and the ambient temperature, the temperature rise is obtained by measuring the subthreshold swing of this detection transistor and based on this approximately linear relationship.

[0053] However, this approach has many drawbacks. First, there is a significant temperature gradient during the temperature diffusion of the transistor, and heating the transistor cannot provide a uniform local ambient temperature. Second, the ambient temperature of the transistor is affected by many uncontrollable factors such as transistor spacing, transistor heating conditions, transistor interface states, and channel capacitance. The relationship between the subthreshold swing of the transistor and temperature does not absolutely follow a linear distribution. In mass testing, the changes in subthreshold swing caused by variations in transistor fabrication processes must also be considered. Therefore, it is difficult to accurately obtain the temperature rise change through the subthreshold swing.

[0054] Based on this, embodiments of this application provide a chip including multiple voltage terminals, multiple current terminals, and multiple identical transistors. The multiple identical transistors refer to transistors in which the process parameters of the same structure are identical, and the relative positions of different structures within the transistors are identical. For example, the multiple transistors have the same channel width and channel length, the same source size, the same drain size, and the same gate size.

[0055] like Figure 2a and Figure 2b As shown, the spacing between two adjacent transistors 10 in the row direction is nx, and the spacing between two adjacent transistors 10 in the column direction is ny. Here, n is a positive integer, and x and y are positive numbers.

[0056] For example, such as Figure 2a As shown, multiple transistors 10 are arranged in a matrix, and each element in the matrix is ​​provided with a transistor 10. In the multiple transistors 10 arranged in this way, the spacing between two adjacent transistors 10 in the row direction is x, and the spacing between two adjacent transistors 10 in the column direction is y.

[0057] refer to Figures 3a-3b , Figures 4a-4b The 3x3 matrix shown in the figure includes 9 transistors, and the 9 transistors include 9 gates 11, namely gate G1, gate G2, gate G3, gate G4, gate G5, gate G6, gate G7, gate G8, and gate G9.

[0058] For example, such as Figure 2b As shown, multiple transistors 10 are arranged in a matrix, but no transistor 10 is placed at the position of some elements in the matrix. In the multiple transistors 10 arranged in this way, the spacing between two adjacent transistors 10 in the row direction is nx, and the spacing between two adjacent transistors 10 in the column direction is ny, where n is an integer greater than or equal to 1.

[0059] Compared to Figure 2b The arrangement shown is as follows. Figure 2aIn the arrangement shown, the temperature diffusion of each transistor is more uniform, making it easier to calculate the temperature effect of any transistor on the other transistors.

[0060] like Figure 3a and Figure 3b As shown, each of the multiple transistors 10 includes a gate 11, and the gates 11 of the transistors 10 arranged along the column direction are electrically connected to each other.

[0061] In some possible implementations, the embodiments of this application do not limit the electrical connection positions of the plurality of gates 11; optionally, such as Figure 3a and Figure 3b As shown, multiple gates 11 are electrically connected in the layer containing the gates 11. Alternatively, as... Figure 3c As shown, the chip also includes a conductive structure 20, which is disposed on a different layer from the gate 11, and multiple gates 11 are electrically connected through the conductive structure 20.

[0062] Compared to multiple gates 11 electrically connected through a conductive structure 20 arranged in different layers, electrically connecting multiple gates 11 within the same layer as the gates 11 can reduce the number of chip layers. Furthermore, electrically connecting multiple gates 11 within the same layer as the gates 11, through a conductive structure 20 arranged in different layers, can save chip area in the planar direction.

[0063] In some possible ways of implementation, such as Figure 3a and Figure 3b As shown, the gates 11 of the transistors 10 arranged along the column direction are electrically connected, but the gates 11 of adjacent columns of transistors 10 are electrically isolated, that is, the gates 11 arranged along the row direction are electrically isolated. The voltage terminals are electrically connected to the two ends of the branch where the gates 11 are arranged along the column direction, and the current terminals are electrically connected to the two ends of the branch where the gates 11 are arranged along the column direction.

[0064] Or, in some other possible ways of implementation, such as Figure 4a and Figure 4b As shown, the gates 11 of the transistors 10 arranged along the column direction are electrically connected. Furthermore, the gates 11 of adjacent columns of transistors 10 are electrically connected, and the gates 11 of multiple transistors 10 are electrically connected in a serpentine pattern. The voltage terminals are electrically connected to the two ends of the branch where the gates 11 arranged along the column direction are located, and the current terminals are electrically connected to the gates 11 located at both ends of the serpentine pattern.

[0065] The gates 11 of multiple transistors 10 are electrically connected in a serpentine pattern, meaning that: the gate 11 at the tail of the i-th column of transistors 10 is electrically connected to the gate 11 at the tail of the (i-1)-th column of transistors 10; the gate 11 at the head of the i-th column of transistors 10 is electrically connected to the gate 11 at the head of the (i+1)-th column of transistors 10, where i is an even number. Similarly, the gate 11 at the head of the j-th column of transistors 10 is electrically connected to the gate 11 at the head of the (j-1)-th column of transistors 10; and the gate 11 at the tail of the j-th column of transistors 10 is electrically connected to the gate 11 at the tail of the (j+1)-th column of transistors 10, where j is an odd number greater than 1.

[0066] based on Figure 3a and Figure 4a The two different gate 11 connection methods shown also differ in the connection methods between the multiple voltage terminals and the multiple current terminals and the gate 11 of the transistor.

[0067] like Figure 3a and Figure 3b As shown, the gates 11 of the transistors 10 arranged along the column direction are electrically connected, but the gates 11 of adjacent columns of transistors 10 are electrically isolated. In this case, the gates 11 located at both ends of the branch containing each column of gates 11 are respectively the first gate and the second gate. The multiple voltage terminals include multiple first voltage terminals and multiple second voltage terminals. The first voltage terminals are electrically connected to the first gate, and the second voltage terminals are electrically connected to the second gate. The multiple current terminals include multiple first current terminals and multiple second current terminals. The first current terminals are electrically connected to the first gate, and the second current terminals are electrically connected to the second gate.

[0068] For example, such as Figure 3a and Figure 3b As shown, in the first column of transistors, gates G1 and G3 are located at both ends of gate 11. Gate G1 is electrically connected to voltage terminal V1 and current terminal I1, and gate G3 is electrically connected to voltage terminal V2 and current terminal I2. In the second column of transistors, gates G4 and G6 are located at both ends of gate 11. Gate G4 is electrically connected to voltage terminal V3 and current terminal I3, and gate G6 is electrically connected to voltage terminal V4 and current terminal I4. In the third column of transistors, gates G7 and G9 are located at both ends of gate 11. Gate G7 is electrically connected to voltage terminal V5 and current terminal I5, and gate G9 is electrically connected to voltage terminal V6 and current terminal I6. Voltage terminals V1, V3, and V5 are the first voltage terminals, and voltage terminals V2, V4, and V6 are the second voltage terminals. Current terminals I1, I3, and I5 are the first current terminals, and current terminals I2, I4, and I6 are the second current terminals.

[0069] When all transistors are off, voltage terminals V1 and V2 are used to detect the first voltage V1_1 across the branch containing the first column of gates 11 (gates G1, G2, and G3); voltage terminals V3 and V4 are used to detect the first voltage V1_2 across the branch containing the second column of gates 11 (gates G4, G5, and G6); and voltage terminals V5 and V6 are used to detect the first voltage V1_3 across the branch containing the third column of gates 11 (gates G7, G8, and G9).

[0070] When all transistors are off, current terminals I1 and I2 are used to supply a first current I1_1 to the branch containing the first column of gates 11 (gates G1, G2, and G3); current terminals I3 and I4 are used to supply a first current I1_2 to the branch containing the second column of gates 11 (gates G4, G5, and G6); and current terminals I5 and I6 are used to supply a first current I1_3 to the branch containing the third column of gates 11 (gates G7, G8, and G9).

[0071] The first current I1_1, the first current I1_2, and the first current I1_3 may be the same or different. This application does not limit this. Optionally, for ease of description, unless otherwise stated, the following description will use the example of the first current I1_1, the first current I1_2, and the first current I1_3 being the same.

[0072] When at least one transistor is turned on, voltage terminals V1 and V2 are used to detect the second voltage V2_1 across the branch containing the first column of gates 11 (gates G1, G2, and G3); voltage terminals V3 and V4 are used to detect the second voltage V2_2 across the branch containing the second column of gates 11 (gates G4, G5, and G6); and voltage terminals V5 and V6 are used to detect the second voltage V2_3 across the branch containing the third column of gates 11 (gates G7, G8, and G9).

[0073] When at least one transistor is turned on, current terminals I1 and I2 are used to supply a second current I2_1 to the branch containing the first column of gates 11 (gates G1, G2, and G3); current terminals I3 and I4 are used to supply a second current I2_2 to the branch containing the second column of gates 11 (gates G4, G5, and G6); and current terminals I5 and I6 are used to supply a second current I2_3 to the branch containing the third column of gates 11 (gates G7, G8, and G9).

[0074] The second current I2_1, the second current I2_2, and the second current I2_3 may be the same or different. This application does not limit this. Optionally, for ease of description, unless otherwise stated, the following description will use the example of the second current I2_1, the second current I2_2, and the second current I2_3 being the same.

[0075] Based on this, the first current I1_1, the first current I1_2, and the first current I1_3 can be the same as or different from the second current I2_1, the second current I2_2, and the second current I2_3. This application does not limit this.

[0076] Among some possible implementation methods, it is also possible to... Figure 3a and Figure 3b The illustrated structure can be further modified so that multiple first voltage terminals are electrically connected as a common voltage terminal, or multiple second voltage terminals are electrically connected as a common voltage terminal. For example, as... Figure 5b As shown, voltage terminals V1, V3, and V5 are electrically connected as a common voltage terminal, or, as... Figure 5a As shown, voltage terminals V2, V4, and V6 are electrically connected as a common voltage terminal. And / or, multiple first current terminals are electrically connected as a common current terminal, or multiple second current terminals are electrically connected as a common current terminal. For example, as... Figure 5a As shown, current terminals I1, I3, and I5 are electrically connected as a common current terminal, or, as... Figure 5b As shown, current terminals I2, I4, and I6 are electrically connected as a common current terminal.

[0077] Taking multiple first voltage terminals electrically connected as a common voltage terminal as an example, the voltages of voltage terminals V1, V3, and V5 are all the same. During measurement, only the voltage of the common voltage terminal and the voltages of the multiple second voltage terminals need to be detected, simplifying the measurement and calculation process. Similarly, taking multiple first current terminals electrically connected as a common current terminal as an example, the current flowing through current terminals I1, I3, and I5 is all the same, further simplifying the measurement process.

[0078] like Figure 4a and Figure 4bAs shown, the gates 11 of the transistors 10 arranged along the column direction are electrically connected, and the gates 11 of adjacent columns of transistors 10 are electrically connected. The gates 11 of the plurality of transistors 10 are connected in a serpentine pattern. In this case, the gates 11 at both ends of the serpentine pattern are the first gate and the second gate, respectively. Multiple voltage terminals include a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal is electrically connected to the first gate, the second voltage terminal is electrically connected to the second gate, and the gates 11 of each adjacent column of transistors are electrically connected to the third voltage terminal. Multiple current terminals include a first current terminal and a second current terminal. The first current terminal is electrically connected to the first gate, and the second current terminal is electrically connected to the second gate.

[0079] For example, such as Figure 4a and Figure 4b As shown, gates G1 and G9 are located at both ends of the serpentine line. Gate G1 is electrically connected to voltage terminal V1 and current terminal I1, gate G9 is electrically connected to voltage terminal V4 and current terminal I2, gates G3 and G6 are electrically connected to voltage terminal V2, and gates G4 and G7 are electrically connected to voltage terminal V3. Voltage terminal V1 is the first voltage terminal, voltage terminal V4 is the second voltage terminal, and voltage terminals V2 and V3 are the third voltage terminals. Current terminal I1 is the first current terminal, and current terminal I2 is the second current terminal.

[0080] When multiple transistors are turned off, voltage terminals V1 and V2 are used to detect the first voltage across the branch containing the first column of gates 11 (gates G1, G2, and G3); voltage terminals V2 and V3 are used to detect the first voltage across the branch containing the second column of gates 11 (gates G4, G5, and G6); and voltage terminals V3 and V4 are used to detect the first voltage across the branch containing the third column of gates 11 (gates G7, G8, and G9).

[0081] Assuming the voltage measured at voltage terminal V1 is V1_1, the voltage measured at voltage terminal V2 is V1_2, the voltage measured at voltage terminal V3 is V1_3, and the voltage measured at voltage terminal V4 is V1_4, then the first voltage detected by voltage terminals V1 and V2 across the branch containing the first column of gates 11 is V1_1-V1_2, the first voltage detected by voltage terminals V2 and V3 across the branch containing the second column of gates 11 is V1_2-V1_3, and the first voltage detected by voltage terminals V3 and V4 across the branch containing the third column of gates 11 is V1_3-V1_4.

[0082] When all transistors are off, current terminals I1 and I2 are used to supply a first current I1_1 to the electrically connected gates G1, G2, G3, G4, G5, G6, G7, G8, and G9.

[0083] When at least one transistor is turned on, voltage terminals V1 and V4 are used to detect the voltage difference across the branches containing gates G1, G2, G3, G4, G5, G6, G7, G8, and G9, i.e., the second voltage.

[0084] When at least one transistor is turned on, current terminals I1 and I2 are used to supply a second current to the electrically connected gates G1, G2, G3, G4, G5, G6, G7, G8, and G9.

[0085] Optionally, the first current I1 and the second current I2 may be the same or different, and this application embodiment does not limit this.

[0086] Compared to Figure 3a and Figure 3b The structure shown, Figure 4a and Figure 4b The structure shown has fewer voltage and current terminals, thus saving the number of pads in the chip.

[0087] In this application, based on the aforementioned connection relationship, all transistors can be turned off first. A first voltage is detected across at least one branch containing a gate 11 using a voltage terminal. A first current is then applied to the gates 11 of multiple transistors using a current terminal. Based on the first voltage and the first current, the resistance value of the gate 11 when the transistors are off can be calculated. Simultaneously, by changing the ambient temperature of the multiple transistors and performing traversal measurements of multiple transistor temperatures, multiple sets of relationships between transistor temperature and gate 11 resistance can be obtained. By establishing a functional relationship between transistor temperature and the resistance of each gate 11, under consistent ambient temperature conditions, the temperature rise of the gate 11 can be calculated from the change in the gate 11 resistance.

[0088] It is also possible to turn on at least one transistor, detect the second voltage across the branch where the electrically connected gate 11 is located using the voltage terminal, and apply a second current to the gates 11 of multiple transistors using the current terminal. Replace the turned-on transistor and repeat the above steps twice, obtaining a total of three sets of second voltages and second currents. Using these three sets of second voltages and second currents, and the gate 11 resistance value when the transistor is turned off, calculate the gate 11 resistance value caused by the transistor's own conduction, the temperature effect of the transistor adjacent to the turned-on transistor in the row direction on the transistor, and the temperature effect of the transistor adjacent to the turned-on transistor in the row direction on the transistor. This allows for the accurate determination of the actual resistance of the gate 11 in the conducting transistor. Furthermore, based on the functional relationship between the transistor temperature and the gate 11 resistance calculated when all transistors are off, the temperature rise of the transistor in the conducting state can be calculated by examining the actual resistance of the gate 11. The temperature rise of the conducting transistor is influenced not only by its own conduction but also by the temperature of the surrounding transistors. Moreover, the temperature rise of the conducting transistor calculated through resistance is unaffected by the transistor's fabrication process.

[0089] The following is based on Figure 4a and Figure 4b Using the serpentine structure shown as an example, this paper describes how to accurately measure the resistance value of the gate 11 in a conducting transistor through the above structure.

[0090] The first step is to perform a thermal chuck test, with all nine transistors in the off state, meaning no current flows through their channels. The environment controlling the transistors is stabilized and adjustable. A first current I1_1 is applied to the electrically connected gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 via current terminals I1 and I2. Voltage changes at the gates 11 of each column of transistors are detected using voltage terminals V1, V2, V3, and V4. Specifically, R1 = (V1_1 - V1_2) / I1_1, R2 = (V1_2 - V1_3) / I1_1, and R3 = (V1_3 - V1_4) / I1_1.

[0091] R1 represents the total resistance of gates G1, G2, and G3 when the first column of transistors is off; R2 represents the total resistance of gates G4, G5, and G6 when the second column of transistors is off; and R3 represents the total resistance of gates G7, G8, and G9 when the third column of transistors is off. In subsequent calculations, the resistance of gates G1, G2, and G3 can be considered as R1 / 3, the resistance of gates G4, G5, and G6 as R2 / 3, and the resistance of gates G7, G8, and G9 as R3 / 3.

[0092] By changing the ambient temperature of the transistor and repeating the first step, multiple sets of transistor temperature and gate 11 resistance can be obtained through repeated temperature measurements. By establishing a functional relationship between transistor temperature and gate 11 resistance, the temperature rise of gate 11 can be calculated from the change in gate 11 resistance under consistent ambient temperature conditions. Since the gate 11 is close to the channel in the transistor, its resistance will be affected by the temperature rise of the channel during operation. Therefore, the actual temperature rise of the channel can be deduced from the resistance of gate 11.

[0093] The first step described above uses a row of gates as an example, calculating the total resistance of the row of gates using a first voltage and a first current. Of course, in other possible implementations, the voltage and current across a single gate or a number of gates can also be measured to calculate the resistance of that single gate or the number of gates. Accordingly, a voltage terminal is positioned across the single gate or the number of gates.

[0094] Measuring the first voltage and first current across a row of gates can save the number of pads in the chip compared to measuring the voltage and current across a single gate or fewer than a row of gates.

[0095] In the second step, all nine transistors are in the ON state. With the ambient temperature kept constant, current flows through the transistor channels, causing the transistor temperature to rise. This temperature change leads to a change in the resistance of gate 11. Simultaneously, considering the influence of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Formula 1:

[0096]

[0097] Where r' represents the gate resistance of any transistor due to its own conduction. This indicates the temperature effect of a transistor adjacent to it in the row direction. This indicates the temperature effect of transistors adjacent to the transistor in the column direction on the transistor; r1 represents the total resistance of the gate paths G1, G2, G3, G4, G5, G6, G7, G8, and G9 when all 9 transistors are turned on. The total resistance r1 of the gate paths G1, G2, G3, G4, G5, G6, G7, G8, and G9 can be calculated by the second voltage detected by voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2.

[0098] for Figure 3a and Figure 3b The non-serpentine line structure shown can be calculated using the second voltage V2_1, second voltage V2_2, second voltage V2_3, second current I2_1, second current I2_2, and second current I2_3. The resistance in the first column is the result of dividing V2_1 by I2_1, the resistance in the second column is the result of dividing V2_2 by I2_2, and the resistance in the third column is the result of dividing V2_3 by I2_3. R1 is the sum of the resistances in the three columns. Correspondingly, r2 in Formula 2 and r3 in Formula 3 below can also be achieved in this way, and will not be elaborated further below.

[0099] With all nine transistors turned on, For the transistor located at the center of the 3x3 matrix (the transistor containing gate G5), r` represents the gate resistance value of this transistor due to its own conduction. This indicates the effect of two transistors adjacent to this transistor in the row direction on the temperature and gate resistance of this transistor. This indicates the effect of two transistors adjacent to this transistor in the column direction on the temperature and gate resistance of this transistor.

[0100] With all nine transistors turned on, For the two transistors containing gates G2 and G8, 2r` represents the gate resistance value of these two transistors due to their own conduction. This indicates the effect of a transistor adjacent to these two transistors in the row direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors. This indicates the effect of the four transistors adjacent to these two transistors in the column direction on the temperature and gate resistance of these two transistors (the transistors containing gates G1 and G3 affect the transistor containing gate G2, and the transistors containing gates G7 and G9 affect the transistor containing gate G8).

[0101] With all nine transistors turned on, For the two transistors containing gates G4 and G6, 2r` represents the gate resistance value of these two transistors due to their own conduction. This indicates the effect of the four transistors adjacent to these two transistors in the row direction on the temperature and gate resistance of these two transistors (the transistors containing gates G1 and G7 affect the transistor containing gate G4, and the transistors containing gates G3 and G9 affect the transistor containing gate G6). This indicates the effect of a transistor adjacent to these two transistors in the column direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0102] With all nine transistors turned on, For the four transistors containing gates G1, G3, G7, and G9, 4r′ represents the gate resistance value of these four transistors due to their own conduction. This indicates the effect of two transistors adjacent to these four transistors in the row direction on the temperature and gate resistance of these four transistors (the transistor with gate G4 affects the transistors with gates G1 and G7, and the transistor with gate G6 affects the transistors with gates G3 and G9). This indicates the effect of two transistors adjacent to these four transistors in the column direction on the temperature and gate resistance of these four transistors (the transistor containing gate G2 affects the transistors containing gate G1 and gate G3, and the transistor containing gate G8 affects the transistors containing gate G7 and gate G9).

[0103] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into In the formulas corresponding to the transistors containing gates G4 and G8, which are affected by the row or column direction of the transistor containing G7, the coefficients within the parentheses can be adjusted accordingly. This adjustment can be obtained experimentally. Any corresponding adjustments made by those skilled in the art under the guidance of this application, without departing from the spirit and scope of the claims, are within the protection scope of this application.

[0104] Third, the three transistors containing gates G4, G5, and G6 are turned on, while all other transistors are turned off. Current flows through the channels of these three transistors, causing their temperature to rise. This temperature rise will result in a change in the resistance of gate 11. Simultaneously, considering the influence of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Formula 2:

[0105]

[0106] Where r2 represents the total resistance of the paths through gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 when the three transistors containing gates G4, G5, and G6 are turned on. This total resistance, r2, can be calculated using the second voltage detected at voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2. r represents the gate resistance (r1) of the transistors when they are turned off, which can be calculated in the first step. For example, when the three transistors containing gates G4, G5, and G6 are turned off, their gate resistance (r1) is R1 / 3; when the three transistors containing gates G7, G8, and G9 are turned off, their gate resistance (r3) is R3 / 3.

[0107] When the three transistors containing gates G4, G5, and G6 are turned on... The six transistors with gates G1, G2, G3, G7, G8, and G9 are respectively turned off. The temperature and gate resistance of the transistors with gates G1 and G7 are affected by the conducting transistor with gate G4, which is adjacent to them in the row direction; the temperature and gate resistance of the transistors with gates G2 and G8 are affected by the conducting transistor with gate G5, which is adjacent to them in the row direction; and the temperature and gate resistance of the transistors with gates G3 and G9 are affected by the conducting transistor with gate G6, which is adjacent to them in the row direction.

[0108] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gates G4 and G6, 2r′ represents the gate resistance value of 11 caused by the conduction of these two transistors. This indicates the effect of a transistor adjacent to these two transistors in the column direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0109] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gate G5, r′ represents the gate resistance value of the transistor due to its own conduction. This indicates the effect of the two transistors adjacent to this transistor in the column direction (the transistors containing gate G4 and gate G6) on the temperature and gate resistance of this transistor.

[0110] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into Any corresponding adjustments made by those skilled in the art based on the teachings of this application, without departing from the spirit and scope of the claims, shall be protected by this application.

[0111] In the fourth step, the three transistors containing gates G2, G5, and G8 are turned on, while all other transistors are turned off. Current flows through the channels of these three transistors, causing their temperature to rise. This temperature rise will result in a change in the resistance of gate 11. Simultaneously, considering the influence of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Formula 3:

[0112]

[0113] Where r3 represents the total resistance of the paths through gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 when the three transistors containing gates G2, G5, and G8 are turned on. This total resistance r2 can be calculated using the second voltage detected at voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2. r represents the gate resistance r11 of the transistors when they are turned off, which can be calculated in the first step. For example, when the transistors containing gates G1 and G3 are turned off, their gate resistance r11 is both R1 / 3; when the transistors containing gates G7 and G9 are turned off, their gate resistance r11 is both R3 / 3.

[0114] When the three transistors containing gates G2, G5, and G8 are turned on... The six transistors with gates G1, G3, G4, G6, G7, and G9 are respectively turned off. The temperature and gate resistance of the transistors with gates G1 and G3 are affected by the conducting transistor with gate G2, which is adjacent to them in the column direction; the temperature and gate resistance of the transistors with gates G4 and G6 are affected by the conducting transistor with gate G5, which is adjacent to them in the column direction; and the temperature and gate resistance of the transistors with gates G7 and G9 are affected by the conducting transistor with gate G8, which is adjacent to them in the column direction.

[0115] When the three transistors containing gates G4, G5, and G6 are turned on... Given the two conducting transistors G2 and G8, 2r′ represents the resistance value of gate 11 caused by the conduction of these two transistors. This indicates the effect of a transistor adjacent to these two transistors in the row direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0116] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gate G5, r′ represents the gate resistance value of the transistor due to its own conduction. This indicates the effect of the two transistors adjacent to this transistor in the column direction (the transistors containing gate G2 and gate G8) on the temperature and gate resistance of this transistor.

[0117] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into Any corresponding adjustments made by those skilled in the art based on the teachings of this application, without departing from the spirit and scope of the claims, shall be protected by this application.

[0118] In the above formula, r1, r2, r3, and r can all be obtained through measurement and calculation, and r′, There are three unknowns. These three unknowns can be obtained using the three formulas mentioned above, thus accurately determining the actual resistance of the gate 11 in the conducting transistor. Furthermore, based on the relationship between transistor temperature and gate 11 resistance obtained in the first step, the temperature rise of the transistor in the conducting state can be calculated by determining the actual resistance of the gate 11. The temperature rise of the conducting transistor is affected not only by its own conduction but also by the temperature of the surrounding transistors. Moreover, the temperature rise of the conducting transistor calculated through resistance is not affected by the transistor's fabrication process.

[0119] In the above formula, the parentheses inside each... and The coefficient is related to factors such as the location of any transistor, the number of transistors affecting the temperature of that transistor and the gate resistance of 11, and whether the adjacent transistors are conducting. The above examples are merely illustrative and do not imply that the calculation method of the embodiments of this application is limited to the above formula. Corresponding adjustments made by those skilled in the art under the guidance of this application without departing from the spirit and scope of protection of the claims are all within the protection of this application. For example, the transistor with gate G5 located at the center is affected by four transistors. Therefore, the transistor corresponding to gate G5 and The coefficient is relatively large.

[0120] The second, third, and fourth steps above illustrate r′ using the examples of all nine transistors being turned on, one column of nine transistors being turned on, and one row of nine transistors being turned on, respectively. The derivation process of the three unknowns. Of course, the scope of protection of this application embodiment is not limited to this; as long as the above three steps only require turning on at least one transistor, making formulas one, two, and three different, and then obtaining r′ through formulas one, two, and three... Three unknowns are sufficient. Furthermore, in addition to a 3x3 matrix, multiple transistors can also form other matrices, such as a 2x2 matrix or a 4x4 matrix, etc.

[0121] In some embodiments, the aforementioned plurality of voltage terminals can be voltmeters with infinite internal resistance, so that no current will enter the voltmeter. In this way, the resistance on the line connecting the gate 11 and the voltage terminals will not be included in the calculation, thus improving the accuracy of the calculation.

[0122] In some embodiments, the transistors in this application can be transistors of any structure. Considering the miniaturization of chip size, multiple transistors can all be vertical gate ring transistors.

[0123] In another embodiment, this application also provides a temperature measurement method applied to a chip. The chip structure of this application embodiment is the same as the chip structure of the previous embodiment, such as... Figure 6 As shown, this can be achieved through the following steps:

[0124] S110: When multiple transistors are turned off, adjust the ambient temperature of the multiple transistors, pass a first current to the gate 11 of the multiple transistors through multiple current terminals, and detect the first voltage across the branch where each column of gate 11 is located under different ambient temperatures through multiple voltage terminals; based on the first current, the first voltage, and the ambient temperature, obtain the temperature relationship between the transistor temperature and the resistance of the gate 11.

[0125] For example, with Figure 4a and Figure 4b Taking the illustrated structure as an example, a thermal chuck test is first performed, with all nine transistors in the off state, and no current flowing through the transistor channels. The environment of the control transistors is stabilized and adjustable, and a first current I1_1 is applied to the electrically connected gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 through current terminals I1 and I2. The voltage changes at the gates 11 of each column of transistors are detected using voltage terminals V1, V2, V3, and V4. Where R1 = (V1_1 - V1_2) / I1_1, R2 = (V1_2 - V1_3) / I1_1, and R3 = (V1_3 - V1_4) / I1_1.

[0126] R1 represents the total resistance of gates G1, G2, and G3 when the first column of transistors is off; R2 represents the total resistance of gates G4, G5, and G6 when the second column of transistors is off; and R3 represents the total resistance of gates G7, G8, and G9 when the third column of transistors is off. In subsequent calculations, the resistance of gates G1, G2, and G3 can be considered as R1 / 3, the resistance of gates G4, G5, and G6 as R2 / 3, and the resistance of gates G7, G8, and G9 as R3 / 3.

[0127] By changing the ambient temperature of the transistor and repeating the first step, multiple sets of transistor temperature and gate 11 resistance can be obtained through repeated temperature measurements. By establishing a functional relationship between transistor temperature and gate 11 resistance, the temperature rise of gate 11 can be calculated from the change in gate 11 resistance under consistent ambient temperature conditions. Since the gate 11 is close to the channel in the transistor, its resistance will be affected by the temperature rise of the channel during operation. Therefore, the actual temperature rise of the channel can be deduced from the resistance of gate 11.

[0128] S120, when different transistors are turned on, repeatedly apply a second current to the gates 11 of multiple transistors through multiple current terminals three times, and detect the second voltage across the branches where the multiple gates 11 are electrically connected through multiple voltage terminals.

[0129] Still with Figure 4a and Figure 4b Taking the illustrated structure as an example, initially, all nine transistors are in the on state. With the ambient temperature kept constant, current flows through the transistor channels, causing the transistor temperature to rise. This temperature change leads to a change in the resistance of the gate 11. Simultaneously, considering the influence of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Formula 1:

[0130]

[0131] Where r` represents the resistance value of the gate 11 in any conducting transistor. This indicates the temperature effect of a transistor adjacent to it in the row direction. This indicates the temperature effect of transistors adjacent to the transistor in the column direction on the transistor; r1 represents the total resistance of the gate paths G1, G2, G3, G4, G5, G6, G7, G8, and G9 when all 9 transistors are turned on. The total resistance r1 of the gate paths G1, G2, G3, G4, G5, G6, G7, G8, and G9 can be calculated by the second voltage detected by voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2.

[0132] for Figure 3a and Figure 3bThe non-serpentine line structure shown can be calculated using the second voltage V2_1, second voltage V2_2, second voltage V2_3, second current I2_1, second current I2_2, and second current I2_3. The resistance in the first column is the result of dividing V2_1 by I2_1, the resistance in the second column is the result of dividing V2_2 by I2_2, and the resistance in the third column is the result of dividing V2_3 by I2_3. R1 is the sum of the resistances in the three columns. Correspondingly, r2 in Formula 2 and r3 in Formula 3 below can also be achieved in this way, and will not be elaborated further below.

[0133] With all nine transistors turned on, For the transistor located at the center of the 3x3 matrix (the transistor containing gate G5), r` represents the gate resistance value of this transistor due to its own conduction. This indicates the effect of two transistors adjacent to this transistor in the row direction on the temperature and gate resistance of this transistor. This indicates the effect of two transistors adjacent to this transistor in the column direction on the temperature and gate resistance of this transistor.

[0134] With all nine transistors turned on, For the two transistors containing gates G2 and G8, 2r` represents the gate resistance value of these two transistors due to their own conduction. This indicates the effect of a transistor adjacent to these two transistors in the row direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors. This indicates the effect of the four transistors adjacent to these two transistors in the column direction on the temperature and gate resistance of these two transistors (the transistors containing gates G1 and G3 affect the transistor containing gate G2, and the transistors containing gates G7 and G9 affect the transistor containing gate G8).

[0135] With all nine transistors turned on, For the two transistors containing gates G4 and G6, 2r` represents the gate resistance value of these two transistors due to their own conduction. This indicates the effect of the four transistors adjacent to these two transistors in the row direction on the temperature and gate resistance of these two transistors (the transistors containing gates G1 and G7 affect the transistor containing gate G4, and the transistors containing gates G3 and G9 affect the transistor containing gate G6). This indicates the effect of a transistor adjacent to these two transistors in the column direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0136] With all nine transistors turned on, For the four transistors containing gates G1, G3, G7, and G9, 4r′ represents the gate resistance value of these four transistors due to their own conduction. This indicates the effect of two transistors adjacent to these four transistors in the row direction on the temperature and gate resistance of these four transistors (the transistor with gate G4 affects the transistors with gates G1 and G7, and the transistor with gate G6 affects the transistors with gates G3 and G9). This indicates the effect of two transistors adjacent to these four transistors in the column direction on the temperature and gate resistance of these four transistors (the transistor containing gate G2 affects the transistors containing gate G1 and gate G3, and the transistor containing gate G8 affects the transistors containing gate G7 and gate G9).

[0137] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into In the formulas corresponding to the transistors containing gates G4 and G8, which are affected by the row or column direction of the transistor containing G7, the coefficients within the parentheses can be adjusted accordingly. This adjustment can be obtained experimentally. Any corresponding adjustments made by those skilled in the art under the guidance of this application, without departing from the spirit and scope of the claims, are within the protection scope of this application.

[0138] The second time, the three transistors containing gates G4, G5, and G6 are turned on, while all other transistors are turned off. Current flows through the channels of these three transistors, causing their temperature to rise. This temperature rise will result in a change in the resistance of gate 11. Simultaneously, considering the effect of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Formula 2:

[0139]

[0140] Where r2 represents the total resistance of the paths through gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 when the three transistors containing gates G4, G5, and G6 are turned on. This total resistance r2 can be calculated using the second voltage detected at voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2. r represents the gate resistance r11 of the transistors when they are turned off, which can be calculated using S110. For example, when the three transistors containing gates G4, G5, and G6 are turned off, their gate resistance r11 is always R1 / 3; when the three transistors containing gates G7, G8, and G9 are turned off, their gate resistance r11 is always R3 / 3.

[0141] When the three transistors containing gates G4, G5, and G6 are turned on... The six transistors with gates G1, G2, G3, G7, G8, and G9 are respectively turned off. The temperature and gate resistance of the transistors with gates G1 and G7 are affected by the conducting transistor with gate G4, which is adjacent to them in the row direction; the temperature and gate resistance of the transistors with gates G2 and G8 are affected by the conducting transistor with gate G5, which is adjacent to them in the row direction; and the temperature and gate resistance of the transistors with gates G3 and G9 are affected by the conducting transistor with gate G6, which is adjacent to them in the row direction.

[0142] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gates G4 and G6, 2r′ represents the gate resistance value of 11 caused by the conduction of these two transistors. This indicates the effect of a transistor adjacent to these two transistors in the column direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0143] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gate G5, r′ represents the gate resistance value of the transistor due to its own conduction. This indicates the effect of the two transistors adjacent to this transistor in the column direction (the transistors containing gate G4 and gate G6) on the temperature and gate resistance of this transistor.

[0144] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into Any corresponding adjustments made by those skilled in the art based on the teachings of this application, without departing from the spirit and scope of the claims, shall be protected by this application.

[0145] The third time, the three transistors containing gates G2, G5, and G8 are turned on, while all other transistors are turned off. Current flows through the channels of these three transistors, causing their temperature to rise. This temperature rise will result in a change in the resistance of gate 11. Simultaneously, considering the effect of the surrounding medium on temperature diffusion, the total resistance measured at multiple voltage and current terminals can be expressed by Equation 3:

[0146]

[0147] Where r3 represents the total resistance of the paths through gates G1, G2, G3, G4, G5, G6, G7, G8, and G9 when the three transistors containing gates G2, G5, and G8 are turned on. This total resistance r2 can be calculated using the second voltage detected at voltage terminals V1 and V4, and the second current flowing through current terminals I1 and I2. r represents the gate resistance r11 of the transistors when they are turned off, which can be calculated using S110. For example, when the two transistors containing gates G1 and G3 are turned off, their gate resistance r11 is both R1 / 3; when the two transistors containing gates G7 and G9 are turned off, their gate resistance r11 is both R3 / 3.

[0148] When the three transistors containing gates G2, G5, and G8 are turned on... The six transistors with gates G1, G3, G4, G6, G7, and G9 are respectively turned off. The temperature and gate resistance of the transistors with gates G1 and G3 are affected by the conducting transistor with gate G2, which is adjacent to them in the column direction; the temperature and gate resistance of the transistors with gates G4 and G6 are affected by the conducting transistor with gate G5, which is adjacent to them in the column direction; and the temperature and gate resistance of the transistors with gates G7 and G9 are affected by the conducting transistor with gate G8, which is adjacent to them in the column direction.

[0149] When the three transistors containing gates G4, G5, and G6 are turned on... Given the two conducting transistors G2 and G8, 2r′ represents the resistance value of gate 11 caused by the conduction of these two transistors. This indicates the effect of a transistor adjacent to these two transistors in the row direction (the transistor containing gate G5) on the temperature and gate resistance of these two transistors.

[0150] When the three transistors containing gates G4, G5, and G6 are turned on... For the two conducting transistors corresponding to gate G5, r′ represents the gate resistance value of the transistor due to its own conduction. This indicates the effect of the two transistors adjacent to this transistor in the column direction (the transistors containing gate G2 and gate G8) on the temperature and gate resistance of this transistor.

[0151] Of course, if transistors are not located at the positions of some elements in the matrix, the above formula can be adjusted accordingly. For example, as... Figure 2b As shown, the 3x3 matrix is ​​missing the transistor containing G7. Therefore... The correspondence can be transformed into Any corresponding adjustments made by those skilled in the art based on the teachings of this application, without departing from the spirit and scope of the claims, shall be protected by this application.

[0152] S130: Based on the first current, the first voltage, the second current, and the second voltage, the actual resistance of the gate 11 in the transistor in the on state is obtained.

[0153] S140: Based on the actual resistance of the gate 11 in the transistor in the on state and the temperature-resistance relationship, the temperature of the transistor in the on state is obtained.

[0154] For example, in the above formula, r1, r2, r3, and r can all be obtained through measurement and calculation, and r′, There are three unknowns. These three unknowns can be obtained using the three formulas mentioned above, thus accurately determining the actual resistance of the gate 11 in the conducting transistor. Furthermore, based on the correspondence between the transistor temperature and the gate 11 resistance obtained in S110, the temperature rise of the transistor in the conducting state can be calculated by obtaining the actual resistance of the gate 11 in the conducting transistor. The temperature rise of the conducting transistor is affected not only by its own conduction but also by the temperature of the surrounding transistors.

[0155] In the above formula, the parentheses inside each... and The coefficient is related to factors such as the location of any transistor, the number of transistors affecting the temperature of that transistor and the gate resistance of 11, and whether the adjacent transistors are conducting. The above examples are merely illustrative and do not imply that the calculation method of the embodiments of this application is limited to the above formula. Corresponding adjustments made by those skilled in the art under the guidance of this application without departing from the spirit and scope of protection of the claims are all within the protection of this application. For example, the transistor with gate G5 located at the center is affected by four transistors. Therefore, the transistor corresponding to gate G5 and The coefficient is relatively large.

[0156] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A chip, characterized in that, It includes multiple voltage terminals, multiple current terminals, and multiple identical transistors; The spacing between two adjacent transistors in the row direction is nx, and the spacing between two adjacent transistors in the column direction is ny, where n is a positive integer, and x and y are positive numbers; Each of the plurality of transistors includes a gate, and the voltage terminals are respectively electrically connected to the two ends of the branch where the gate is located, which is arranged along the column direction; The gates of the plurality of transistors are electrically connected in a serpentine pattern, and the current terminals are respectively electrically connected to the gates located at both ends of the serpentine pattern; and / or, the gates arranged along the column direction are electrically connected to each other, and the gates arranged along the row direction are electrically isolated from each other, and the current terminals are respectively electrically connected to both ends of the branch where the gates are located along the column direction.

2. The chip according to claim 1, characterized in that, The plurality of voltage terminals are used to: detect a first voltage across each branch containing the gate when all the plurality of transistors are off; and detect a second voltage across the branches containing the plurality of electrically connected gates when at least one of the transistors is on. The plurality of current terminals are used to: when all the plurality of transistors are turned off, to pass a first current to the gate of the plurality of transistors; And, when at least one of the transistors is turned on, a second current is supplied to the gate of the plurality of transistors.

3. The chip according to claim 1 or 2, characterized in that, The gates of the plurality of transistors are electrically connected in a serpentine line, and the gates at both ends of the serpentine line are the first gate and the second gate, respectively. The plurality of voltage terminals include a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal is electrically connected to the first gate, the second voltage terminal is electrically connected to the second gate, and two adjacent columns of the gates are electrically connected to the third voltage terminal. The plurality of current terminals include a first current terminal and a second current terminal, wherein the first current terminal is electrically connected to the first gate and the second current terminal is electrically connected to the second gate.

4. The chip according to claim 1 or 2, characterized in that, The gates arranged along the column direction are electrically connected to each other, and the gates arranged along the row direction are electrically isolated from each other; the gates located at both ends of the branch where the gates in each column are located are the first gate and the second gate, respectively. The plurality of voltage terminals include a plurality of first voltage terminals and a plurality of second voltage terminals, wherein the first voltage terminals are electrically connected to the first gate and the second voltage terminals are electrically connected to the second gate; The plurality of current terminals include a plurality of first current terminals and a plurality of second current terminals, wherein the first current terminals are electrically connected to the first gate and the second current terminals are electrically connected to the second gate.

5. The chip according to claim 4, characterized in that, The plurality of first voltage terminals are electrically connected as a common voltage terminal, and / or the plurality of first current terminals are electrically connected as a common current terminal.

6. The chip according to any one of claims 1-5, characterized in that, The plurality of transistors are arranged in an array, with the spacing between two adjacent transistors in the row direction being x and the spacing between two adjacent transistors in the column direction being y.

7. The chip according to any one of claims 1-6, characterized in that, The plurality of gates that are electrically connected are electrically connected in the layer in which the gates reside; or, The chip also includes a conductive structure, which is disposed on a different layer from the gate, and the plurality of gates are electrically connected through the conductive structure.

8. The chip according to claim 7, characterized in that, The gates of the plurality of transistors are electrically connected in the layer where the gates are located, and the plurality of transistors are all vertical gate ring transistors.

9. A temperature measurement method applied to a chip, characterized in that, The chip includes multiple voltage terminals, multiple current terminals, and multiple identical transistors; The spacing between two adjacent transistors in the row direction is nx, and the spacing between two adjacent transistors in the column direction is ny. Each of the plurality of transistors includes a gate, and the gates arranged at least along the column direction are electrically connected; wherein, n is a positive integer, and x and y are positive numbers. When all transistors are turned off, the ambient temperature of the transistors is adjusted, a first current is supplied to the gates of the transistors through the multiple current terminals, and the first voltage across the branch where the gate is located is detected at different ambient temperatures through the multiple voltage terminals; based on the first current, the first voltage, and the ambient temperature, the temperature-resistance relationship between the transistor temperature and the gate resistance is obtained. When different transistors are turned on, the second current is repeatedly supplied to the gates of the multiple transistors through the multiple current terminals three times, and the second voltage across the branches where the multiple gates are electrically connected is detected through the multiple voltage terminals; Based on the first current, the first voltage, the second current, and the second voltage, the actual resistance of the gate in the transistor in the on state is obtained; The temperature of the transistor in the on-state is obtained based on the actual resistance and the temperature-resistance relationship.

10. The temperature measurement method according to claim 9, characterized in that, The plurality of transistors are arranged in an array, with the spacing between two adjacent transistors in the row direction being x and the spacing between two adjacent transistors in the column direction being y.

11. The temperature measurement method according to claim 9 or 10, characterized in that, The gates of the plurality of transistors are electrically connected in a serpentine line, and the gates at both ends of the serpentine line are the first gate and the second gate, respectively. The plurality of voltage terminals include a first voltage terminal, a second voltage terminal, and a third voltage terminal. The first voltage terminal is electrically connected to the first gate, the second voltage terminal is electrically connected to the second gate, and two adjacent columns of the gates are electrically connected to the third voltage terminal. The plurality of current terminals include a first current terminal and a second current terminal, wherein the first current terminal is electrically connected to the first gate and the second current terminal is electrically connected to the second gate.

12. The temperature measurement method according to claim 9 or 10, characterized in that, The gates arranged along the column direction are electrically connected to each other, and the gates arranged along the row direction are electrically isolated from each other; the gates located at both ends of the branch where the gates in each column are located are the first gate and the second gate, respectively. The plurality of voltage terminals include a plurality of first voltage terminals and a plurality of second voltage terminals, wherein the first voltage terminals are electrically connected to the first gate and the second voltage terminals are electrically connected to the second gate; The plurality of current terminals include a plurality of first current terminals and a plurality of second current terminals, wherein the first current terminals are electrically connected to the first gate and the second current terminals are electrically connected to the second gate.

13. The temperature measurement method according to any one of claims 9-12, characterized in that, The step of repeatedly supplying a second current to the gates of the plurality of transistors through the plurality of current terminals three times when different transistors are turned on, and detecting the second voltage across the branches where the gates are electrically connected through the plurality of voltage terminals, includes: When all the transistors are turned on, a first sub-current is supplied to the gates of the transistors through the current terminal, and a first sub-voltage is detected across the branches where the gates are electrically connected through the multiple voltage terminals. When all the transistors in one column are turned on and all the other transistors are turned off, a second sub-current is supplied to the gates of the plurality of transistors through the current terminal, and the second sub-voltages at both ends of the branches where the gates are electrically connected are detected through the plurality of voltage terminals. When all the transistors in one row are turned on and all the other transistors are turned off, a third sub-current is supplied to the gates of the plurality of transistors through the current terminal, and the third sub-voltage at both ends of the branches where the gates are electrically connected is detected through the plurality of voltage terminals.

14. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-8, the chip being disposed on the circuit board.

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