Electronic device and method of manufacturing same

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device includes a substrate and a first dielectric disposed over the substrate. The first dielectric defines a first trace opening. A first conductive pattern may be disposed in the trace opening and recessed from an upper side of the first dielectric. The first conductive pattern includes a first trace. A second conductive pattern may be disposed over the upper side of the first dielectric. The second conductive pattern may include second traces interleaved over the first traces. A second dielectric may be disposed over the second conductive pattern and extend to the first trace in the trace opening. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically, to electronic devices and methods of manufacturing electronic devices. Background Technology

[0002] Previous electronic packaging and methods for forming electronic packages have shortcomings, such as resulting in excessive cost, reduced reliability, relatively low performance, or excessively large package size. Other limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with those disclosed herein and referring to the drawings. Summary of the Invention

[0003] One embodiment of the present invention is an electronic device comprising: a substrate; a first dielectric disposed above the substrate, the first dielectric defining a first trace opening; a first conductive pattern disposed in the trace opening and recessed from an upper side of the first dielectric, the first conductive pattern including a first trace; a second conductive pattern disposed above the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; and a second dielectric disposed above the second conductive pattern and extending into the first trace in the trace opening.

[0004] In the electronic device according to the present invention, the first dielectric defines an opening transverse to the trace opening and extending through the first dielectric, wherein the first conductive pattern includes a first conductive via disposed in the opening and recessed from the upper side of the first dielectric.

[0005] In the electronic device according to the present invention, the second conductive pattern includes a conductive pad coupled to the first conductive via.

[0006] In the electronic device according to the present invention, the second dielectric is disposed above the conductive pad.

[0007] In the electronic device according to the present invention, the first trace is embedded in the first dielectric.

[0008] In the electronic device according to the present invention, the second trace is formed over the first dielectric using a semi-additive method before the second dielectric is provided.

[0009] The electronic device according to the present invention further includes a seed layer disposed between the second conductive pattern and the upper side of the first dielectric.

[0010] The electronic device according to the present invention further includes: a third dielectric disposed between the first dielectric and the substrate, the third dielectric defining a ground opening; and a third conductive pattern located in the ground opening, the third conductive pattern including a ground plane disposed between the first trace and the substrate.

[0011] In the electronic device according to the present invention, the substrate includes electronic components, the electronic components comprising component interconnects electrically coupled to the first conductive pattern.

[0012] The electronic device according to the present invention further includes a bottom filler disposed between the electronic component and the first dielectric.

[0013] Another embodiment of the present invention is an electronic device comprising: a substrate; a first dielectric disposed above the substrate, the first dielectric defining a first trace opening; a first conductive pattern disposed in the first trace opening and recessed from an upper side of the first dielectric, the first conductive pattern including a first trace; a second conductive pattern disposed above the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; a second dielectric disposed above the second conductive pattern and extending into the trace opening of the first conductive pattern; a third dielectric disposed above the second dielectric, the third dielectric defining a second trace opening; a third conductive pattern disposed in the second trace opening and recessed from the upper side of the third dielectric, the third conductive pattern including a third trace; a fourth conductive pattern disposed above the upper side of the third dielectric, the fourth conductive pattern including fourth traces intersecting above the third trace; and a fourth dielectric disposed above the fourth conductive pattern and extending into the trace opening of the third trace.

[0014] The electronic device according to another embodiment of the invention further includes a fifth conductive pattern disposed in a ground opening defined by a second dielectric, the fifth conductive pattern being included in a ground plane between the second trace and the third trace.

[0015] The electronic device according to another embodiment of the invention further includes an outward terminal disposed in an opening defined in the fourth dielectric.

[0016] Another aspect of the present invention is a method of manufacturing an electronic device, comprising: providing a substrate; providing a first dielectric over the substrate, the first dielectric defining a first trace opening; providing a first conductive pattern in the first trace opening, wherein the first conductive pattern is recessed from an upper side of the first dielectric, the first conductive pattern including a first trace; providing a second conductive pattern over the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; and providing a second dielectric over the second conductive pattern, wherein the second dielectric extends into the first trace in the first trace opening.

[0017] In yet another embodiment of the method according to the invention, providing the second conductive pattern further comprises: providing a seed layer over the first dielectric; providing a mask over the first conductive pattern, wherein the seed layer over the first dielectric is exposed through a second trace opening defined by the mask; providing the second conductive pattern in the opening; and removing the mask.

[0018] In another embodiment of the method according to the invention, the first trace is provided as an embedded trace.

[0019] In yet another embodiment of the method according to the invention, the second trace is provided using a semi-additive method prior to the provision of the second dielectric.

[0020] The method according to another embodiment of the present invention further includes: providing a third dielectric over the substrate, the third dielectric defining a ground opening; and providing a third conductive pattern in the ground opening, the third conductive pattern including a ground plane.

[0021] The method according to another embodiment of the present invention further comprises: providing a third dielectric disposed above the second dielectric, the third dielectric defining a second trace opening; providing a third conductive pattern disposed in the second trace opening and recessed from the upper side of the third dielectric, the third conductive pattern including a third trace; providing a fourth conductive pattern disposed above the upper side of the third dielectric, the fourth conductive pattern including fourth traces intersecting above the third trace; and providing a fourth dielectric disposed above the fourth conductive pattern and extending into the third trace in the second trace opening.

[0022] The method according to another embodiment of the invention further includes providing a ground plane in the opening defined by the second dielectric and above the second conductive pattern. Attached Figure Description

[0023] Figure 1 A cross-sectional view of an example electronic device is shown.

[0024] Figures 2A to 2N This demonstrates an exemplary method for manufacturing electronic devices using cross-sectional views.

[0025] Figure 3 A cross-sectional view of an example electronic device is shown.

[0026] Figure 4 A cross-sectional view of an example electronic device is shown.

[0027] Figure 5 A cross-sectional view of an example electronic device is shown.

[0028] Figures 6A to 6E This demonstrates an exemplary method for manufacturing electronic devices using cross-sectional views.

[0029] Figure 7 A cross-sectional view of an example electronic device is shown. Detailed Implementation

[0030] The following discussion presents various examples of providing electronic devices and methods of manufacturing electronic devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0031] The drawings illustrate general construction methods and may omit descriptions and details of well-known features and techniques to avoid unnecessarily obscuring this disclosure. Furthermore, elements in the drawings are not necessarily drawn to scale. For example, some elements in the drawings may be enlarged relative to other elements to aid in understanding the examples discussed in this disclosure. The same reference numerals in different drawings denote the same elements.

[0032] The term "or" refers to any one or more items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0033] The terms “comprises / comprising” and “includes / including” are “open” terms and specify the presence of the stated feature, but do not exclude the presence or addition of one or more other features.

[0034] The terms “first,” “second,” etc., may be used herein to describe various elements. These elements are not limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element discussed herein may be referred to as the second element.

[0035] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled by one or more other elements. For example, if element A is coupled to element B, then element A may be in contact with element B or indirectly coupled to element B by intervening element C. Similarly, the terms "above" or "on" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled by one or more other elements. As used herein, the term "coupled" may refer to mechanical coupling or electrical coupling.

[0036] An exemplary electronic device includes a substrate and a first dielectric disposed above the substrate. The first dielectric defines a first trace opening. A first conductive pattern may be disposed in the trace opening and recessed from the upper side of the first dielectric. The first conductive pattern includes the first trace. A second conductive pattern may be disposed above the upper side of the first dielectric. The second conductive pattern may include second traces intersecting above the first trace. The second dielectric may be disposed above the second conductive pattern and extend into the first trace in the trace opening.

[0037] Another example electronic device may include a substrate and a first dielectric disposed above the substrate. The first dielectric may define a first trace opening. A first conductive pattern may be disposed in the first trace opening and recessed from the upper side of the first dielectric. The first conductive pattern may include a first trace. A second conductive pattern may be disposed above the upper side of the first dielectric and may include second traces intersecting above the first trace. The second dielectric may be disposed above the second conductive pattern and extend into the first conductive pattern in the trace opening. A third dielectric may be disposed above the second dielectric. The third dielectric may define a second trace opening. The third conductive pattern may be disposed in the second trace opening and recessed from the upper side of the third dielectric. The third conductive pattern may include a third trace. A fourth conductive pattern may be disposed above the upper side of the third dielectric. The fourth conductive pattern may include fourth traces intersecting above the third trace. The fourth dielectric may be disposed above the fourth conductive pattern and extend into the third trace in the trace opening.

[0038] An exemplary method of manufacturing an electronic device may include the steps of: providing a substrate, providing a first dielectric over the substrate, and providing a first conductive pattern in a first trace opening. The first dielectric defines the first trace opening, and the first conductive pattern may be recessed from an upper side of the first dielectric. The first conductive pattern may include a first trace. A second conductive pattern may be provided above the upper side of the first dielectric. The second conductive pattern may include second traces intersecting above the first trace. The second dielectric may be provided above the second conductive pattern. The second dielectric may extend into the first trace in the first trace opening.

[0039] This disclosure contains other examples. These examples can be found in the drawings, claims, or description of this disclosure.

[0040] Figure 1 A cross-sectional view of an example electronic device 100 is shown. Figure 1 In the example shown, electronic device 100 includes electronic components 110 and a redistribution layer (RDL) substrate 11. The RDL substrate 11 includes a dielectric structure 120 and a conductive structure 130. In some examples, electronic device 100 may also include interconnects 140.

[0041] According to various examples, dielectric structure 120 may include a first dielectric 121, a second dielectric 122, a third dielectric 123, a fourth dielectric 124, and a fifth dielectric 125. Conductive structure 130 may include a first conductive pattern 131, a second conductive pattern 132, a third conductive pattern 133, a fourth conductive pattern 134, a fifth conductive pattern 135, and a sixth conductive pattern 136. Conductive structure 130 may include an inward terminal 130a and an outward terminal 130b. The inward terminal 130a may be coupled to the component interconnect 111 of electronic component 110.

[0042] Figures 2A to 2N Demonstrates the use of electronic devices (e.g., Figure 1 A cross-sectional view of an exemplary method of electronic device 100. Figure 2A A cross-sectional view of an electronic device 100 in its early manufacturing stages is shown. Figure 2A In the example shown, a first dielectric 121 may be provided on electronic component 110. Electronic component 110 may include, or be referred to as, a semiconductor die, a semiconductor chip, or a package. For example, electronic component 110 may include a digital signal processor, a network processor, a power management unit, an audio processor, radio frequency circuitry, a wireless baseband system-on-a-chip (SoC) processor, a sensor, or an application-specific integrated circuit (ASIC). In some examples, electronic component 110 may be configured to perform computations, control processing, store data, or remove noise from electrical signals.

[0043] Electronic component 110 may include component interconnect 111. Component interconnect 111 may be disposed above the active side of electronic component 110. Component interconnect 111 may include, or be referred to as, a pad, solder pad, UBM (under-bump metal), post, bump, or pillar.

[0044] According to various examples, electronic component 110 may be part of substrate 102. In some examples, substrate 102 may include, or be referred to as, a wafer, a reconstructed wafer, or a panel. For example, substrate 102 may be a semiconductor wafer containing multiple electronic components 110 formed across the wafer in rows and columns and separated by saw tracks. In some examples, substrate 102 may be a reconstructed wafer containing multiple known good electronic components 110 arranged in rows and columns, with encapsulation located between adjacent known good electronic components 110. In some examples, substrate 102 may be a panel containing one or more semiconductor wafers and / or reconstructed wafers located thereon. The thickness of substrate 102 may range from about 20 micrometers (μm) to about 1000 μm. The terms about, approximately, or similar terms used with numerical values ​​herein may mean + / - 5%, + / - 10%, + / - 15%, + / - 20%, or + / - 25%. In some examples, substrate 102 may be a temporary carrier, as referenced below. Figure 6A The discussion.

[0045] According to various examples, a first dielectric 121 may be provided to cover the upper side of the substrate 102. The first dielectric 121 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), spin coating, spray coating, dip coating, rod coating, or any other suitable deposition process.

[0046] The first dielectric 121 can be patterned to provide one or more openings 1211, one or more trace recesses 1212, and one or more pad recesses 1213 within the first dielectric 121. The openings 1211 may extend completely through the first dielectric 121 and expose the component interconnect 111. The one or more trace recesses 1212 and one or more pad recesses 1213 may be formed to partially extend through the first dielectric 121, such that a portion of the first dielectric 121 remains above the electronic component 110 and forms the underlying layer of the one or more trace recesses 1212 and one or more pad recesses 1213. The layout and shape of the one or more trace recesses 1212 and one or more pad recesses 1213 are selected to form a conductive pattern 131. Figure 2B The desired conductive structure (e.g., trace, pad, ground plane).

[0047] In some examples, the first dielectric 121 can be patterned by providing a patterned mask (e.g., patterned photoresist) on the upper side of the first dielectric 121. The portion of the first dielectric 121 exposed from the mask is then removed to form an opening 1211, one or more trace recesses 1212, and one or more pad recesses 1213. The mask is removed after the first dielectric 121 has been patterned.

[0048] In some examples, the first dielectric 121 may comprise one or more layers of electrically insulating material, such as organic dielectrics (e.g., polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT)) or inorganic dielectrics (e.g., silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON)). In some examples, the thickness of the first dielectric 121 may range from about 2 μm to about 20 μm.

[0049] Figure 2B A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2B In the example shown, a first conductive pattern 131 may be provided over the first dielectric 121. The first conductive pattern 131 may be located in and / or fill the opening 1211, one or more trace grooves 1212 and one or more pad grooves 1213.

[0050] In some examples, the first conductive pattern 131 can be provided by forming a seed layer 131s covering the upper side of the first dielectric 121. For example, the seed layer 131s can be provided above the sidewalls and bottom layer of the uppermost surface of the first dielectric 121, the opening 1211, one or more trace grooves 1212 and one or more pad grooves 1213, and along the exposed upper side of the component interconnect 111. The seed layer 131s can be formed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD or any other suitable deposition process, and can include one or more layers of titanium (Ti), titanium-tungsten (TiW), tungsten (W), chromium (Cr), aluminum (Al), nickel (Ni), gold (Au), silver (Ag) or copper (Cu). In some examples, the thickness of the seed layer 131s can range from about 0.01 μm to about 1 μm. Conductive materials (e.g., Cu, Al, Au, Ag, or Ni) can be provided above the seed layer 131s by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition.

[0051] Figure 2CA cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2C In the illustrated example, the first conductive pattern 131 is planarized to remove portions of the first conductive pattern 131 located outside the opening 1211, one or more trace recesses 1212, and one or more pad recesses 1213. In some examples, chemical mechanical planarization (CMP) may be used to remove the first conductive pattern 131 from above the uppermost surface of the first dielectric 121. After the CMP process, the upper side of the first conductive pattern 131 may be coplanar with the upper side of the first dielectric 121. The thickness of the first conductive pattern 131 may range from about 1 μm to about 20 μm. In some instances, the first conductive pattern 131 may include, or be referred to as, an embedded trace RDL. For example, the upper side of the first conductive pattern 131 may be coplanar with or recessed relative to the upper side of the first dielectric 121.

[0052] The first conductive pattern 131 may include, or be referred to as, a trace, pad, via, one or more ground planes, one or more wiring patterns, or one or more circuit patterns. According to various examples, a portion of the first conductive pattern 131 located in the opening 1211 may be coupled to a component interconnect 111 of the electronic device 110 and may include, or be referred to as, a first conductive via 131a. The thickness of the first conductive via 131a may be similar to or equal to the thickness of the first dielectric 121. A portion of the first conductive pattern 131 located at the bottom layer of the opening 1211 (i.e., at the bottom side of the first conductive via 131a) may be referred to as a substrate-in-place terminal 130a. In some examples, one or more of the one or more trace recesses 1212 and one or more portions of the first conductive pattern 131 located in the one or more trace recesses 1212 may include and / or form one or more ground planes.

[0053] Figure 2D A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2DIn the illustrated example, a second dielectric 122 may be provided on the first conductive pattern 131 and the first dielectric 121. In some examples, a second dielectric 122 may be provided covering the first conductive pattern 131 and the first dielectric 121. A portion of the second dielectric 122 may be removed (i.e., the second dielectric 122 may be patterned) to form an opening 1221 and a trace groove 1222. The trace groove 1222 and the opening 1221 may be formed by etching (e.g., wet etching or dry etching), laser ablation, or any other suitable patterning process. According to various specific examples, the trace groove 1222 may extend partially through the second dielectric 122, such that a portion of the second dielectric 122 remains above the first dielectric 121 and the first conductive pattern 131 and forms the underlying layer of the trace groove 1222. The opening 1221 may extend completely through the second dielectric 122 and may expose a portion of the first conductive pattern 131. In some examples, the second dielectric 122 may have elements, features, materials, or manufacturing methods similar to those of the first dielectric 121.

[0054] Figure 2E A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2E In the example shown, a second conductive pattern 132 may be provided above the second dielectric 122 and the first conductive pattern 131. The second conductive pattern 132 may be located in and / or fill the opening 1221 and the trace groove 1222. The second conductive pattern 132 may have elements, features, materials, or manufacturing methods similar to those of the first conductive pattern 131.

[0055] According to various examples, the second conductive pattern 132 can be provided by forming a seed layer 132s (similar to seed layer 131s) covering the upper side of the second dielectric 122. The seed layer 132s can be provided along the uppermost surface of the second dielectric 122, the sidewalls and bottom layer of the opening 1221 and the trace groove 1222, and along the exposed upper side of the first conductive pattern 131. The seed layer 132s can be formed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition process. The seed layer 132s may comprise one or more layers of Ti, TiW, W, Cr, Al, Ni, Au, Ag, or Cu. In some examples, the thickness of the seed layer 132s can range from about 0.01 μm to about 1 μm. Conductive materials (e.g., Cu, Al, Au, Ag, or Ni) can be provided above the seed layer 132s by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition.

[0056] The second conductive pattern 132 can then be planarized to remove the portion of the second conductive pattern 132 located outside the opening 1221 and the trace groove 1222, which includes the seed layer 132s. In some examples, CMP can be used to remove the second conductive pattern 132 from above the uppermost surface of the second dielectric 122. After the CMP process, the upper side of the second conductive pattern 132 may be coplanar with the upper side of the second dielectric 122.

[0057] Figure 2F A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2F In the example shown, a portion of the upper side of the second conductive pattern 132 can be removed, for example, by etching or laser ablation. In response to this removal, the upper side of the second conductive pattern 132 may be lower than the uppermost side of the second dielectric 122. For example, the upper side of the second conductive pattern 132 may be recessed relative to the upper side of the second dielectric 122. In some examples, the height difference between the upper side of the second conductive pattern 132 and the upper side of the second dielectric 122 may be in the range of about 2 μm to about 20 μm, about 3 μm to about 15 μm, or about 5 μm to about 10 μm.

[0058] The second conductive pattern 132 may include, or be referred to as, a trace, pad, via, one or more wiring patterns, or one or more circuit patterns. According to various examples, a portion of the second conductive pattern 132 located in the opening 1221 may be coupled to and contact the upper side of the first conductive pattern 131, and may include, or be referred to as, a second conductive via 132a. The second conductive pattern 132 may be electrically coupled to the electronic component 110 via the first conductive pattern 131 (e.g., via the first conductive via 131a). The thickness of the second conductive via 132a may be less than the thickness of the second dielectric 122. A portion of the second conductive pattern 132 located in the trace recess 1222 may include, or be referred to as, an embedded trace 132b.

[0059] In some examples, the thickness of the second conductive pattern 132 may range from about 0.1 μm to about 20 μm. In some examples, the width of the embedded trace 132b may range from about 0.5 μm to about 10 μm, about 1.0 μm to about 5 μm, or about 1.5 μm to about 2.5 μm. The line spacing of the embedded trace 132b (i.e., the distance between adjacent embedded traces 132b) may range from about 0.5 μm to about 10 μm, about 1.0 μm to about 5 μm, or about 1.5 μm to about 2.5 μm. In some examples, the embedded trace 132b may have a width of about 2.0 μm and a line spacing of about 2.0 μm. In some examples, the embedded trace 132b may have a width of about 1.0 μm and a line spacing of about 1.0 μm.

[0060] Figure 2G A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2G In the example shown, the third conductive pattern 133 ( Figure 2H A seed layer 133s may be provided above the second conductive pattern 132 and the second dielectric 122. The seed layer 133s may cover the upper side of the second dielectric 122 and the upper side of the second conductive pattern 132. The thickness of the seed layer 133s is less than the height difference between the upper side of the second conductive pattern 132 and the upper side of the second dielectric 122. According to various examples, the elements, features, materials, or manufacturing methods of the seed layer 133s may be similar to or the same as the elements, features, materials, or manufacturing methods of the seed layer 131s and / or seed layer 132s. For simplicity, Figure 2G Seed layer 133s is derived from some diagrams depicting subsequent processing steps (e.g., Figures 2J to 2N (The text is omitted, but it should be understood that the seed layer 133s may exist in examples of subsequent diagrams, even if not depicted therein.)

[0061] According to various specific examples, a mask 1 is provided over the seed layer 133s, the second conductive pattern 132, and the second dielectric 122. In some examples, the mask 1 may include photoresist. The mask 1 may be patterned by, for example, exposure, development, etching, and curing to provide mask openings 1a and 1b. Mask openings 1a and 1b may expose portions of the seed layer 133s. Mask opening 1a may expose the portion of the seed layer 133s located on the second dielectric 122 and may include, or be referred to as a trace opening or trace recess. Mask opening 1b may expose the portion of the seed layer 133s located on the second conductive via 132a and may include, or be referred to as a pad opening. In some examples, the width or diameter of mask opening 1b may be greater than the width or diameter of the second conductive via 132a, such that mask opening 1b also exposes the portion of the seed layer 133s located on the upper side of the second dielectric 122.

[0062] Figure 2H A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2HIn the example shown, the conductive material (e.g., Cu, Al, Au, Ag, or Ni) of the third conductive pattern 133 can be provided in the mask openings 1a and 1b. The conductive material can be coupled to and contact the seed layer 133s. The conductive material can be provided by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition. The portion of the third conductive pattern 133 located in the mask opening 1b can be coupled to and contact the upper side of the second conductive pattern 132 (e.g., coupled to the upper side of the second conductive via 132a) and may include, or be referred to as, a conductive pad 133a. The portion of the third conductive pattern 133 located in the mask opening 1a may include, or be referred to as a trace 133b. The thickness of the third conductive pattern 133 can range from about 0.1 μm to about 20 μm. The thickness of the conductive pad 133a can be greater than the thickness of the trace 133b because the conductive pad 133a extends into the second dielectric 122 to contact and couple to the second conductive via 132a.

[0063] Figure 2I A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2I In the example shown, portions of the mask 1 and seed layer 133s not covered by trace 133b or pad 133a are removed. In some examples, the third conductive pattern 133 may include, or is referred to as, a semi-additive process (SAP) RDL. For example, after forming the third conductive pattern 133, a third dielectric 123 is provided around and / or on the lateral and upper sides of the contact trace 133b. Figure 2J ).

[0064] In some examples, the width of trace 133b can range from about 0.5 μm to about 10 μm, from about 1.0 μm to about 5 μm, or from about 1.5 μm to about 2.5 μm. The spacing between traces 133b (i.e., the distance between adjacent traces 133b) can range from about 0.5 μm to about 10 μm, from about 1.0 μm to about 5 μm, or from about 1.5 μm to about 2.5 μm. In some examples, trace 133b can have a width of about 2.0 μm and a spacing of about 2.0 μm. In some examples, trace 133b can have a width of about 1.0 μm and a spacing of about 1.0 μm.

[0065] In some examples, traces 133b of the third conductive pattern 133 may be located between traces 132b of the second conductive pattern 132 and intersect generally vertically with respect to the traces. Traces 133b may not substantially overlap with traces 132b. As used herein, the phrase "substantially non-overlapping" may mean that trace 133b is oriented horizontally between adjacent traces 132b and positioned vertically above or below trace 132b at a distance D, wherein trace 132b is positioned outside the coverage area of ​​trace 133b. Substantially non-overlapping traces may slightly overlap, wherein trace 132b in some examples extends into the coverage area of ​​another trace 133b due to, for example, manufacturing tolerances or defects.

[0066] In some examples, the distance D can be between the lower side of trace 133b and the upper side of trace 132b, and can vertically separate the lower and upper sides of the trace. Traces 133b and 132b, laterally located and vertically separated, can increase the integration and density of the conductive pattern. Compared to a package with the same number of redistribution layers (e.g., two redistribution layers and a ground plane layer) without interleaving, using the above-described interleaving technique to increase density can reduce package thickness. Compared to a package with the same or similar dimensions but without interleaving, some examples of interleaved traces described herein can increase the number of redistribution layers.

[0067] Figure 2J A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2J In the example shown, a third dielectric 123 may be provided over the third conductive pattern 133, the second conductive pattern 132, and the second dielectric 122. The third dielectric 123 may cover and contact the upper side of trace 132b and the upper and lateral sides of trace 133b and pad 133a. According to various examples, the elements, features, materials, or manufacturing methods of the third dielectric 123 may be similar to or the same as the elements, features, materials, or manufacturing methods of the first dielectric 121.

[0068] The first dielectric 121 may be patterned to provide one or more openings 1231, one or more trace grooves 1232, and one or more pad grooves 1233 in the third dielectric 123. The openings 1231 may extend completely through the third dielectric 123 and expose the pads 133a of the third conductive pattern 133. The one or more trace grooves 1232 and the one or more pad grooves 1233 may be formed to partially extend through the third dielectric 123, such that a portion of the third dielectric 123 remains above the third conductive pattern 133 and forms the underlying layer of the one or more trace grooves 1232 and the one or more pad grooves 1233. In some examples, the thickness of the third dielectric 123 may range from about 0.5 μm to about 20 μm.

[0069] Figure 2K A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2K In the illustrated example, a fourth conductive pattern 134 may be provided above the third dielectric 123. The fourth conductive pattern 134 may be located in and / or fill the opening 1231, one or more trace recesses 1232, and one or more pad recesses 1233. According to various examples, the elements, features, materials, or manufacturing methods of the fourth conductive pattern 134 may be similar to or the same as those of the first conductive pattern 131. In some examples, the fourth conductive pattern 134 may be initially positioned above the uppermost side of the third dielectric 123. The portion of the fourth conductive pattern 134 above the uppermost side of the third dielectric 123 may be removed by a planarization process (e.g., using CMP). After planarization, the upper side of the fourth conductive pattern 134 and the upper side of the third dielectric 123 may be coplanar.

[0070] The fourth conductive pattern 134 may include, or be referred to as, a trace, pad, via, one or more ground planes, one or more wiring patterns, or one or more circuit patterns. According to various examples, a portion of the fourth conductive pattern 134 located in the opening 1231 may be coupled to and contact the third conductive pattern 133 (e.g., the upper side of the pad 133a). The portion of the fourth conductive pattern 134 disposed in the opening 1231 may include, or be referred to as, a conductive via 134a. The thickness of the conductive via 134a may be similar to or equal to the thickness of the third dielectric 123. In some examples, one or more portions of one or more trace recesses 1232 and one or more portions of the fourth conductive pattern 134 located in one or more trace recesses 1232 may include and / or form one or more ground planes.

[0071] Figure 2L A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2L In the example shown, the fourth dielectric 124 and the fifth conductive pattern 135 are provided above the third dielectric 123 and the fourth conductive pattern 134. According to various examples, the elements, features, materials, or manufacturing methods of the fourth dielectric 124 and the fifth conductive pattern 135 may be similar to or identical to the elements, features, materials, or manufacturing methods of the second dielectric 122 and the second conductive pattern 132, respectively. For example, the fourth dielectric 124 and the fifth conductive pattern 135 may be formed in a manner similar to or identical to that of the second dielectric 122 and the second conductive pattern 132, such as... Figure 2D , Figure 2E and Figure 2FAs shown in the diagram, the fifth conductive pattern 135 may include a conductive via 135a and a trace 135b. In some examples, the trace 135b may be referred to as an embedded trace. The upper side of the fifth conductive pattern 135 may be recessed relative to the upper side of the fourth dielectric 124.

[0072] Figure 2M A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2M In the example shown, a sixth conductive pattern 136 is provided over the fourth dielectric 124 and the conductive via 135a, and a fifth dielectric 125 is provided over the fourth dielectric 124, the fifth conductive pattern 135, and the sixth conductive pattern 136. According to various examples, the elements, features, materials, or manufacturing methods of the fifth dielectric 125 and the sixth conductive pattern 136 may be similar to or the same as the elements, features, materials, or manufacturing methods of the third dielectric 123 and the third conductive pattern 133, respectively. For example, the sixth conductive pattern 136 may be formed in a manner similar to or the same as that of the third conductive pattern 133, such as... Figure 2G , Figure 2H and Figure 2I As shown, and the fifth dielectric 125 can be formed in a similar or identical manner to the third dielectric 123, such as Figure 2J As shown in the diagram, the sixth conductive pattern 136 may include a conductive pad 136a and a trace 136b. The pad 136a may be coupled to and contact the upper side of the first conductive pattern 135 (e.g., the upper side of the via 135a). The thickness of the conductive pad 136a may be greater than the thickness of the trace 136b because the conductive pad 136a extends into the fourth dielectric 124 to contact and couple to the conductive via 135a.

[0073] In some examples, the trace 136b of the sixth conductive pattern 136 may be located between the traces 135b of the fifth conductive pattern 135 and intersects them generally vertically relative to the traces. The distance between the lower side of the trace 136b and the upper side of the trace 135b may be... Figure 2I The distance D in the traces is similar or the same. Trace 136b may not substantially overlap with trace 135b.

[0074] In some examples, traces 136b and 135b, located laterally between each other and vertically separated, can increase the integration and density of the conductive pattern. Compared to packages with the same number of redistribution layers (e.g., two redistribution layers and a ground plane layer) without interleaving, using the aforementioned interleaving technique to increase density can reduce package thickness. Compared to packages with the same or similar dimensions but without interleaving, some examples using the interleaved traces described herein can increase the number of redistribution layers.

[0075] The fifth dielectric 125 may cover the fourth dielectric 124, the fifth conductive pattern 135, and the sixth conductive pattern 136. The fifth dielectric 125 may extend into the fourth dielectric 124 and contact the upper side of the trace 135b. The fifth dielectric may include an aperture 1251 exposing the conductive pad 136a.

[0076] Figure 2N A cross-sectional view of an electronic device 100 in the late stages of manufacturing is shown. Figure 2N In the example shown, an external terminal 130b is provided in an aperture 1251 of a fifth dielectric 125, and an interconnect 140 is provided on the external terminal 130b.

[0077] According to various examples, the outward terminal 130b may fill the orifice 1251 of the fifth dielectric 125. The outward terminal 130b is coupled to and can contact the conductive pad 136a. According to various examples, the elements, features, materials, or manufacturing methods of the outward terminal 130b may be similar to or the same as the elements, features, materials, or manufacturing methods of the first conductive pattern 131 and / or the third conductive pattern 133. For example, the outward terminal 130b may be formed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or any other suitable deposition process, and may include conductive materials such as Cu, Al, Au, Ag, or Ni. The outward terminal 130b may contain a seed crystal similar to the seed layer 131s. In some examples, a similar material may be provided when forming the conductive material of the outward terminal 130b. Figure 2H The mask of mask 1 in the middle.

[0078] Interconnect 140 is coupled to and accessible to outgoing terminal 130b. In some examples, interconnect 140 may include tin (Sn), Ag, lead (Pb), Cu, Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, interconnect 140 may be provided by forming a solder-containing conductive material on outgoing terminal 130b using a ball drop and reflow process. In some examples, interconnect 140 may also include under-bump metal (UBM) formed between the bump and outgoing terminal 130b. Interconnect 140 may include, or be referred to as, a conductive ball (e.g., a solder ball), a conductive pillar (e.g., a copper pillar), or a conductive bar having a solder cap formed on the copper pillar. In some examples, interconnect 140 may be referred to as an external input / output terminal of electronic device 100. In some examples, electronic device 100 may be a planar grid array package (LGA), wherein the component outgoing terminal 130b serves as the external input / output terminal of electronic device 100 (i.e., electronic device 100 may not contain component interconnect 140).

[0079] According to various examples, the dielectric structure 120 and the conductive structure 130 may be referred to as the RDL substrate 11. In some examples, each conductive and dielectric layer of the RDL substrate 11 may have a minimum thickness of about 1 μm. In some examples, the overall thickness of the RDL substrate 11 may range from about 16 μm to 200 μm.

[0080] Although the conductive structure 130 is shown to have a total of seven layers, including a first conductive pattern 131, a second conductive pattern 132, a third conductive pattern 133, a fourth conductive pattern 134, a fifth conductive pattern 135, a sixth conductive pattern 136, and an outward terminal 130b, the number of conductive pattern layers may be less than or more than seven. The conductive structure 130 has at least one conductive pattern (similar to the third conductive pattern 133 and the sixth conductive pattern 136) having traces formed using a semi-additive process and a conductive pattern (similar to the second conductive pattern 132 and the fifth conductive pattern 135) formed as an embedded trace. For example, a set of conductive pattern traces of the conductive structure 130 may be formed in a groove provided in a dielectric (i.e., an embedded trace), and a set of conductive pattern traces may be formed, and then a dielectric may be subsequently deposited over the formed conductive pattern traces (i.e., a SAP trace).

[0081] Depending on the specific instance, after the interconnect 140 is provided, a dicing process can be performed to divide the substrate 102 into individual electronic devices 100. The dicing process may involve sawing through the RDL substrate 11 and between adjacent electronic components 110 (e.g., sawing through saw marks S). The dicing process may utilize blades, laser beams, or any other suitable cutting means. After dicing, the lateral sides of the RDL substrate 11 may be coplanar with the lateral sides of the electronic components 110.

[0082] Electronic devices 100 with interlaced, substantially non-overlapping traces can have a greater signal trace density than packages of similar size without interlaced traces. Traces that are laterally positioned relative to each other and vertically separated (i.e., interlaced traces) can support increased integration and density of conductive patterns. Using the aforementioned interlacing technique to increase density can reduce package thickness compared to packages with the same number of redistribution layers (e.g., two redistribution layers and a ground plane layer) without interlacing. Some examples using interlaced traces can increase the number of redistribution layers compared to packages of the same or similar size but lacking interlaced traces.

[0083] Figure 3 A cross-sectional view of example electronic device 100A is shown. Figure 3In the example shown, electronic device 100A may include electronic component 110A, RDL substrate 11, and interconnect 140. Electronic component 110A includes component interconnect 111a. RDL substrate 11 includes dielectric structure 120 and conductive structure 130. In some examples, it may be similar to that described above. Figures 2A to 2N The process shown is similar to that used to manufacture electronic device 100A.

[0084] Electronic device 100A may include a seventh conductive pattern 137 and a sixth dielectric 126. The sixth dielectric 126 may have elements, features, materials, or manufacturing methods similar to or identical to those of the second dielectric 122. The seventh conductive pattern 137 may have elements, features, materials, or manufacturing methods similar to or identical to those of the second conductive pattern 132. In some examples, electronic device 100A may include, or be referred to as, a wafer-level package (WLP) or a wafer-level chip-scale package (WLCSP).

[0085] Figure 4 A cross-sectional view of example electronic device 100B is shown. Figure 4 In the example shown, electronic device 100B includes electronic component 110B, RDL substrate 11, interconnect 140, and encapsulation 150B. RDL substrate 11 includes dielectric structure 120 and conductive structure 130. Electronic component 110B may include component interconnect 111B. Figure 4 The electronic device 100B shown can be connected with Figure 3 The electronic device 100A shown is similar, but the encapsulation 150B is provided around the electronic device 100B and can be similar to that described above. Figures 2A to 2N The process shown is similar to the manufacturing process. For example, Figures 2A to 2N The substrate 102 may include a reconstructed wafer having an encapsulation 150B provided between adjacent electronic components 110B. In some examples, such as Figure 2N As shown, the encapsulant 150B can be cut into individual pieces, such that after cutting, the encapsulant 150B is coplanar with the RDL substrate 11.

[0086] In some examples, the encapsulation 150B may include, or be referred to as, an encapsulation body, encapsulation structure, mold, epoxy molding compound, resin, filler-reinforced polymer, B-stage compression film, or gel. The encapsulation 150B may be provided by transfer molding, compression molding, liquid encapsulation molding, vacuum lamination, paste printing, film-assisted molding, or other processes known to those skilled in the art. In some examples, the encapsulation 150B may contact or cover the bottom side and / or lateral side of the electronic component 110B. In some examples, the bottom side of the encapsulation 150B and the bottom side of the electronic component 110B may be coplanar, and the bottom side of the electronic component 110B may be exposed from the bottom side of the encapsulation 150B. The encapsulation 150B protects the electronic component 110B from external environmental conditions or environmental exposure.

[0087] In some examples, the RDL substrate 11 may be provided on the top side of the encapsulation 150B and on the top side of the electronic component 110B. In some examples, the top side of the electronic component 110B and the top side of the encapsulation 150B may be coplanar. In some examples, the electronic device 100B may include, or be referred to as, a wafer-level fan-out (WLFO).

[0088] Figure 5 A cross-sectional view of the example electronic device 100C is shown. Figure 5 In the examples shown, electronic device 100C may include electronic components 110C, RDL substrate 11, interconnects 140, and encapsulation 150C. In some examples, electronic device 100C may also include underfill 160C. RDL substrate 11 includes dielectric structure 120 and conductive structure 130. Figure 5 The electronic device 100C shown can be respectively connected with Figure 3 and Figure 4 The electronic devices 100A and 100B shown are similar, but in which dielectric structure 120 and conductive structure 130 may be provided before electronic component 110C is coupled to RDL substrate 11 and encapsulation 150C is provided.

[0089] Figures 6A to 6E Demonstrates the use of electronic devices (e.g., Figure 5 A cross-sectional view of an exemplary method for an electronic device 100C. Figure 6A A cross-sectional view of an electronic device 100C in its early manufacturing stages is shown. Figure 6A In the example shown, an RDL substrate 11 comprising a dielectric structure 120 and a conductive structure 130 may be provided on a carrier 202. According to various examples, it can be used with... Figures 2A to 2N The method shown is similar or identical to that used to provide the RDL substrate 11 on top of the carrier 202.

[0090] In some examples, carrier 202 may include, or be referred to as, a wafer, plate, panel, strip, substrate, or temporary carrier. Carrier 202 may include semiconductor materials (e.g., Si), glass, metal, ceramic, etc. In some examples, a temporary adhesive may be provided on the upper side of carrier 202 to facilitate separation of RDL substrate 11 from carrier 202. The temporary adhesive may be, for example, a thermal release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength by heat or light, respectively.

[0091] Figure 6B A cross-sectional view of electronic device 100C during its late-stage manufacturing process is shown. Figure 6B In the example shown, the support carrier 220 is coupled to the upper side of the RDL substrate 11, and the carrier 202 is removed from the opposite side of the RDL substrate 11.

[0092] The support carrier 220 may include, or be referred to as, a wafer, plate, panel, strip, substrate, or temporary carrier. The support carrier 220 may include semiconductor materials (e.g., Si), glass, metal, ceramic, etc. In some examples, a temporary adhesive 222 may be provided on the support carrier 220 to facilitate separation of the RDL substrate 11 from the support carrier 220. The temporary adhesive 222 may be, for example, a thermal release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength by heat or light, respectively. In some examples, the sixth dielectric 126 of the conductive structure 130 and the outward terminal 130b may be coupled to and / or contact the temporary adhesive 222.

[0093] According to various examples, the carrier 202 can be removed from the RDL substrate 11 by grinding, etching, laser ablation, physical force, application of heat and / or light, or another suitable removal method. Figure 6A The removal of carrier 202 exposes the bottom side of conductive via 131a and the first dielectric 121. In some examples, the removal of carrier 202 may expose the inward terminal 130a of conductive structure 130. In other examples, and as... Figure 6C As shown, an inward terminal 130a may be provided after the carrier 202 is removed.

[0094] Figure 6C A cross-sectional view of electronic device 100C during its late-stage manufacturing process is shown. Figure 6C In the example shown, the RDL substrate 11 can be relative to Figure 6B The view shown is flipped, and electronic component 110C is provided above RDL substrate 11. Electronic component 110C may include, or be referred to as, a die, chip, package (e.g., one or more dies in an encapsulation and / or coupled to a laminate or RDL substrate), or passive element. In some examples, the thickness of electronic component 110C may range from about 20 μm to about 1000 μm.

[0095] According to the examples, electronic component 110C may be coupled to conductive structure 130. For example, component interconnect 111C of electronic component 110C may be coupled to and / or contact the inward terminal 130A of conductive structure 130. Component interconnect 111C may include, or be referred to as, bumps, pads, or pillars. In some examples, the thickness of component interconnect 111C may be in the range of about 1 μm to about 10 μm. In some examples, component interconnect 111C may be electrically coupled to substrate inward terminal 130a via solder. In some examples, component interconnect 111C may be electrically coupled to inward terminal 130a by thermocompression bonding, ultrasonic bonding, laser-assisted bonding, or hybrid bonding (e.g., the interconnect between component interconnect 111C and inward terminal 130a may be solderless). In some examples, the elements, features, materials, or manufacturing methods of inward terminal 130A may be similar to or the same as the elements, features, materials, or manufacturing methods of third conductive pattern 133.

[0096] According to various examples, underfill 160C may be provided between RDL substrate 11 and electronic component 110C. In some examples, underfill 160C may contact RDL substrate 11 (e.g., dielectric structure 120 or conductive structure 130), component interconnect 111C, and electronic component 110C. In some examples, underfill 160C may include, or be referred to as, capillary underfill, a non-conductive paste, or a non-conductive film. In some examples, underfill 160C may be inserted into the gap between electronic component 110C and RDL substrate 11 after electronic component 110C is electrically coupled to RDL substrate 11. In some examples, underfill 160C may be pre-coated onto RDL substrate 11 before electronic component 110C is coupled to RDL substrate 11. In some examples, underfill 160C may be pre-coated onto electronic component 110C before electronic component 110C is coupled to RDL substrate 11. In some examples, a curing process (e.g., thermosetting or photocuring) can be performed on the underfill 160C.

[0097] Figure 6D A cross-sectional view of electronic device 100C during its late-stage manufacturing process is shown. Figure 6DIn the examples shown, encapsulation 150C is provided over electronic component 110C and RDL substrate 11. In some examples, encapsulation 150C may cover and / or contact RDL substrate 11, electronic component 110C, and underfill 160C. In some examples, underfill 160C may be omitted, and encapsulation 150C may be filled between electronic component 110C and RDL substrate 11. In some examples, encapsulation 150C may be removed from the back side of electronic component 110C. For example, the back side of electronic component 110C may be exposed from encapsulation 150C. In some specific instances, the back sides of electronic component 110C and encapsulation 150C may be coplanar. In some specific instances, encapsulation 150C may cover the back side of electronic component 110C. The elements, features, materials or manufacturing methods of encapsulation 150C may be similar to or the same as those of encapsulation 150B.

[0098] Figure 6E A cross-sectional view of electronic device 100C during its late-stage manufacturing process is shown. Figure 6E In the example shown, the support 252 is coupled to the encapsulation 150C and the electronic component 110C, and the support carrier is removed from the RDL substrate 11.

[0099] According to various examples, the support 252 may include, or be referred to as, a wafer, plate, panel, strip, substrate, tape, or temporary carrier. In some examples, a temporary adhesive may be provided on the upper side of the support 252 to facilitate the separation of the support 252 from the electronic device 100C. The temporary adhesive may be, for example, a thermal release tape (or film) or an optical release tape (or film), configured to reduce its adhesive strength by heat or light, respectively.

[0100] According to various examples, the support carrier 220 can be removed from the RDL substrate 11 by grinding, etching, laser ablation, physical force, application of heat and / or light, or another suitable removal method. Figure 6D The support carrier 220 removes the exposed external terminal 130b and the sixth dielectric 126. An interconnect 140 may be provided on the external terminal 130b, as referenced above. Figure 2N As described.

[0101] According to various specific examples, after the interconnect 140 is provided, a dicing process can be performed to divide the RDL substrate 11 having electronic components 110C coupled thereto into individual electronic devices 100C. The dicing process may involve sawing through the RDL substrate 11 and the encapsulation 150C (e.g., sawing along a saw line X). The dicing process may utilize a blade, a laser beam, or any other suitable cutting member. After dicing, the lateral sides of the RDL substrate 11 may be coplanar with the lateral sides of the encapsulation 150C. In some examples, the dicing process may remove the encapsulation 150C from the lateral sides of the electronic components 110C, such that after dicing, the lateral sides of the RDL substrate 11 are coplanar with the lateral sides of the electronic components 110C.

[0102] Figure 7 A cross-sectional view of an example electronic device 200 is shown. Figure 7 In the example shown, electronic device 200 may include electronic device 100D, bottom filler 170D, substrate 180D, external interconnect 190D, and cover 195D. Electronic device 100D may be coupled to substrate 180D and may include electronic component 110D, RDL substrate 11, component interconnect 111D, interconnect 140, encapsulation 150D, and bottom filler 160D. RDL substrate 11 may include dielectric structure 120 and conductive structure 130. According to various examples, electronic device 100D may be coupled to... Figure 5 The electronic device 100C is similar and can be like Figures 6A to 6E Provided as shown.

[0103] According to various examples, interconnects 140 of electronic device 100D are coupled to a substrate 180D. The substrate 180D may include a dielectric structure 181D and a conductive structure 182D. In some examples, the dielectric structure 181D may include a dielectric layer. The dielectric layer may include one or more dielectric material layers interposed with the conductive structure layer. In some examples, the dielectric material may include PI, BCB, PBO, resin, or ANZOC laminate (ABF). In some examples, the conductive structure 182D may include one or more conductive layers defining signal distribution elements (e.g., traces, vias, pads, conductive paths, or UBMs). The conductive structure 182D may include a substrate-inward terminal 182D1 and a substrate-outward terminal 182D2. In some examples, the substrate-inward terminal 182D1 may include a pad, solder pad, UBM, or pillar. In some examples, the substrate-outward terminal 182D2 may include a pad or solder pad. External interconnect 190D may include solder balls, bumps, pads, or pillars. In some examples, electronic device 200 may be an LGA (e.g., external interconnect 190D may be omitted).

[0104] In some examples, the substrate 180D may be a preformed substrate. The preformed substrate may be fabricated prior to attachment to an electronic device and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photo-definable layer and may serve as a preformed film rather than a liquid attachment, and may contain a resin with fillers such as strands, fabrics, or other inorganic particles for rigid and / or structural support. Because the dielectric layer is non-photo-definable, features such as vias or openings can be formed using drilling or lasers. In some examples, the dielectric layer may include a prepreg material or ABF. The preformed substrate may include a permanent core structure or carrier, such as a dielectric material comprising bismaleimide triazine (BT) or a flame-retardant laminate (FR4), and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate that omits a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier that can be removed after the dielectric and conductive layers are formed and before being attached to an electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminated substrate.

[0105] In some examples, substrate 180D may be an RDL substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and may (a) be formed layer-by-layer over the electronic device to which the RDL substrate will be electrically coupled, or (b) be formed layer-by-layer over the carrier, and may be completely or partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be fabricated layer-by-layer on a circular wafer as a wafer-level substrate using wafer-level processes, and / or layer-by-layer on a rectangular or square panel carrier using panel-level processes. The RDL substrate may be formed using an additive buildup process and may include one or more dielectric layers stacked alternately with one or more conductive layers and defining corresponding conductive redistribution patterns or traces configured to collectively (a) fan out of the coverage area of ​​the electronic device, and / or (b) fan in into the coverage area of ​​the electronic device. The conductive patterns may be formed using, for example, electroplating or electroless plating processes. The conductive patterns may include conductive materials, such as copper or other plating-compatible metals. The location of conductive patterns can be formed using photolithography, for example, photolithography, and photoresist materials to create a photomask. The dielectric layer of the RDL substrate can be patterned using photolithography and may include a photomask through which light is exposed to photo-pattern the desired features, such as vias in the dielectric layer. The dielectric layer can be made of photodeterminable organic dielectric materials such as polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO). These dielectric materials can be spin-coated or otherwise coated in liquid form, rather than attached as a preform. To allow for proper formation of the desired photodeterminable features, these photodeterminable dielectric materials may omit structural reinforcing agents or may be filler-free, without strands, fabrics, or other particles that could interfere with light from the photolithography process. In some examples, this filler-free characteristic of filler-free dielectric materials allows for a reduction in the thickness of the resulting dielectric layer. Although the light-defined dielectric material described above can be organic, in some examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), and / or SiON. In some examples, one or more inorganic dielectric layers may be formed by growing the inorganic dielectric layer using oxidation or nitridation processes, rather than using light-defined organic dielectric materials. These inorganic dielectric layers may be filler-free, strandless, woven, or other different inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including BT or FR4, and these types of RDL substrates may be referred to as coreless substrates.

[0106] Interconnect 140 of electronic device 100D may be electrically coupled to substrate-in-place terminal 182D1 of substrate substrate 180D. In some examples, interconnect 140 may be electrically coupled to substrate-in-place terminal 182D1 by thermoforming, ultrasonic bonding, laser-assisted bonding, or hybrid bonding. In some examples, solder may be inserted between interconnect 140 and substrate-in-place terminal 182D1. In some examples, underfill 170D may be inserted between RDL substrate 11 and substrate substrate 180D. The elements, features, materials, or manufacturing methods of underfill 170D may be similar to or the same as the elements, features, materials, or manufacturing methods of underfill 160C.

[0107] In some examples, the cover 195D can be attached to the substrate 180D via an adhesive material 197D and to the electronic component 110D via a cover attachment material 196D. In some examples, the cover attachment material 196D may also be inserted between the encapsulation 150D and the cover 195D. The cover attachment material 196D includes, or is referred to as, a thermal interface material (TIM) (e.g., a metallic TIM or a polymeric TIM), an adhesive, or a back-side metallization. The cover 195D may include, or is referred to as, a heat sink, a shroud, a cover plate, a housing, a protective shield, or a shell. In some examples, the cover 195D may include a metal or a metal alloy (e.g., Cu, Al, Ni, Ag, etc.). In some examples, the thickness of the cover 195D may range from about 100 μm to about 1000 μm. The cover 195D can dissipate heat from the electronic component 110D, protect the electronic component 110D from electromagnetic interference, and / or protect the RDL substrate 11 and the electronic component 110D from external environmental influences.

[0108] Electronic devices using interleaved, substantially non-overlapping traces can reduce manufacturing costs by decreasing the number of steps required to fabricate a similar structure. Hybrid processes can be used by embedding lower traces followed by a semi-additive process to interleave the substantially non-overlapping upper traces. Hybrid processes use fewer steps, which reduces manufacturing time and cost. Interleaved, substantially non-overlapping traces increase the integration and density of conductive patterns. For the same number of traces, increased density reduces package thickness. Increased density also increases the number of redistribution layers in a package of similar size.

[0109] This disclosure includes references to specific examples; however, those skilled in the art will understand that various changes and substitutions for equivalents can be made without departing from the scope of this disclosure. Furthermore, modifications can be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure be limited to the disclosed examples, but rather to include all examples falling within the scope of the appended claims.

Claims

1. An electronic device, characterized in that, include: Substrate; A first dielectric material is disposed above the substrate, the first dielectric material defining a first trace opening; A first conductive pattern is disposed in the trace opening and recessed from the upper side of the first dielectric, the first conductive pattern including a first trace. A second conductive pattern is disposed above the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; and A second dielectric material is disposed above the second conductive pattern and extends into the first trace in the trace opening.

2. The electronic device according to claim 1, characterized in that, The first dielectric defines an opening transverse to the trace opening and extending through the first dielectric, wherein the first conductive pattern includes a first conductive via disposed in the opening and recessed from the upper side of the first dielectric.

3. The electronic device according to claim 2, characterized in that, The second conductive pattern includes a conductive pad coupled to the first conductive via.

4. The electronic device according to claim 3, characterized in that, The second dielectric is disposed above the conductive pad.

5. The electronic device according to claim 1, characterized in that, The first trace is embedded in the first dielectric.

6. The electronic device according to claim 1, characterized in that, The second trace is formed over the first dielectric using a semi-additive method before the second dielectric is provided.

7. The electronic device according to claim 1, characterized in that, It further includes a seed layer disposed between the second conductive pattern and the upper side of the first dielectric.

8. The electronic device according to claim 1, characterized in that, Further includes: A third dielectric is disposed between the first dielectric and the substrate, the third dielectric defining a grounding opening; and A third conductive pattern is located in the grounding opening, the third conductive pattern including a grounding plane disposed between the first trace and the substrate.

9. The electronic device according to claim 1, characterized in that, The substrate includes electronic components that include component interconnects electrically coupled to the first conductive pattern.

10. The electronic device according to claim 9, characterized in that, It further includes a bottom filler disposed between the electronic component and the first dielectric.

11. An electronic device, characterized in that, include: Substrate; A first dielectric material is disposed above the substrate, the first dielectric material defining a first trace opening; A first conductive pattern is disposed in the opening of the first trace and recessed from the upper side of the first dielectric, the first conductive pattern including the first trace. A second conductive pattern is disposed above the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; A second dielectric, which is disposed above the second conductive pattern and extends into the first conductive pattern in the trace opening; A third dielectric is disposed above the second dielectric, the third dielectric defining the second trace opening; A third conductive pattern is disposed in the opening of the second trace and recessed from the upper side of the third dielectric, the third conductive pattern including the third trace; A fourth conductive pattern is disposed above the upper side of the third dielectric, the fourth conductive pattern comprising fourth traces intersecting above the third trace; and A fourth dielectric, which is disposed above the fourth conductive pattern and extends into the third trace in the trace opening.

12. The electronic device according to claim 11, characterized in that, It further includes a fifth conductive pattern disposed in a grounding opening defined by a second dielectric, the fifth conductive pattern being included in a grounding plane between the second trace and the third trace.

13. The electronic device according to claim 11, characterized in that, It further includes an outward terminal disposed in an opening defined in the fourth dielectric.

14. A method for manufacturing an electronic device, characterized in that, include: Provide substrate; A first dielectric is provided over the substrate, the first dielectric defining a first trace opening; A first conductive pattern is provided in the first trace opening, wherein the first conductive pattern is recessed from the upper side of the first dielectric, and the first conductive pattern includes a first trace; A second conductive pattern is provided above the upper side of the first dielectric, the second conductive pattern including second traces intersecting above the first trace; and A second dielectric is provided above the second conductive pattern, wherein the second dielectric extends into the first trace in the opening of the first trace.

15. The method according to claim 14, characterized in that, Providing the second conductive pattern further includes: A seed layer is provided above the first dielectric; A mask is provided over the first conductive pattern, wherein the seed layer over the first dielectric is exposed through a second trace opening defined by the mask; The second conductive pattern is provided in the opening; and Remove the mask.

16. The method according to claim 14, characterized in that, The first trace is provided as an embedded trace.

17. The method according to claim 14, characterized in that, The second trace is provided using a semi-additive method prior to the provision of the second dielectric.

18. The method according to claim 14, characterized in that, Further includes: A third dielectric is provided above the substrate, the third dielectric defining a grounding opening; and A third conductive pattern is provided in the grounding opening, the third conductive pattern including the grounding plane.

19. The method according to claim 14, characterized in that, Further includes: A third dielectric is provided disposed above the second dielectric, the third dielectric defining a second trace opening; A third conductive pattern is provided, which is disposed in the second trace opening and recessed from the upper side of the third dielectric, the third conductive pattern including the third trace; A fourth conductive pattern is provided disposed above the upper side of the third dielectric, the fourth conductive pattern including fourth traces intersecting above the third trace; and A fourth dielectric is provided, which is disposed above the fourth conductive pattern and extends into the opening of the second trace.

20. The method according to claim 14, characterized in that, It further includes providing a ground plane in the opening defined by the second dielectric and above the second conductive pattern.

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