Shifting register unit, driving method thereof, display driving circuit and display device

Abstract

The invention provides a shift register unit, a driving method thereof, a display driving circuit and a display device, and belongs to the technical field of display. The input circuit in the shift register unit can respond to the clock signal to control the input end to transmit the signal to the first node, and can respond to the potential of the first node to control the first power supply end and the second power supply end to transmit the power supply signal to the second node in different time periods; the output circuit can control the first power supply end and the third power supply end to transmit power supply signals to the first output end in different time periods in response to the potential of the second node or the potential of the first node and the second node. Therefore, it can be determined that the shift register unit comprises both the P-type transistor and the N-type transistor. Accordingly, the shift register unit can output required driving signals to pixels on the design basis of simple structure and simple driving principle. In addition, due to the simple structure, the narrow frame design of the display device can be facilitated.

Description

Shift register unit and driving method thereof, display driving circuit and display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a shift register unit and driving method thereof, a display driving circuit and a display device. BACKGROUND

[0002] With the development of display technology, the array substrate row driving (GOA) technology can be used to set a display driving circuit (e.g., a gate driving circuit) for driving the light-emitting of pixels on the substrate of a display device. Accordingly, the display driving circuit can also be referred to as a GOA circuit.

[0003] At present, the GOA circuit usually includes a plurality of GOA units (also referred to as shift register units) connected in cascade, which are connected in one-to-one correspondence with a plurality of rows of pixels in the display device and used to transmit the required display driving signals to the plurality of rows of pixels row by row to drive the plurality of rows of pixels to emit light row by row. For example, in the case where the display driving circuit is a gate driving circuit, the display driving circuit can be connected in one-to-one correspondence with a plurality of rows of pixels through a plurality of gate lines and used to transmit gate driving signals to the plurality of rows of pixels row by row through the plurality of gate lines.

[0004] However, the current GOA unit is usually a full P-type or full N-type circuit, which has a complex structure and a complex driving principle, and cannot be well used for the narrow frame design of the display device.

[0005] SUMMARY

[0006] A shift register unit and driving method thereof, a display driving circuit and a display device are provided. The technical solutions are as follows:

[0007] In one aspect, a shift register unit is provided, which includes:

[0008] A first input circuit connected with a first clock terminal, an input terminal and a first node respectively, and used to control the on-off of the input terminal and the first node in response to a first clock signal provided by the first clock terminal;

[0009] A second input circuit connected with the first node, a first power terminal, a second power terminal and a second node respectively, and used to control the on-off of the first power terminal and the second node and the on-off of the second power terminal and the second node in response to the potential of the first node, and the first power terminal and the second power terminal are turned on with the second node in different time periods respectively;

[0010] The first output circuit is connected with the second node, the first target node, the first power supply end, the third power supply end and the first output end respectively, and is configured to control the on-off of the first power supply end and the first output end in response to the potential of the second node, and control the on-off of the third power supply end and the first output end in response to the potential of the first target node, and the first power supply end and the third power supply end are conductive with the first output end in different time periods respectively; wherein the first target node is shared with the first node or the second node.

[0011] Optionally, the second power supply end and the third power supply end are shared.

[0012] Alternatively, the second power supply end and the third power supply end are independent of each other, and the potential of the second power supply signal provided by the second power supply end is less than the potential of the third power supply signal provided by the third power supply end.

[0013] Optionally, the first input circuit comprises a first transistor; the first transistor is a P-type transistor.

[0014] The gate of the first transistor is connected with the first clock end, the first pole of the first transistor is connected with the input end, and the second pole of the first transistor is connected with the first node.

[0015] Optionally, the second input circuit comprises a second transistor and a third transistor; the second transistor and the third transistor are a P-type transistor and an N-type transistor respectively.

[0016] The gate of the second transistor is connected with the first node, the first pole of the second transistor is connected with the first power supply end, and the second pole of the second transistor is connected with the second node.

[0017] The gate of the third transistor is connected with the first node, the first pole of the third transistor is connected with the second power supply end, and the second pole of the third transistor is connected with the second node.

[0018] Optionally, the first output circuit comprises a fourth transistor and a fifth transistor; the fourth transistor and the fifth transistor are both P-type transistors, or are an N-type transistor and a P-type transistor respectively.

[0019] The gate of the fourth transistor is connected with the first target node, the first pole of the fourth transistor is connected with the third power supply end, and the second pole of the fourth transistor is connected with the first output end.

[0020] A gate of the fifth transistor is connected with the second node, a first pole of the fifth transistor is connected with the first power supply end, and a second pole of the fifth transistor is connected with the first output end.

[0021] Optionally, the second input circuit is further connected with a third node and is configured to control the first power supply end and the third node in response to a potential of the first node; and the shift register unit further comprises:

[0022] A third input circuit is connected with the third node, a second clock end and the second node respectively, and is configured to control the second clock end and the second node in response to a potential of the third node, and adjust the potential of the third node based on a second clock signal provided by the second clock end.

[0023] Optionally, the second input circuit further comprises a sixth transistor, and the sixth transistor is a P-type transistor.

[0024] A gate of the sixth transistor is connected with the first node, a first pole of the sixth transistor is connected with the first power supply end, and a second pole of the sixth transistor is connected with the third node.

[0025] Optionally, the third input circuit comprises a seventh transistor and a first capacitor, and the seventh transistor is a P-type transistor.

[0026] A gate of the seventh transistor is connected with the third node, a first pole of the seventh transistor is connected with the second clock end, and a second pole of the seventh transistor is connected with the second node.

[0027] One end of the first capacitor is connected with the third node, and the other end of the first capacitor is connected with the second clock end.

[0028] Optionally, the first node comprises a first sub-node and a second sub-node, and the shift register unit further comprises:

[0029] A first control circuit is connected with the third power supply end, the first sub-node and the second sub-node respectively, and is configured to control the first sub-node and the second sub-node in response to a third power supply signal provided by the third power supply end.

[0030] The first input circuit is connected with the first sub-node, and is configured to control the input end and the first sub-node in response to the first clock signal.

[0031] The second input circuit is connected with the first sub-node and the second sub-node respectively, and is configured to control the first power supply end and the second node to be connected or disconnected in response to the potential of the first sub-node, and control the first power supply end and the third node to be connected or disconnected in response to the potential of the first sub-node, and control the second power supply end and the second node to be connected or disconnected in response to the potential of the second sub-node; or, in the case that the first target node is shared by the first node, the second input circuit is connected with the first sub-node, and is configured to control the first power supply end and the second node to be connected or disconnected in response to the potential of the first sub-node, and control the second power supply end and the second node to be connected or disconnected in response to the potential of the first sub-node, and control the first power supply end and the third node to be connected or disconnected; the first output circuit is connected with the second sub-node, and is configured to control the third power supply end and the first output end to be connected or disconnected in response to the potential of the second sub-node.

[0032] Optionally, the first control circuit comprises an eighth transistor; the eighth transistor is a P-type transistor.

[0033] The gate of the eighth transistor is connected with the third power supply end, the first pole of the eighth transistor is connected with the first sub-node, and the second pole of the eighth transistor is connected with the second sub-node.

[0034] Optionally, the first output end is configured to be connected with the input end of another shift register unit in cascade and a pixel.

[0035] Alternatively, the first output end is configured to be connected with the input end of another shift register unit in cascade, and the shift register unit further comprises:

[0036] The second output circuit is connected with the first output end, a second target node, a third clock end, a fourth power supply end and a second output end respectively, and is configured to control the third clock end and the second output end to be connected or disconnected in response to the signal output through the first output end, and control the fourth power supply end and the second output end to be connected or disconnected in response to the potential of the second target node, and the third clock end and the fourth power supply end are connected with the second output end in different time periods respectively; wherein, the second output end is configured to be connected with the pixel; the second target node is shared by the first node connected with the first output circuit or the second node connected with the first output circuit.

[0037] Optionally, the fourth power supply end is shared by the third power supply end.

[0038] Alternatively, the fourth power supply end and the third power supply end are independent of each other, and the fourth power supply end provides a fourth power supply signal with a potential smaller than that of a third power supply signal provided by the third power supply end.

[0039] Optionally, the second output circuit comprises a ninth transistor and a tenth transistor; the ninth transistor and the tenth transistor are P-type transistor and N-type transistor respectively;

[0040] a gate of the ninth transistor is connected with the first output end, a first pole of the ninth transistor is connected with the third clock end, and a second pole of the ninth transistor is connected with the second output end;

[0041] a gate of the tenth transistor is connected with the second target node, a first pole of the tenth transistor is connected with the fourth power supply end, and a second pole of the tenth transistor is connected with the second output end.

[0042] Optionally, the shift register unit further comprises:

[0043] a second control circuit connected between the first output end and the second output circuit, and further connected with the third power supply end, and configured to control on-off of the first output end and the second output circuit in response to a third power supply signal provided by the third power supply end.

[0044] Optionally, the second control circuit comprises an eleventh transistor; the eleventh transistor is P-type transistor;

[0045] a gate of the eleventh transistor is connected with the third power supply end, a first pole of the eleventh transistor is connected with the first output end, and a second pole of the eleventh transistor is connected with the second output circuit.

[0046] Optionally, the shift register unit further comprises at least one of the following circuits:

[0047] a first potential adjusting circuit connected with the first target node and the first output end respectively, and configured to adjust a potential of the first target node based on a signal output through the first output end, the first target node being shared with the first node;

[0048] a second potential adjusting circuit connected with the second node and the first power supply end respectively, and configured to adjust a potential of the second node based on a first power supply signal provided by the first power supply end;

[0049] a third potential adjusting circuit, connected with the target signal end and a connection node of the second control circuit and the second output circuit respectively, and configured to adjust a potential of the connection node based on a signal provided by the target signal end; wherein, in a case that the second target node is shared with the first node, the target signal end is the third clock end or the second output end; in a case that the second target node is shared with the second node, the target signal end is the second output end.

[0050] Optionally, the first potential adjusting circuit comprises a second capacitor; the second potential adjusting circuit comprises a third capacitor; and the third potential adjusting circuit comprises a fourth capacitor.

[0051] One end of the second capacitor is connected with the first target node, and the other end of the second capacitor is connected with the first output end.

[0052] One end of the third capacitor is connected with the second node, and the other end of the third capacitor is connected with the first power supply end.

[0053] One end of the fourth capacitor is connected with the connection node, and the other end of the fourth capacitor is connected with the target signal end.

[0054] In another aspect, a driving method of a shift register unit is provided, for driving the shift register unit as described in the above aspect; the method comprises:

[0055] In an input stage, the first input circuit controls the input end to be conductive with the first node in response to a first clock signal provided by the first clock end, the second input circuit controls the first power supply end to be conductive with the second node and controls the second power supply end to be disconnected with the second node in response to a potential of the first node, and the first output circuit controls the first power supply end to be disconnected with the first output end in response to the potential of the second node and controls the third power supply end to be conductive with the first output end in response to a potential of the first target node; wherein, the first target node is shared with the first node or the second node.

[0056] In an output stage, the first input circuit controls the input end to be conductive with the first node in response to the first clock signal, the second input circuit controls the first power supply end to be disconnected with the second node in response to the potential of the first node and controls the second power supply end to be conductive with the second node, and the first output circuit controls the first power supply end to be conductive with the first output end in response to the potential of the second node and controls the third power supply end to be disconnected with the first output end in response to the potential of the first target node.

[0057] Optionally, the first output terminal is connected with an input terminal of another shift register unit in cascade and a pixel, respectively; or the first output terminal is connected with an input terminal of another shift register unit in cascade, and the shift register unit further comprises a second output circuit; the method further comprises:

[0058] In the input stage, the second output circuit controls the third clock terminal to be connected with the second output terminal in response to the signal output through the first output terminal, and controls the fourth power terminal to be disconnected from the second output terminal in response to the potential of the second target node; wherein the second output terminal is used to be connected with the pixel; the second target node is shared by the first node connected with the first output circuit or the second node connected with the first output circuit.

[0059] In the output stage, the second output circuit controls the third clock terminal to be disconnected from the second output terminal in response to the signal output through the first output terminal, and controls the fourth power terminal to be connected with the second output terminal in response to the potential of the second target node.

[0060] In another aspect, a display driving circuit is provided, comprising at least two shift register units in cascade as described in the above aspect.

[0061] In still another aspect, a display device is provided, comprising a display panel and a display driving circuit as described in the above aspect.

[0062] Wherein the display panel comprises a plurality of pixels, and the display driving circuit is connected with the plurality of pixels and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0064] Fig. 1 is a structural schematic diagram of a shift register unit provided by an embodiment of the present application;

[0065] Fig. 2 is a structural schematic diagram of another shift register unit provided by an embodiment of the present application;

[0066] Fig. 3 is a structural schematic diagram of still another shift register unit provided by an embodiment of the present application;

[0067] FIG. 4 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0068] FIG. 5 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0069] FIG. 6 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0070] FIG. 7 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0071] FIG. 8 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0072] FIG. 9 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0073] FIG. 10 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0074] FIG. 11 is a structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0075] FIG. 12 is a circuit structural schematic diagram of a shift register unit according to an embodiment of the present application;

[0076] FIG. 13 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0077] FIG. 14 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0078] FIG. 15 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0079] FIG. 16 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0080] FIG. 17 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0081] FIG. 18 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0082] FIG. 19 is a circuit structural schematic diagram of another shift register unit according to an embodiment of the present application;

[0083] FIG. 20 is a flow schematic diagram of a driving method of a shift register unit according to an embodiment of the present application;

[0084] FIG. 21 is a flow schematic diagram of a driving method of another shift register unit according to an embodiment of the present application;

[0085] Fig. 22 is a driving timing simulation diagram of the shift register unit shown in Fig. 12 or Fig. 13 according to an embodiment of the present application;

[0086] Fig. 23 is a driving timing simulation diagram of the shift register unit shown in Fig. 14 according to an embodiment of the present application;

[0087] Fig. 24 is a driving timing simulation diagram of the shift register unit shown in Fig. 15 according to an embodiment of the present application;

[0088] Fig. 25 is a driving timing simulation diagram of the shift register unit shown in Fig. 16 according to an embodiment of the present application;

[0089] Fig. 26 is a driving timing simulation diagram of the shift register unit shown in Fig. 17 according to an embodiment of the present application;

[0090] Fig. 27 is a driving timing simulation diagram of the shift register unit shown in Fig. 18 according to an embodiment of the present application;

[0091] Fig. 28 is a driving timing simulation diagram of the shift register unit shown in Fig. 19 according to an embodiment of the present application;

[0092] Fig. 29 is a structural diagram of a display driving circuit according to an embodiment of the present application;

[0093] Fig. 30 is a structural diagram of another display driving circuit according to an embodiment of the present application;

[0094] Fig. 31 is a structural diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0095] In order to make the purpose, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in further detail below with reference to the drawings.

[0096] It should be noted that the transistors used in all the embodiments of the present application can be thin film transistors or field effect transistors or other devices with the same characteristics. The field effect transistor can be a metal-oxide-semiconductor (MOS) field effect transistor, also known as MOS transistor. In addition, the transistors used in the embodiments of the present application are mainly switching transistors according to their functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and drain can be interchangeable. In the embodiments of the present application, the source is referred to as the first electrode and the drain is referred to as the second electrode. According to the configuration in the drawings, the middle terminal of the transistor is the control electrode, which can also be referred to as the gate electrode, the signal input terminal is the source electrode, and the signal output terminal is the drain electrode. In addition, the switching transistor used in the embodiments of the present application can include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate electrode is at a low potential and is turned off when the gate electrode is at a high potential, and the N-type switching transistor is turned on when the gate electrode is at a high potential and is turned off when the gate electrode is at a low potential. In addition, the plurality of signals in each embodiment of the present application correspond to a first potential and a second potential. The first potential and the second potential only represent two states of the potential of the signal, and do not represent that the first potential or the second potential has a specific value throughout the text.

[0097] The embodiment of the present application provides a shift register unit, which has a simple driving principle and is beneficial to the narrow frame design of a display device.

[0098] For example, the shift register unit can be a shift register unit of a CMOS structure, which can realize cascade driving through the combination of NMOS and PMOS, has a simple circuit structure and a simple driving principle, and is beneficial to the narrow frame design of a display device. The NMOS refers to an N-type MOS transistor, the PMOS refers to a P-type MOS transistor, and the CMOS structure refers to a structure including NMOS and PMOS.

[0099] As shown in FIG. 1, the shift register unit includes a first input circuit 01, a second input circuit 02, and a first output circuit 03.

[0100] The first input circuit 01 is connected with a first clock terminal CK, an input terminal IN, and a first node N1 respectively, and is configured to control the on-off of the input terminal IN and the first node N1 in response to a first clock signal provided by the first clock terminal CK.

[0101] For example, the first input circuit 01 can control the input terminal IN to be connected to the first node N1 when the first clock signal provided by the first clock terminal CK has the first potential, so that the input signal provided by the input terminal IN can be transmitted to the first node N1; and can control the input terminal IN to be disconnected from the first node N1 when the first clock signal provided by the first clock terminal CK has the second potential.

[0102] Optionally, in the embodiment of the present application, the first potential can be a valid potential, the second potential can be an invalid potential, and the first potential can be a low potential relative to the second potential, that is, the first potential of the valid potential can be a low potential, and the second potential of the invalid potential can be a high potential. Of course, in some other embodiments, the first potential can also be a high potential relative to the second potential, that is, the first potential of the valid potential can be a high potential, and the second potential of the invalid potential can be a low potential. And it can be understood that for a P-type transistor, the first potential is a low potential relative to the second potential; for an N-type transistor, the first potential is a high potential relative to the second potential. Accordingly, it can be known that the first input circuit 01 can at least include a P-type transistor based on the above examples.

[0103] The second input circuit 02 is connected with the first node N1, the first power terminal V1, the second power terminal V2 and the second node N2 respectively, and is configured to control the connection and disconnection of the first power terminal V1 and the second node N2, and control the connection and disconnection of the second power terminal V2 and the second node N2 in response to the potential of the first node N1. And the first power terminal V1 and the second power terminal V2 are connected with the second node N2 at different time periods respectively.

[0104] For example, the second input circuit 02 can control the first power terminal V1 to be connected with the second node N2 and the second power terminal V2 to be disconnected from the second node N2 when the potential of the first node N1 is the first potential, so that the first power signal provided by the first power terminal V1 can be transmitted to the second node N2; and can control the first power terminal V1 to be disconnected from the second node N2 and the second power terminal V2 to be connected with the second node N2 when the potential of the first node N1 is the second potential, so that the second power signal provided by the second power terminal V2 can be transmitted to the second node N2.

[0105] That is, as described above, the second input circuit 02 can control the first power supply end V1 and the second power supply end V2 to be respectively turned on with the second node N2 in different time periods under the control of the potential of the first node N1. It can be known that the second input circuit 02 can include at least one P-type transistor and one N-type transistor, and one of the P-type transistor and the N-type transistor can be connected with the first power supply end V1, and the other can be connected with the second power supply end V2. For example, based on the first potential being a low potential and the second potential being a high potential, the transistor connected with the first power supply end V1 can be a P-type transistor, and the transistor connected with the second power supply end V2 can be an N-type transistor.

[0106] Alternatively, the first power supply end V1 can provide a first power supply signal with a high potential, and the second power supply end V2 can provide a second power supply signal with a low potential. Correspondingly, in the embodiment of the present application, the first power supply end V1 can also be referred to as an upper pull power supply end VGH, and the second power supply end V2 can also be referred to as a lower pull power supply end VGL. In this way, based on the first potential being a low potential and the second potential being a high potential, it can also be known that when the potential of the first node N1 is the first potential (i.e., a low potential), the potential of the second node N2 can be the second potential (i.e., a high potential); on the contrary, when the potential of the first node N1 is the second potential (i.e., a low potential), the potential of the second node N2 can be the first potential (i.e., a low potential). That is, the second input circuit 02 can control the potential of the second node N2 to be exactly opposite to the potential of the first node N1 in the same time period. In addition, since the potential of the first node N1 is the potential of the input signal provided by the input end IN transmitted by the first input circuit 01, it can be known that the second input circuit 02 actually controls the potential of the second node N2 to be exactly opposite to the potential of the input signal in the same time period.

[0107] The first output circuit 03 is connected with the second node N2, the first target node N01, the first power supply end V1, the third power supply end V3 and the first output end OUT1 respectively, and is configured to control the turn-on and turn-off of the first power supply end V1 and the first output end OUT1 in response to the potential of the second node N2, and control the turn-on and turn-off of the third power supply end V3 and the first output end OUT1 in response to the potential of the first target node N01. In addition, the first power supply end V1 and the third power supply end V3 are turned on with the first output end OUT1 in different time periods. The first target node N01 is shared by the first node N1 or the second node N2.

[0108] For example, referring to FIG. 1, the first target node N01 is shared with the second node N2, i.e., the second node N2 can also serve as the first target node N01, so that the first output circuit 03 controls the third power supply end V3 and the first output end OUT1 in response to the potential of the second node N2. Alternatively, referring to FIG. 2, the first target node N01 is shared with the first node N1, i.e., the first node N1 can also serve as the first target node N01, so that the first output circuit 03 controls the third power supply end V3 and the first output end OUT1 in response to the potential of the first node N1.

[0109] For example, in combination with FIG. 1, taking the first target node N01 shared with the second node N2 as an example, the first output circuit 03 can control the first power supply end V1 and the first output end OUT1 to be connected in a conductive state and control the third power supply end V3 and the first output end OUT1 to be disconnected when the potential of the second node N2 is the first potential, so that the first power supply signal provided by the first power supply end V1 can be transmitted to the first output end OUT1; and the first output circuit 03 can control the first power supply end V1 and the first output end OUT1 to be disconnected and control the third power supply end V3 and the first output end OUT1 to be connected in a conductive state when the potential of the second node N2 is the second potential, so that the third power supply signal provided by the third power supply end V3 can be transmitted to the first output end OUT1.

[0110] That is, in the case that the first target node N01 is shared with the second node N2, the first output circuit 03 can control the first power supply end V1 and the third power supply end V3 to be connected with the first output end OUT1 in different time periods under the control of the potential of the second node N2, so as to output the first power supply signal or the third power supply signal through the first output end OUT1 in a time period. On this basis, it can be known that the first output circuit 03 can include at least one P-type transistor and one N-type transistor, and one of the P-type transistor and the N-type transistor can be connected with the first power supply end V1, and the other one can be connected with the third power supply end V3. For example, on the basis that the first potential is a low potential and the second potential is a high potential, the transistor connected with the first power supply end V1 can be a P-type transistor, and the transistor connected with the third power supply end V3 can be an N-type transistor. Alternatively, the potential of the third power supply signal provided by the third power supply end V3 can be a low potential. For example, in some embodiments, the third power supply end V3 can also be referred to as a pull-down power supply end VGL.

[0111] For example, in combination with FIG. 2, taking the case that the first target node N01 shares the first node N1 as an example, because the second input circuit 02 can control the potential of the first node N1 and the potential of the second node N2 to be exactly opposite in the same time period, it can be known that the first output circuit 03 can control the first power supply end V1 and the first output end OUT1 to be connected in a state that the potential of the second node N2 is the first potential, that is, the potential of the first node N1 is the second potential, and control the third power supply end V3 and the first output end OUT1 to be disconnected, so that the first power supply signal provided by the first power supply end V1 can be transmitted to the first output end OUT1, and can control the first power supply end V1 and the first output end OUT1 to be disconnected in a state that the potential of the second node N2 is the second potential, that is, the potential of the first node N1 is the first potential, and control the third power supply end V3 and the first output end OUT1 to be connected, so that the third power supply signal provided by the third power supply end V3 can be transmitted to the first output end OUT1.

[0112] That is, in the case that the first target node N01 shares the first node N1, the first output circuit 03 can also be controlled by the potentials of the second node N2 and the first node N1 respectively to control the first power supply end V1 and the third power supply end V3 to be connected with the first output end OUT1 in different time periods respectively, so as to output the first power supply signal or the third power supply signal through the first output end OUT1 in a time period. It can be known on this basis that the first output circuit 03 can include at least two P-type transistors or two N-type transistors of the same type. For example, on the basis that the first potential is a low potential and the second potential is a high potential, the first output circuit 03 can include two P-type transistors.

[0113] Therefore, it can be known from the foregoing embodiments that the shift register unit provided by the embodiments of the present application can be a CMOS structure including PMOS tubes and NMOS tubes, which is simple in structure and simple in driving principle, and is thus conducive to the narrow frame design of the display device.

[0114] In summary, the embodiments of the present application provide a shift register unit. The shift register unit includes two input circuits and one output circuit. One input circuit can control the input end to transmit an input signal to the first node in response to a clock signal, and the other input circuit can control the first power supply end and the second power supply end to transmit power supply signals to the second node in different time periods respectively in response to the potential of the first node. The output circuit can control the first power supply end and the third power supply end to transmit power supply signals to the first output end in different time periods respectively in response to the potential of the second node or the potentials of the first node and the second node. It can be seen that the shift register unit includes P-type transistors and N-type transistors, the structure of the shift register unit is simple, the driving principle is simple, and the shift register unit is conducive to the narrow frame design of the display device.

[0115] Optionally, in an embodiment, as can be seen with reference to FIG. 1 and FIG. 2, the second power terminal V2 and the third power terminal V3 can be shared. For example, the second power terminal V2 and the third power terminal V3 can both be the same pull-down power terminal VGL. In this way, the wiring can be simplified, the cost can be saved, and further, the narrow frame design of the display device is facilitated.

[0116] Alternatively, in another embodiment, as can be seen with reference to FIG. 1 and FIG. 2, the second power terminal V2 and the third power terminal V3 can be independent of each other, and the second power signal provided by the second power terminal V2 can have a lower potential than the third power signal provided by the third power terminal V3. Here, the comparison can be the absolute value of the potential. For example, the third power terminal V3 can be the pull-down power terminal VGL as described above, and the second power terminal V2 can be a pull-down power terminal VGLL capable of providing a lower potential signal. In this way, when the transistor connected to the second power terminal V2 is an N-type transistor, the bias of the N-type transistor can be reduced, thereby facilitating the improvement of the reliability of the shift register unit.

[0117] For example, the potential of the power signal provided by the pull-down power terminal VGLL (i.e., the second power terminal V2) and the potential of the power signal provided by the pull-down power terminal VGL (i.e., the third power terminal V3) can differ by about 0.5 volts (V).

[0118] Optionally, in some embodiments, as can be seen with reference to FIG. 3, which shows a structural schematic diagram of another shift register unit, the second input circuit 02 can also be connected to the third node N3 and can be used to control the on-off of the first power terminal V1 and the third node N3 in response to the potential of the first node N1.

[0119] For example, the second input circuit 02 can control the first power terminal V1 and the third node N3 to be conductive when the potential of the first node N1 is a first potential, so that the first power signal provided by the first power terminal V1 can be transmitted to the third node N3; and can control the first power terminal V1 and the third node N3 to be disconnected when the potential of the first node N1 is a second potential. On this basis, in combination with the working principle of the second input circuit 02 as described above, which also controls the first power terminal V1 and the second node N2 to be conductive when the potential of the first node N1 is the first potential, and also controls the first power terminal V1 and the second node N2 to be disconnected when the potential of the first node N1 is the second potential, it can be known that in the second input circuit 02, the transistor connected to the first power terminal V1 and the third node N3 and the transistor connected to the first power terminal V1 and the second node N2 can be the same type of transistor. For example, on the basis that the first potential is a low potential and the second potential is a high potential, the same type of transistor can be a P-type transistor.

[0120] And, on this basis, it can be seen from further reference to FIG. 3 that the shift register unit can further include a third input circuit 04.

[0121] The third input circuit 04 can be connected with the third node N3, the second clock terminal CB and the second node N2 respectively, and can be configured to control the on-off of the second clock terminal CB and the second node N2 in response to the potential of the third node N3, and adjust the potential of the third node N3 based on the second clock signal provided by the second clock terminal CB.

[0122] For example, the third input circuit 04 can control the second clock terminal CB and the second node N2 to be connected when the potential of the third node N3 is the first potential, so that the second clock signal provided by the second clock terminal CB can be transmitted to the second node N2; and can control the second clock terminal CB and the second node N2 to be disconnected when the potential of the third node N3 is the second potential. Alternatively, on the basis that the first potential is a low potential and the second potential is a high potential, the third input circuit 04 can include at least a P-type transistor.

[0123] In addition, the third input circuit 04 can also adjust the potential of the third node N3 based on the second clock signal through coupling effect. For example, the third input circuit 04 can pull up the potential of the third node N3 through coupling effect when the potential of the second clock signal jumps from a low potential to a high potential. In this way, the potential stability of the third node N3 can be ensured to be better, and the potential stability of the second node N2 can be ensured to be better.

[0124] It can be understood that by providing that the shift register unit further includes the third input circuit 04, the second clock signal provided by the second clock terminal CB can be further flexibly adjusted to control the potential of the second node N2, and the working flexibility of the shift register unit is better.

[0125] Alternatively, in some embodiments, it can be seen from another structural schematic diagram of a shift register unit shown in FIG. 4 that the first node N1 can include a first sub-node N1-1 and a second sub-node N1-2. And the shift register unit can further include a first control circuit 05.

[0126] The first control circuit 05 can be connected with the third power terminal V3, the first sub-node N1-1 and the second sub-node N1-2 respectively, and can be configured to control the on-off of the first sub-node N1-1 and the second sub-node N1-2 in response to the third power signal provided by the third power terminal V3.

[0127] For example, the third power supply signal provided by the third power supply terminal V3 can be a low potential, and the first control circuit 05 can control the first sub-node N1-1 and the second sub-node N1-2 to be continuously turned on under the control of the low potential third power supply signal. Thus, it can be known that the potential of the second sub-node N1-2 can be consistent with the potential of the first sub-node N1-1. And the first control circuit 05 can at least include a P-type transistor.

[0128] On this basis, it can be seen from the continuing reference to FIG. 4 that the first input circuit 01 can be connected with the first sub-node N1-1, and can be used to control the on-off of the input terminal IN and the first sub-node N1-1 in response to the first clock signal.

[0129] And in an embodiment, as shown in FIG. 4, the second input circuit 02 can be connected with the first sub-node N1-1 and the second sub-node N1-2 respectively, and can be used to control the on-off of the first power supply terminal V1 and the second node N2 in response to the potential of the first sub-node N1-1, and control the on-off of the first power supply terminal V1 and the third node N3, and can control the on-off of the second power supply terminal V2 and the second node N2 in response to the potential of the second sub-node N1-2. Or in another embodiment, as shown in FIG. 5, in the case that the first target node N01 shares the first node N1 (i.e. the first target node N01 is the first node N1), the second input circuit 02 can be connected with the first sub-node N1-1, and can be used to control the on-off of the first power supply terminal V1 and the second node N2 in response to the potential of the first sub-node N1-1, and control the on-off of the second power supply terminal V2 and the second node N2, and control the on-off of the first power supply terminal V1 and the third node N3. The first output circuit 03 can be connected with the second sub-node N1-2, and can be used to control the on-off of the third power supply terminal V3 and the first output terminal OUT1 in response to the potential of the second sub-node N1-2.

[0130] Of course, for the embodiment shown in FIG. 4, the first target node N01 can also share the first node N1, or can also share the second node N2. And in the case that the first target node N01 shares the first node N1, as shown in FIG. 4, the first output circuit 03 can also be connected with the second sub-node N1-2 in the first node N1, and can be used to control the on-off of the third power supply terminal V3 and the first output terminal OUT1 in response to the potential of the second sub-node N1-2. That is, the first output circuit 03 can be connected with the second input circuit 02, the third input circuit 03 and the first control circuit 05 at the same time.

[0131] It can be understood that by setting the first control circuit 05, the purpose of isolating the first sub-node N1-1 and the second sub-node N1-2 can be achieved, and the potential fluctuation of one of the nodes directly affects the potential of the other node N1-2. For example, in some embodiments, when the potential of the second sub-node N1-2 decreases greatly, the first control circuit 05 can be used as a resistor to divide the potential between the first sub-node N1-1 and the second sub-node N1-2, and ensure that the potential of the first sub-node N1-1 is relatively stable. In turn, the bias stress of each transistor connected to the first sub-node N1-1 in the second input circuit 02 can be reduced. Therefore, the transistors connected to the first sub-node N1-1 can be protected from the potential change of the second sub-node N1-2. In addition, on the basis that the potential of the first sub-node N1-1 remains relatively stable, the potential of the second sub-node N1-2 can be further adjusted, so that the potential of the second sub-node N1-2 also recovers to be stable, and in turn the third output circuit 03 can reliably transmit the power signal to the first output terminal OUT1, avoiding the tailing phenomenon of the signal output through the first output terminal OUT1, that is, the output stability can be ensured to be good.

[0132] Alternatively, in an embodiment, as can be seen in combination with FIGS. 1 to 5, the first output terminal OUT1 can be used to be connected with the input terminal IN of the other cascaded shift register unit and the pixel, respectively. That is, the first output terminal OUT1 can be used as a shift output terminal CR to drive the work of the cascaded shift register unit, and also used as a driving output terminal to drive the pixel Pixel to emit light.

[0133] Alternatively, in another embodiment, as can be seen in combination with the structural schematic diagram of another shift register unit shown in FIG. 6, the first output terminal OUT1 can be used to be connected with the input terminal IN of the other cascaded shift register unit. That is, the first output terminal OUT1 can be used as a shift output terminal CR to drive the work of the cascaded shift register unit. On this basis, to drive the pixel Pixel to emit light, it can be seen in combination with FIG. 6 that the shift register unit can further include a second output circuit 06.

[0134] The second output circuit 06 can be connected with the first output terminal OUT1, the second target node N02, the third clock terminal NCK, the fourth power terminal V4 and the second output terminal OUT2, respectively, and can be used to control the on-off of the third clock terminal NCK and the second output terminal OUT2 in response to the signal output through the first output terminal OUT1, and control the on-off of the fourth power terminal V4 and the second output terminal OUT2 in response to the potential of the second target node N02. Moreover, the third clock terminal NCK and the fourth power terminal V4 can be turned on with the second output terminal OUT2 in different time periods, respectively.

[0135] The second output end OUT2 can be used to connect with the pixel Pixel. That is, in combination with FIG. 6, in the case that the first output end OUT1 is used as the shift output end CR, the second output end OUT2 can be used as the drive output end to drive the pixel Pixel to emit light. In this way, relative to the embodiment that the first output end OUT1 is used as both the shift output end to drive the cascaded shift register units to work and the drive output end to drive the pixel Pixel to emit light, because the signals output through the first output end OUT1 and the second output end OUT2 can be independent of each other, the purpose of reliably driving the pixel to emit light and ensuring that each shift register unit can reliably work can be achieved.

[0136] The second target node N02 can share the first node N1 connected with the first output circuit 03 or the second node N2 connected with the first output circuit 03.

[0137] For example, referring to FIG. 7, the second target node N02 is shared with the second node N2, that is, the second node N2 can also serve as the second target node N02, so that the second output circuit 06 controls the on-off of the fourth power end V4 and the second output end OUT2 in response to the potential of the second node N2. It can be known on this basis that because the first output circuit 03 controls the first power end V1 to output the high-potential first power signal to the first output end OUT1 when the potential of the second node N2 is the first potential (i.e., the low potential), the potential of the second target node N02 can be exactly opposite to the potential of the signal output through the first output end OUT1 in the same period.

[0138] Alternatively, referring to FIG. 6, the second target node N02 is shared with the first node N1, that is, the first node N1 can also serve as the second target node N02, so that the second output circuit 06 controls the on-off of the fourth power end V4 and the second output end OUT2 in response to the potential of the first node N1. It can be known on this basis that, based on the fact that the first target node N01 is shared with the first node N1, because the first output circuit 03 controls the third power end V2 to output the low-potential first power signal to the first output end OUT1 when the potential of the first node N1 is the first potential (i.e., the low potential), the potential of the second target node N02 can be exactly the same as the potential of the signal output through the first output end OUT1 in the same period. It can be understood that, based on the fact that the first node N1 includes the first sub-node N1-1 and the second sub-node N1-2, the second target node N02 here can be shared with the second sub-node N1-2, and of course, in some other embodiments, the second target node N02 can also be shared with the first sub-node N1-1.

[0139] For example, the second output circuit 06 can control the third clock terminal NCK and the second output terminal OUT2 to be conductive, and control the fourth power terminal V4 and the second output terminal OUT2 to be disconnected, so that the third clock terminal NCK outputs the third clock signal to the second output terminal OUT2, when the potential of the signal output through the first output terminal OUT1 is the first potential, i.e. the potential of the second target node N02 is the first potential or the second potential; and can control the third clock terminal NCK and the second output terminal OUT2 to be disconnected, and control the fourth power terminal V4 and the second output terminal OUT2 to be conductive, so that the fourth power terminal V4 outputs the fourth power signal to the second output terminal OUT2, when the potential of the signal output through the first output terminal OUT1 is the second potential, i.e. the potential of the second target node N02 is the first potential or the second potential.

[0140] That is, the second output circuit 06 can control the third clock terminal NCK and the fourth power terminal V4 to be conductive with the second output terminal OUT2 in different time periods under the control of the potential of the signal output through the first output terminal OUT1 and the potential of the second target node N02, so as to output the third clock signal or the fourth power signal through the second output terminal OUT2 in a time period. On this basis, it can be known that the second output circuit 06 can include at least one P-type transistor and one N-type transistor, and one of the P-type transistor and the N-type transistor can be connected with the third clock terminal NCK, and the other can be connected with the fourth power terminal V4. For example, on the basis that the first potential is a low potential and the second potential is a high potential, the transistor connected with the third clock terminal NCK can be a P-type transistor, and the transistor connected with the fourth power terminal V4 can be an N-type transistor.

[0141] Optionally, the third clock signal provided by the third clock terminal NCK and the second clock signal provided by the second clock terminal CB can be exactly opposite in the same time period.

[0142] Optionally, the potential of the fourth power signal provided by the fourth power terminal V4 can be a low potential. For example, in some embodiments, the fourth power terminal V4 can also be referred to as a pull-down power terminal VGL.

[0143] Optionally, in an embodiment, as shown in FIGS. 6 and 7, the fourth power terminal V4 and the third power terminal V3 can be shared. For example, the fourth power terminal V4 and the third power terminal V3 can both be the same pull-down power terminal VGL. In this way, the wiring can be simplified, the cost can be saved, and the narrow frame design of the display device is further facilitated.

[0144] Alternatively, in another embodiment, referring to FIG. 6 and FIG. 7, the fourth power supply terminal V4 and the third power supply terminal V3 can be independent of each other, and the fourth power supply signal provided by the fourth power supply terminal V4 can have a lower potential than the third power supply signal provided by the third power supply terminal V3, which can refer to the absolute value of the potential. For example, the third power supply terminal V3 can be the pull-down power supply terminal VGL as described above, and the fourth power supply terminal V4 can be a pull-down power supply terminal VGL2 capable of providing a lower potential signal. In this way, when the transistor connected to the fourth power supply terminal V4 is an N-type transistor, the bias voltage of the N-type transistor can be reduced, thereby improving the reliability of the shift register unit.

[0145] For example, the potential of the power supply signal provided by the pull-down power supply terminal VGL2 (i.e., the fourth power supply terminal V4) and the potential of the power supply signal provided by the pull-down power supply terminal VGL (i.e., the third power supply terminal V3) can also differ by about 0.5V.

[0146] Alternatively, in the embodiment in which the second power supply terminal V2 and the third power supply terminal V3 are independent of each other, and the fourth power supply terminal V4 and the third power supply terminal V3 are independent of each other, the fourth power supply terminal V4 and the second power supply terminal V2 can be shared, such as both being pull-down power supply terminals VGLL. In this way, it can also simplify the wiring and save costs, thereby facilitating the narrow frame design of the display device.

[0147] Alternatively, based on the first node N1 including the first sub-node N1-1 and the second sub-node N1-2, for the embodiment in which the fourth power supply terminal V4 and the third power supply terminal V3 are shared, the second target node N02 can be shared with the second sub-node N1-2, so that, compared to the second target node N02 being shared with the first sub-node N1-1, the transistor connected to the fourth power supply terminal V4 in the second output circuit 06 can avoid leakage, thereby ensuring that the second output circuit 06 reliably outputs the fourth power supply signal to the second output terminal OUT2. For the embodiment in which the potential of the fourth power supply signal provided by the fourth power supply terminal V4 is lower than the potential of the third power supply signal provided by the third power supply terminal V3, the second target node N02 can be shared with the second sub-node N1-2 or the first sub-node N1-1.

[0148] Optionally, as the first output end OUT1 or the second output end OUT2 of the pixel Pixel, it can be connected with a transistor included in the pixel circuit in the pixel Pixel through a gate line Gate, to output a gate driving signal to the connected transistor through the gate line Gate, and here the transistor included in the pixel circuit can be a data writing transistor of N type for example. Correspondingly, the shift register unit can also be referred to as a Gate GOA driving circuit of CMOS structure. Of course, it can also be connected with a transistor included in the pixel circuit in the pixel Pixel through other signal lines, to output a signal to the connected transistor through the other signal lines. For example, the other signal lines can be an emission control line EM, and correspondingly, the transistor included in the pixel circuit can be an emission control transistor of N type for example, and the signal output through the emission control line EM can be an emission control signal. Correspondingly, the shift register unit can also be referred to as an EM GOA driving circuit of CMOS structure.

[0149] It can be understood that, in combination with FIGS. 1 to 7, it can also be seen that, for the first stage shift register unit in the cascaded multi-stage shift register unit, the input end IN can be connected with the start signal end STV to receive the start signal provided by the start signal end STV, and work under the control of the start signal.

[0150] Optionally, in some embodiments, the high level and the low level of the start signal provided by the start signal end STV, the high level and the low level of the first clock signal provided by the first clock end CK, and the high level and the low level of the second clock signal provided by the second clock end CB can respectively equal to: the level of the power signal provided by the pull-up power supply end VGH and the level of the power signal provided by the pull-down power supply end VGL. The high level and the low level of the third clock signal provided by the third clock end NCK can respectively equal to: the level of the power signal provided by the pull-up power supply end VGH and the level of the power signal provided by the pull-down power supply end VGL2.

[0151] Optionally, in some embodiments, as can be seen from another structural schematic diagram of a shift register unit shown in FIG. 8, the shift register unit can further include a second control circuit 07.

[0152] The second control circuit 07 can be connected between the first output end OUT1 and the second output circuit 06 respectively, and can also be connected with the third power supply end V3, and can be used to control the on-off of the first output end OUT1 and the second output circuit 06 in response to the third power signal provided by the third power supply end V3. The connection node of the second control circuit 07 and the second output circuit 06 in the figure is identified as the fourth node N4.

[0153] For example, the second control circuit 07 can control the first output terminal OUT1 and the second output circuit 06 to be continuously turned on under the control of the third power signal at a low potential, that is, control the first output terminal OUT1 and the fourth node N4 to be continuously turned on. As can be seen, the potential of the fourth node N4 can be consistent with the potential of the signal output through the first output terminal OUT1. Moreover, the second control circuit 07 can at least include a P-type transistor.

[0154] It can be understood that, by setting the second control circuit 07, the first output terminal OUT1 and the fourth node N4 can also be isolated from each other, preventing the potential fluctuation of one end from directly affecting the potential of the other end, as with the first control circuit 05. For example, in some embodiments, when the potential of the fourth node N4 drops by a large amount, the second control circuit 07 can be used as a resistor to divide the potential between the first output terminal OUT1 and the fourth node N4, ensuring that the potential of the signal output through the first output terminal OUT1 is relatively stable, that is, the output stability can be ensured to be good.

[0155] Optionally, in some embodiments, referring to the structural schematic diagrams of another shift register unit respectively shown in FIGS. 9 to 11, it can be seen that the shift register unit further includes at least one of the following circuits: a first potential adjusting circuit 08, a second potential adjusting circuit 09, and a third potential adjusting circuit 10.

[0156] The first potential adjusting circuit 08 can be connected with the first target node N01 and the first output terminal OUT1 respectively, and can be used to adjust the potential of the first target node N01 based on the signal output through the first output terminal OUT1. Here, the first target node N01 can be shared with the first node N1. That is, the first potential adjusting circuit 08 can be connected with the first node N1 and the first output terminal OUT1 respectively. Moreover, it can also be seen from FIGS. 9 to 11 that, on the basis that the first node N1 includes a first sub-node N1-1 and a second sub-node N1-2, the first target node N01 here can be shared with the second sub-node N1-2. That is, the first potential adjusting circuit 08 can be connected with the second sub-node N1-2 and the first output terminal OUT1 respectively.

[0157] The second potential adjusting circuit 09 can be connected with the second node N2 and the first power terminal V1 respectively, and can be used to adjust the potential of the second node N2 based on the first power signal provided by the first power terminal V1.

[0158] The third potential adjusting circuit 10 can be connected with the target signal terminal V0, and the connection node (that is, the fourth node N4) of the second control circuit 07 and the second output circuit 06 respectively, and can be used to adjust the potential of the connection node based on the signal provided by the target signal terminal V0.

[0159] In combination with FIG. 6, in the case that the second target node N02 is shared by the first node N1 (e.g., the second sub-node N1-2), the target signal end V0 can be the third clock end NCK shown in FIG. 9 or the second output end OUT2 shown in FIG. 11. That is, in the case that the second target node N02 is the first node N1, the third potential adjusting circuit 10 can adjust the potential of the fourth node N4 based on the third clock signal provided by the third clock end NCK or the signal output through the second output end OUT2. In combination with FIG. 7, in the case that the second target node N02 is shared by the second node N2, the target signal end V0 can be the second output end OUT2 shown in FIG. 10. That is, in the case that the second target node N02 is the second node N2, the third potential adjusting circuit 10 can adjust the potential of the fourth node N4 based on the signal output through the second output end OUT2.

[0160] Optionally, no matter the first potential adjusting circuit 08, the second potential adjusting circuit 09 or the third potential adjusting circuit 10, each of them can adjust the potential of the connected node through coupling. In this way, the stability of the potential of each node can be ensured, thereby ensuring the reliable operation of the shift register unit.

[0161] It can be understood that, in combination with FIG. 9, in the case that the second target node N02 is shared by the second sub-node N1-2 in the first node N1, and the target signal end V0 is set as the third clock end NCK, that is, the third potential adjusting circuit 10 is connected with the third clock end NCK and adjusts the potential of the fourth node N4 based on the third clock signal provided by the third clock end NCK, the potential fluctuation of the third clock signal will be coupled to the first output end OUT1 due to the coupling effect, causing the potential of the signal output through the first output end OUT1 to also fluctuate.

[0162] In combination with FIG. 10, in the case that the second target node N02 is set to be shared with the second node N2, and the target signal terminal V0 is set to be the second output terminal OUT2, i.e. the third potential adjusting circuit 10 is connected to the second output terminal OUT2 and adjusts the potential of the fourth node N4 based on the signal output through the second output terminal OUT2, the problem of fluctuation of the potential of the signal output through the first output terminal OUT1 in the structure of FIG. 9 can be improved. However, when the potential of the first node N1 is high and the potential of the second node N2 is low, the first output circuit 03 controls the first power supply terminal V1 to output the first power supply signal with high potential to the first output terminal OUT1, i.e. the potential of the signal output through the first output terminal OUT1 is high. Thus, the N-type transistor connected to the fourth power supply terminal V4 and the P-type transistor connected to the third clock terminal NCK in the second output circuit 06 are both turned off, and the second output terminal OUT2 is in a floating state, so that the second output circuit 06 cannot normally control the fourth power supply terminal V4 to output the fourth power supply signal with low potential to the second output terminal OUT2.

[0163] In combination with FIG. 11, in the case that the second target node N02 is set to be shared with the second sub-node N1-2 in the first node N1, and the target signal terminal V0 is set to be the second output terminal OUT2, i.e. the third potential adjusting circuit 10 is connected to the second output terminal OUT2 and adjusts the potential of the fourth node N4 based on the signal output through the second output terminal OUT2, when the potential of the second sub-node N1-2 is low and the potential of the second node N2 is high, the first output circuit 03 controls the third power supply terminal V3 to output the third power supply signal with low potential to the first output terminal OUT1, i.e. the potential of the signal output through the first output terminal OUT1 is low, so that the second output circuit 06 can reliably output signals to the second output terminal OUT2 through the fourth power supply terminal V4 or the third clock terminal NCK. Thus, the problem of fluctuation of the potential of the signal output through the first output terminal OUT1 in the structure of FIG. 9 is improved, and the second output terminal OUT2 is not in a floating state in the structure of FIG. 10, so that the effect is better.

[0164] Optionally, taking the structure shown in FIG. 4 as an example, and taking the second power supply end V2 and the third power supply end V3 as the same pull-down power supply end VGL as an example, FIG. 12 schematically shows a circuit structure schematic diagram of a shift register unit provided in an embodiment of the present application. Taking the structure shown in FIG. 5 as an example, and taking the second power supply end V2 and the third power supply end V3 as the pull-down power supply ends VGLL and VGL respectively as an example, FIG. 13 schematically shows another circuit structure schematic diagram of a shift register unit provided in an embodiment of the present application. Taking the structure shown in FIG. 3 as an example, and taking the second power supply end V2 and the third power supply end V3 as the pull-down power supply ends VGLL and VGL respectively as an example, FIG. 14 schematically shows still another circuit structure schematic diagram of a shift register unit provided in an embodiment of the present application. And taking the structure shown in FIG. 1 in combination with the structure shown in FIG. 4 as an example, and taking the second power supply end V2 and the third power supply end V3 as the same pull-down power supply end VGL as an example, FIG. 15 schematically shows still another circuit structure schematic diagram of a shift register unit provided in an embodiment of the present application.

[0165] Optionally, as can be seen with reference to FIGS. 12 to 15, the first input circuit 01 can include a first transistor T1. And the first transistor T1 can be a P-type transistor.

[0166] The gate of the first transistor T1 can be connected with the first clock end CK, the first pole of the first transistor T1 can be connected with the input end IN, and the second pole of the first transistor T1 can be connected with the first node N1. Of course, the input end IN of the first shift register unit can be connected with the start signal end STV.

[0167] It can be understood that, in the case that the first node N1 includes a first sub-node N1-1 and a second sub-node N1-2, in combination with FIG. 12, the second pole of the first transistor T1 can be connected with the first sub-node N1-1.

[0168] Optionally, as can be seen with reference to FIGS. 12 to 15, the second input circuit 02 can include a second transistor T2 and a third transistor T3. And the second transistor T2 and the third transistor T3 can be a P-type transistor and an N-type transistor respectively.

[0169] The gate of the second transistor T2 can be connected with the first node N1, the first pole of the second transistor T2 can be connected with the first power supply end V1, and the second pole of the second transistor T2 can be connected with the second node N2.

[0170] The gate of the third transistor T3 can be connected with the first node N1, the first pole of the third transistor T3 can be connected with the second power supply end V2, and the second pole of the third transistor T3 can be connected with the second node N2.

[0171] It can be understood that, in the case that the first node N1 includes the first sub-node N1-1 and the second sub-node N1-2, in combination with FIG. 12, the gate of the second transistor T2 can be connected with the first sub-node N1-1. In combination with FIG. 12 and FIG. 13, it can be seen that the gate of the third transistor T3 can be connected with the first sub-node N1-1 or the second sub-node N1-2. Moreover, as described above, on the basis that the second power supply end V2 is set as the pull-down power supply end VGLL capable of providing a lower potential signal, the leakage of the third transistor T3 can be improved, so that the bias of the third transistor T3 is reduced, which is beneficial to improving the reliability of the shift register unit.

[0172] Optionally, in combination with FIG. 12 to FIG. 15, it can be seen that the first output circuit 03 can include a fourth transistor T4 and a fifth transistor T5. Moreover, the fourth transistor T4 and the fifth transistor T5 can both be P-type transistors, or can be N-type transistors and P-type transistors respectively.

[0173] The gate of the fourth transistor T4 can be connected with the first target node N01, the first pole of the fourth transistor T4 can be connected with the third power supply end V3, and the second pole of the fourth transistor T4 can be connected with the first output end OUT1.

[0174] The gate of the fifth transistor T5 can be connected with the second node N2, the first pole of the fifth transistor T5 can be connected with the first power supply end V1, and the second pole of the fifth transistor T5 can be connected with the first output end OUT1.

[0175] For example, in the case that the first target node N01 is shared by the first node N1 and the second sub-node N1-2, in combination with FIG. 12 and FIG. 13, the fourth transistor T4 and the fifth transistor T5 can both be P-type transistors. In the case that the first target node N01 is shared by the first node N1 and the second node N2, in combination with FIG. 14 and FIG. 15, the fourth transistor T4 can be an N-type transistor, and the fifth transistor T5 can be a P-type transistor.

[0176] It can be understood that the first output circuit 03 shown in FIG. 14 and FIG. 15 can be considered as a CMOS Buffer structure. In the CMOS Buffer structure, the NMOS can adopt high-gate-voltage output bottom-gate, and the PMOS can adopt low-gate-voltage output high-gate.

[0177] It can also be understood that, in the case that the first target node N01 is shared by the first node N1 and the second sub-node N1-2, in combination with FIG. 12 and FIG. 13, the gate of the fourth transistor T4 can be connected with the second sub-node N1-2. In the case that the first target node N01 is shared by the first node N1 and the second node N2, in combination with FIG. 14 and FIG. 15, the gate of the fourth transistor T4 can be connected with the second node N2.

[0178] Optionally, with continued reference to FIGS. 12-14, it can be seen that, on the basis of comprising the third input circuit 04, the second input circuit 02 can further comprise: a sixth transistor T6. And the sixth transistor T6 can be a P-type transistor.

[0179] The gate of the sixth transistor T6 can be connected with the first node N1, the first pole of the sixth transistor T6 can be connected with the first power supply end V1, and the second pole of the sixth transistor T6 can be connected with the third node N3.

[0180] It can be understood that, in the case that the first node N1 comprises a first sub-node N1-1 and a second sub-node N1-2, in combination with FIGS. 12-14, it can be seen that the gate of the sixth transistor T6 can be connected with the first sub-node N1-1.

[0181] Optionally, with continued reference to FIGS. 12-14, it can be seen that the third input circuit 04 can comprise: a seventh transistor T7 and a first capacitor C1. And the seventh transistor T7 can be a P-type transistor.

[0182] The gate of the seventh transistor T7 can be connected with the third node N3, the first pole of the seventh transistor T7 can be connected with the second clock end CB, and the second pole of the seventh transistor T7 can be connected with the second node N2.

[0183] One end of the first capacitor C1 can be connected with the third node N3, and the other end of the first capacitor C1 can be connected with the second clock end CB. That is, the first capacitor C1 can be connected in series between the second clock end CB and the third node N3.

[0184] Optionally, with continued reference to FIGS. 12, 13 and 15, it can be seen that, on the basis of comprising the first control circuit 05, the first control circuit 05 can comprise: an eighth transistor T8. And the eighth transistor T8 can be a P-type transistor.

[0185] The gate of the eighth transistor T8 can be connected with the third power supply end V3, the first pole of the eighth transistor T8 can be connected with the first sub-node N1-1, and the second pole of the eighth transistor T8 can be connected with the second sub-node N1-2.

[0186] Optionally, based on FIG. 12, taking the structure shown in FIG. 9 as an example, FIG. 16 schematically shows a circuit structure schematic diagram of another shift register unit provided in an embodiment of the present application. Based on FIG. 12, taking the structure shown in FIG. 10 as an example, FIG. 17 schematically shows a circuit structure schematic diagram of another shift register unit provided in an embodiment of the present application. Based on FIG. 12, taking the structure shown in FIG. 11 as an example, FIG. 18 schematically shows a circuit structure schematic diagram of another shift register unit provided in an embodiment of the present application. And, based on FIG. 15 in combination with FIG. 8 and FIG. 12, FIG. 19 schematically shows a circuit structure schematic diagram of another shift register unit provided in an embodiment of the present application.

[0187] Optionally, as can be seen from FIG. 16 to FIG. 19, the second output circuit 06 can include a ninth transistor T9 and a tenth transistor T10. And, the ninth transistor T9 and the tenth transistor T10 can be a P-type transistor and an N-type transistor respectively.

[0188] The gate of the ninth transistor T9 can be connected with the first output end OUT1, the first pole of the ninth transistor T9 can be connected with the third clock end NCK, and the second pole of the ninth transistor T9 can be connected with the second output end OUT2.

[0189] The gate of the tenth transistor T10 can be connected with the second target node N02, the first pole of the tenth transistor T10 can be connected with the fourth power supply end V4, and the second pole of the tenth transistor T10 can be connected with the second output end OUT2.

[0190] It can be understood that, the second output circuit 06 shown in FIG. 16 to FIG. 19 can be considered as a CMOS Buffer structure as the first output circuit 03. Among them, the NMOS can adopt high gate voltage output bottom gate, and the PMOS can adopt low gate voltage output high gate.

[0191] It can also be understood that, in the case that the second target node N02 is shared with the second sub-node N1-2, as can be seen from FIG. 16, FIG. 18 and FIG. 19, the gate of the tenth transistor T10 can be connected with the second sub-node N1-2. In the case that the second target node N02 is shared with the second node N2, as can be seen from FIG. 17, the gate of the tenth transistor T10 can be connected with the second node N2.

[0192] Optionally, continuing to refer to FIG. 16 to FIG. 19, it can be seen that the second control circuit 07 can include an eleventh transistor T11. And, the eleventh transistor T11 can be a P-type transistor.

[0193] The gate of the eleventh transistor T11 can be connected with the third power supply end V3, the first pole of the eleventh transistor T11 can be connected with the first output end OUT1, and the second pole of the eleventh transistor T11 can be connected with the second output circuit 06 (that is, the fourth node N4).

[0194] Optionally, with continuous reference to FIG. 12, FIG. 13, and FIG. 16 to FIG. 19, it can be seen that the first potential adjusting circuit 08 can include a second capacitor C2. The second potential adjusting circuit 09 can include a third capacitor C3. The third potential adjusting circuit 10 can include a fourth capacitor C4.

[0195] One end of the second capacitor C2 can be connected with the first target node N01, and the other end of the second capacitor C2 can be connected with the first output end OUT1. That is, the second capacitor C2 can be connected in series between the first target node N01 and the first output end OUT1. Here, the first target node N01 can be a second sub-node N1-2 included in the first node N1.

[0196] One end of the third capacitor C3 can be connected with the second node N2, and the other end of the third capacitor C3 can be connected with the first power supply end V1. That is, the third capacitor C3 can be connected in series between the second node N2 and the first power supply end V1.

[0197] One end of the fourth capacitor C4 can be connected with the connection node (that is, the fourth node N4), and the other end of the third capacitor C3 can be connected with the target signal end V0. That is, the fourth capacitor C4 can be connected in series between the second node N2 and the target signal end V0.

[0198] It can be understood that in the case that the target signal end V0 is the third clock end NCK, in combination with FIG. 16, it can be seen that the fourth capacitor C4 can be connected in series between the second node N2 and the third clock end NCK. In the case that the target signal end V0 is the second output end OUT2, in combination with FIG. 17 and FIG. 18, it can be seen that the fourth capacitor C4 can be connected in series between the second node N2 and the second output end OUT2.

[0199] It can be understood that the circuit diagrams shown in FIG. 12 to FIG. 19 are only schematic illustrations, and any circuit diagram that can be formed in combination with the structural diagrams shown in FIG. 1 to FIG. 11 is within the protection scope of the embodiments of the present application.

[0200] Based on the above embodiments, on one hand, the embodiments of the present application provide a brand-new CMOS EM GOA driving circuit (for example, as shown in FIG. 12), which can realize cascade driving through the collocation of NMOS and PMOS, so as to control the light-emitting elements in the pixels to emit light and realize signal resetting and the like functions. The CMOS structure can make the structure of the EM GOA driving circuit more simplified, thereby being beneficial to the narrow frame design of the display device.

[0201] In another aspect, the embodiments of the present application provide a brand new CMOS Gate GOA driving circuit (as shown in FIG. 16), which can also realize cascade driving through the combination of NMOS and PMOS. By taking advantage of the characteristic difference between N-type transistor made of oxide material and P-type transistor made of low temperature poly-silicon (LTPS) material, the CMOS Gate GOA driving circuit can ensure the stable output of the gate driving signal required for the N-type transistor in the pixel circuit, and can also save the number of transistors to be set, ensuring the simplicity of the circuit, thereby being conducive to the narrow frame design of the display device. In addition, the CMOS Gate GOA driving circuit adopts a double-output structure of a shift output end and a driving output end, and can also stably output the capacity. It can be understood that the transistor architecture including LTPS+oxide material can also be referred to as LTPO architecture.

[0202] In still another aspect, with the increase of the size of the display panel, the resolution and frequency thereof are increased, and the time of 1 row scanning (i.e., 1H) is less and less, which seriously affects the picture quality compensation. When the pixel circuit driven by the traditional shift register unit driving oxide structure works, the data writing and threshold voltage compensation in the pixel circuit are performed at the same time, and the less the 1H time is, the less the compensation time is, so that reliable compensation cannot be realized. However, the shift register unit of the CMOS architecture provided by the embodiments of the present application can also avoid this problem, and ensure that the pixel circuit can reliably complete the compensation of the threshold voltage.

[0203] In summary, the embodiments of the present application provide a shift register unit. The shift register unit includes two input circuits and one output circuit. One of the input circuits can control the input end to transmit an input signal to a first node in response to a clock signal, and the other input circuit can control a first power supply end and a second power supply end to transmit a power supply signal to a second node in different time periods in response to the potential of the first node. The output circuit can control the first power supply end and a third power supply end to transmit a power supply signal to a first output end in different time periods in response to the potential of the second node or the potentials of the first node and the second node. As can be seen, the shift register unit includes both P-type transistors and N-type transistors, the structure of the shift register unit is simple, the driving principle is simple, and the shift register unit is conducive to the narrow frame design of the display device.

[0204] The embodiments of the present application also provide a driving method of a shift register unit. The method is used for driving the shift register unit shown in any one of FIGS. 1 to 19. As shown in FIG. 20, the method includes:

[0205] In step 2001, in the input stage, the first input circuit controls the input terminal to be connected to the first node in response to the first clock signal provided by the first clock terminal, the second input circuit controls the first power terminal to be connected to the second node in response to the potential of the first node, and controls the second power terminal to be disconnected from the second node, and the first output circuit controls the first power terminal to be disconnected from the first output terminal in response to the potential of the second node, and controls the third power terminal to be connected to the first output terminal in response to the potential of the first target node.

[0206] The first target node is shared by the first node or the second node.

[0207] In step 2002, in the output stage, the first input circuit controls the input terminal to be connected to the first node in response to the first clock signal, the second input circuit controls the first power terminal to be disconnected from the second node in response to the potential of the first node, and controls the second power terminal to be connected to the second node, and the first output circuit controls the first power terminal to be connected to the first output terminal in response to the potential of the second node, and controls the third power terminal to be disconnected from the first output terminal in response to the potential of the first target node.

[0208] Alternatively, in some embodiments, the first output terminal can be used to be connected to the input terminal of another shift register unit in cascade and a pixel, respectively. Alternatively, the first output terminal can be used to be connected to the input terminal of another shift register unit in cascade, and on this basis, the shift register unit can further comprise a second output circuit. In this way, as shown in FIG. 21, the method can further comprise:

[0209] In step 2001, in the input stage, the second output circuit controls the third clock terminal to be connected to the second output terminal in response to the signal output through the first output terminal, and controls the fourth power terminal to be disconnected from the second output terminal in response to the potential of the second target node. The second output terminal is used to be connected to a pixel.

[0210] The second target node is shared by the first node connected to the first output circuit or the second node connected to the first output circuit.

[0211] In step 2002, in the output stage, the second output circuit controls the third clock terminal to be disconnected from the second output terminal in response to the signal output through the first output terminal, and controls the fourth power terminal to be connected to the second output terminal in response to the potential of the second target node.

[0212] Alternatively, with the circuit structure shown in FIG. 12, and taking the first potential as a low potential and the second potential as a high potential as an example, FIG. 22 shows a driving timing simulation diagram of a shift register unit. As shown in FIG. 22, the shift register unit can perform four stages t1 to t4.

[0213] In the t1 stage, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, the potential of the second clock signal provided by the second clock terminal CB can be a high potential, and the potential of the input signal provided by the input terminal IN can be a low potential. Thus, the first transistor T1 of the P type can be turned on. Further, the low potential input signal provided by the input terminal IN can be transmitted to the first sub-node N1-1 through the turned-on first transistor T1, so that the potential of the first sub-node N1-1 is a low potential. Since the potential of the third power signal provided by the third power supply terminal V3 (i.e., the pull-down power supply terminal VGL) remains a low potential, the eighth transistor T8 of the P type can remain turned on. Further, the low potential of the first sub-node N1-1 can be transmitted to the second sub-node N1-2 through the turned-on eighth transistor T8, so that the potential of the second sub-node N1-2 is also a low potential. On the basis of controlling the potentials of the first sub-node N1-1 and the second sub-node N1-2 to be low potentials, the second transistor T2 of the P type, the sixth transistor T6 of the P type, and the fourth transistor T4 of the P type can all be turned on, and the third transistor T3 of the N type can be turned off. Further, the high potential first power signal provided by the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH) can be transmitted to the second node N2 and the third node N3 through the turned-on second transistor T2 and the sixth transistor T6, respectively, and the low potential third power signal provided by the third power supply terminal V3 can be transmitted to the first output terminal OUT1 through the turned-on fourth transistor T4. On the basis of controlling the potentials of the second node N2 and the third node N3 to be high potentials, the seventh transistor T7 of the P type and the fifth transistor T5 of the P type can all be turned off.

[0214] In the t2 stage, the potential of the first clock signal provided by the first clock terminal CK can be high, the potential of the second clock signal provided by the second clock terminal CB can be low, and the potential of the input signal provided by the input terminal IN can be low. Thus, the first transistor T1 of the P type can be turned off. Under the coupling effect of the first capacitor C1, the potential of the third node N3 can be kept high. Under the coupling effect of the second capacitor C2, the potential of the second sub-node N1-2 can be kept low, and correspondingly, under the keeping open state of the eighth transistor T8, the potential of the first sub-node N1-1 can also be kept low. Under the coupling effect of the third capacitor C3, the potential of the second node N2 can be kept high. On the basis that the potential of the first sub-node N1-1 and the potential of the second sub-node N1-2 are kept low, the second transistor T2 of the P type, the sixth transistor T6 of the P type and the fourth transistor T4 of the P type can all be kept open, and the third transistor T3 of the N type can be kept off. Further, the high potential first power signal provided by the first power supply terminal V1 can continue to be transmitted to the second node N2 and the third node N3 through the open second transistor T2 and the sixth transistor T6 respectively, and the low potential third power signal provided by the third power supply terminal V3 can be transmitted to the first output terminal OUT1 through the open fourth transistor T4. On the basis that the potential of the second node N2 and the potential of the third node N3 are kept high, the seventh transistor T7 of the P type and the fifth transistor T5 of the P type can all be kept off.

[0215] At the stage t3, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, the potential of the second clock signal provided by the second clock terminal CB can be a high potential, and the potential of the input signal provided by the input terminal IN can be a high potential. Thus, the first transistor T1 of the P type can be turned on. Further, the high potential input signal provided by the input terminal IN can be transmitted to the first sub-node N1-1 through the turned-on first transistor T1, so that the potential of the first sub-node N1-1 is a high potential. Since the eighth transistor T8 is kept on, the high potential of the first sub-node N1-1 can be transmitted to the second sub-node N1-2 through the turned-on eighth transistor T8, so that the potential of the second sub-node N1-2 is also a high potential. On the basis of controlling the potentials of the first sub-node N1-1 and the second sub-node N1-2 to be high potentials, the second transistor T2 of the P type, the sixth transistor T6 of the P type, and the fourth transistor T4 of the P type can be all turned off, and the third transistor T3 of the N type can be turned on. Further, the low potential second power signal provided by the second power supply terminal V2 (i.e., the pull-down power supply terminal VGL) can be transmitted to the second node N2 through the turned-on third transistor T3. In addition, under the coupling effect of the first capacitor C1, the potential of the third node N3 can be kept as a high potential. On the basis of controlling the potential of the second node N2 to be a low potential and the potential of the third node N3 to be a high potential, the seventh transistor T7 of the P type can be turned off, and the fifth transistor T5 of the P type can be turned on. Further, the high potential first power signal provided by the first power supply terminal V1 can be transmitted to the first output terminal OUT1 through the turned-on fifth transistor T5.

[0216] At the t4 stage, the potential of the first clock signal provided by the first clock terminal CK can be high, the potential of the second clock signal provided by the second clock terminal CB can be low, and the potential of the input signal provided by the input terminal IN can be high. Thus, the first transistor T1 of the P type can be turned off. Under the coupling of the first capacitor C1, the potential of the third node N3 can become low. Under the coupling of the second capacitor C2, the potential of the second sub-node N1-2 can remain high, and accordingly, under the state that the eighth transistor T8 remains turned on, the potential of the first sub-node N1-1 can also remain high. Under the coupling of the third capacitor C3, the potential of the second node N2 can remain low. On the basis that the potentials of the first sub-node N1-1 and the second sub-node N1-2 remain high, the second transistor T2 of the P type, the sixth transistor T6 of the P type, and the fourth transistor T4 of the P type can all remain turned off, and the third transistor T3 of the N type can remain turned on. Further, the low potential second power signal provided by the second power terminal V2 can continue to be transmitted to the second node N2 through the turned-on third transistor T3. On the basis that the potentials of the second node N2 and the third node N3 are both low, the seventh transistor T7 of the P type and the fifth transistor T5 of the P type can both be turned on. Further, not only can the low potential second clock signal provided by the second clock terminal CB be transmitted to the second node N2 through the turned-on seventh transistor T7, so that the second node N2 is pulled down to a lower potential, to ensure that the fifth transistor T5 of the P type is fully turned on, but also the high potential first power signal provided by the first power terminal V1 can continue to be reliably transmitted to the first output terminal OUT1 through the fully turned-on fifth transistor T5.

[0217] Alternatively, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 22 that:

[0218] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal output through the first output terminal OUT1 can all be low VGL1, and the potential of the second node N2 and the potential of the third node N3 can both be high VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, and OUT1 / CR = VGL1.

[0219] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal output through the first output terminal OUT1 can all be low VGL1, and the potential of the second node N2 and the potential of the third node N3 can both be high VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, and OUT1 / CR = VGL1.

[0220] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the third node N3, and the potential of the signal outputted through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2 can be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGH1, OUT1 / CR = VGH1.

[0221] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal outputted through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2 and the potential of the third node N3 can all be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGL1, OUT1 / CR = VGH1.

[0222] It can be understood that the driving timing simulation diagram of the shift register unit of the structure shown in FIG. 13 can refer to FIG. 22, and the difference is that, in the structure shown in FIG. 13, the second power terminal V2 adopts the pull-down power terminal VGLL which can provide a lower potential signal, so that the potential of the second node N2 can be pulled to a lower potential.

[0223] Optionally, with the circuit structure shown in FIG. 14, and taking the first potential as the low potential and the second potential as the high potential as an example, FIG. 23 shows a driving timing simulation diagram of another shift register unit. It can be seen from FIG. 23 that the shift register unit can perform four t1 stages to t4.

[0224] In the t1 stage, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, the potential of the second clock signal provided by the second clock terminal CB can be a high potential, and the potential of the input signal provided by the input terminal IN can be a low potential. In this way, the first transistor T1 of the P type can be turned on. Further, the low potential input signal provided by the input terminal IN can be transmitted to the first node N1 through the turned-on first transistor T1, so that the potential of the first node N1 is a low potential. On the basis of controlling the potential of the first node N1 to be a low potential, the second transistor T2 of the P type and the sixth transistor T6 of the P type can be turned on, and the third transistor T3 of the N type can be turned off. Further, the high potential first power signal provided by the first power supply terminal V1 (i.e., the pull-up power supply terminal VGH) can be transmitted to the second node N2 and the third node N3 through the turned-on second transistor T2 and the sixth transistor T6, respectively. On the basis of controlling the potential of the second node N2 and the potential of the third node N3 to be high potentials, the fifth transistor T5 of the P type and the seventh transistor T7 of the P type can be turned off, and the fourth transistor T4 of the N type can be turned on. Further, the low potential third power signal provided by the third power supply terminal V3 can be transmitted to the first output terminal OUT1 through the turned-on fourth transistor T4.

[0225] In the t2 stage, the potential of the first clock signal provided by the first clock terminal CK can be a high potential, the potential of the second clock signal provided by the second clock terminal CB can be a low potential, and the potential of the input signal provided by the input terminal IN can be a low potential. In this way, the first transistor T1 of the P type can be turned off. Under the coupling action of the first capacitor C1, the potential of the third node N3 can remain a high potential. In addition, the potential of the first node N1 can remain a low potential, and the potential of the second node N2 can remain a high potential. On the basis of the potential of the first node N1 remaining a low potential, the second transistor T2 of the P type and the sixth transistor T6 of the P type can remain turned on, and the third transistor T3 of the N type can remain turned off. In this way, the high potential first power signal provided by the first power supply terminal V1 can continue to be transmitted to the second node N2 and the third node N3 through the turned-on second transistor T2 and the sixth transistor T6, respectively. On the basis of the potential of the second node N2 and the potential of the third node N3 remaining high potentials, the fifth transistor T5 of the P type and the seventh transistor T7 of the P type can remain turned off, and the fourth transistor T4 of the N type can remain turned on. Further, the low potential third power signal provided by the third power supply terminal V3 can continue to be transmitted to the first output terminal OUT1 through the turned-on fourth transistor T4.

[0226] At the t3 stage, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, the potential of the second clock signal provided by the second clock terminal CB can be a high potential, and the potential of the input signal provided by the input terminal IN can be a high potential. In this way, the first transistor T1 of the P type can be turned on. Further, the high potential input signal provided by the input terminal IN can be transmitted to the first node N1 through the turned-on first transistor T1, so that the potential of the first node N1 is a high potential. On the basis of controlling the potential of the first node N1 to be a high potential, the second transistor T2 of the P type and the sixth transistor T6 of the P type can be both turned off, and the third transistor T3 of the N type can be turned on. Further, the low potential second power supply signal provided by the second power supply terminal V2 can be transmitted to the second node N2 through the turned-on third transistor T3. In addition, on the basis of the coupling of the first capacitor C1, the potential of the third node N3 can be maintained as a high potential. On the basis of controlling the potential of the second node N2 to be a low potential and the potential of the third node N3 to be a high potential, the fifth transistor T5 of the P type can be turned on, and the seventh transistor T7 of the P type and the fourth transistor T4 of the N type can be both turned off. Further, the high potential first power supply signal provided by the first power supply terminal V1 can be transmitted to the first output terminal OUT1 through the turned-on fifth transistor T5.

[0227] At the t4 stage, the potential of the first clock signal provided by the first clock terminal CK can be a high potential, the potential of the second clock signal provided by the second clock terminal CB can be a low potential, and the potential of the input signal provided by the input terminal IN can be a high potential. In this way, the first transistor T1 of the P type can be turned off. On the basis of the coupling of the first capacitor C1, the potential of the third node N3 can become a low potential. In addition, the potential of the first node N1 can be maintained as a high potential. On the basis of controlling the potential of the first node N1 to be a high potential and the potential of the third node N3 to be a low potential, the second transistor T2 of the P type and the sixth transistor T6 of the P type can be both maintained as turned off, and the third transistor T3 of the N type can be maintained as turned on. In this way, the low potential second power supply signal provided by the second power supply terminal V2 can continue to be transmitted to the second node N2 through the turned-on third transistor T3. On the basis of the potential of the second node N2 and the potential of the third node N3 both being low potentials, the fourth transistor T4 of the N type can be turned off, and the seventh transistor T7 of the P type and the fifth transistor T5 of the P type can be both turned on. In this way, not only can the low potential second clock signal provided by the second clock terminal CB be transmitted to the second node N2 through the turned-on seventh transistor T7, so that the second node N2 is pulled down to a lower potential, but also the high potential first power supply signal provided by the first power supply terminal V1 can continue to be reliably transmitted to the first output terminal OUT1 through the fully turned-on fifth transistor T5.

[0228] Optionally, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 23 that:

[0229] At the t1 stage, the potential of the first node N1 and the potential of the signal output through the first output terminal OUT1 can both be the low potential VGL1, and the potential of the second node N2 and the potential of the third node N3 can both be the high potential VGH1. That is, N1 = VGL1, N2 = VGH1, N3 = VGH1, and OUT1 / CR = VGL1.

[0230] At the t2 stage, the potential of the first node N1 and the potential of the signal output through the first output terminal OUT1 can both be the low potential VGL1, and the potential of the second node N2 and the potential of the third node N3 can both be the high potential VGH1. That is, N1 = VGL1, N2 = VGH1, N3 = VGH1, and OUT1 / CR = VGL1.

[0231] At the t3 stage, the potential of the first node N1, the potential of the third node N3, and the potential of the signal output through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2 can be the low potential VGL1. That is, N1 = VGH1, N2 = VGL1, N3 = VGH1, and OUT1 / CR = VGH1.

[0232] At the t4 stage, the potential of the first node N1 and the potential of the signal output through the first output terminal OUT1 can both be the high potential VGH1, and the potential of the second node N2 and the potential of the third node N3 can both be the low potential VGL1. That is, N1 = VGH1, N2 = VGL1, N3 = VGL1, and OUT1 / CR = VGH1.

[0233] Optionally, with the circuit structure shown in FIG. 15, and taking the first potential as the low potential and the second potential as the high potential as an example, FIG. 24 shows another driving timing simulation diagram of the shift register unit. It can be seen from FIG. 24 that the shift register unit can perform four t1 stages to t4.

[0234] At the t1 stage, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, and the potential of the input signal provided by the input terminal IN can be a low potential. Thus, the first transistor T1 of the P type can be turned on. Further, the low potential input signal provided by the input terminal IN can be transmitted to the first sub-node N1-1 through the turned-on first transistor T1, so that the potential of the first sub-node N1-1 is a low potential. Since the potential of the third power supply signal provided by the third power supply terminal V3 remains a low potential, the eighth transistor T8 of the P type can remain turned on. Further, the low potential of the first sub-node N1-1 can be transmitted to the second sub-node N1-2 through the turned-on eighth transistor T8, so that the potential of the second sub-node N1-2 is also a low potential. On the basis of controlling the potentials of the first sub-node N1-1 and the second sub-node N1-2 to be low potentials, the second transistor T2 of the P type can be turned on, and the third transistor T3 of the N type can be turned off. Further, the high potential first power supply signal provided by the first power supply terminal V1 can be transmitted to the second node N2 through the turned-on second transistor T2. On the basis of controlling the potential of the second node N2 to be a high potential, the fifth transistor T5 of the P type can be turned off, and the fourth transistor T4 of the N type can be turned on. Further, the low potential third power supply signal provided by the third power supply terminal V3 can be transmitted to the first output terminal OUT1 through the turned-on fourth transistor T4.

[0235] At the t2 stage, the potential of the first clock signal provided by the first clock terminal CK can be a high potential, and the potential of the input signal provided by the input terminal IN can be a low potential. Thus, the first transistor T1 of the P type can be turned off. Further, the potentials of the first sub-node N1-1 and the second sub-node N1-2 can remain low potentials, and the potential of the second node N2 can remain a high potential. On the basis of the potentials of the first sub-node N1-1 and the second sub-node N1-2 remaining low potentials, the second transistor T2 of the P type can remain turned on, and the third transistor T3 of the N type can remain turned off. Thus, the high potential first power supply signal provided by the first power supply terminal V1 can continue to be transmitted to the second node N2 through the turned-on second transistor T2. On the basis of the potential of the second node N2 remaining a high potential, the fifth transistor T5 of the P type can remain turned off, and the fourth transistor T4 of the N type can remain turned on. Further, the low potential third power supply signal provided by the third power supply terminal V3 can continue to be transmitted to the first output terminal OUT1 through the turned-on fourth transistor T4.

[0236] At the t3 stage, the potential of the first clock signal provided by the first clock terminal CK can be a low potential, and the potential of the input signal provided by the input terminal IN can be a high potential. In this way, the first transistor T1 of the P type can be turned on. Further, the high potential input signal provided by the input terminal IN can be transmitted to the first sub-node N1-1 through the turned-on first transistor T1, so that the potential of the first sub-node N1-1 is a high potential. Since the eighth transistor T8 is kept on, the high potential of the first sub-node N1-1 can be transmitted to the second sub-node N1-2 through the turned-on eighth transistor T8, so that the potential of the second sub-node N1-2 is also a high potential. On the basis of controlling the potentials of the first sub-node N1-1 and the second sub-node N1-2 to be high potentials, the second transistor T2 of the P type can be turned off, and the third transistor T3 of the N type can be turned on. Further, the low potential second power signal provided by the second power supply terminal V2 can be transmitted to the second node N2 through the turned-on third transistor T3. On the basis of controlling the potential of the second node N2 to be a low potential, the fifth transistor T5 of the P type can be turned on, and the fourth transistor T4 of the N type can be turned off. Further, the high potential first power signal provided by the first power supply terminal V1 can be transmitted to the first output terminal OUT1 through the turned-on fifth transistor T5.

[0237] At the t4 stage, the potential of the first clock signal provided by the first clock terminal CK can be a high potential, and the potential of the input signal provided by the input terminal IN can be a high potential. In this way, the first transistor T1 of the P type can be turned off. In addition, the potentials of the first sub-node N1-1 and the second sub-node N1-2 can be kept as high potentials, and the potential of the second node N2 can be kept as a low potential. On the basis of keeping the potentials of the first sub-node N1-1 and the second sub-node N1-2 as high potentials, the second transistor T2 of the P type can be kept off, and the third transistor T3 of the N type can be kept on. In this way, the low potential second power signal provided by the second power supply terminal V2 can be transmitted to the second node N2 through the turned-on third transistor T3. On the basis of the potential of the second node N2 being a low potential, the fourth transistor T4 of the N type can be kept off, and the fifth transistor T5 of the P type can be kept on. In this way, the high potential first power signal provided by the first power supply terminal V1 can continue to be transmitted to the first output terminal OUT1 through the turned-on fifth transistor T5.

[0238] Optionally, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 24 that:

[0239] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal outputted through the first output terminal OUT1 can all be low potential VGL1, and the potential of the second node N2 can be high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, and OUT1 / CR = VGL1.

[0240] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal outputted through the first output terminal OUT1 can all be low potential VGL1, and the potential of the second node N2 can be high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, and OUT1 / CR = VGL1.

[0241] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal outputted through the first output terminal OUT1 can all be high potential VGH1, and the potential of the second node N2 can be low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, and OUT1 / CR = VGH1.

[0242] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, and the potential of the signal outputted through the first output terminal OUT1 can all be high potential VGH1, and the potential of the second node N2 can be low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, and OUT1 / CR = VGH1.

[0243] Optionally, with the circuit structure shown in FIG. 16, and taking the example that the first potential is low potential and the second potential is high potential, FIG. 25 shows another driving timing simulation diagram of the shift register unit. As can be seen from FIG. 25, the shift register unit can perform four t1 stages to t4.

[0244] Since FIG. 16 is a shift register unit further including the second output circuit 06 part on the basis of the structure shown in FIG. 12, the manner of controlling the first output terminal OUT1 of FIG. 16 can refer to the related description about FIG. 22 above, which will not be repeated here. In addition, for the structure shown in FIG. 16, the driving principle further includes:

[0245] In the t1 stage and the t2 stage: the potential of the signal output through the first output terminal OUT1 is low, and the potential of the second sub-node N1-2 is low. In addition, because the potential of the third power supply signal provided by the third power supply terminal V3 remains low, the eleventh transistor T11 of the P type can be kept open. Further, the low potential signal output through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also low. In this way, the ninth transistor T9 of the P type can be open. Because the second target node N02 is shared with the second sub-node N1-2, it can be known that the potential of the second target node N02 is also low at this time. In this way, the tenth transistor T10 of the N type can be turned off. Further, the third clock signal provided by the third clock terminal NCK can be transmitted to the second output terminal OUT2 through the open ninth transistor T9. Based on the foregoing, it can be known that the potential of the third clock signal is just opposite to the potential of the second clock signal at the same period. In this way, because the potential of the second clock signal is high in the t1 stage, it can be known that the potential of the third clock signal is low. Accordingly, it can be known that the potential of the signal output through the second output terminal OUT2 is low in the t1 stage. Because the potential of the second clock signal is low in the t2 stage, it can be known that the potential of the third clock signal is high. Accordingly, it can be known that the potential of the signal output through the second output terminal OUT2 is high in the t2 stage.

[0246] The difference is that, in the t2 stage, because the potential of the second clock signal is high, it can be known that the potential of the third clock signal is high. In this way, under the coupling effect of the fourth capacitor C4, the potential of the fourth node N4 is easily pulled high in the opposite direction, so that the potential of the signal output through the first output terminal OUT1 also fluctuates in the opposite direction, and it is not conducive to the reliable opening of the ninth transistor T9.

[0247] In the t3 stage and the t4 stage: the potential of the signal output through the first output terminal OUT1 is high, and the potential of the second sub-node N1-2 is high. In addition, because the eleventh transistor T11 remains open, the high potential signal output through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also high. In this way, the ninth transistor T9 of the P type can be turned off. Because the second target node N02 is shared with the second sub-node N1-2, it can be known that the potential of the second target node N02 is also high at this time. In this way, the tenth transistor T10 of the N type can be open. Further, the low potential fourth power supply signal provided by the fourth power supply terminal V4 (such as the pull-down power supply terminal VGL) can be transmitted to the second output terminal OUT2 through the open tenth transistor T10.

[0248] Optionally, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 25 that:

[0249] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, the potential of the signal output through the first output terminal OUT1, and the potential of the signal output through the second output terminal OUT2 can all be the low potential VGL1, and the potential of the second node N2 and the potential of the third node N3 can all be the high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, N4 = VGL1, OUT1 / CR = VGL1, and OUT2 = VGL1.

[0250] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be the low potential VGL1, and the potential of the second node N2, the potential of the third node N3, and the potential of the signal output through the second output terminal OUT2 can all be the high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, OUT1 / CR = VGL1, and OUT2 = VGH1.

[0251] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the third node N3, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2 and the potential of the signal output through the second output terminal OUT2 can all be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGH1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0252] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2, the potential of the third node N3, and the potential of the signal output through the second output terminal OUT2 can all be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGL1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0253] Optionally, in the circuit structure shown in FIG. 17, and taking the first potential as low potential and the second potential as high potential as an example, FIG. 26 shows a driving timing simulation diagram of another shift register unit. It can be seen from FIG. 26 that the shift register unit can perform four t1 stages to t4.

[0254] Since FIG. 17 is a shift register unit further including the second output circuit 06 part on the basis of the structure shown in FIG. 12, the manner of controlling the first output end OUT1 in FIG. 17 can refer to the related description about FIG. 22, which will not be repeated here. In addition, for the structure shown in FIG. 17, the driving principle further includes:

[0255] In the t1 stage: the potential of the signal output through the first output end OUT1 is low potential, and the potential of the second node N2 is high potential. In addition, since the potential of the third power supply signal provided by the third power supply end V3 remains low potential, the P-type eleventh transistor T11 can be kept open. Further, the low potential signal output through the first output end OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also low potential. In this way, the P-type ninth transistor T9 can be opened. Since the second target node N02 and the second node N2 are shared, it can be known that the potential of the second target node N02 is also high potential at this time. In this way, the N-type tenth transistor T10 can be opened. Further, the third clock signal provided by the third clock end NCK can be transmitted to the second output end OUT2 through the open ninth transistor T9, and the low potential fourth power supply signal provided by the fourth power supply end V4 can also be transmitted to the second output end OUT2 through the open tenth transistor T10. Based on the foregoing, it can be known that since the potential of the third clock signal is low potential in the t1 stage, it can be known that the low potential signal can be reliably output through the second output end OUT2 at this time.

[0256] At t2 stage, the potential of the signal outputted through the first output terminal OUT1 is low potential, and the potential of the second node N2 is high potential. In addition, because the eleventh transistor T11 keeps open, the low potential signal outputted through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also low potential. In addition, under the coupling effect of the fourth capacitor C4, the potential of the fourth node N4 can be further pulled down to a lower potential based on the low potential signal outputted through the second output terminal OUT2. In this way, although the potential of the second target node N02 shared with the second node N2 is also high potential, it can be ensured that the P-type ninth transistor T9 is fully open relative to the N-type tenth transistor T10. Further, the third clock signal provided by the third clock terminal NCK can be transmitted to the second output terminal OUT2 through the open ninth transistor T9. Based on the foregoing, because the potential of the third clock signal is high potential at t2 stage, it can be known that at this time the high potential signal can be reliably outputted through the second output terminal OUT2.

[0257] At t3 stage and t4 stage, the potential of the signal outputted through the first output terminal OUT1 is high potential, and the potential of the second node N2 is low potential. In addition, because the eleventh transistor T11 keeps open, the high potential signal outputted through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also high potential. In this way, the P-type ninth transistor T9 can be turned off. Because the second target node N02 is shared with the second node N2, it can be known that the potential of the second target node N02 is also low potential at this time. In this way, the N-type tenth transistor T10 can be turned off. At this time, as described above, the second output terminal OUT2 is in a floating state. However, because at any stage from t1 stage to t4 stage, under the coupling effect of the fourth capacitor C4, the potential of the fourth node N4 can be further adjusted to a required lower or higher potential based on the signal outputted through the second output terminal OUT2, instead of being adjusted to the opposite potential, the problem that the potential of the signal outputted through the first output terminal OUT1 is reversely fluctuated due to the coupling effect under the structure shown in FIG. 16 can be solved.

[0258] Alternatively, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 26 that:

[0259] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, the potential of the signal outputted through the first output terminal OUT1, and the potential of the signal outputted through the second output terminal OUT2 can all be low potential VGL1, and the potential of the second node N2 and the potential of the third node N3 can all be high potential VGH1. That is, N1-1=VGL1, N1-2=VGL1, N2=VGH1, N3=VGH1, N4=VGL1, OUT1 / CR=VGL1, and OUT2=VGL1.

[0260] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be low potential VGL1, and the potential of the second node N2, the potential of the third node N3, and the potential of the signal outputted through the second output terminal OUT2 can all be high potential VGH1. That is, N1-1=VGL1, N1-2=VGL1, N2=VGH1, N3=VGH1, OUT1 / CR=VGL1, and OUT2=VGH1.

[0261] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the third node N3, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be high potential VGH1, and the potential of the second node N2 can be low potential VGL1. That is, N1-1=VGH1, N1-2=VGH1, N2=VGL1, N3=VGH1, OUT1 / CR=VGH1, and the second output terminal OUT2 is in a floating state.

[0262] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be high potential VGH1, and the potential of the second node N2 and the potential of the third node N3 can all be low potential VGL1. That is, N1-1=VGH1, N1-2=VGH1, N2=VGL1, N3=VGL1, OUT1 / CR=VGH1, and the second output terminal OUT2 is in a floating state.

[0263] Optionally, with the circuit structure shown in FIG. 18, and taking the first potential as low potential and the second potential as high potential as an example, FIG. 27 shows a driving timing simulation diagram of another shift register unit. As can be seen from FIG. 27, the shift register unit can perform four t1 stages to t4.

[0264] Since Fig. 18 is a shift register unit further comprising the second output circuit 06 part based on the structure shown in Fig. 12, the manner of controlling the first output end OUT1 in Fig. 18 can refer to the above-mentioned related description about Fig. 22, and will not be repeated here. In addition, for the structure shown in Fig. 18, the driving principle also includes:

[0265] In the t1 stage and the t2 stage: the potential of the signal output through the first output end OUT1 is low, and the potential of the second sub-node N1-2 is low. In addition, since the potential of the third power supply signal provided by the third power supply end V3 remains low, the P-type eleventh transistor T11 can be kept open. Further, the low potential signal output through the first output end OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also low. In this way, the P-type ninth transistor T9 can be opened. Since the second target node N02 and the second sub-node N1-2 are shared, it can be known that the potential of the second target node N02 is also low at this time. In this way, the N-type tenth transistor T10 can be turned off. Further, the third clock signal provided by the third clock end NCK can be transmitted to the second output end OUT2 through the open ninth transistor T9. Based on the foregoing, since the potential of the third clock signal is low in the t1 stage, it can be known that the potential of the signal output through the second output end OUT2 is low in the t1 stage. Since the potential of the third clock signal is high in the t2 stage, it can be known that the potential of the signal output through the second output end OUT2 is high in the t2 stage.

[0266] In the t3 stage and the t4 stage: the potential of the signal output through the first output end OUT1 is high, and the potential of the second sub-node N1-2 is high. In addition, since the eleventh transistor T11 remains open, the high potential signal output through the first output end OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also high. In this way, the P-type ninth transistor T9 can be turned off. Since the second target node N02 and the second sub-node N1-2 are shared, it can be known that the potential of the second target node N02 is also high at this time. In this way, the N-type tenth transistor T10 can be opened. Further, the low potential fourth power supply signal provided by the fourth power supply end V4 can be transmitted to the second output end OUT2 through the open tenth transistor T10.

[0267] Thus, not only the problem that the second output terminal OUT2 is in floating state at the t3 stage and the t4 stage in the structure shown in Fig. 17 can be solved, but also the problem that the signal outputted through the first output terminal OUT1 is opposite fluctuated due to the coupling effect in the structure shown in Fig. 16 can be solved, because at any stage from the t1 stage to the t4 stage, the potential of the fourth node N4 can be further adjusted to a required lower or higher potential based on the signal outputted through the second output terminal OUT2 under the coupling effect of the fourth capacitor C4, instead of being adjusted to an opposite potential.

[0268] Alternatively, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from Fig. 27 that:

[0269] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, the potential of the signal outputted through the first output terminal OUT1, and the potential of the signal outputted through the second output terminal OUT2 can all be the low potential VGL1, and the potential of the second node N2 and the potential of the third node N3 can all be the high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, N4 = VGL1, OUT1 / CR = VGL1, and OUT2 = VGL1.

[0270] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be the low potential VGL1, and the potential of the second node N2, the potential of the third node N3, and the potential of the signal outputted through the second output terminal OUT2 can all be the high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N3 = VGH1, OUT1 / CR = VGL1, and OUT2 = VGH1.

[0271] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the third node N3, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be the high potential VGH1, and the potential of the second node N2 and the potential of the signal outputted through the second output terminal OUT2 can all be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGH1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0272] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal outputted through the first output terminal OUT1 can all be the high potential VGH1, the potential of the second node N2, the potential of the third node N3, and the potential of the signal outputted through the second output terminal OUT2 can all be the low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, N3 = VGL1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0273] Alternatively, with the circuit structure shown in FIG. 19, and taking the first potential as the low potential and the second potential as the high potential as an example, FIG. 28 shows a driving timing simulation diagram of another shift register unit. As can be seen from FIG. 28, the shift register unit can perform four t1 stages to t4.

[0274] Since FIG. 19 is a shift register unit further including the second output circuit 06 part in combination with the first output circuit 03 shown in FIG. 12 based on the structure shown in FIG. 15, the manner of controlling the first output terminal OUT1 in FIG. 19 can refer to the related description about FIG. 22 and FIG. 24 above, which will not be repeated here. In addition, for the structure shown in FIG. 19, the driving principle further includes:

[0275] At the t1 stage and the t2 stage: the potential of the signal outputted through the first output terminal OUT1 is the low potential, and the potential of the second sub-node N1-2 is the low potential. In addition, since the potential of the third power supply signal provided by the third power supply terminal V3 remains the low potential, the eleventh transistor T11 of the P type can be kept open. Further, the low potential signal outputted through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also the low potential. In this way, the ninth transistor T9 of the P type can be opened. Since the second target node N02 is shared with the second sub-node N1-2, it can be known that the potential of the second target node N02 is also the low potential at this time. In this way, the tenth transistor T10 of the N type can be turned off. Further, the third clock signal provided by the third clock terminal NCK can be transmitted to the second output terminal OUT2 through the open ninth transistor T9. Based on the foregoing, it can be known that the potential of the signal outputted through the second output terminal OUT2 is the low potential at the t1 stage, since the potential of the third clock signal is the low potential at the t1 stage. Since the potential of the third clock signal is the high potential at the t2 stage, it can be known that the potential of the signal outputted through the second output terminal OUT2 is the high potential at the t2 stage.

[0276] At the t3 stage and the t4 stage, the potential of the signal output through the first output terminal OUT1 is high, and the potential of the second sub-node N1-2 is high. In addition, because the eleventh transistor T11 is kept open, the high potential signal output through the first output terminal OUT1 can be transmitted to the fourth node N4 through the open eleventh transistor T11, that is, the potential of the fourth node N4 is also high. In this way, the ninth transistor T9 of the P type can be turned off. Because the second target node N02 is shared with the second sub-node N1-2, it can be known that the potential of the second target node N02 is also high at this time. In this way, the tenth transistor T10 of the N type can be turned on. Further, the low potential fourth power signal provided by the fourth power supply terminal V4 can be transmitted to the second output terminal OUT2 through the open tenth transistor T10.

[0277] Optionally, assuming that the low potential is VGL1 and the high potential is VGH1, it can be seen from FIG. 28 that:

[0278] At the t1 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, the potential of the signal output through the first output terminal OUT1, and the potential of the signal output through the second output terminal OUT2 can all be low potential VGL1, and the potential of the second node N2 is high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, N4 = VGL1, OUT1 / CR = VGL1, and OUT2 = VGL1.

[0279] At the t2 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be low potential VGL1, the potential of the second node N2, and the potential of the signal output through the second output terminal OUT2 can all be high potential VGH1. That is, N1-1 = VGL1, N1-2 = VGL1, N2 = VGH1, OUT1 / CR = VGL1, and OUT2 = VGH1.

[0280] At the t3 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be high potential VGH1, the potential of the second node N2, and the potential of the signal output through the second output terminal OUT2 can all be low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0281] At the t4 stage, the potential of the first sub-node N1-1, the potential of the second sub-node N1-2, the potential of the fourth node N4, and the potential of the signal output through the first output terminal OUT1 can all be a high potential VGH1, the potential of the second node N2, and the potential of the signal output through the second output terminal OUT2 can all be a low potential VGL1. That is, N1-1 = VGH1, N1-2 = VGH1, N2 = VGL1, OUT1 / CR = VGH1, and OUT2 = VGL1.

[0282] In addition, it can also be seen from FIGS. 22, 23, and 25 to 27 that, for the structure in which the shift register unit is connected to the first clock terminal CK and the second clock terminal CB respectively, there can also be an interval (which can be seen in FIG. 22) between any two adjacent stages among the t1 stage to the t4 stage, and during the interval, the potential of the first clock signal provided by the first clock terminal CK and the potential of the second clock signal provided by the second clock terminal CB can both be a high potential. In this way, the potential of the third node N3 can be pulled high to a high potential under the coupling action of the first capacitor C1. Further, the P-type first transistor T1 and the P-type seventh transistor T7 can both be turned off. On this basis, the potential of the first node N1 and the potential of the second node N2 can both remain the potential of the previous stage adjacent to the interval. For example, taking the interval between the t1 stage and the t2 stage as an example, the potential of the first node N1 during the interval can remain the low potential of the adjacent t1 stage, and the potential of the second node N2 can remain the high potential of the adjacent t1 stage. In this way, it can be ensured that, during the interval, the first output circuit 03 reliably outputs a signal to the first output terminal OUT1 under the control of the potential of the first node N1 and the potential of the second node N2, that is, the output stability of the shift register unit can be better. Of course, in some other embodiments, there can also be no interval between any two adjacent stages.

[0283] It can be understood that the above is a schematic description of the driving principle of the shift register unit of part of the circuit, and the driving principle of the shift register unit of other structures can be understood by analogy with the above description, and will not be described one by one.

[0284] It can also be understood that, since the driving method of the shift register unit has substantially the same technical effects as the shift register unit described above, for the purpose of brevity, the technical effects of the driving method of the shift register unit will not be described again.

[0285] The embodiments of the present application also provide a display driving circuit. As shown in FIGS. 29 and 30, the display driving circuit comprises at least two cascaded shift register units 00 as described above.

[0286] For example, FIG. 29 and FIG. 30 each schematically show n cascaded shift register units 00(1), 00(2), …, 00(n), where n can be an integer greater than 1.

[0287] It can be seen that FIG. 29 is a structural schematic diagram of a display driving circuit, which is based on the circuit structure shown in FIG. 12, i.e., the first output terminal OUT1 in the shift register unit 00 is used to drive the work of the cascaded shift register units as the shift output terminal CR and to drive the pixel Pixel to emit light as the driving output terminal. On this basis, each shift register unit 00 is connected with the first output terminal OUT1, and the first output terminal OUT1 is further connected with the pixel Pixel and the input terminal IN of the other cascaded shift register units 00. For example, referring to FIG. 29, the first output terminal OUT1 of the first shift register unit 00(1) is connected with the pixel Pixel and the input terminal IN of the second cascaded shift register unit 00(2), respectively.

[0288] FIG. 30 is another structural schematic diagram of a display driving circuit, which is based on the circuit structure shown in FIG. 16, i.e., the first output terminal OUT1 in the shift register unit 00 is used to drive the work of the cascaded shift register units as the shift output terminal CR, and the second output terminal OUT2 is used to drive the pixel Pixel to emit light as the driving output terminal. On this basis, each shift register unit 00 is connected with the first output terminal OUT1 and the second output terminal OUT2, and the first output terminal OUT1 is used to connect with the input terminal IN of the other cascaded shift register units 00, and the second output terminal OUT2 is used to connect with the pixel Pixel. For example, referring to FIG. 30, the first output terminal OUT1 of the first shift register unit 00(1) is connected with the input terminal IN of the second cascaded shift register unit 00(2).

[0289] Of course, it can also be seen from FIG. 29 and FIG. 30 that the input terminal IN of the first shift register unit 00(1) can be connected with the start signal terminal STV to receive the start signal, so as to drive the work of the cascaded shift register units. In addition, it can also be seen from FIG. 12 to FIG. 19 that each shift register unit 00 can be further connected with other signal terminals such as the clock terminal and the power terminal, which are not shown in FIG. 29 and FIG. 30.

[0290] It can be understood that in the display driving circuit shown in FIGS. 29 and 30, each stage of the shift register units 00 is cascaded with an adjacent stage of the shift register units 00. However, in some other embodiments, the cascaded manner is not limited. For example, each stage of the shift register units 00 can be cascaded with multiple stages of the shift register units 00 that are not adjacent. In addition, in the display driving circuit shown in FIGS. 29 and 30, each stage of the shift register units 00 is connected to one-to-one correspondingly with multiple rows of pixels. However, in some other embodiments, the one-to-one corresponding connection manner is not limited. For example, one stage of the shift register units 00 can be connected to multiple rows of pixels.

[0291] It can be understood that the display driving circuit has substantially the same technical effects as the shift register unit described above, and therefore, for the purpose of brevity, the technical effects of the driving method of the display driving circuit will not be described again.

[0292] The embodiments of the present application further provide a display device. As shown in FIG. 31, the display device comprises a display panel 100 and a display driving circuit 000 as shown in FIG. 29 or FIG. 30.

[0293] The display panel 100 comprises multiple pixels, and the display driving circuit 000 is connected to the multiple pixels and is configured to transmit display driving signals to the multiple pixels to drive the multiple pixels to emit light. For example, the display driving circuit 000 can be a gate driving circuit configured to transmit gate driving signals to the multiple pixels.

[0294] Optionally, the display device described in the embodiments of the present application can be any product or component with display function, such as an active-matrix organic light-emitting diode (AMOLED) display device, an organic light-emitting diode (OLED) display device, and a liquid crystal display device.

[0295] The AMOLED display device has low power consumption, a wide working temperature range, low cost, high contrast, wide viewing angle, wide color gamut, and thin display panel, and can realize flexible display, gradually becoming the display crown of the next generation. The OLED display device can meet most of the requirements of high performance and large capacity of display devices in today's information age, can be used for indoor and outdoor lighting, can be used as wallpaper decoration, can be made into foldable electronic newspapers, and can also be applied to portable electronic products such as mobile phones, tablet computers, and wearable electronic devices.

[0296] It can be understood that the display device has substantially the same technical effects as the shift register unit described above, and therefore, for the purpose of brevity, the technical effects of the driving method of the display device will not be described again.

[0297] It should be noted that the terms used in the embodiments of the present application are only used to explain the embodiments, and are not intended to limit the present application. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be understood as the general meaning understood by those skilled in the art in the field of the present application.

[0298] As used in the patent application specification and claims of the present application, "first", "second", or "third" and the like words do not indicate any order, number or importance, but are only used to distinguish different components.

[0299] Similarly, "one" or "a" and the like words do not indicate a quantity limitation, but indicate the existence of at least one.

[0300] "Include" or "contain" and the like words mean that the elements or objects appearing before "include" or "contain" cover the elements or objects listed after "include" or "contain" and their equivalents, and do not exclude other elements or objects.

[0301] "Up", "down", "left" or "right" and the like are only used to represent relative positional relationships, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "connected" means electrical connection.

[0302] "And / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0303] The above is only an optional embodiment of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A shift register unit, comprising: a first input circuit connected with a first clock terminal, an input terminal and a first node respectively, and configured to control the input terminal and the first node in response to a first clock signal provided by the first clock terminal; a second input circuit connected with the first node, a first power supply terminal, a second power supply terminal and a second node respectively, and configured to control the first power supply terminal and the second node in response to a potential of the first node, and control the second power supply terminal and the second node, and the first power supply terminal and the second power supply terminal are conductive to the second node in different time periods respectively; a first output circuit connected with the second node, a first target node, the first power supply terminal, a third power supply terminal and a first output terminal respectively, and configured to control the first power supply terminal and the first output terminal in response to a potential of the second node, and control the third power supply terminal and the first output terminal in response to a potential of the first target node, and the first power supply terminal and the third power supply terminal are conductive to the first output terminal in different time periods respectively; wherein the first target node is shared by the first node or the second node.

2. The shift register cell of claim 1, wherein, the second power supply terminal is shared by the third power supply terminal; or, the second power supply terminal and the third power supply terminal are independent of each other, and a potential of a second power supply signal provided by the second power supply terminal is less than a potential of a third power supply signal provided by the third power supply terminal.

3. The shift register cell of claim 1 or 2, wherein, the first input circuit comprises a first transistor, and the first transistor is a P-type transistor; a gate of the first transistor is connected with the first clock terminal, a first pole of the first transistor is connected with the input terminal, and a second pole of the first transistor is connected with the first node.

4. The shift register cell of any one of claims 1 to 3, wherein, the second input circuit comprises a second transistor and a third transistor, and the second transistor and the third transistor are a P-type transistor and an N-type transistor respectively; a gate of the second transistor is connected with the first node, a first pole of the second transistor is connected with the first power supply terminal, and a second pole of the second transistor is connected with the second node; a gate of the third transistor is connected with the first node, a first pole of the third transistor is connected with the second power supply terminal, and a second pole of the third transistor is connected with the second node.

5. The shift register cell of any one of claims 1 to 4, wherein, the first output circuit comprises a fourth transistor and a fifth transistor, and the fourth transistor and the fifth transistor are P-type transistors, or an N-type transistor and a P-type transistor respectively; a gate of the fourth transistor is connected with the first target node, a first pole of the fourth transistor is connected with the third power supply terminal, and a second pole of the fourth transistor is connected with the first output terminal; a gate of the fifth transistor is connected with the second node, a first pole of the fifth transistor is connected with the first power supply terminal, and a second pole of the fifth transistor is connected with the first output terminal.

6. The shift register cell of any one of claims 1 to 5, wherein, The second input circuit is also connected with a third node, and is configured to control the first power supply end and the third node to be connected or disconnected in response to the potential of the first node. The shift register unit further comprises: A third input circuit is connected with the third node, a second clock end and the second node respectively, and is configured to control the second clock end and the second node to be connected or disconnected in response to the potential of the third node, and adjust the potential of the third node based on a second clock signal provided by the second clock end.

7. The shift register cell of claim 6, wherein, The second input circuit further comprises a sixth transistor, which is a P-type transistor. The gate of the sixth transistor is connected with the first node, the first pole of the sixth transistor is connected with the first power supply end, and the second pole of the sixth transistor is connected with the third node.

8. The shift register cell of claim 6 or 7, wherein, The third input circuit comprises a seventh transistor and a first capacitor, and the seventh transistor is a P-type transistor. The gate of the seventh transistor is connected with the third node, the first pole of the seventh transistor is connected with the second clock end, and the second pole of the seventh transistor is connected with the second node. One end of the first capacitor is connected with the third node, and the other end of the first capacitor is connected with the second clock end. The first node comprises a first sub-node and a second sub-node, and the shift register unit further comprises:

9. The shift register cell of any of claims 6 to 8, wherein, A first control circuit is connected with the third power supply end, the first sub-node and the second sub-node respectively, and is configured to control the first sub-node and the second sub-node to be connected or disconnected in response to a third power supply signal provided by the third power supply end. The first input circuit is connected with the first sub-node, and is configured to control the input end and the first sub-node to be connected or disconnected in response to the first clock signal. The second input circuit is connected with the first sub-node and the second sub-node respectively, and is configured to control the first power supply end and the second node to be connected or disconnected in response to the potential of the first sub-node, and control the first power supply end and the third node to be connected or disconnected in response to the potential of the second sub-node; or, in the case that the first target node is shared by the first node, the second input circuit is connected with the first sub-node, and is configured to control the first power supply end and the second node to be connected or disconnected in response to the potential of the first sub-node, and control the second power supply end and the second node to be connected or disconnected, and control the first power supply end and the third node to be connected or disconnected; and the first output circuit is connected with the second sub-node, and is configured to control the third power supply end and the first output end to be connected or disconnected in response to the potential of the second sub-node. The first control circuit comprises an eighth transistor, which is a P-type transistor.

10. The shift register cell of claim 9, wherein, The gate of the eighth transistor is connected with the third power supply end, the first pole of the eighth transistor is connected with the first sub-node, and the second pole of the eighth transistor is connected with the second sub-node. ​ 11. The shift register cell of any one of claims 1 to 10, wherein, The first output end is connected with an input end of another shift register unit in cascade and a pixel respectively; Alternatively, the first output end is connected with an input end of another shift register unit in cascade, and the shift register unit further comprises: A second output circuit connected with the first output end, a second target node, a third clock end, a fourth power supply end and a second output end respectively, and configured to control on-off of the third clock end and the second output end in response to a signal output through the first output end, and control on-off of the fourth power supply end and the second output end in response to a potential of the second target node, and the third clock end and the fourth power supply end are turned on with the second output end in different time periods respectively; wherein the second output end is connected with the pixel; the second target node is shared by the first node connected with the first output circuit or the second node connected with the first output circuit. The fourth power supply end is shared by the third power supply end; 12. The shift register cell of claim 11, wherein, Alternatively, the fourth power supply end and the third power supply end are independent of each other, and a fourth power supply signal provided by the fourth power supply end has a potential smaller than that of a third power supply signal provided by the third power supply end. The second output circuit comprises a ninth transistor and a tenth transistor; the ninth transistor and the tenth transistor are P-type transistor and N-type transistor respectively; 13. The shift register cell of claim 11 or 12, wherein, A gate of the ninth transistor is connected with the first output end, a first pole of the ninth transistor is connected with the third clock end, and a second pole of the ninth transistor is connected with the second output end; A gate of the tenth transistor is connected with the second target node, a first pole of the tenth transistor is connected with the fourth power supply end, and a second pole of the tenth transistor is connected with the second output end. The shift register unit further comprises:

14. The shift register cell of any of claims 11 to 13, wherein, A second control circuit connected between the first output end and the second output circuit, and further connected with the third power supply end, and configured to control on-off of the first output end and the second output circuit in response to a third power supply signal provided by the third power supply end. The second control circuit comprises an eleventh transistor; the eleventh transistor is P-type transistor; 15. The shift register cell of claim 14, wherein, A gate of the eleventh transistor is connected with the third power supply end, a first pole of the eleventh transistor is connected with the first output end, and a second pole of the eleventh transistor is connected with the second output circuit. The shift register unit further comprises at least one of the following circuits:

16. The shift register cell of claim 14 or 15, wherein, A first potential adjusting circuit connected with the first target node and the first output end respectively, and configured to adjust a potential of the first target node based on a signal output through the first output end, and the first target node is shared by the first node; A second potential adjusting circuit connected with the second node and the first power supply end respectively, and configured to adjust a potential of the second node based on a first power supply signal provided by the first power supply end; and A third potential adjusting circuit connected with the second node and the second power supply end respectively, and configured to adjust a potential of the second node based on a second power supply signal provided by the second power supply end. a third potential adjusting circuit, connected with the target signal end and a connection node of the second control circuit and the second output circuit respectively, and configured to adjust a potential of the connection node based on a signal provided by the target signal end; wherein, in a case that the second target node is shared with the first node, the target signal end is the third clock end or the second output end; in a case that the second target node is shared with the second node, the target signal end is the second output end.

17. The shift register cell of claim 16, wherein, the first potential adjusting circuit comprises a second capacitor; the second potential adjusting circuit comprises a third capacitor; and the third potential adjusting circuit comprises a fourth capacitor; one end of the second capacitor is connected with the first target node, and the other end of the second capacitor is connected with the first output end; one end of the third capacitor is connected with the second node, and the other end of the third capacitor is connected with the first power end; one end of the fourth capacitor is connected with the connection node, and the other end of the fourth capacitor is connected with the target signal end.

18. A driving method of a shift register unit, configured to drive the shift register unit according to any one of claims 1 to 17; the method comprising: in an input stage, a first input circuit controls the input end and the first node to be conductive in response to a first clock signal provided by a first clock end, a second input circuit controls the first power end and the second node to be conductive in response to a potential of the first node, and controls the second power end to be disconnected with the second node, and a first output circuit controls the first power end and the first output end to be disconnected in response to the potential of the second node, and controls the third power end and the first output end to be conductive in response to a potential of a first target node; wherein, the first target node is shared with the first node or the second node; in an output stage, the first input circuit controls the input end and the first node to be conductive in response to the first clock signal, the second input circuit controls the first power end and the second node to be disconnected in response to the potential of the first node, and controls the second power end and the second node to be conductive, and the first output circuit controls the first power end and the first output end to be conductive in response to the potential of the second node, and controls the third power end and the first output end to be disconnected in response to the potential of the first target node. the first output end is configured to be connected with an input end of another shift register unit in cascade and a pixel; or, the first output end is configured to be connected with an input end of another shift register unit in cascade, and the shift register unit further comprises a second output circuit; the method further comprises:

19. The method of claim 18, wherein, ​ In the input stage, the second output circuit controls the third clock terminal and the second output terminal to be connected in response to the signal output through the first output terminal, and controls the fourth power terminal and the second output terminal to be disconnected in response to the potential of the second target node; wherein the second output terminal is used to be connected with the pixel; the second target node is shared by the first node connected with the first output circuit or the second node connected with the first output circuit; In the output stage, the second output circuit controls the third clock terminal and the second output terminal to be disconnected in response to the signal output through the first output terminal, and controls the fourth power terminal and the second output terminal to be connected in response to the potential of the second target node.

20. A display drive circuit, the display drive circuit comprising: At least two cascaded shift register units as claimed in any one of claims 1 to 17.

21. A display device comprising: A display panel, and a display driving circuit as claimed in claim 20; Wherein the display panel comprises a plurality of pixels, the display driving circuit is connected with the plurality of pixels and is used to transmit display driving signals to the plurality of pixels to drive the plurality of pixels to emit light.

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