Thin film transistor, preparation method thereof and display panel

Abstract

The invention relates to the technical field of display, in particular to a thin film transistor, a preparation method of the thin film transistor and a display panel. The active layer, the gate insulation layer and the gate layer are sequentially arranged in a stacked mode, the active layer is arranged close to the substrate, and the active layer comprises a channel region and connecting regions located on the two opposite sides of the channel region; and the metal cushion layer is arranged between the gate insulation layer and the substrate and comprises a first metal pattern and a second metal pattern, and the first metal pattern and the second metal pattern are respectively in ohmic contact with the connecting region of the active layer.

Description

Thin film transistor, preparation method thereof and display panel TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of display, in particular to a thin film transistor, a preparation method thereof and a display panel. BACKGROUND

[0002] An array substrate in a display device includes a plurality of pixel regions, each of which is provided with a thin film transistor (TFT) for controlling pixel display. The thin film transistor is a device for controlling current, which generally includes a gate, a gate insulating layer, an active layer, a source and a drain, the active layer being electrically connected to the source and the drain, respectively, and the carrier concentration in the active layer can be regulated by adjusting the gate voltage, so as to control the output current between the source and the drain.

[0003] At present, the main active layer materials used in the industry are amorphous silicon (such as a-Si), metal oxide and low-temperature polysilicon (LTPS), and with the increasing demand of users for narrow frame, high PPI (Pixels per inch) and other products of display panels, higher requirements are put forward for the performance of thin film transistor devices.

[0004] SUMMARY

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] The first aspect of the embodiments of the present disclosure provides a thin film transistor, which comprises:

[0007] a substrate substrate;

[0008] an active layer, a gate insulating layer and a gate layer which are sequentially stacked, the active layer being arranged close to the substrate substrate, the active layer comprising a channel region and a connection region located on opposite sides of the channel region;

[0009] a metal pad layer, the metal pad layer being arranged between the gate insulating layer and the substrate substrate, comprising a first metal pattern and a second metal pattern, the first metal pattern and the second metal pattern forming ohmic contact with the connection region of the active layer, respectively.

[0010] In an optional embodiment, the thin film transistor further comprises a source and a drain which are arranged in the same layer, wherein one of the first metal pattern and the second metal pattern is multiplexed as the source, and the other is multiplexed as the drain.

[0011] In an alternative implementation, at least part of the metal pad layer is arranged between the active layer and the gate insulating layer, and a projection of the metal pad layer on the substrate substrate at least partially overlaps with a projection of the connection region of the active layer on the substrate substrate.

[0012] In an alternative implementation, the metal pad layer includes a first portion and a second portion, the second portion is arranged on a side of the first portion away from the active layer in a first direction, the first direction is a direction in which the channel region points to the connection region.

[0013] The first portion is arranged on a side of the active layer away from the substrate substrate, and the second portion is arranged on a side of the connection region away from the channel region.

[0014] In an alternative implementation, a projection of the first portion on the substrate substrate is located inside a projection of the connection region of the active layer on the substrate substrate.

[0015] In an alternative implementation, at least part of the metal pad layer is arranged between the active layer and the substrate substrate, and a projection of the metal pad layer on the substrate substrate at least partially overlaps with a projection of the connection region of the active layer on the substrate substrate.

[0016] In an alternative implementation, the metal pad layer includes a first portion and a second portion, the second portion is arranged on a side of the first portion away from the active layer in a first direction, the first direction is a direction in which the channel region points to the connection region.

[0017] The first portion is arranged on a side of the connection region of the active layer close to the substrate substrate, and a projection of the second portion on the substrate substrate does not overlap with a projection of the active layer on the substrate substrate.

[0018] In an alternative implementation, the thin film transistor further includes a source-drain electrode layer, the source-drain electrode layer is arranged on a side of the gate layer away from the substrate substrate.

[0019] The source-drain electrode layer includes a source and a drain, one of the source and the drain forms an ohmic contact with the first metal pattern, and the other forms an ohmic contact with the second metal pattern.

[0020] In an alternative implementation, the thin film transistor further includes an interlayer insulating layer, the interlayer insulating layer is arranged between the source-drain electrode layer and the gate layer, and the interlayer insulating layer covers at least a side surface of the gate layer and the gate insulating layer away from the substrate substrate.

[0021] In an optional implementation, the thin film transistor further comprises a first via hole penetrating through the interlayer insulating layer and the gate insulating layer along a second direction, the source-drain electrode layer forms an ohmic contact with the metal pad layer through the first via hole, and the second direction is a direction in which the substrate points to the interlayer insulating layer.

[0022] In an optional implementation, at least part of the metal pad layer is arranged between the active layer and the gate insulating layer, or,

[0023] at least part of the metal pad layer is arranged between the active layer and the substrate.

[0024] A projection of the metal pad layer on the substrate at least partially overlaps with a projection of the connection region of the active layer on the substrate.

[0025] In an optional implementation, the metal pad layer comprises a first part and a second part, the second part is arranged on a side of the first part away from the active layer along a first direction, and the first direction is a direction in which the channel region points to the connection region.

[0026] A projection of the first via hole on the substrate is inside a projection of the second part on the substrate.

[0027] In an optional implementation, the material of the active layer is metal oxide.

[0028] In an optional implementation, a width of the gate layer along a first direction is less than a width of the active layer along the first direction, and the first direction is a direction in which the channel region points to the connection region.

[0029] In an optional implementation, a projection of the gate insulating layer on the substrate covers a projection of the metal pad layer on the substrate and a projection of the active layer on the substrate.

[0030] A second aspect of the embodiments of the present disclosure provides a display panel, which comprises the thin film transistor according to any one of the first aspect of the embodiments of the present disclosure.

[0031] A third aspect of the embodiments of the present disclosure provides a preparation method of a thin film transistor, which comprises:

[0032] providing a substrate;

[0033] The active layer, the gate insulating layer and the gate layer are sequentially formed on one side of the substrate, the active layer is arranged close to the substrate, and the active layer comprises a channel region and connection regions on opposite sides of the channel region.

[0034] The metal pad layer comprises a first metal pattern and a second metal pattern, and the first metal pattern and the second metal pattern form ohmic contacts with the connection regions of the active layer, respectively.

[0035] In an optional embodiment, the step of sequentially forming the active layer, the gate insulating layer and the gate layer on one side of the substrate comprises:

[0036] The active layer is formed on one side of the substrate.

[0037] The metal pad layer is formed on one side of the active layer, and at least part of the structure of the metal pad layer is arranged between the connection regions of the active layer and the substrate.

[0038] The gate insulating layer is formed on one side of the metal pad layer away from the substrate, and the gate insulating layer at least covers the metal pad layer and the surface of the active layer away from the substrate.

[0039] The gate layer is formed on one side of the gate insulating layer away from the substrate.

[0040] In an optional embodiment, the step of sequentially forming the active layer, the gate insulating layer and the gate layer on one side of the substrate comprises:

[0041] The metal pad layer is formed on one side of the substrate.

[0042] The active layer is formed on one side of the metal pad layer away from the substrate, and the channel region of the active layer covers the region between the first metal pattern and the second metal pattern, and at least part of the structure of the metal pad layer is arranged between the connection regions of the active layer and the substrate.

[0043] The gate insulating layer is formed on one side of the active layer away from the substrate, and the gate insulating layer at least covers the metal pad layer and the surface of the active layer away from the substrate.

[0044] The gate layer is formed on one side of the gate insulating layer away from the substrate. Advantages:

[0045] The embodiment of the present disclosure provides a thin film transistor and a preparation method thereof and a display panel, the thin film transistor comprising: a substrate; an active layer, a gate insulating layer and a gate layer which are sequentially stacked, the active layer is arranged close to the substrate, and the active layer comprises a channel region and a connecting region located on opposite sides of the channel region; and a metal pad layer arranged between the gate insulating layer and the substrate, comprising a first metal pattern and a second metal pattern, and the first metal pattern and the second metal pattern form ohmic contact with the connecting region of the active layer, respectively. The metal pad layer is arranged, so that the active layer forms ohmic contact with the metal pad layer at the connecting region without additional conductor treatment, the uniformity gap of the active layer at the connecting region and the channel region caused by the conductor treatment is effectively avoided, the characteristic uniformity of the display device is improved, and the electrical performance of the display device is improved.

[0046] The above description is only a summary of the technical solutions of the present disclosure. In order to more clearly understand the technical means of the present disclosure, the embodiments of the present disclosure can be implemented according to the content of the description, and in order to make the above and other purposes, characteristics and advantages of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described below. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the drawings needed to be used in the embodiments or the related art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creating any creative labor.

[0048] Fig. 1 is a schematic view of a cross-sectional structure of a thin film transistor along A-A' according to an embodiment of the present disclosure, in which a metal pad layer is multiplexed as a source-drain electrode layer;

[0049] Fig. 2 is an enlarged schematic view of a metal pad layer region of a thin film transistor according to an embodiment of the present disclosure, in which a metal pad layer is multiplexed as a source-drain electrode layer;

[0050] Fig. 3 is a schematic view of a cross-sectional structure of a thin film transistor along A-A' according to an embodiment of the present disclosure, in which a metal pad layer is multiplexed as a source-drain electrode layer;

[0051] Fig. 4 is an enlarged schematic view of a metal pad layer region of a thin film transistor according to an embodiment of the present disclosure, in which a metal pad layer is multiplexed as a source-drain electrode layer;

[0052] Fig. 5 is a schematic view of a top perspective view of a thin film transistor according to an embodiment of the present disclosure, in which a metal pad layer is multiplexed as a source-drain electrode layer;

[0053] Figure 6 is a schematic view of a cross-section along A-A' of a thin film transistor with a metal pad layer connecting the active layer and the source-drain electrode layer according to an embodiment of the present disclosure;

[0054] Figure 7 is a schematic view of a cross-section along A-A' of a thin film transistor with a metal pad layer connecting the active layer and the source-drain electrode layer according to an embodiment of the present disclosure;

[0055] Figure 8 is a schematic view of a top perspective of a thin film transistor with a metal pad layer connecting the active layer and the source-drain electrode layer according to an embodiment of the present disclosure;

[0056] Figure 9 is a schematic view of forming a light shielding layer in a method of manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0057] Figure 10 is a schematic view of forming a buffer insulating layer in a method of manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0058] Figure 11 is a schematic view of forming an active layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing away from the substrate according to an embodiment of the present disclosure;

[0059] Figure 12 is a schematic view of forming a metal pad layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing away from the substrate according to an embodiment of the present disclosure;

[0060] Figure 13 is a schematic view of forming a gate insulating layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing away from the substrate according to an embodiment of the present disclosure;

[0061] Figure 14 is a schematic view of forming a gate layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing away from the substrate according to an embodiment of the present disclosure;

[0062] Figure 15 is a schematic view of forming a metal pad layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing the substrate according to an embodiment of the present disclosure;

[0063] Figure 16 is a schematic view of forming an active layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing the substrate according to an embodiment of the present disclosure;

[0064] Figure 17 is a schematic view of forming a gate insulating layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing the substrate according to an embodiment of the present disclosure;

[0065] Figure 18 is a schematic view of forming a gate layer in a method of manufacturing a thin film transistor with a metal pad layer disposed on a side of the active layer facing the substrate according to an embodiment of the present disclosure;

[0066] FIG. 19 is a schematic view of forming an interlayer insulating layer in a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0067] FIG. 20 is a schematic view of forming a source-drain electrode layer in a method for manufacturing a thin film transistor according to an embodiment of the present disclosure.

[0068] Legend: 11, substrate; 12, light shielding layer; 13, buffer insulating layer; 21, source-drain electrode layer; 211, source electrode; 212, drain electrode; 22, metal pad layer; 221, first metal pattern; 222, second metal pattern; 223, first part; 224, second part; 23, active layer; 231, channel region; 232, connection region; 24, gate insulating layer; 25, gate layer; 31, interlayer insulating layer; 311, first via hole; 32, passivation layer; A1, channel region; A2, connection region. Specific embodiments

[0069] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0070] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or there can be an intermediate layer between the layer or element and the other layer or substrate.

[0071] An array substrate in a display device includes a plurality of pixel regions, each of which is provided with a thin film transistor (TFT) for controlling pixel display. The thin film transistor is a device for controlling current, and generally includes a gate, a gate insulating layer, an active layer, a source electrode and a drain electrode. The active layer is electrically connected to the source electrode and the drain electrode, respectively. The carrier concentration in the active layer can be adjusted by adjusting the gate voltage, so that the output current between the source electrode and the drain electrode can be controlled.

[0072] Currently, the main active layer materials used in the industry are amorphous silicon (such as a-Si), metal oxide and low-temperature polysilicon (LTPS). As users' demand for narrow frame, high PPI (Pixels per inch) and other products of display panels continues to increase, higher requirements are put forward for the performance of thin film transistor devices, and therefore it is urgent to improve the performance level of thin film transistors.

[0073] In the prior art, thin film transistors can be divided into top gate (Top Gate) structure and bottom gate (Bottom Gate) structure according to the upper and lower hierarchical relationship of the gate and the active layer. In the thin film transistor of the top gate structure, the active layer of the metal oxide material is processed, which is one of the main ways to improve the performance level of the device. Specifically, by conducting a conductorization process on the position where the active layer of the metal oxide material in the thin film transistor contacts the source and drain, when the active layer at the conductorization position directly overlaps with the source and drain, a good ohmic contact is formed.

[0074] However, on the one hand, on the basis of the existing TFT-LCD production line, only the plasma method can be used to conduct the conductorization process on the active layer, but the uniformity of this conductorization process is poor, which causes the performance uniformity of the device to be very poor, and the performance of different positions of the device shows a large difference, thereby affecting the electrical performance of the display device. On the other hand, if the ion implantation equipment in the LTPS technology is used to form the active layer of low-temperature polysilicon (LTPS), although the uniformity can be improved, it needs to make a costly investment on the production line, which greatly reduces the low-cost advantage of the metal oxide as the active layer material.

[0075] Therefore, the embodiments of the present disclosure provide a thin film transistor, FIG. 1 shows one of the cross-sectional structure schematic diagrams of the thin film transistor along A-A' according to an embodiment of the present disclosure, in which a metal pad layer is reused as a source and drain electrode layer, FIG. 5 shows a top perspective schematic diagram of the thin film transistor according to an embodiment of the present disclosure, in which a metal pad layer is reused as a source and drain electrode layer, as shown in FIG. 1 and FIG. 5, the thin film transistor comprises: a substrate 11; an active layer 23, a gate insulating layer 24 and a gate layer 25 which are sequentially stacked, the active layer 23 is arranged close to the substrate 11; a source and drain electrode layer 21 comprising a source electrode 211 and a drain electrode 212, the source electrode 211 and the drain electrode 212 are arranged in the same layer. Wherein, the active layer 23 comprises a channel region A1 and a connection region A2, the channel region A1 is arranged between the source electrode 211 and the drain electrode 212, for forming a flow path of carriers between the source electrode 211 and the drain electrode 212, the connection region A2 is located on the opposite sides of the channel region A1, for forming electrical connection with the source electrode 211 and the drain electrode 212 respectively.

[0076] Optionally, the material of the active layer 23 is a metal oxide, and the material of the active layer 23 includes at least one of IGZTO, IGZO and IGO, etc. The material of the source and drain electrode layer 21 includes at least one of Mo-based alloy and corresponding Cu, Al composite metal structure. The material of the gate layer 25 includes at least one of Mo-based alloy and corresponding Cu, Al composite metal structure.

[0077] Optionally, a width of the gate layer 25 along a first direction is less than a width of the active layer 23 along the first direction, the first direction being a direction in which the channel region A1 points to the connection region A2. By setting the width of the gate layer 25 along the first direction to be less than the width of the active layer 23 along the first direction, on one hand, it helps to reduce unnecessary current leakage while maintaining sufficient current driving capability, thereby improving the on-off ratio and current modulation capability of the thin-film transistor; on the other hand, it can adjust the electrical characteristics of the thin-film transistor, such as threshold voltage, mobility, etc., thereby improving the contrast, color saturation and response speed of the display.

[0078] Optionally, a material of the gate insulating layer 24 includes at least one of silicon oxide SiO2, silicon nitride SiN x and silicon oxynitride SiON, preferably, the material of the gate insulating layer 24 is silicon oxide SiO2. A thickness of the gate insulating layer 24 along a second direction is greater than or equal to 10 nm and less than or equal to 30 nm, the second direction being a direction in which the substrate 11 points to the gate insulating layer 24.

[0079] In the embodiments of the present disclosure, since the active layer 23 is a semiconductor material, when the active layer 23 is directly overlapped with the source-drain electrode layer 21, a Schottky contact is formed between the active layer 23 and the source-drain electrode layer 21, the energy band of the semiconductor material at the interface is bent, a higher Schottky barrier is formed, and thus the electrical performance of the thin film transistor is affected. In order to reduce the barrier of the contact interface between the source-drain electrode layer 21 and the active layer 23, an ohmic contact needs to be formed between the active layer 23 and the source-drain electrode layer 21, in which the energy band structure between the semiconductor material of the active layer 23 and the metal material of the source-drain electrode layer 21 is relatively flat, no barrier is formed, and thus the electrons can easily enter the metal from the semiconductor or enter the semiconductor from the metal, so that the current at the contact is linearly related to the voltage, which conforms to the Ohm's law. However, when the active layer 23 is directly overlapped with the source-drain electrode layer 21, the connection region A2 of the active layer 23 needs to be subjected to a conductorization treatment to form an ohmic contact between the active layer 23 and the source-drain electrode layer 21, which causes poor uniformity of the active layer 23. Therefore, in the embodiments of the present disclosure, the thin film transistor further comprises a metal pad layer 22, which is a metal layer directly overlapped with the active layer 23 and the source-drain electrode layer 21 respectively, that is, as an electrical connection structure between the active layer 23 and the source-drain electrode layer 21. The metal pad layer 22 is used to form an ohmic contact with the connection region A2 of the active layer 23 and the source-drain electrode layer 21 respectively, and by arranging the metal pad layer 22, the connection region A2 of the active layer 23 can form an ohmic contact with the source-drain electrode layer 22 without conductorization treatment, so as to ensure that the connection region A2 of the active layer 23 and the channel region A1 maintain high uniformity. The metal pad layer 22 is arranged between the gate insulating layer 24 and the substrate 11 and directly overlapped with the connection region A2 of the active layer 23. Alternatively, the metal pad layer 22 can be arranged on the side of the active layer 23 away from the substrate 11, or the metal pad layer 22 can be arranged on the side of the active layer 23 close to the substrate 11.

[0080] The metal pad layer 22 comprises a first metal pattern 221 and a second metal pattern 222, and the first metal pattern 221 and the second metal pattern 222 form ohmic contacts with the connection region A2 of the active layer 23 respectively. By arranging the metal pad layer 22 forming an ohmic contact with the active layer 23, the metal pad layer 22 realizes the ohmic contact between the active layer 23 and the source-drain electrode layer 21 without conductorization treatment of the connection region A2 of the active layer 23, so as to effectively avoid the problem of reduced uniformity of the active layer 23 caused by the conductorization treatment, and improve the electrical performance of the thin film transistor.

[0081] It is easy to understand that the source 211 and the drain 212 of the thin film transistor in the embodiment of the present disclosure can be symmetrical in structure, so that the source 211 and the drain 212 are not different in structure, and the source 211 and the drain 212 involved in the embodiment of the present disclosure can be exchanged according to the actual situation of the thin film transistor; correspondingly, the first metal pattern 221 and the second metal pattern 222 can also be not different in structure, and can be exchanged according to the actual situation, and the above-mentioned exchange belongs to the protection scope of the present disclosure.

[0082] In the process of the thin film transistor, the active layer 23 is formed before the gate insulating layer 24, and the orthographic projection of the gate insulating layer 24 on the substrate 11 covers the orthographic projection of the metal pad layer 22 on the substrate 11 and the orthographic projection of the active layer 23 on the substrate 11. By setting the gate insulating layer 24, the electrical isolation between the metal pad layer 22 and the gate layer 25 is realized. However, the process of forming the gate insulating layer 24 will cause the conductivity of the active layer 23 to decrease, and it is difficult to form an ohmic contact with metal without conductorization treatment. Therefore, in the embodiment of the present disclosure, the metal pad layer 22 is arranged between the gate insulating layer 24 and the substrate 11, and the gate insulating layer 24 is not formed when the metal pad layer 22 is formed. Therefore, when the metal pad layer 22 is overlapped with the active layer 23, the active layer 23 is not affected by the formation of the gate insulating layer 24, and an ohmic contact is formed between the metal pad layer 22 and the active layer 23.

[0083] Optionally, the material of the metal pad layer 22 includes at least one of Mo-based alloy and corresponding Cu-Al composite metal structure.

[0084] In some optional embodiments, since the metal pad layer 22 is located between the gate insulating layer 24 and the substrate 11, the active layer 23 can form an ohmic contact with the metal pad layer 22 without conductorization treatment, and therefore the metal pad layer 22 can be directly reused as the source-drain electrode layer 21. Specifically, one of the first metal pattern 221 and the second metal pattern 222 is reused as the source 211, and the other is reused as the drain 222. The metal pad layer 22 can be arranged on the side of the active layer 23 close to the substrate 11, or on the side of the active layer 23 away from the substrate 11.

[0085] In some optional embodiments, as shown in FIG. 1, the first metal pattern 221 is multiplexed as the source electrode 211, the second metal pattern 222 is multiplexed as the drain electrode 212, at least part of the structure of the metal pad layer 22 (including the first metal pattern 221 and the second metal pattern 222) is arranged between the active layer 23 and the gate insulating layer 24, and the orthogonal projection of the metal pad layer 22 on the substrate 11 at least partially overlaps with the orthogonal projection of the connection region A2 of the active layer 23 on the substrate 11, so as to ensure that the metal pad layer 22 and the connection region A2 of the active layer 23 are effectively overlapped.

[0086] Specifically, FIG. 2 shows one of the enlarged schematic diagrams of the metal pad layer region of the thin film transistor in which the metal pad layer is multiplexed as the source-drain electrode layer according to an embodiment of the present disclosure. As shown in FIG. 2, the metal pad layer 22 is arranged on the side of the active layer 23 away from the substrate 11, and the metal pad layer 22 (including the first metal pattern 221 and the second metal pattern 222) at least partially covers the surface of the connection region A2 of the active layer 23 away from the substrate 11.

[0087] Optionally, in order to ensure that the metal pad layer 22 can be effectively overlapped with the connection region A2 of the active layer 23 when the metal pad layer 22 is formed, the metal pad layer 22 includes a first part 223 and a second part 224, the second part 224 is arranged on the side of the first part 221 away from the active layer 23 in a first direction, and the first direction is the direction in which the channel region A1 points to the connection region A2. The first part 223 is arranged on the side of the active layer 23 away from the substrate 11, the orthogonal projection of the first part 223 on the substrate 11 is located inside the orthogonal projection of the connection region A2 of the active layer 23 on the substrate 11, and the first part 223 is configured to form an ohmic contact with the side surface of the connection region A2 of the active layer 23 away from the substrate 11; the second part 224 is arranged on the side of the connection region A2 away from the channel region A1. The second part 224 is configured to form an ohmic contact with the side surface of the active layer A2 away from the channel region A1.

[0088] In some optional embodiments, the first metal pattern 221 is multiplexed as the source electrode 211, and the second metal pattern 222 is multiplexed as the drain electrode 212. In the case where the metal pad layer 22 is arranged on the side of the active layer 23 away from the substrate 11, the metal material forming the metal pad layer 22 covers the active layer 23. In the process of patterning the metal material to form the first metal pattern 221 and the second metal pattern 222 of the metal pad layer 22, the patterning process will cause damage to the surface of the active layer 23 away from the substrate 11, resulting in a large number of defects on the surface of the active layer 23 away from the substrate 11, and further causing the characteristics of the thin film transistor to deteriorate. Therefore, in order to avoid the adverse effects of forming the metal pad layer 22 on the active layer 23, the metal pad layer 22 can also be arranged on the side of the active layer 23 close to the substrate 11. Specifically, FIG. 3 shows a cross-sectional structure along A-A' of a thin film transistor in which the metal pad layer is multiplexed as a source-drain electrode layer according to an embodiment of the present disclosure. As shown in FIG. 3, at least part of the structure of the metal pad layer 22 is arranged between the active layer 23 and the substrate 11. The orthogonal projection of the metal pad layer 22 on the substrate 11 at least partially overlaps with the orthogonal projection of the connection region A2 of the active layer 23 on the substrate 11, so that the metal pad layer 22 and the connection region A2 of the active layer 23 form an ohmic contact.

[0089] In the embodiment of the present disclosure, by arranging at least part of the structure of the metal pad layer 22 between the active layer 23 and the substrate 11, in the process of manufacturing the thin film transistor, the metal material forming the metal pad layer is first formed, and the metal material is patterned to form the first metal pattern 221 and the second metal pattern 222, and then the active layer 23 is formed. Since the active layer 23 is not formed during the patterning process of the metal pad layer 22, the active layer 23 is effectively prevented from being damaged by the patterning process of the metal pad layer 22, and the device characteristics of the thin film transistor are ensured.

[0090] Optionally, FIG. 4 shows a second enlarged schematic view of a metal pad layer region of a thin film transistor according to an embodiment of the present disclosure, in which the metal pad layer 22 includes a first portion 223 and a second portion 224, and the second portion 224 is arranged on a side of the first portion 223 away from the active layer 23 along the first direction. The first portion 223 is arranged on a side of the connection region A2 of the active layer 23 close to the substrate 11, and is configured to form an ohmic contact with a side surface of the connection region A2 of the active layer 23 close to the substrate 11 and a side surface of the channel region A1; and a projection of the second portion 224 on the substrate 11 does not overlap with a projection of the active layer 23 on the substrate 11.

[0091] Optionally, the first portion 223 and the second portion 224 of the metal pad layer 22 are arranged flush along the second direction, and a side surface of the metal pad layer 22 (including the first portion 223 and the second portion 224) close to the substrate 11 is arranged flush with a side surface of the channel region A1 of the active layer 23 close to the substrate 11. In the second direction, the connection region A2 of the active layer 23 is arranged away from the substrate 11 relative to the channel region A1 of the active layer 23, so that the connection region A2 of the active layer 23 is arranged on a side surface of the first portion 223 away from the substrate 11.

[0092] In some optional embodiments, in a case where the first metal pattern 221 and the second metal pattern 222 of the metal pad layer 22 are directly reused as the source 211 and the drain 212 of the source-drain electrode layer 21, although the ohmic contact between the source-drain electrode layer 21 and the metal pad layer 22 can be formed without conducting the active layer 23, the reuse of the metal pad layer 22 as the source-drain electrode layer 21 directly forms an electrical connection with the active layer 23, which causes only a gate insulating layer 24 with a small thickness to be arranged between the gate layer 25 and the source-drain electrode layer 21 (i.e., the metal pad layer 22), thereby causing a short circuit (DGS) between the data line and the gate line, resulting in an abnormal display effect of the display device. Therefore, in order to ensure the uniformity of the active layer 23 and avoid the short circuit between the gate layer 25 and the source-drain electrode layer 21, in the embodiments of the present disclosure, the source-drain electrode layer 21 is arranged on a side of the gate layer 25 away from the substrate 11, and forms an ohmic contact with the active layer 23 through the metal pad layer 22, wherein one of the source 211 and the drain 212 forms an ohmic contact with the first metal pattern 221, and the other forms an ohmic contact with the second metal pattern 222.

[0093] In an alternative embodiment, FIG. 6 shows a schematic view of a cross-section along A-A' of a thin film transistor having an active layer connected to a source-drain electrode layer through a metal pad layer according to an embodiment of the present disclosure, and FIG. 8 shows a schematic view of a top perspective view of a thin film transistor having an active layer connected to a source-drain electrode layer through a metal pad layer according to an embodiment of the present disclosure. As shown in FIG. 6 and FIG. 8, the thin film transistor further comprises an interlayer insulating layer 31 disposed between the source-drain electrode layer 21 and the gate layer 25, the interlayer insulating layer 31 covering at least the side surface of the gate layer 25 and the gate insulating layer 24 facing away from the substrate 11. The interlayer insulating layer 31 is configured to achieve electrical isolation between the source-drain electrode layer 21 and the gate layer 25, preventing short circuit between the source-drain electrode layer 21 and the gate layer 25 and affecting the performance of the thin film transistor.

[0094] The thin film transistor further comprises a first via hole 311 penetrating the interlayer insulating layer 31 and the gate insulating layer 24 along a second direction, the first via hole 311 being filled with the metal material of the source-drain electrode layer 21, the first via hole 311 being configured to achieve ohmic contact between the source-drain electrode layer 21 and the metal pad layer 22, the second direction being the direction of the substrate 11 pointing to the interlayer insulating layer. It is easily understood that the first via hole 311 comprises at least two, corresponding to the source 211 and the drain 212 respectively. Exemplarily, the first metal pattern 221 and the source 211 achieve ohmic contact through one first via hole 311, and the second metal pattern 222 and the drain 212 achieve ohmic contact through another first via hole 311.

[0095] In order to ensure that the source-drain electrode layer 21 is electrically connected to the metal pad layer 22 through the first via hole 311, the orthographic projection of the first via hole 311 on the substrate 11 is located inside the orthographic projection of the metal pad layer 22 on the substrate 11. Specifically, the orthographic projection of the first via hole 311 on the substrate 11 can be located inside the orthographic projection of the first part 223 on the substrate 11, and the orthographic projection of the first via hole 311 on the substrate 11 can also be located inside the orthographic projection of the second part 224 on the substrate 11. Preferably, the width of the second part 224 along the first direction is greater than the width of the first part 223 along the first direction. In order to ensure sufficient overlap area between the source-drain electrode layer 21 and the metal pad layer 22, the orthographic projection of the first via hole 311 on the substrate 11 is located inside the orthographic projection of the second part 224 on the substrate 11.

[0096] In the embodiment of the present disclosure, the source-drain electrode layer 21 forms an ohmic contact with the metal pad layer 22 through the first via 311, so that the source-drain electrode layer 21 located on the side of the interlayer insulating layer 31 away from the substrate 11 forms an ohmic contact with the active layer 23 located on the side of the interlayer insulating layer 31 close to the substrate 11 through the metal pad layer 22, thereby ensuring the uniformity of the active layer 23. On the other hand, by providing the interlayer insulating layer 31 with a large thickness, short circuit between the gate layer 25 and the source-drain electrode layer 21 is avoided.

[0097] Optionally, the material of the interlayer insulating layer 31 includes at least one of silicon oxide SiO2, silicon nitride SiN x and silicon oxynitride SiON. In order to ensure the electrical isolation effect of the interlayer insulating layer 31 between the source-drain electrode layer 21 and the gate layer 25, the thickness of the interlayer insulating layer 31 along the second direction is greater than the thickness of the gate insulating layer 24 along the second direction. For example, the thickness of the interlayer insulating layer 31 along the second direction is greater than or equal to 300 nm and less than or equal to 600 nm.

[0098] In some optional embodiments, as shown in FIG. 6, in the case where the source-drain electrode layer 21 is arranged on the side of the interlayer insulating layer 31 away from the substrate 11 and forms an ohmic contact with the active layer 23 through the first via 311, at least part of the structure of the metal pad layer 22 is arranged between the active layer 23 and the gate insulating layer 24, and the orthogonal projection of the metal pad layer 22 on the substrate 11 at least partially overlaps the connection region A2 of the active layer 23 on the substrate 11.

[0099] In some optional embodiments, FIG. 7 shows a second cross-sectional structure along A-A' of a thin film transistor connecting an active layer and a source-drain electrode layer through a metal pad layer according to an embodiment of the present disclosure. As shown in FIG. 7, in the case where the source-drain electrode layer 21 is arranged on the side of the interlayer insulating layer 31 away from the substrate 11 and forms an ohmic contact with the active layer 23 through the first via 311, at least part of the structure of the metal pad layer 22 is arranged between the active layer 23 and the substrate 11, and the orthogonal projection of the metal pad layer 22 on the substrate 11 at least partially overlaps the connection region A2 of the active layer 23 on the substrate 11.

[0100] In some optional embodiments, as shown in FIG. 1 and FIG. 5, the thin film transistor further comprises a light shielding layer 12, which is arranged between the substrate 11 and the active layer 23, the orthographic projection of the active layer 23 on the substrate 11 is inside the light shielding layer 12, the light shielding layer 12 is configured to block external light from entering the sensitive area of the thin film transistor, reduce the generation of leakage current, at the same time reduce the light cross talk between pixels, improve the contrast of the display picture, make the image more clear and sharp. Optionally, the material of the light shielding layer 12 comprises at least one of the following: Mo-based alloy and corresponding Cu, Al composite metal structure.

[0101] In some optional embodiments, the thin film transistor further comprises a buffer insulating layer 13, which is arranged between the active layer 23 and the light shielding layer 12, and covers the light shielding layer 12 at least in the whole surface, the buffer insulating layer 13 is configured to protect the internal levels of the thin film transistor, and plays a role of planarization in the process of other layers in the thin film transistor. Optionally, the material of the buffer insulating layer 13 comprises at least one of the following: silicon oxide SiO2, silicon nitride SiN x and silicon oxynitride SiON; the thickness of the buffer insulating layer 13 along the second direction is greater than or equal to 200 nm, and less than or equal to 500 nm.

[0102] In some optional embodiments, the thin film transistor further comprises a passivation layer 32, which is arranged on the side of the gate layer 25 away from the substrate 11, the passivation layer 32 is configured to protect the internal structure of the thin film transistor. Optionally, the material of the buffer insulating layer 13 comprises at least one of the following: silicon oxide SiO2, silicon nitride SiN x and silicon oxynitride SiON.

[0103] In an embodiment, the metal pad layer 22 is multiplexed as the source-drain electrode layer 21, the passivation layer 32 covers the gate layer 25 and the side surface of the gate insulating layer 24 away from the substrate 11, since the source-drain electrode layer 21 directly forms ohmic contact with the active layer 23 at this time, the thin film transistor does not arrange the interlayer insulating layer 31, at this time, the thickness of the passivation layer 32 along the second direction is larger, exemplarily, the thickness of the passivation layer 32 along the second direction is greater than or equal to 300 nm, and less than or equal to 600 nm.

[0104] In another embodiment, the thin film transistor is provided with an interlayer insulating layer 31 between the metal pad layer 22 and the source-drain electrode layer 21, and the passivation layer 32 covers the source 311, the drain 312, and a side surface of the interlayer insulating layer 31 away from the substrate 11; the passivation layer 32 has a thickness in the second direction, which is greater than or equal to 100 nm and less than or equal to 300 nm.

[0105] The thin film transistor provided by the embodiments of the present disclosure includes a substrate, an active layer, a gate insulating layer, and a gate layer which are sequentially stacked, the active layer is arranged close to the substrate, and the active layer includes a channel region and connection regions located on opposite sides of the channel region; and a metal pad layer which is arranged between the gate insulating layer and the substrate and includes a first metal pattern and a second metal pattern, the first metal pattern and the second metal pattern form ohmic contacts with the connection regions of the active layer, respectively. By arranging the metal pad layer, the active layer can form ohmic contacts with the metal pad layer at the connection regions without additional conductorization treatment, which effectively avoids the difference in uniformity of the active layer at the connection regions and the channel region caused by the conductorization treatment, improves the characteristic uniformity of the display device, and helps to improve the electrical performance of the display device.

[0106] Based on the same inventive concept, the embodiments of the present disclosure provide a display panel including the thin film transistor provided by the embodiments of the present disclosure. Optionally, the display panel can be a liquid crystal display (LCD) panel, an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, or the like, which is not specifically limited herein.

[0107] Based on the same inventive concept, the embodiments of the present disclosure provide a display device including the display panel provided by the embodiments of the present disclosure.

[0108] In some optional embodiments, the display device includes, but is not limited to, a television, a notebook computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, or any product or component having a touch display function. Those skilled in the art can select accordingly based on the actual use of the display device, and the disclosure will not be repeated here.

[0109] It should be noted that the display device includes not only the display panel but also other necessary components and components. For example, the display device can include a housing, a circuit board, a power line, and the like. Those skilled in the art can supplement accordingly based on the specific use requirements of the display device, and the disclosure will not be repeated here.

[0110] Based on the same inventive concept, the disclosure provides a preparation method of a thin film transistor. The preparation method includes the following steps: providing a substrate 11; sequentially forming an active layer 23, a gate insulating layer 24, and a gate layer 25 arranged in a stack on one side of the substrate 11, the active layer 23 being arranged close to the substrate 11, and the active layer 23 including a channel region A1 and a connecting region A2 located on opposite sides of the channel region A1; wherein a metal pad layer 22 is arranged between the gate insulating layer 24 and the substrate 11, the metal pad layer 22 including a first metal pattern 221 and a second metal pattern 222, and the first metal pattern 221 and the second metal pattern 222 respectively forming an ohmic contact with the connecting region A2 of the active layer 23.

[0111] In order for those skilled in the art to better understand the preparation method of the thin film transistor provided by the embodiments of the disclosure, the steps of the preparation method are described in detail as follows.

[0112] FIG. 9 shows a schematic diagram of forming a light shielding layer in a preparation method of a thin film transistor according to an embodiment of the disclosure. As shown in FIG. 9, the substrate 11 is provided first, and the light shielding layer 12 is formed on one side of the substrate 11. FIG. 10 shows a schematic diagram of forming a buffer insulating layer in a preparation method of a thin film transistor according to an embodiment of the disclosure. As shown in FIG. 10, the buffer insulating layer 13 is formed on the side of the light shielding layer 12 away from the substrate 11, and the buffer insulating layer 13 covers the light shielding layer 12 and the substrate 11 entirely.

[0113] In some optional embodiments, at least part of the metal pad layer 22 is arranged on the side of the active layer 23 away from the substrate 11, and the metal pad layer 22 is used to realize the ohmic contact between the source-drain electrode layer 21 and the active layer 23 (including the metal pad layer 22 being multiplexed as the source-drain electrode layer 21, or the metal pad layer 22 being used to realize the ohmic contact between the source-drain electrode layer 21 and the active layer 23). FIG. 11 shows a schematic diagram of forming an active layer in a preparation method of a thin film transistor with a metal pad layer arranged on the side of the active layer away from the substrate, as shown in FIG. 11, after the buffer insulating layer 13 is formed, the active layer 23 is formed on the side of the buffer insulating layer 13 away from the substrate 11 based on a patterning process and an annealing process. FIG. 12 shows a schematic diagram of forming a metal pad layer in a preparation method of a thin film transistor with a metal pad layer arranged on the side of the active layer away from the substrate, as shown in FIG. 12, the metal pad layer 22 is formed on the side of the active layer 23 based on a patterning process, and at least part of the metal pad layer 22 is arranged on the side of the connection area A2 of the active layer 23 away from the substrate 11. FIG. 13 shows a schematic diagram of forming a gate insulating layer in a preparation method of a thin film transistor with a metal pad layer arranged on the side of the active layer away from the substrate, as shown in FIG. 13, the gate insulating layer 24 is formed on the side of the metal pad layer 22 away from the substrate 11, and the gate insulating layer 24 at least covers the side surface of the metal pad layer 22 and the side surface of the active layer 23 away from the substrate 11. FIG. 14 shows a schematic diagram of forming a gate layer in a preparation method of a thin film transistor with a metal pad layer arranged on the side of the active layer away from the substrate, as shown in FIG. 14, the gate layer 25 is formed on the side of the gate insulating layer 24 away from the substrate 11 based on a patterning process.

[0114] In some optional embodiments, at least part of the metal pad layer 22 is arranged on the side of the active layer 23 close to the substrate 11, and the ohmic contact between the source-drain electrode layer 21 and the active layer 23 is realized through the metal pad layer 22 (including that the metal pad layer 22 is multiplexed as the source-drain electrode layer 21, or the ohmic contact between the source-drain electrode layer 21 and the active layer 23 is realized through the metal pad layer 22). FIG. 15 shows a schematic diagram of forming a metal pad layer in a preparation method of a thin film transistor in which the metal pad layer is arranged on the side of the active layer close to the substrate, as shown in FIG. 15, after the buffer insulating layer 13 is formed, the metal pad layer 22 is formed on the side of the buffer insulating layer 13 away from the substrate 11 based on a patterning process. FIG. 16 shows a schematic diagram of forming an active layer in a preparation method of a thin film transistor in which the metal pad layer is arranged on the side of the active layer close to the substrate, as shown in FIG. 16, the active layer 23 is formed on the side of the metal pad layer 22 away from the substrate 11 based on a patterning process and an annealing process, the channel region A1 of the active layer 23 covers the region between the first metal pattern 221 and the second metal pattern 222, and at least part of the metal pad layer 22 is arranged between the connection region A2 of the active layer 23 and the substrate 11. FIG. 17 shows a schematic diagram of forming a gate insulating layer in a preparation method of a thin film transistor in which the metal pad layer is arranged on the side of the active layer close to the substrate, as shown in FIG. 17, the gate insulating layer 24 is formed on the side of the active layer 23 away from the substrate 11, and the gate insulating layer 24 at least covers the metal pad layer 22 and the surface of the active layer 23 away from the substrate 11. FIG. 18 shows a schematic diagram of forming a gate layer in a preparation method of a thin film transistor in which the metal pad layer is arranged on the side of the active layer close to the substrate, as shown in FIG. 18, the gate layer 25 is formed on the side of the gate insulating layer 24 away from the substrate 11 based on a patterning process.

[0115] In some optional embodiments, one of the first metal pattern 221 and the second metal pattern 222 is multiplexed as the source electrode 211, and the other is multiplexed as the drain electrode 222. After the gate layer 25 is formed, the passivation layer 32 is formed on the side of the gate layer 25 away from the substrate 11, and the passivation layer 32 covers the gate layer 25 and the surface of the gate insulating layer 24 away from the substrate 11.

[0116] In some optional embodiments, one of the source 211 and the drain 212 forms an ohmic contact with the first metal pattern 221, and the other forms an ohmic contact with the second metal pattern 222. FIG. 19 shows a schematic diagram of forming an interlayer insulating layer in a method of manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 19, after the gate layer 25 is formed, an interlayer insulating layer 31 is formed on the side of the gate layer 25 away from the substrate 11; the interlayer insulating layer 31 and the gate insulating layer 24 are etched to form a first via 311, the first via 311 penetrates the interlayer insulating layer 31 and the gate insulating layer 24 along the second direction, and the orthographic projection of the first via 311 on the substrate 11 is located inside the orthographic projection of the metal pad layer 22 on the substrate 11. FIG. 20 shows a schematic diagram of forming a source-drain electrode layer in a method of manufacturing a thin film transistor according to an embodiment of the present disclosure. As shown in FIG. 20, after the interlayer insulating layer 31 is formed, a source-drain electrode layer 21 (including a source 211 and a drain 212) is formed on the side of the interlayer insulating layer 31 away from the substrate 11 based on a patterning process, the material of the source-drain electrode layer 21 fills the first via 311, and the source-drain electrode layer 21 and the metal pad layer 22 form an ohmic contact through the first via 311. Finally, a passivation layer 32 is formed on the side of the source-drain electrode layer 21 away from the substrate 11, and the passivation layer 32 covers the source 311, the drain 312, and the surface of the interlayer insulating layer 31 away from the substrate 11.

[0117] Each of the embodiments in the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between embodiments can be referred to each other.

[0118] In the description of the present specification, it should be understood that the terms “center”, “thickness”, “upper”, “lower”, “front”, “back”, “horizontal”, “top”, “bottom”, “inner”, “outer”, “axial”, “radial”, “circumferential” and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0119] In the present disclosure, unless specifically defined otherwise, the terms "mount", "connected", "connecting", "fixed", and "fixedly" mean to be connected by any means, for example, fixed connection, detachable connection, or integral, mechanical connection, electrical connection, or communication, direct connection, or indirect connection via an intermediate medium, or internal connection between two elements, or interaction between two elements. For those skilled in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances.

[0120] In the present disclosure, unless specifically defined otherwise, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is higher than the second feature in horizontal height. The first feature "under", "below" and "under" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the first feature is lower than the second feature in horizontal height.

[0121] The above application provides many different embodiments or examples for implementing different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described in the above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeatedly refer to numbers and / or letters in different examples, and such repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0122] As used herein, "one embodiment", "an embodiment", or "one or more embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Moreover, it is noted that the word "example" as used herein means that a particular feature, structure, or characteristic under discussion is included in at least one embodiment of the disclosure. However, it is not necessarily the same embodiment.

[0123] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0124] Finally, it needs to be pointed out that in this document, relational terms such as first and second and the like can only be used to distinguish one entity or action from another entity or action, without necessarily requiring or implying that there is any such actual relationship or order between these entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or terminal device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article, or terminal device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article, or terminal device including the element.

[0125] The above describes in detail a thin film transistor and a preparation method thereof, and a display panel provided by the present disclosure. The principles and implementation manners of the present disclosure are described by using specific examples. The above description of the examples is only used to help understand the method of the present disclosure and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present disclosure, the specific implementation manners and application ranges can be changed. In summary, the content of the present description should not be understood as a limitation of the present disclosure.

Claims

1. A thin film transistor, characterized by comprising: The thin film transistor comprises: a substrate substrate; an active layer, a gate insulating layer and a gate layer arranged in sequence, the active layer is arranged close to the substrate substrate, the active layer comprises a channel region and a connecting region located on the opposite sides of the channel region; a metal pad layer, the metal pad layer is arranged between the gate insulating layer and the substrate substrate, comprising a first metal pattern and a second metal pattern, the first metal pattern and the second metal pattern form ohmic contact with the connecting region of the active layer respectively.

2. The thin film transistor according to claim 1, wherein The thin film transistor further comprises a source and a drain, the source and the drain are arranged in the same layer, wherein one of the first metal pattern and the second metal pattern is multiplexed as the source, and the other is multiplexed as the drain.

3. The thin film transistor according to claim 2, wherein At least part of the structure of the metal pad layer is arranged between the active layer and the gate insulating layer, and the orthographic projection of the metal pad layer on the substrate substrate at least partially overlaps with the orthographic projection of the connecting region of the active layer on the substrate substrate.

4. The thin film transistor according to claim 3, wherein The metal pad layer comprises a first part and a second part, the second part is arranged on the side of the first part away from the active layer in a first direction, the first direction is the direction of the channel region pointing to the connecting region; The first part is arranged on the side of the active layer away from the substrate substrate, and the second part is arranged on the side of the connecting region away from the channel region.

5. The thin film transistor according to claim 4, wherein The orthographic projection of the first part on the substrate substrate is located inside the orthographic projection of the connecting region of the active layer on the substrate substrate.

6. The thin film transistor according to claim 2, wherein At least part of the structure of the metal pad layer is arranged between the active layer and the substrate substrate, and the orthographic projection of the metal pad layer on the substrate substrate at least partially overlaps with the orthographic projection of the connecting region of the active layer on the substrate substrate.

7. The thin film transistor according to claim 6, wherein The metal pad layer comprises a first part and a second part, the second part is arranged on the side of the first part away from the active layer in a first direction, the first direction is the direction of the channel region pointing to the connecting region; The first part is arranged on the side of the connecting region of the active layer close to the substrate substrate, and the orthographic projection of the second part on the substrate substrate does not overlap with the orthographic projection of the active layer on the substrate substrate.

8. The thin film transistor according to claim 1, wherein The thin film transistor further comprises a source-drain electrode layer, which is arranged on the side of the gate layer away from the substrate substrate; The source-drain electrode layer comprises a source and a drain, wherein one of the source and the drain forms ohmic contact with the first metal pattern, and the other forms ohmic contact with the second metal pattern.

9. The thin film transistor according to claim 8, wherein The thin film transistor further comprises an interlayer insulating layer, which is arranged between the source-drain electrode layer and the gate layer, and covers at least the side surface of the gate layer and the gate insulating layer away from the substrate substrate.

10. The thin film transistor according to claim 9, wherein The thin film transistor further comprises a first via, which penetrates the interlayer insulating layer and the gate insulating layer in a second direction, and the source-drain electrode layer forms ohmic contact with the metal pad layer through the first via, and the second direction is the direction of the substrate substrate pointing to the interlayer insulating layer.

11. The thin film transistor according to any one of Claims 8 to 10, wherein At least part of the metal pad layer is arranged between the active layer and the gate insulating layer, or At least part of the metal pad layer is arranged between the active layer and the substrate. The orthogonal projection of the metal pad layer on the substrate at least partially overlaps with the orthogonal projection of the connection region of the active layer on the substrate.

12. The thin film transistor according to claim 11, wherein The metal pad layer includes a first part and a second part, the second part is arranged on the side of the first part away from the active layer in a first direction, the first direction is the direction of the channel region pointing to the connection region. The orthogonal projection of the first via on the substrate is located inside the orthogonal projection of the second part on the substrate.

13. The thin film transistor according to claim 1, wherein The material of the active layer is metal oxide.

14. The thin film transistor according to claim 1, wherein The width of the gate layer in the first direction is smaller than the width of the active layer in the first direction, the first direction is the direction of the channel region pointing to the connection region.

15. The thin film transistor according to claim 1, wherein The orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the metal pad layer on the substrate and the orthogonal projection of the active layer on the substrate.

16. A display panel, characterized by The display panel includes the thin film transistor as claimed in any one of claims 1 to 15.

17. A method for fabricating a thin-film transistor, characterized in that, The preparation method of the thin film transistor includes: Providing a substrate; Forming the active layer, the gate insulating layer and the gate layer arranged in sequence on one side of the substrate, the active layer is arranged close to the substrate, the active layer includes a channel region and a connection region located on the opposite sides of the channel region; The metal pad layer is arranged between the gate insulating layer and the substrate, the metal pad layer includes a first metal pattern and a second metal pattern, the first metal pattern and the second metal pattern form ohmic contact with the connection region of the active layer respectively. The forming of the active layer, the gate insulating layer and the gate layer arranged in sequence on one side of the substrate includes:

18. The method for manufacturing a thin film transistor according to claim 17, wherein Forming the active layer on one side of the substrate; Forming the metal pad layer on one side of the active layer, at least part of the structure of the metal pad layer is arranged on the side of the connection region of the active layer away from the substrate; Forming the gate insulating layer on the side of the metal pad layer away from the substrate, the gate insulating layer at least covers the side surface of the metal pad layer and the active layer away from the substrate; Forming the gate layer on the side of the gate insulating layer away from the substrate. The forming of the active layer, the gate insulating layer and the gate layer arranged in sequence on one side of the substrate includes:

19. The method for fabricating a thin-film transistor according to claim 17, characterized in that, Forming the metal pad layer on one side of the substrate; Forming the active layer on the side of the metal pad layer away from the substrate, the channel region of the active layer covers the region between the first metal pattern and the second metal pattern, at least part of the structure of the metal pad layer is arranged between the connection region of the active layer and the substrate; Forming the gate insulating layer on the side of the active layer away from the substrate, the gate insulating layer at least covers the side surface of the metal pad layer and the active layer away from the substrate; ​ The gate layer is formed on a side of the gate insulating layer facing away from the substrate.

Images