Test method, device and equipment of storage chip and storage medium
By configuring appropriate test modes and environments in memory chip testing, conducting multiple tests, and comparing read/write speeds and error rates, the problems of low efficiency and insufficient accuracy in traditional testing are solved, achieving more efficient and accurate performance evaluation.
Patent Information
- Application Number
- CN202610033011.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-12
- Publication Date
- 2026-04-28
AI Technical Summary
Traditional memory chip performance testing is inefficient and the results are not accurate enough, making it difficult to meet the high capacity and high quality requirements of artificial intelligence for memory chips.
By acquiring the first test environment and the first test environment of the memory chip, configuring the test mode and test environment of the memory chip, determining the test cases, and conducting N tests, the chip performance is evaluated by comparing the test results with the reference read/write rate and reference error rate.
It improves the testing efficiency and accuracy of memory chips, ensures the relevance and fairness of testing, and enables more accurate evaluation of chip performance.
Smart Images
Figure CN121938437A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and specifically to a testing method, apparatus, device, and storage medium for memory chips. Background Technology
[0002] With the rapid development of artificial intelligence technology, the importance of memory chips has also risen significantly. The development of AI not only demands increasingly larger capacity from memory chips but also higher quality. The performance of a memory chip determines its quality. Traditional performance testing of memory chips typically employs ergonomic testing methods, which are inefficient and produce inaccurate results. Therefore, improving the testing efficiency and accuracy of memory chips is a pressing issue that needs to be addressed. Summary of the Invention
[0003] This invention provides a testing method, apparatus, device, and storage medium for memory chips, which can adapt test cases, test modes, and test environments to ensure the relevance, fairness, and efficiency of memory chip testing. Based on the test mode and test environment, a corresponding test benchmark is obtained, and the test results are compared with the test benchmark. The comparison results are used to characterize the performance of the memory chip under test, thereby improving the testing efficiency and accuracy of memory chips.
[0004] First, this embodiment of the invention provides a testing method for a memory chip, the testing method for the memory chip including: Obtain the first test mode and first test environment for the memory chip under test; The first test case is determined based on the first test mode and the first test environment; The memory chip under test is configured based on the first test mode and the first test environment, and the memory chip under test is tested N times according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. Based on the results of the N tests, the first test mode, and the first test environment, a first performance evaluation value of the memory chip under test is determined. When the first performance evaluation value is greater than the set value, the memory chip under test is determined to have passed the test; If the first performance evaluation value is less than or equal to the set value, the test of the memory chip under test is determined to be unsuccessful.
[0005] Then, this embodiment of the invention provides a testing apparatus for a memory chip, the testing apparatus comprising: an acquisition module, a first determination module, a testing module, and a second determination module, wherein, The acquisition module is used to acquire the first test mode and the first test environment for the memory chip to be tested; The first determining module is used to determine a first test case based on the first test mode and the first test environment; The testing module is used to configure the memory chip under test based on the first testing mode and the first testing environment, and to perform N tests on the memory chip under test according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. The second determining module is configured to determine a first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment; and to determine that the memory chip under test has passed the test when the first performance evaluation value is greater than a set value; and to determine that the memory chip under test has failed the test when the first performance evaluation value is less than or equal to the set value.
[0006] Next, an embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that the processor executes the computer program to implement a testing method for the memory chip as described in the first aspect.
[0007] Finally, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program causes a computer device to perform a testing method for a memory chip as described in the first aspect.
[0008] Implementing the embodiments of the present invention has the following beneficial effects: As can be seen, the testing method, apparatus, equipment, and storage medium for memory chips described in the embodiments of the present invention not only enable the test cases to be adapted to the test modes and test environments, ensuring the relevance, fairness, and efficiency of memory chip testing, but also, based on the first test mode and the first test environment, obtain a corresponding test benchmark, namely, the reference read / write rate and the reference error rate. Furthermore, the results of N tests can be compared with the reference read / write rate and the reference error rate to obtain the corresponding comparison results. These comparison results can be used to determine the first performance evaluation value of the memory chip under test. The first performance evaluation value characterizes the performance of the memory chip under test, thus improving the testing efficiency and accuracy of memory chips. Attached Figure Description
[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is a first structural schematic diagram of a computer device provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating a testing method for a memory chip provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the second structure of a computer device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a testing device for a memory chip provided in an embodiment of the present invention. Detailed Implementation
[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0012] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0013] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this invention, "multiple" refers to two or more.
[0014] In this invention, "at least one item" or similar expressions refer to any combination of these items, including any combination of a single item or multiple items. "One or more" means one or more, while "multiple" means two or more. For example, "at least one item" of a, b, or c can represent the following seven cases: a, b, c, a and b, a and c, b and c, a, b, and c. Each of a, b, and c can be an element or a set containing one or more elements.
[0015] In the embodiments of this invention, "connection" refers to various connection methods such as direct connection or indirect connection to achieve communication between devices. The embodiments of this invention do not impose any limitations on this.
[0016] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0017] The computer equipment can refer to the testing equipment used to perform memory chip testing. The testing equipment may include dedicated testing equipment or other computer equipment that can perform the testing content of this invention.
[0018] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device includes a processor, a memory, a communication interface, and one or more programs. The one or more programs are stored in the memory and configured to be executed by the processor. The memory includes a memory chip.
[0019] The memory may include volatile memory or non-volatile memory, or both. The memory may include memory chips.
[0020] Non-volatile memory can be read-only memory (ROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or memory chips.
[0021] Among them, volatile memory can be random access memory (RAM), which is used as an external cache.
[0022] By way of example, but not limitation, many forms of random access memory (RAM) are available, such as synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), dynamic random access memory (DRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).
[0023] The processor is the core component of a computer device, responsible for executing instructions and processing data. A processor can be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), a general-purpose processor, an Application-Specific Integrated Circuit (ASIC), a transistor logic device, a Field-Programmable Gate Array (FPGA), or other programmable logic devices, hardware components, or any combination thereof.
[0024] The processor can implement or execute various exemplary logic blocks, units, and circuits described in conjunction with the disclosure of this invention. The processor can also be a combination of components that implement computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.
[0025] The communication interface can be a transceiver, transceiver circuit, etc.
[0026] The one or more programs are stored in the aforementioned memory and configured to be executed by the aforementioned processor, and the one or more programs include instructions for performing any step in any of the following method embodiments.
[0027] The computer device may also include more or fewer structural elements than those shown in the above block diagram, such as power modules, physical buttons, Wi-Fi modules, speakers, Bluetooth modules, sensors, display modules, etc., without limitation.
[0028] The following functions can be achieved using this computer device: Obtain the first test mode and first test environment for the memory chip under test; The first test case is determined based on the first test mode and the first test environment; The memory chip under test is configured based on the first test mode and the first test environment, and the memory chip under test is tested N times according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. Based on the results of the N tests, the first test mode, and the first test environment, a first performance evaluation value of the memory chip under test is determined. When the first performance evaluation value is greater than the set value, the memory chip under test is determined to have passed the test; If the first performance evaluation value is less than or equal to the set value, the test of the memory chip under test is determined to be unsuccessful.
[0029] Please see Figure 2 , Figure 2 This is a flowchart illustrating a testing method for a memory chip provided in an embodiment of the present invention. The testing method for a memory chip includes: S201. Obtain the first test mode and the first test environment for the memory chip under test.
[0030] The computer device may include at least one memory chip, and the memory chip to be tested may be one of the memory chips to be tested.
[0031] Different test modes require different test environments. A test environment can include at least one of the following: a hardware environment, a software environment, or a physical environment. The hardware environment refers to the hardware configuration, the software environment to the software configuration, and the physical environment to the physical space where the test is conducted.
[0032] For example, a mapping table between test modes and test environments can be stored in advance, and the first test environment corresponding to the first test mode can be determined based on this mapping table.
[0033] S202. Determine the first test case based on the first test mode and the first test environment.
[0034] Different test modes can correspond to different test case sets. Each test case set can include at least one test case. For example, a pre-stored correspondence between preset test modes and test case sets can be stored. Each test case in each test case set corresponds to a test environment. Based on this correspondence, the first test case set corresponding to the first test mode can be determined. Then, the first test case corresponding to the first test environment can be selected from the first test case set. By making the test cases compatible with the test modes and test environments, the testing of memory chips can be guaranteed to be targeted, fair, and efficient.
[0035] S203. Configure the memory chip under test based on the first test mode and the first test environment, and perform N tests on the memory chip under test according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1.
[0036] The test can be configured based on the first test mode and the first test environment. After the test environment is configured, the test can be performed N times according to the first test case. That is, the first test case is run in the configured test environment, and the corresponding test results are recorded to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1.
[0037] In practice, N tests can be consecutive tests, or the time interval between two adjacent tests in N tests can be less than a specified threshold. This specified threshold can be preset or set by the system default. For example, the specified threshold can be 0.01s or 0.001s.
[0038] During each test, read / write speed and error rate can be collected in real time. For each test, the average read / write speed is calculated by averaging the corresponding read / write speeds, and the average error rate is calculated by averaging the corresponding error rates.
[0039] Among them, the read and write speed of the memory chip directly affects its performance. Generally speaking, a higher read and write speed means that data can be accessed faster within a phase time. The higher the read and write speed, the better the performance.
[0040] The error rate of a memory chip can be understood as the probability that a memory chip will malfunction within a certain period of time. The error rate reflects the reliability and stability of the memory chip; the lower the error rate, the better the quality and reliability of the memory chip.
[0041] S204. Determine the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment.
[0042] First, a corresponding test benchmark, namely the reference read / write rate and the reference error rate, can be obtained based on the first test mode and the first test environment. Then, the results of N tests can be compared with the reference read / write rate and the reference error rate to obtain the corresponding comparison results. These comparison results can be used to determine the first performance evaluation value of the memory chip under test. The first performance evaluation value is used to characterize the performance of the memory chip under test.
[0043] Specifically, a pre-stored mapping relationship between preset test modes and read / write rate sets can be used. This read / write rate set can include multiple read / write rates, each corresponding to a test environment. That is, a first read / write rate set corresponding to a first test mode can be determined based on this mapping relationship. This first read / write rate set can include multiple read / write rates, each corresponding to a test environment. Then, the read / write rate corresponding to the first test environment can be obtained from the first read / write rate set to obtain a reference read / write rate.
[0044] Correspondingly, a pre-stored mapping relationship between preset test modes and error rate sets can be stored. The error rate set can include multiple error rates, each corresponding to a test environment. That is, the first error rate set corresponding to the first test mode can be determined based on the mapping relationship. The first error rate set can include multiple error rates, each corresponding to a test environment. Then, the error rate corresponding to the first test environment can be obtained from the first error rate set to obtain the reference error rate.
[0045] S205. When the first performance evaluation value is greater than the set value, it is determined that the memory chip under test has passed the test.
[0046] The settings can be preset or set by system default.
[0047] The set value can be related to at least one of the following parameters: the attribute parameters of the memory chip under test, the test mode of the memory chip under test, and the test environment of the memory chip under test.
[0048] The attribute parameters of the memory chip under test may include at least one of the following: the model of the memory chip under test, the memory of the memory chip under test, the circuit structure of the memory chip under test, the computing power of the memory chip under test, etc., which are not limited here.
[0049] In practice, if the first performance evaluation value is greater than the set value, it indicates that the performance of the memory chip under test is good and meets the test requirements, thus confirming that the memory chip under test has passed the test.
[0050] S206. When the first performance evaluation value is less than or equal to the set value, it is determined that the test of the memory chip under test has failed.
[0051] In practice, if the first performance evaluation value is less than or equal to the set value, it indicates that the performance of the memory chip under test is poor and does not meet the test requirements, and the memory chip under test is determined to have failed the test.
[0052] As can be seen, the testing method for the memory chip described in this embodiment of the invention involves obtaining a first test mode and a first test environment for the memory chip under test, determining a first test case based on the first test mode and the first test environment, configuring the memory chip under test based on the first test mode and the first test environment, and performing N tests on the memory chip under test according to the first test case to obtain N test results. Each test result includes an average read / write speed and an average error rate; N is an integer greater than 1. A first performance evaluation value for the memory chip under test is determined based on the N test results, the first test mode, and the first test environment. When the first performance evaluation value is greater than a set value, the memory chip under test is determined to have passed the test. When the first performance evaluation value is less than or equal to the set value, the test of the memory chip under test is determined to be unsuccessful. This not only ensures that the test cases are adapted to the test mode and test environment, but also guarantees the relevance, fairness, and efficiency of the memory chip test. Based on the first test mode and first test environment, a corresponding test benchmark is obtained, namely the reference read / write rate and the reference error rate. The results of N tests can then be compared with the reference read / write rate and the reference error rate to obtain the corresponding comparison results. These comparison results can be used to determine the first performance evaluation value of the memory chip under test. The first performance evaluation value is used to characterize the performance of the memory chip under test. In this way, the testing efficiency and accuracy of the memory chip can be improved.
[0053] Preferably, the above step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment can be implemented in the following manner: Based on the first test mode and the first test environment, obtain the reference read / write rate and reference error rate; Based on the results of the N tests, the reference read / write speed, and the reference error rate, N sets of comparison results are determined. Each comparison result includes a read / write speed difference and an error rate difference. The read / write speed difference is the difference between the average read / write speed and the reference read / write speed, and the error rate difference is the difference between the average error rate and the reference error rate. The first performance evaluation value is determined based on the N sets of comparison results.
[0054] Specifically, a pre-stored mapping relationship between preset test modes and read / write rate sets can be used. This read / write rate set can include multiple read / write rates, each corresponding to a test environment. That is, a first read / write rate set corresponding to a first test mode can be determined based on this mapping relationship. This first read / write rate set can include multiple read / write rates, each corresponding to a test environment. Then, the read / write rate corresponding to the first test environment can be obtained from the first read / write rate set to obtain a reference read / write rate.
[0055] Correspondingly, a pre-stored mapping relationship between preset test modes and error rate sets can be stored. The error rate set can include multiple error rates, each corresponding to a test environment. That is, the first error rate set corresponding to the first test mode can be determined based on the mapping relationship. The first error rate set can include multiple error rates, each corresponding to a test environment. Then, the error rate corresponding to the first test environment can be obtained from the first error rate set to obtain the reference error rate.
[0056] In practical implementation, the average read / write speed and average error rate from N test results can be compared with the reference read / write speed and reference error rate to determine N sets of comparison results. Each comparison result includes a read / write speed difference and an error rate difference. The read / write speed difference is the difference between the average read / write speed and the reference read / write speed, and the error rate difference is the difference between the average error rate and the reference error rate. Specifically, the difference between the average read / write speed and the reference read / write speed from the N test results can be used to obtain N read / write speed differences, meaning each test result corresponds to one read / write speed difference. Similarly, the difference between the average error rate and the reference error rate from the N test results can be used to obtain N error rate differences, meaning each test result corresponds to one error rate.
[0057] Next, the first performance evaluation value can be determined based on the N sets of comparison results, that is, the performance of the memory chip can be evaluated from two dimensions: read / write speed and error rate.
[0058] Preferably, the above step of determining the first performance evaluation value based on the N sets of comparison results can be implemented in the following manner: Obtain the test times for the N tests to obtain N test times; Based on the N sets of comparison results and the N test times, determine the linear curves for the changes in read / write rate difference and error rate difference; Obtain the slope of the straight line showing the change in the read / write rate difference to obtain the first slope; Obtain the slope of the straight line showing the change in the error rate difference to obtain the second slope; The first performance evaluation value is determined based on the first slope and the second slope.
[0059] In the specific implementation, the test times of N tests can be obtained to get N test times (such as the start time (i.e., the test start time)). Then, based on the N sets of comparison results and the N test times, the straight lines for the change of read / write rate difference and the change of error rate difference can be determined. Specifically, N coordinate points can be determined based on the N test times and the N read / write rate differences. The horizontal axis of each coordinate is time, and the vertical axis is the read / write rate difference. Then, the N coordinate points are fitted to obtain the straight line for the change of read / write rate difference. Correspondingly, N coordinate points can be determined based on the N test times and the N error rate differences. The horizontal axis of each coordinate is time, and the vertical axis is the error rate difference. Then, the N coordinate points are fitted to obtain the straight line for the change of error rate difference.
[0060] Next, we can obtain the slope of the line representing the change in read / write speed difference to get the first slope, and then obtain the slope of the line representing the change in error rate difference to get the second slope. Finally, we can determine the first performance evaluation value based on the first and second slopes. That is, since the first slope reflects the stability of the read / write speed of the memory chip to a certain extent, and the second slope reflects the stability of the error rate of the memory chip to a certain extent, the lines representing the change in read / write speed difference and the lines representing the change in error rate also have a certain predictive power. Since the testing process of the memory chip is limited in duration, while the usage time of the memory chip can be as long as several years or even decades, we can use data from a short period of time to extrapolate the overall performance changes of the memory chip. Based on the extrapolation results, we can make decisions on the quality of the memory chip. That is, we can use the slopes of the two dimensions to determine the final first performance evaluation value, so that the first performance evaluation value can withstand the test of time, which helps to improve the reliability of the first performance evaluation value, and also helps to improve the testing efficiency and accuracy of the memory chip.
[0061] Preferably, the above step of determining the first performance evaluation value based on the first slope and the second slope can be implemented in the following manner: Determine the first reference performance evaluation value corresponding to the first slope; Determine the second reference performance evaluation value corresponding to the second slope; Obtain the first attribute parameters of the memory chip under test; A first weight pair is determined based on the first attribute parameter, wherein the first weight includes a first weight corresponding to the read / write rate and a second weight corresponding to the error rate; the sum of the first weight and the second weight is 1. The first performance evaluation value is obtained by performing a weighted operation on the first reference performance evaluation value, the second reference performance evaluation value, and the first weight.
[0062] In a specific implementation, a first mapping relationship between the slope and the performance evaluation value (the mapping relationship corresponding to the read / write rate dimension) and a second mapping relationship between the slope and the performance evaluation value (the mapping relationship corresponding to the error rate dimension) can be stored in advance. The first mapping relationship and the second mapping relationship can be the same or different. Then, based on the first mapping relationship, the first reference performance evaluation value corresponding to the first slope is determined, and based on the second mapping relationship, the second reference performance evaluation value corresponding to the second slope is determined.
[0063] Next, the first attribute parameters of the memory chip under test can be obtained. These first attribute parameters characterize the performance of the memory chip under test and may include at least one of the following: the model of the memory chip under test, the memory of the memory chip under test, the circuit structure of the memory chip under test, the computing power of the memory chip under test, etc., without limitation. A pre-stored mapping relationship between the attribute parameters and weight pairs of the memory chip can be established. Each weight pair may include two weights, corresponding to the read / write rate and the error rate respectively, and the sum of these two weights is 1. Based on this mapping relationship, a first weight pair corresponding to the first attribute parameter is determined. This first weight pair includes a first weight corresponding to the read / write rate and a second weight corresponding to the error rate; the sum of the first weight and the second weight is 1.
[0064] Next, a weighted calculation can be performed on the first reference performance evaluation value, the second reference performance evaluation value, and the first weight to obtain the first performance evaluation value, i.e., the first performance evaluation value = the first reference performance evaluation value × the first weight + the second reference performance evaluation value × the second weight. In other words, the slope of the two dimensions can be used to determine the final first performance evaluation value, so that the first performance evaluation value can stand the test of time, which helps to improve the reliability of the first performance evaluation value, and also helps to improve the testing efficiency and accuracy of the memory chip.
[0065] Preferably, the memory chip under test includes a temperature sensor, and the method further includes: The temperature sensor is used to obtain the first temperature value of the memory chip under test at the start time of the N tests. The temperature sensor is used to obtain the second temperature value of the memory chip under test at the end of the N tests. Determine the temperature difference between the first temperature value and the second temperature value; When the temperature difference is within the set temperature range, the step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment is executed. If the temperature difference is not within the set temperature range, the test of the memory chip under test is determined to have failed.
[0066] Among them, such as Figure 3 As shown, the computer device may include a memory chip to be tested, and the memory chip to be tested may include a temperature sensor that can acquire the temperature value of the memory chip to be tested.
[0067] The temperature range can be preset or set by system default. The temperature range can be related to the attribute parameters of the memory chip under test.
[0068] In specific implementation, a temperature sensor can be used to obtain the first temperature value of the memory chip under test at the start of N tests. Then, a temperature sensor can be used to obtain the second temperature value of the memory chip under test at the end of N tests. The temperature difference between the first and second temperature values is then determined. This temperature difference = second temperature value - first temperature value. The temperature difference reflects the temperature change of the memory chip under test before and after the test. Since the memory chip under test generates corresponding energy during the test, the amount of energy is related to its own characteristics. When the temperature difference is within the set temperature range, it indicates that the heat dissipation of the memory chip under test is normal. Then, the step of determining the first performance evaluation value of the memory chip under test based on the results of the N tests, the first test mode, and the first test environment can be executed. Conversely, when the temperature difference is not within the set temperature range, it indicates that the heat dissipation of the memory chip under test is abnormal, that is, it may have a fault or abnormality. It is determined that the test of the memory chip under test has failed. This can eliminate the possibility of abnormal heat dissipation of the memory chip under test, so as to ensure the fairness and efficiency of the test.
[0069] Please see Figure 4 , Figure 4 This is a schematic diagram of a testing device for a memory chip provided in an embodiment of the present invention. Applied to computer equipment, the testing device 400 for the memory chip includes: an acquisition module 410, a first determination module 420, a testing module 430, and a second determination module 440, wherein... The acquisition module 410 is used to acquire the first test mode and the first test environment for the memory chip to be tested. The first determining module 420 is used to determine a first test case based on the first test mode and the first test environment; The testing module 430 is used to configure the memory chip under test based on the first testing mode and the first testing environment, and to perform N tests on the memory chip under test according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. The second determining module 440 is configured to determine a first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment; and to determine that the memory chip under test has passed the test when the first performance evaluation value is greater than a set value; and to determine that the memory chip under test has failed the test when the first performance evaluation value is less than or equal to the set value.
[0070] Preferably, the second determining module 440 performs the step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment by following steps: Based on the first test mode and the first test environment, obtain the reference read / write rate and reference error rate; Based on the results of the N tests, the reference read / write speed, and the reference error rate, N sets of comparison results are determined. Each comparison result includes a read / write speed difference and an error rate difference. The read / write speed difference is the difference between the average read / write speed and the reference read / write speed, and the error rate difference is the difference between the average error rate and the reference error rate. The first performance evaluation value is determined based on the N sets of comparison results.
[0071] Preferably, the second determining module 440 performs the step of determining the first performance evaluation value based on the N sets of comparison results according to the following steps: Obtain the test times for the N tests to obtain N test times; Based on the N sets of comparison results and the N test times, determine the linear curves for the changes in read / write rate difference and error rate difference; Obtain the slope of the straight line showing the change in the read / write rate difference to obtain the first slope; Obtain the slope of the straight line showing the change in the error rate difference to obtain the second slope; The first performance evaluation value is determined based on the first slope and the second slope.
[0072] It is understood that the functions of each program module of the memory chip testing device in this embodiment can be specifically implemented according to the methods in the above method embodiments. The specific implementation process can be referred to the relevant descriptions in the above method embodiments, and will not be repeated here.
[0073] This invention also provides a computer storage medium storing a computer program for electronic data interchange, which causes a computer to perform some or all of the steps of any of the methods described in the above method embodiments.
[0074] This invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. This computer program product can be a software installation package.
[0075] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.
[0076] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0077] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.
[0078] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0079] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0080] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned memory includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.
[0081] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage device, which may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.
[0082] The embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A testing method for a memory chip, characterized in that, The testing methods for the memory chip include: Obtain the first test mode and first test environment for the memory chip under test; The first test case is determined based on the first test mode and the first test environment; The memory chip under test is configured based on the first test mode and the first test environment, and the memory chip under test is tested N times according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. Based on the results of the N tests, the first test mode, and the first test environment, a first performance evaluation value of the memory chip under test is determined. When the first performance evaluation value is greater than the set value, the memory chip under test is determined to have passed the test; If the first performance evaluation value is less than or equal to the set value, the test of the memory chip under test is determined to be unsuccessful.
2. The testing method for a memory chip as described in claim 1, characterized in that, The step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment includes: Based on the first test mode and the first test environment, obtain the reference read / write rate and reference error rate; Based on the N test results, the reference read / write rate, and the reference error rate, N sets of comparison results are determined. Each comparison result includes a read / write rate difference and an error rate difference. The read / write rate difference is the difference between the average read / write rate and the reference read / write rate, and the error rate difference is the difference between the average error rate and the reference error rate. The first performance evaluation value is determined based on the N sets of comparison results.
3. The testing method for a memory chip as described in claim 2, characterized in that, Determining the first performance evaluation value based on the N sets of comparison results includes: Obtain the test times for the N tests to obtain N test times; Based on the N sets of comparison results and the N test times, determine the linear curves for the changes in read / write rate difference and error rate difference; Obtain the slope of the straight line showing the change in the read / write rate difference to obtain the first slope; Obtain the slope of the straight line showing the change in the error rate difference to obtain the second slope; The first performance evaluation value is determined based on the first slope and the second slope.
4. The testing method for a memory chip as described in claim 3, characterized in that, Determining the first performance evaluation value based on the first slope and the second slope includes: Determine the first reference performance evaluation value corresponding to the first slope; Determine the second reference performance evaluation value corresponding to the second slope; Obtain the first attribute parameters of the memory chip under test; A first weight pair is determined based on the first attribute parameter, wherein the first weight includes a first weight corresponding to the read / write rate and a second weight corresponding to the error rate; the sum of the first weight and the second weight is 1. The first performance evaluation value is obtained by performing a weighted operation on the first reference performance evaluation value, the second reference performance evaluation value, and the first weight.
5. The testing method for a memory chip as described in any one of claims 1-4, characterized in that, The memory chip under test includes a temperature sensor, and the testing method for the memory chip further includes: The temperature sensor is used to obtain the first temperature value of the memory chip under test at the start time of the N tests. The temperature sensor is used to obtain the second temperature value of the memory chip under test at the end of the N tests. Determine the temperature difference between the first temperature value and the second temperature value; When the temperature difference is within the set temperature range, the step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment is executed. If the temperature difference is not within the set temperature range, the test of the memory chip under test is determined to have failed.
6. A testing apparatus for a memory chip, characterized in that, The testing device for the memory chip includes: an acquisition module, a first determination module, a testing module, and a second determination module, wherein, The acquisition module is used to acquire the first test mode and the first test environment for the memory chip under test; The first determining module is used to determine a first test case based on the first test mode and the first test environment; The testing module is used to configure the memory chip under test based on the first testing mode and the first testing environment, and to perform N tests on the memory chip under test according to the first test case to obtain N test results. Each test result includes the average read / write speed and the average error rate; N is an integer greater than 1. The second determining module is configured to determine a first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment; and to determine that the memory chip under test has passed the test when the first performance evaluation value is greater than a set value; and to determine that the memory chip under test has failed the test when the first performance evaluation value is less than or equal to the set value.
7. The testing apparatus for a memory chip as described in claim 6, characterized in that, The second determining module, when performing the step of determining the first performance evaluation value of the memory chip under test based on the N test results, the first test mode, and the first test environment, executes the following steps: Based on the first test mode and the first test environment, obtain the reference read / write rate and reference error rate; Based on the N test results, the reference read / write rate, and the reference error rate, N sets of comparison results are determined. Each comparison result includes a read / write rate difference and an error rate difference. The read / write rate difference is the difference between the average read / write rate and the reference read / write rate, and the error rate difference is the difference between the average error rate and the reference error rate. The first performance evaluation value is determined based on the N sets of comparison results.
8. The testing apparatus for a memory chip as described in claim 7, characterized in that, The second determining module performs the step of determining the first performance evaluation value based on the N sets of comparison results according to the following steps: Obtain the test times for the N tests to obtain N test times; Based on the N sets of comparison results and the N test times, determine the linear curves for the changes in read / write rate difference and error rate difference; Obtain the slope of the straight line showing the change in the read / write rate difference to obtain the first slope; Obtain the slope of the straight line showing the change in the error rate difference to obtain the second slope; The first performance evaluation value is determined based on the first slope and the second slope.
9. A computer device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the testing method for the memory chip as described in any one of claims 1-5.
10. A computer-readable storage medium, characterized in that, It stores a computer program, wherein the computer program causes a computer device to perform a test method for the memory chip as described in any one of claims 1-5.