Multilayer ceramic capacitor and method of manufacturing same

Abstract

Disclosed are a multilayer ceramic capacitor and a method of manufacturing the same, the multilayer ceramic capacitor including: a capacitor body including a plurality of dielectric layers and a plurality of inner electrode layers, the plurality of inner electrode layers stacked such that the dielectric layer is interposed between the plurality of inner electrode layers; and an outer electrode disposed on an outer surface of the capacitor body, in which the capacitor body includes an active region in which the dielectric layers and the inner electrode layers are alternately disposed, and a cover region in which the dielectric layers are disposed on an upper surface and a lower surface of the active region in a stacking direction, and an outer electrode including an inner layer disposed on a surface of the active area and connected to the inner electrode layer, and an outer layer covering the inner layer, the inner layer including a conductive metal and glass, and in a cross-section of the inner layer, the outer layer is disposed on a surface of the active area and connected to the inner electrode layer. The area occupied by the glass is greater than about 0% of the total area of the inner layer and less than or equal to about 6% of the total area of the inner layer.

Description

Technical Field

[0001] This disclosure relates to a multilayer ceramic capacitor and a method for manufacturing the same. Background Technology

[0002] Ceramic electronic components include capacitors, inductors, piezoelectric elements, varistors, and thermistors. Among ceramic electronic components, multilayer ceramic capacitors (MLCCs) are used in various electronic devices due to their advantages such as small size, high capacitance, and ease of installation.

[0003] For example, a multilayer ceramic capacitor can be a chip capacitor mounted on a printed circuit board of various electronic products (such as imaging devices (e.g., liquid crystal displays (LCDs), plasma display panels (PDPs)), computers, personal portable terminals (e.g., smartphones)) for charging or discharging from them.

[0004] Recently, with the miniaturization and thinning of MLCCs, not only has the miniaturization of the metal particles used in the electrodes become important, but also, due to the high reliability requirements of automotive MLCCs, improving the contact between the inner and outer electrodes has become crucial.

[0005] However, as the metal particles used become smaller, the cost of each particle increases due to the greater difficulty in synthesis, and there is a side effect that causes a relative increase in the content of other polymers (such as dispersants and binders) required for the dispersion and bonding of the paste. With the increase in the content of other polymers, the metal solids content becomes relatively low, altering viscosity and flow properties and affecting printability. Therefore, metal electrodes using pastes with dispersed metal particles have these limitations. Summary of the Invention

[0006] Some embodiments of this disclosure provide a multilayer ceramic capacitor with improved connectivity between its inner electrode layer and outer electrode, thereby exhibiting excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability.

[0007] Another embodiment of this disclosure provides a method for manufacturing a multilayer ceramic capacitor.

[0008] Some embodiments of this disclosure provide a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: a capacitor body including a plurality of dielectric layers and a plurality of inner electrode layers, the plurality of inner electrode layers being stacked such that the dielectric layer is located between the plurality of inner electrode layers; and an outer electrode disposed on the outer surface of the capacitor body, wherein the capacitor body includes an effective region in which the dielectric layers and the inner electrode layers are alternately disposed, and a covering region in which the dielectric layers are disposed on an upper surface and a lower surface of the effective region along a stacking direction, the outer electrode including an inner layer and an outer layer covering the inner layer, the inner layer being disposed on the surface of the effective region and connected to the inner electrode layers, the inner layer including a conductive metal and glass, and in the cross-section of the inner layer, the area occupied by the glass is greater than about 0% and less than or equal to about 6% of the total area of ​​the inner layer.

[0009] Based on the total amount of the inner layer, the glass of the inner layer may be included in an amount greater than about 0% by weight and less than or equal to about 5% by weight.

[0010] Based on the total amount of the inner layer, the conductive metal of the inner layer may be included in an amount greater than about 95% by weight and less than about 100% by weight.

[0011] The conductive metal of the inner layer may include at least one selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof.

[0012] The conductive metal in the inner layer may include copper (Cu) and nickel (Ni).

[0013] The inner glass may include at least one selected from the group consisting of alumina (Al2O3), silicon dioxide (SiO2), lithium oxide (Li2O), sodium oxide (Na2O), iron(III) oxide (Fe2O3), zinc oxide (ZnO), barium oxide (BaO), calcium oxide (CaO), boron trioxide (B2O3), and tin(IV) oxide (SnO2).

[0014] The inner layer may extend into the interior of the capacitor body and connect to the inner electrode layer.

[0015] A Cu-Ni alloy may be present at the interface between the inner layer of the outer electrode and the inner electrode layer.

[0016] The glass of the inner layer may be present on the surface of the dielectric layer in the effective region.

[0017] The thickness of the inner layer can be from about 1 μm to about 5 μm.

[0018] The grain size of the conductive metal in the inner layer can be from about 0.5 μm to about 1 μm.

[0019] The outer layer may include a conductive metal and glass, and the conductive metal of the outer layer may be the same as or different from the conductive metal of the inner layer, and the glass of the outer layer may be the same as or different from the glass of the inner layer.

[0020] Based on the total amount of the outer layer, the outer layer may include about 70% to about 90% by weight of conductive metal and about 10% to about 30% by weight of glass.

[0021] The inner electrode layer may include nickel (Ni) and copper (Cu).

[0022] Another embodiment provides a method for manufacturing a multilayer ceramic capacitor, the method comprising: coating a capacitor body with metal-organic decomposition (MOD) ink and reducing it to form a metal particle film, the capacitor body including a plurality of dielectric layers and a plurality of internal electrode layers, the plurality of internal electrode layers being stacked such that the dielectric layer is interposed between the plurality of internal electrode layers; coating a paste comprising a composition of conductive metal and glass onto the surface of the capacitor body on which the metal particle film is formed; and firing the paste to form an external electrode, the external electrode including an inner layer formed of the metal particle film and an outer layer covering the inner layer and formed of the paste, wherein the inner layer includes conductive metal and glass, and in a cross-section of the inner layer, the area occupied by the glass is greater than about 0% and less than or equal to about 6% of the total area of ​​the inner layer.

[0023] The metal-organic decomposition (MOD) ink may include metal ligand materials, amine compounds, binders, antioxidants, and solvents.

[0024] The metal-organic decomposition (MOD) ink can be coated with a thickness of about 50 μm to about 400 μm.

[0025] Reduction can be performed at temperatures ranging from approximately 170°C to approximately 300°C for approximately 30 minutes to approximately 3 hours.

[0026] The metal particle film may include metal nanoparticles having a particle size of about 10 nm to about 50 nm.

[0027] Based on the total amount of the paste, the glass composition may be included in an amount of about 10% to about 30% by weight.

[0028] With improved connectivity between the inner electrode layer and the outer electrode, multilayer ceramic capacitors according to some embodiments can exhibit excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability. Attached Figure Description

[0029] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment.

[0030] Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'.

[0031] Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II'.

[0032] Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure in the capacitor body.

[0033] Figure 5 This is a schematic diagram showing the external electrodes of a multilayer ceramic capacitor according to an embodiment.

[0034] Figure 6A and Figure 6B The images are low-magnification scanning electron microscope (SEM) analysis images of the external electrodes of the multilayer ceramic capacitors of Comparative Example 1 and Example 1, respectively.

[0035] Figure 7A and Figure 7B The images are high-magnification scanning electron microscope (SEM) analysis images of the external electrodes of the multilayer ceramic capacitors of Comparative Example 1 and Example 1, respectively.

[0036] Figure 8 The images are scanning electron microscope (SEM) analysis images of the external electrodes of the multilayer ceramic capacitor according to Example 1.

[0037] Figure 9A and Figure 9B The images shown are electron probe microanalysis (EPMA) images of Cu diffusion on the external electrodes of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1, respectively.

[0038] Figure 10A and Figure 10B The images shown are electron probe microanalysis (EPMA) images of the outer electrodes of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1, respectively, illustrating Ni diffusion.

[0039] Figure 11A and Figure 11B The images shown are electron probe microanalysis (EPMA) images of the external electrodes of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1, respectively, showing the glass distribution.

[0040] Figure 12The images are electron backscatter diffraction (EBSD) images of the external electrodes of the multilayer ceramic capacitors of Comparative Example 1 and Example 1.

[0041] Figure 13 This is a graph showing the capacitance characteristics of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1.

[0042] Figure 14 This is a graph showing the equivalent series resistance (ESR) of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1.

[0043] Figure 15 This is a graph showing the DC resistance (Rdc) of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1.

[0044] Figure 16A This is a graph showing the moisture resistance reliability of the multilayer ceramic capacitor according to Comparative Example 1.

[0045] Figure 16B This is a graph showing the moisture resistance reliability of the multilayer ceramic capacitor according to Example 1.

[0046] Figure 16C The photograph shows the defects occurring in the multilayer ceramic capacitors according to Comparative Example 1 and Example 1. Detailed Implementation

[0047] The present disclosure will now be described in detail with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. The drawings and description are to be considered illustrative rather than restrictive in nature. Throughout the specification, the same reference numerals denote the same elements. In the drawings, some components are exaggerated, omitted, or shown schematically, and the dimensions of each component do not perfectly reflect their actual dimensions.

[0048] The accompanying drawings are intended only to facilitate understanding of the embodiments disclosed in this specification, and it should be understood that the technical concepts disclosed herein are not limited to the drawings, and include all modifications, equivalents or alternatives within the scope of the technical concepts disclosed herein.

[0049] Although terms such as "first" and "second" are used to describe various components, the components are not limited by these terms. These terms are only used to distinguish one component from another.

[0050] Furthermore, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. Additionally, when an element is referred to as being "on" or "above" a reference element, it may be positioned above or below the reference element, and it is not necessarily referred to as being positioned "on" or "above" in a direction opposite to gravity.

[0051] Throughout this specification, the terms “comprising” or “having” are intended to indicate the presence of the stated features, quantities, steps, operations, components, parts, or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts, and / or combinations thereof. Therefore, unless expressly stated otherwise, the words “comprising” and variations such as “including” or “containing” will be understood to imply the inclusion of the stated elements but not the exclusion of any other elements.

[0052] Furthermore, throughout the instruction manual, the phrase "in plan view" or "in plane / in middle" indicates the target portion as viewed from the top, while the phrase "in section view" or "in section / in middle" indicates the section formed by vertically cutting the target portion as viewed from the side.

[0053] Throughout the specification, the term "connection" can mean not only a direct connection between two or more constituent components, but also an indirect connection between two or more constituent components through another constituent component, an electrical connection and a physical connection between two or more constituent components, or a connection between two or more constituent components that are referred to by different names due to their location or function but are actually integrated.

[0054] Furthermore, throughout the specification, when it says "including...as a main component," it means that among at least one component present in the region, one component has the highest content based on the total amount of all components.

[0055] In the following text, reference will be made to Figures 1 to 4 A multilayer ceramic capacitor according to an embodiment is described.

[0056] Figure 1 This is a perspective view showing a multilayer ceramic capacitor according to an embodiment. Figure 2 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken by line I-I'. Figure 3 It is along Figure 1 A cross-sectional view of a multilayer ceramic capacitor taken from line II-II', and Figure 4 It is shown Figure 1 An exploded perspective view of the stacked structure in the capacitor body.

[0057] Figures 1 to 4 The L-axis, W-axis, and T-axis directions shown represent the length, width, and thickness directions of the capacitor body 110, respectively. Here, the thickness direction (T-axis) can be perpendicular to the wide surface (main surface) of the sheet assembly, and can be used, for example, as the same concept as the stacking direction of the stacked dielectric layers 111. The length direction (L-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be substantially perpendicular to the thickness direction (T-axis). For example, the length direction (L-axis) can be the direction in which the first external electrode 131 and the second external electrode 132 are opposite each other. The width direction (W-axis) can be parallel to the wide surface (main surface) of the sheet assembly and can be substantially perpendicular to both the thickness direction (T-axis) and the length direction (L-axis). The dimension of the sheet assembly in the length direction (L-axis) can be longer than the dimension in the width direction (W-axis).

[0058] Reference Figures 1 to 4 According to an embodiment, the multilayer ceramic capacitor 100 includes a capacitor body 110 and external electrodes 131 and 132 disposed on the outer surface of the capacitor body 110. The external electrodes 131 and 132 may include a first external electrode 131 and a second external electrode 132 disposed at opposite ends of the capacitor body 110 in the longitudinal direction (L-axis direction).

[0059] For example, the capacitor body 110 may have a generally hexahedral shape.

[0060] For ease of description of the embodiments, two surfaces that are opposite to each other in the thickness direction (T-axis direction) of the capacitor body 110 are referred to as the first surface and the second surface, two surfaces that are connected to the first surface and the second surface and are opposite to each other in the length direction (L-axis direction) are referred to as the third surface and the fourth surface, and two surfaces that are connected to the first surface and the second surface, and connected to the third surface and the fourth surface and are opposite to each other in the width direction (W-axis direction) are referred to as the fifth surface and the sixth surface.

[0061] As an example, the first surface, which serves as the lower surface, can be a mounting surface. Alternatively, the first to sixth surfaces can be flat, but the embodiment is not limited to this. For example, the first to sixth surfaces can be curved surfaces with a convex central portion, and the edges serving as the boundaries of each surface can be rounded.

[0062] The shape and size of the capacitor body 110 and the number of stacked dielectric layers 111 are not limited to the shape and size and the number of stacked layers shown in the accompanying drawings of the embodiment.

[0063] The capacitor body 110 includes a plurality of dielectric layers 111 and inner electrode layers 121 and 122. Specifically, the capacitor body 110 includes: a plurality of dielectric layers 111; and a first inner electrode layer 121 and a second inner electrode layer 122, which are alternately arranged in the thickness direction (T-axis direction) and the dielectric layers 111 are located between them.

[0064] At this point, the adjacent dielectric layers 111 of the capacitor body 110 can be integrated to such an extent that the boundaries between them are difficult to distinguish without the use of a scanning electron microscope (SEM).

[0065] The capacitor body 110 may include an effective area A and a coverage area B.

[0066] The effective region A is a region in which dielectric layers 111 and inner electrode layers 121 and 122 are alternately disposed, which can contribute to the capacitance of the multilayer ceramic capacitor 100. Specifically, the effective region A can be the region where the first inner electrode layer 121 and / or the second inner electrode layer 122 stacked along the thickness direction (T-axis direction) overlap.

[0067] Coverage region B is the edge portion in the thickness direction, and can be disposed on the upper and lower surfaces of effective region A in the thickness direction (T-axis direction). Coverage region B can be a single dielectric layer 111 or two or more dielectric layers 111 stacked on the upper and lower surfaces of effective region A respectively.

[0068] In addition, the capacitor body 110 may also include a side edge region.

[0069] The side edge region is an edge portion in the width direction, and can be disposed on opposite surfaces of the effective region A in the width direction (W-axis direction), i.e., respectively disposed on the fifth and sixth surfaces. The side edge region can be formed by stacking a dielectric green sheet on which a conductive paste layer for an internal electrode is partially coated, and then firing it. Therefore, the side edge region can be the uncoated side edge portion of the dielectric green sheet. The method of forming the side edge region is not limited to this.

[0070] Coverage area B and side edge areas can be used to prevent damage to inner electrode layers 121 and 122 due to physical stress and / or chemical stress.

[0071] A detailed description of dielectric layer 111 and inner electrode layers 121 and 122 will be provided later.

[0072] external electrode According to some embodiments, the outer electrodes 131 and 132 may be provided with voltages of different polarities and may be electrically connected to the exposed portions of the first inner electrode layer 121 and the second inner electrode layer 122, respectively.

[0073] According to the above structure, when a predetermined voltage is applied to the first external electrode 131 and the second external electrode 132, charge can accumulate between the first inner electrode layer 121 and the second inner electrode layer 122 that face each other. At this time, the capacitance of the multilayer ceramic capacitor 100 is proportional to the overlap area of ​​the first inner electrode layer 121 and the second inner electrode layer 122 that overlap each other along the T-axis direction in the effective region A.

[0074] The first external electrode 131 may include a first connecting portion and a first strip portion, and the second external electrode 132 may include a second connecting portion and a second strip portion. The first connecting portion is disposed on the third surface of the capacitor body 110 and connected to the first inner electrode layer 121. The second connecting portion is disposed on the fourth surface of the capacitor body 110 and connected to the second inner electrode layer 122. The first strip portion is disposed on the edge where the third surface of the capacitor body 110 intersects with the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. The second strip portion is disposed on the edge where the fourth surface of the capacitor body 110 intersects with the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110.

[0075] As another example, the first strip may extend from the first connecting portion to a portion of the first surface and a portion of the second surface of the capacitor body 110, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110; the second strip may extend from the second connecting portion to a portion of the first surface and a portion of the second surface of the capacitor body 110, and / or a portion of the fifth surface and a portion of the sixth surface of the capacitor body 110. The first and second strips can be used to improve the adhesive strength between the first external electrode 131 and the second external electrode 132 and the capacitor body 110.

[0076] Figure 5 This is a schematic diagram showing the external electrodes of a multilayer ceramic capacitor according to some embodiments of the present disclosure.

[0077] Reference Figure 2 and Figure 5 According to some embodiments, the external electrodes 131 and 132 may each include inner layers 10 and 30 and outer layers 20 and 40. The inner layers 10 and 30 are disposed on the surface of the effective region A of the capacitor body 110 and connected to the inner electrode layers 121 and 122, and the outer layers 20 and 40 respectively cover the inner layers 10 and 30. Specifically, the first external electrode 131 may include a first inner layer 10 connected to the first inner electrode layer 121 and a first outer layer 20 covering the first inner layer 10. In addition, the second external electrode 132 may include a second inner layer 30 connected to the second inner electrode layer 122 and a second outer layer 40 covering the second inner layer 30.

[0078] Inner layers 10 and 30 may include conductive metal and glass G.

[0079] Based on the total amount of inner layers 10 and 30, glass G can be included in an amount greater than about 0 wt% and less than or equal to about 5 wt% (e.g., about 0.01 wt% to about 5 wt%, about 0.1 wt% to about 4.5 wt%, or about 1 wt% to about 4 wt%). Furthermore, based on the total amount of inner layers 10 and 30, conductive metal can be included in an amount greater than about 95 wt% and less than about 100 wt% (e.g., about 95 wt% to about 99.99 wt%, about 95.5 wt% to about 99.9 wt%, or about 96 wt% to about 99 wt%). When the inner layers made of conductive metal and glass have the above composition, the connection between the inner electrode layer and the outer electrode is improved as the contact between the inner electrode layer and the outer electrode is strengthened. Thus, a multilayer ceramic capacitor with excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability can be obtained. Additionally, a small amount of glass can partially supplement the interfacial bonding strength between the outer electrode and the dielectric layer.

[0080] According to some embodiments, in the cross-sections of the inner layers 10 and 30, based on the total area of ​​the inner layers 10 and 30, the ratio of the area occupied by glass in the inner layers 10 and 30 can be greater than about 0% and less than or equal to about 6% (e.g., about 0.1% to about 5.5%, about 0.5% to about 5.0%, or about 1% to about 4.5%). When the ratio of the area occupied by glass in the inner layers is within the above range, the connectivity between the inner electrode layer and the outer electrode can be improved, thereby ensuring that the multilayer ceramic capacitor has excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability.

[0081] Specifically, the inner layers 10 and 30 can be defined as: regions in a direction perpendicular to the stacking direction (i.e., in the length (L-axis) direction of the multilayer ceramic capacitor), extending from the interface between the outer electrodes 131 and 132 and the inner electrode layers 121 and 122 toward the outer electrodes 131 and 132 to a depth of about 1 μm to about 5 μm (e.g., a depth of about 2 μm to about 4 μm from the interface).

[0082] The area of ​​the glass within the inner layers 10 and 30 can be measured as follows: A multilayer ceramic capacitor 100 is mounted on tape with its L-axis and T-axis surfaces (LT surfaces) facing upwards, placed in an epoxy resin mixture, and cured. Then, the LT surface of the capacitor body 110 is ground to a point halfway down the W-axis direction, thereby obtaining a cross-sectional sample with the LT surface, allowing observation of the outer electrode. Next, one side of the obtained cross-sectional sample can be measured using a scanning electron microscope (SEM) to reveal the capacitor body and outer electrode. For example, the SEM can be performed at an accelerating voltage of 20 kV and a magnification of 10 k. In the SEM image of the obtained cross-sectional sample, a region designated as the inner layer within the outer electrode can be specified, specifically, in a direction perpendicular to the stacking direction, from the interface between the outer and inner electrode layers towards the outer electrode to a depth of approximately 1 μm to approximately 5 μm from the interface (e.g., a depth of approximately 2 μm to approximately 4 μm from the interface). The area within the inner layer occupied by glass can then be obtained. Glass does not exhibit electrical conductivity, so it appears darker in SEM images compared to metal, allowing for the determination of its area ratio relative to the entire inner layer.

[0083] Typically, the first approach to ensuring connectivity between the inner electrode layer and the outer electrode is to increase the exposure of the inner electrode layer between the dielectric layers, allowing the outer electrode to connect to the exposed inner electrode layer. However, when using etching to increase the exposure of the inner electrode layer, damage to the entire wafer may occur in addition to the electrode portion, affecting electrical properties (such as reliability degradation).

[0084] As a second method, a direct plating electrode formation method is being introduced, which involves directly connecting the outer electrode to the inner electrode layer. However, the direct plating method is not suitable for coating a large number of sheets at once or maintaining consistent quality. Furthermore, while the energy applied directly to the sheet is low and therefore does not cause physical damage, chemical reactions or damage caused by the plating solution may occur as the plating electrode formation process continues. Therefore, it has the disadvantage of only being applicable to certain models.

[0085] Additionally, the outer electrode is typically formed by coating a paste containing metal particles and then performing a heat treatment. Due to the reduced thickness caused by the thinning of the inner electrode layer, the metal particles may become larger than the thickness of the inner electrode layer. This can lead to a deterioration in the connectivity between the inner and outer electrodes, resulting in side effects such as reduced capacitance and increased equivalent series resistance (ESR).

[0086] Furthermore, when forming the external electrode by direct plating, a metal layer such as Cu or Ni or a conductive polymer layer should be applied to the internal electrode layer for plating. Plating can be performed on the applied conductive polymer layer, or it can be performed from a metal layer that acts as a support layer formed on the strip.

[0087] According to some embodiments, since the outer electrode has an inner layer comprising a conductive metal (as the main component) and a small amount of glass, it can not only be distinguished from layers formed by conventional plating methods, but also the connectivity between the inner electrode layer and the outer electrode can be improved due to the increase in, for example, Ni-Cu alloy.

[0088] Specifically, according to some embodiments, the inner layers 10 and 30 can be formed by coating the surface of the capacitor body 110 with a metal-organic decomposition (MOD) ink comprising a metal ligand material. This can be a method in which the metal ligand material generates fine metal particles at the ends of the inner electrode layer through a reduction process. Since the metal-organic decomposition (MOD) ink does not contain a dispersant for dispersing the metal particles, the physical distance from the inner electrode layer and the gap between the metal particles can be significantly reduced. This is because, for example, with the increase of Ni-Cu alloy, in addition to the effect of reducing the distance between metal particles, the metal particles are also formed at the ends of the inner electrode layer with a recessed structure, which can improve the contact between the inner electrode layer and the outer electrode during the final electrode sintering process.

[0089] Furthermore, according to some embodiments, compared to conventional plating, inner layers 10 and 30 can be formed without a support layer, and in the final product, inner layers 10 and 30 can be formed only on the effective area A of the capacitor body 110. Additionally, in the case of conventional plating, no materials such as glass are found other than metal particles; however, according to some embodiments of this disclosure, the inner layer disposed between the outer layer of the external electrode and the capacitor body may include a small amount of glass.

[0090] According to some embodiments, the external electrodes 131 and 132 can be formed by coating a metal-organic decomposition (MOD) ink comprising a metal ligand material onto the surface of a capacitor body 110 and reducing it to form a metal particle film, then coating a paste comprising a conductive metal and a glass composition (for forming the outer layer) onto the surface of the capacitor body 110 where the metal particle film is formed, and then firing. The external electrodes 131 and 132 thus formed include inner layers 10 and 30 formed of the metal particle film and outer layers 20 and 40 formed of the paste. The conductive metal included in the inner layers 10 and 30 may be derived from the metal ligand material of the MOD ink, and the glass included in the inner layers 10 and 30 may be derived from the glass composition of the paste. That is, since the process of forming the inner layers 10 and 30 is not a growth method like a plating method, the glass composition included in the coated paste for forming the outer layer can move and become the glass included in the inner layers 10 and 30.

[0091] The conductive metal included in the inner layers 10 and 30 may include one or more selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof, and may include, for example, copper (Cu).

[0092] For example, inner layers 10 and 30 may include copper (Cu) and nickel (Ni). In this case, as the contact between the outer electrode and the inner electrode layer is strengthened, the nickel (Ni) of inner layers 10 and 30 may diffuse from the nickel (Ni) of inner electrode layers 121 and 122.

[0093] The glass of the inner layers 10 and 30 may include, but is not limited to, at least one selected from the group consisting of alumina (Al2O3), silicon dioxide (SiO2), lithium oxide (Li2O), sodium oxide (Na2O), iron(III) oxide (Fe2O3), zinc oxide (ZnO), barium oxide (BaO), calcium oxide (CaO), boron trioxide (B2O3), and tin(IV) oxide (SnO2).

[0094] Inner layers 10 and 30 may have a structure extending into the interior of capacitor body 110 and connected to inner electrode layers 121 and 122. In other words, at least some of inner electrode layers 121 and 122 may have a structure recessed relative to the surface of capacitor body 110. When the above structure is present, the Cu-Ni alloy can be increased at the interface between the inner layer of the outer electrode and the inner electrode layer, thereby strengthening the contact between the inner electrode layer and the outer electrode.

[0095] The interface between the inner layers 10 and 30 of the outer electrodes 131 and 132 and the inner electrode layers 121 and 122 may include a Cu-Ni alloy. Increasing the amount of Cu-Ni alloy at the interface between the inner layers of the outer electrodes and the inner electrode layers can improve the connectivity between the inner electrode layers and the outer electrodes.

[0096] The glass in the inner layers 10 and 30 may be present on the surface of the dielectric layer 111 within the effective region A of the capacitor body 110, and for example, may be present only on the surface of the dielectric layer 111. In other words, the glass in the inner layers 10 and 30 may be present at the interface between the dielectric layer 111 and the outer electrodes 131 and 132. Furthermore, the glass may be thinly dispersed on the surface of the dielectric layer 111 without agglomeration or clustering. By thinly dispersing the glass only on the surface of the dielectric layer 111, the contact between the inner electrode layer and the outer electrode can be strengthened.

[0097] The structure, composition, and content of the external electrodes 131 and 132 according to some embodiments can be confirmed by scanning electron microscopy (SEM) analysis and electron probe microanalysis (EPMA).

[0098] Specifically, a multilayer ceramic capacitor 100 is mounted on an adhesive tape with its L-axis and T-axis surfaces (LT surfaces) facing upwards, placed in an epoxy resin mixture, and cured. Then, the LT surface of the capacitor body 110 is ground to half its length along the W-axis, thus obtaining a cross-sectional sample with the LT surface, allowing observation of the external electrodes. Next, one side of the obtained cross-sectional sample can be measured using a scanning electron microscope (SEM) to reveal the capacitor body and external electrodes. For example, the SEM can be performed at an accelerating voltage of 20 kV and a magnification of 10 k.

[0099] In addition, electron probe microanalysis (EPMA) can be performed on the cross-sectional samples obtained by the above method. For example, EPMA can identify the composition and content of the external electrode by measuring with an accelerating voltage of 20 kV and a magnification of 3 k.

[0100] According to some embodiments, since the outer electrodes 131 and 132 have inner layers 10 and 30 at the interface with the effective region A of the capacitor body 110, the connectivity between the outer electrodes and the inner electrode layers can be from about 90% to about 100%, for example, from about 91% to about 100% or from about 92% to about 100%. Because the connectivity between the outer electrodes and the inner electrode layers is within the above range, a multilayer ceramic capacitor with excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability can be obtained.

[0101] The connectivity between the outer and inner electrode layers can be obtained through SEM analysis. Specifically, in the SEM image of the cross-sectional sample obtained by the above method, when the bonding surfaces of the outer electrodes 131 and 132 with the capacitor body 110 are divided into three parts (i.e., divided into upper, central, and lower parts) in the stacking direction (i.e., the thickness direction (T-axis direction) of the multilayer ceramic capacitor), the connectivity is measured for each region and its average value is calculated. Here, the connectivity of each region can be obtained through Equation 1.

[0102] [Equation 1] Connectivity between outer and inner electrode layers (%) = (Number of inner electrode layers connected to the outer electrode / Total number of inner electrode layers) × 100% The thickness of each of the inner layers 10 and 30 can be from about 1 μm to about 5 μm, for example, from about 1 μm to about 4 μm, from about 1.1 μm to about 3 μm, from about 1.2 μm to about 2.9 μm, or from about 1.3 μm to about 2.8 μm. When the thickness of the inner layer is within the above range, the connectivity between the inner electrode layer and the outer electrode can be improved.

[0103] The thickness of each of the inner layers 10 and 30 can be obtained through SEM analysis. Specifically, in the SEM image of the cross-sectional sample obtained by the above method, the thickness of the inner layers 10 and 30, which are located between the effective region A of the capacitor body 110 and the outer layers 20 and 40 of the outer electrodes 131 and 132, can be measured. The center point of the inner layers 10 and 30 in the thickness direction (T-axis direction) of the multilayer ceramic capacitor 100 is used as a reference point, and the arithmetic mean of the thickness of the inner layers 10 and 30 at 10 points spaced at predetermined intervals from the reference point can be obtained. The interval between the 10 points can be adjusted according to the scale of the SEM image, and for example, it can be from about 1 μm to about 100 μm, from about 1 μm to about 50 μm, or from about 1 μm to about 10 μm. At this time, all 10 points should be located within the inner layers 10 and 30, and if not all 10 points are located within the inner layers 10 and 30, the position of the reference point can be changed, or the interval between the 10 points can be adjusted.

[0104] The inner layers 10 and 30 may include grains. That is, the conductive metal included in the inner layers 10 and 30 may be in the form of grains. The grain size of the conductive metal may be from about 0.5 μm to about 1 μm, for example from about 0.55 μm to about 0.95 μm or from about 0.6 μm to about 0.9 μm.

[0105] The grain size of the conductive metal can be obtained through EBSD (electron backscatter diffraction) analysis. Specifically, the inner layers 10 and 30 of the outer electrodes 131 and 132 can be observed and measured by electron backscatter diffraction (EBSD) in the cross-sectional samples obtained by the above method. For example, EBSD can be performed with an accelerating voltage of 15 kV, a step size of 0.025 μm, a scan area of ​​16 μm × 4 μm, a grain boundary orientation difference of 10°, and a magnification of 3 k.

[0106] When straight lines of the same length are drawn from the obtained EBSD images, the grain size of the conductive metal can be calculated using Equation 2.

[0107] [Equation 2] Grain size (μm) = (Total length of all straight lines) / (Total number of intersections between the straight lines and the grains) The outer layers 20 and 40 may include conductive metal and glass. Here, the conductive metal of the outer layers 20 and 40 may be the same as or different from the conductive metal of the inner layers 10 and 30, and the glass of the outer layers 20 and 40 may be the same as or different from the glass of the inner layers 10 and 30.

[0108] Based on the total amount of outer layers 20 and 40, outer layers 20 and 40 may comprise about 70% to about 90% by weight of conductive metal and about 10% to about 30% by weight of glass, for example, about 75% to about 85% by weight of conductive metal and about 15% to about 25% by weight of glass. When the outer layers have the above composition, a multilayer ceramic capacitor with excellent capacitance characteristics, electrical characteristics, and moisture resistance reliability can be obtained.

[0109] The external electrodes 131 and 132 may also include a conductive resin layer disposed on the outer layers 20 and 40 to cover the aforementioned outer layers 20 and 40, and a plating layer configured to cover the conductive resin layer.

[0110] The conductive resin layer extends to the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110, and the length of the region (i.e., the strip portion) where the conductive resin layer extends and is disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110 may be longer than the length of the region (i.e., the strip portion) where the outer layers 20 and 40 extend and are disposed on the first and second surfaces and / or the fifth and sixth surfaces of the capacitor body 110. In other words, the conductive resin layer may be formed on the outer layers 20 and 40, and may be formed to completely cover the outer layers 20 and 40 (sintered metal layers).

[0111] The conductive resin layer may include resin and conductive metal.

[0112] The resin included in the conductive resin layer can be, but is not limited to, a material that has adhesive and shock-absorbing properties and can form a paste when mixed with conductive metal powder. For example, the resin may include phenolic resin, acrylic resin, silicone resin, epoxy resin, or polyimide resin.

[0113] The conductive metal included in the conductive resin layer is used for electrical connection to the inner electrode layers 121 and 122 or the inner layers 10 and 30 and the outer layers 20 and 40.

[0114] The conductive metal included in the conductive resin layer may have a spherical shape, a sheet shape, or a combination thereof. That is, the conductive metal may be formed only as a sheet shape, only as a spherical shape, or a mixture of sheet and spherical shapes.

[0115] Here, spherical shape may also include shapes that are not perfect spheres, for example, shapes whose length ratio of the major axis to the minor axis (major axis / minor axis) is less than or equal to about 1.45. Sheet shape refers to a flat and elongated shape, without particular limitation, for example, a length ratio of the major axis to the minor axis (major axis / minor axis) may be greater than or equal to about 1.95.

[0116] The first external electrode 131 and the second external electrode 132 may further include a plating layer disposed on the outer surface of the conductive resin layer.

[0117] The coating may include at least one selected from the group consisting of nickel (Ni), copper (Cu), tin (Sn), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. For example, the coating may be a nickel (Ni) coating or a tin (Sn) coating, which may be in the form of nickel (Ni) coatings and tin (Sn) coatings stacked sequentially, or in the form of tin (Sn) coatings, nickel (Ni) coatings, and tin (Sn) coatings stacked sequentially. Additionally, the coating may include multiple nickel (Ni) coatings and / or multiple tin (Sn) coatings. In some embodiments, the coating does not include copper (Cu).

[0118] The coating can improve the mountability, structural reliability, external durability, heat resistance and equivalent series resistance (ESR) of the multilayer ceramic capacitor 100 relative to the substrate.

[0119] Dielectric layer and inner electrode layer According to some embodiments, dielectric layer 111 may include a barium titanate-based compound comprising barium (Ba) and titanium (Ti) as main components. Barium titanate-based compounds are dielectric fundamental materials with high dielectric constants and contribute to the dielectric constant of the multilayer ceramic capacitor 100. For example, the barium titanate-based compound may include compounds selected from BaTiO3, Ba(TiO3)2, etc. ,At least one of the group consisting of Zr)O3, Ba(Ti,Sn)O3, (Ba,Ca)TiO3, (Ba,Ca)(Ti,Zr)O3, (Ba,Ca)(Ti,Sn)O3, (Ba,Sr)TiO3, (Ba,Sr)(Ti,Zr)O3 and (Ba,Sr)(Ti,Sn)O3.

[0120] The dielectric layer 111 may also include secondary components. These secondary components may include one or more selected from, for example, manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), and vanadium (V).

[0121] The average thickness (average dimension in the T-axis direction) of the dielectric layer 111 can be from about 0.1 μm to about 8.0 μm, for example, from about 0.1 μm to about 6.0 μm. When the average thickness of the dielectric layer 111 is within the above range, the reliability of the multilayer ceramic capacitor can be improved.

[0122] The average thickness of dielectric layer 111 can be measured by placing the multilayer ceramic capacitor 100 in an epoxy resin mixture, allowing it to cure, polishing it, then ion-milling it, and finally analyzing it using a scanning electron microscope (SEM). A scanning electron microscope, such as the Verios G4 from Thermo Fisher Scientific, can be used with measurement conditions of 10 kV and 0.2 nA, an analytical magnification of 100x, and the ability to measure at least one, three, five, or ten or more dielectric layers. In the SEM image of the measured cross-sectional sample, using the center point of dielectric layer 111 in the length direction (L-axis direction) or width direction (W-axis direction) as a reference point, the arithmetic mean of the thickness of dielectric layer 111 at 10 points spaced at predetermined intervals from the reference point can be obtained. The spacing between the 10 points can be adjusted according to the scale of the SEM image, and for example, it can be from about 1 μm to about 100 μm, from about 1 μm to about 50 μm, or from about 1 μm to about 10 μm. In this case, all 10 points should be located within the dielectric layer 111, and if not all 10 points are located within the dielectric layer 111, the position of the reference point can be changed, or the spacing between the 10 points can be adjusted.

[0123] The inner electrode layers 121 and 122, namely the first inner electrode layer 121 and the second inner electrode layer 122, are electrodes with different polarities and are alternately arranged to face each other along the T-axis direction, with the dielectric layer 111 between them, and one end of the first inner electrode layer 121 and one end of the second inner electrode layer 122 can be exposed through the third surface and the fourth surface of the capacitor body 110, respectively.

[0124] The first inner electrode layer 121 and the second inner electrode layer 122 are electrically insulated from each other by a dielectric layer 111 disposed between them.

[0125] The ends of the first inner electrode layer 121 and the second inner electrode layer 122, which are alternately exposed through the third and fourth surfaces of the capacitor body 110, can be electrically connected to the first outer electrode 131 and the second outer electrode 132, respectively.

[0126] The inner electrode layers 121 and 122 may include conductive metals, and for example, may include metals such as Ni, Cu, Ag, Pd, Au or alloys thereof (e.g., Ag-Pd alloys).

[0127] For example, inner electrode layers 121 and 122 may include nickel (Ni) and copper (Cu). In this case, as the contact between the outer electrode and the inner electrode layers is strengthened, copper (Cu) can diffuse from the copper (Cu) in the inner layers 10 and 30 that form the outer electrodes 131 and 132.

[0128] Additionally, the inner electrode layers 121 and 122 may include dielectric particles having the same composition as the ceramic material included in the dielectric layer 111.

[0129] The inner electrode layers 121 and 122 can be formed using a conductive paste comprising a conductive metal. The conductive paste can be printed using either screen printing or gravure printing.

[0130] The average thickness of the inner electrode layers 121 and 122 can be from about 0.1 μm to about 2 μm. When the average thickness of the inner electrode layers 121 and 122 is within the above range, the reliability of the multilayer ceramic capacitor is improved.

[0131] The average thickness of the inner electrode layers 121 and 122 can be measured by scanning electron microscopy (SEM) analysis. Specifically, in the SEM image of the cross-sectional sample measured as described above, the center point of the inner electrode layers 121 and 122 in the length direction (L-axis direction) or width direction (W-axis direction) is used as a reference point, and the arithmetic mean of the thickness of the inner electrode layers 121 and 122 at 10 points spaced at predetermined intervals from the reference point can be obtained. The interval between the 10 points can be adjusted according to the scale of the SEM image, and for example, it can be about 1 μm to about 100 μm, about 1 μm to about 50 μm, or about 1 μm to about 10 μm. In this case, all 10 points should be located within the inner electrode layers 121 and 122, and if not all 10 points are located within the inner electrode layers 121 and 122, the position of the reference point can be changed, or the interval between the 10 points can be adjusted.

[0132] The capacitor body 110 can be formed by firing a stacked structure in which multiple dielectric layers 111 and internal electrode layers 121 and 122 are stacked.

[0133] In the following, a method for manufacturing a multilayer ceramic capacitor 100 according to an embodiment will be described.

[0134] Methods for manufacturing multilayer ceramic capacitors According to some embodiments, a multilayer ceramic capacitor 100 may be manufactured by the following steps: applying metal-organic decomposition (MOD) ink to the surface of a capacitor body 110 and reducing it to form a metal particle film; applying a paste comprising a composition of conductive metal and glass to the surface of the capacitor body on which the metal particle film is formed; and firing the paste to form external electrodes 131 and 132, the external electrodes 131 and 132 comprising inner layers 10 and 30 formed of the metal particle film and outer layers 20 and 40 formed of the paste and covering the inner layers.

[0135] The method of manufacturing the capacitor body 110 will be described below.

[0136] The capacitor body 110 can be manufactured by: using dielectric paste to manufacture dielectric green sheets and forming a conductive paste layer on the surface of the dielectric green sheets; manufacturing a dielectric green sheet stack by stacking dielectric green sheets on which the conductive paste layer is formed; and firing the dielectric green sheet stack.

[0137] Dielectric pastes can be prepared by mixing barium titanate-based main component powders and optional secondary component powders.

[0138] Since the barium titanate-based main component powder is the same as the barium titanate-based main component included in the dielectric layer, its description is omitted here.

[0139] The secondary component powder may include at least one selected from the group consisting of manganese (Mn), chromium (Cr), silicon (Si), aluminum (Al), magnesium (Mg), tin (Sn), antimony (Sb), germanium (Ge), gallium (Ga), indium (In), barium (Ba), lanthanum (La), yttrium (Y), actinium (Ac), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), hafnium (Hf), vanadium (V), and combinations thereof, but is not limited thereto. Based on 100 moles of barium titanate-based primary component powder, each of the secondary component powders may be included in an amount from about 0.01 moles to about 5 moles.

[0140] The secondary component powder can be used in the form of oxides or salt compounds of each metal, or in the form of a sol dispersed in an organic solvent.

[0141] In addition, dielectric pastes can be prepared by mixing additional additives such as dispersants, binders, plasticizers, lubricants, antistatic agents, and solvents.

[0142] A wet ball mill or a stirred mill can be used to mix the barium titanate-based main component powder and optional secondary component powder. When using zirconia balls in a wet ball mill, multiple zirconia balls with a diameter of about 0.1 mm to about 10 mm can be used for wet mixing for about 8 hours to about 48 hours or about 10 hours to about 24 hours.

[0143] The prepared dielectric paste forms a dielectric layer after firing.

[0144] As a method for forming the prepared dielectric paste into a sheet, a strip forming method such as a doctor blade method or a calendering roll method can be used. For example, a roller forming coating machine with a coating head discharge type can be used, and then the dielectric sheet can be obtained by drying the formed body.

[0145] To form a conductive paste layer that becomes the inner electrode layer after firing, the conductive paste can be prepared by mixing conductive powder (made of conductive metal or alloys thereof), a binder, and a solvent. Additionally, barium titanate powder can be mixed as a co-material if desired. The co-material can be used to suppress the sintering of the conductive powder during the firing process. In the step of manufacturing the dielectric green sheet, a dielectric paste can be prepared by mixing a barium titanate-based compound as the main component powder and optional secondary component powders.

[0146] The conductive powder may include nickel (Ni) or nickel (Ni) alloys.

[0147] Next, a dielectric green sheet stack is manufactured by stacking multiple layers of dielectric green sheets with internal electrode patterns formed thereon, and then pressing the multiple layers of dielectric green sheets in the stacking direction. In addition, dielectric green sheets without internal electrode patterns can be disposed on the upper and lower surfaces of the dielectric green sheet stack in the stacking direction.

[0148] Alternatively, the manufactured dielectric green sheet stack can be cut into predetermined sizes by cutting or the like.

[0149] Additionally, if necessary, the dielectric green sheet stack can be cured and dried to remove plasticizers, etc., and after curing and drying, the dielectric green sheet stack can be tumble polished using a horizontal centrifugal tumbler or similar device. In tumble polishing, the dielectric green sheet stack is placed in a tumbler container containing a dielectric and polishing fluid, and rotational motion or vibration is applied to the tumbler container, thus removing unwanted parts (such as burrs generated during cutting). After tumble polishing, the dielectric green sheet stack can be washed with a cleaning solution (such as water) and then dried.

[0150] Subsequently, the capacitor body is manufactured after adhesive removal and firing processes of the dielectric wafer stack.

[0151] The adhesive removal conditions can be appropriately adjusted according to the composition of the dielectric layer or internal electrode layer. For example, the heating rate during the adhesive removal process can be from about 5°C / hour to about 300°C / hour, the holding temperature can be from about 180°C to about 400°C, and the temperature holding time can be from about 0.5 hours to about 24 hours. Adhesive removal can be performed in an air atmosphere or a reducing atmosphere.

[0152] The firing conditions can be appropriately adjusted according to the main composition of the dielectric layer or the main composition of the inner electrode layer. For example, firing can be carried out at a temperature of about 1100°C to about 1400°C (e.g., at a temperature of about 1200°C to about 1350°C). Furthermore, firing can be carried out for about 0.5 to about 8 hours (e.g., about 1 to about 3 hours). Additionally, firing can be carried out in a reducing atmosphere (e.g., in a humidified mixture of nitrogen and hydrogen). When the inner electrode layer comprises nickel (Ni) or a nickel (Ni) alloy, the oxygen partial pressure in the firing atmosphere can be about 1.0 × 10⁻⁶. -14 MPa to approximately 1.0 × 10 -10 MPa.

[0153] After firing, annealing can be performed as needed. Annealing is a process that re-oxidizes the dielectric layer. If firing is carried out in a reducing atmosphere, annealing can be performed. The annealing conditions can also be adjusted appropriately according to the composition of the dielectric layer. For example, the annealing temperature can be from about 950°C to about 1150°C, the time can be greater than about 0 hours and less than or equal to about 20 hours, and the heating rate can be from about 50°C / hour to about 500°C / hour. The annealing atmosphere can be a humidified nitrogen (N2) atmosphere, and the oxygen partial pressure can be about 1.0 × 10⁻⁶. -9 MPa to approximately 1.0 × 10 -5 MPa.

[0154] In the adhesive removal process, firing process, or annealing process, a wetting agent (e.g., water) may be used to wet the nitrogen or mixed gas. In this case, the temperature of the wetting agent (e.g., water temperature) may be from about 5°C to about 75°C. The adhesive removal process, firing process, and annealing process may be performed sequentially or independently.

[0155] Optionally, surface treatments such as sandblasting, laser irradiation, and tumble polishing can be performed on the third and fourth surfaces of the prepared capacitor body 110. By performing this surface treatment, the ends of the first inner electrode and the second inner electrode can be exposed to the third and fourth surfaces, thereby improving the electrical connection between the first outer electrode and the first inner electrode layer, as well as the electrical connection between the second outer electrode and the second inner electrode layer, and facilitating the formation of alloy portions.

[0156] Next, the method for manufacturing the external electrodes 131 and 132 will be described.

[0157] The surface of the capacitor body 110 manufactured above is coated with metal-organic decomposition (MOD) ink and reduced to form a metal particle film.

[0158] Metal-organic decomposition (MOD) ink is applied to at least the third and fourth surfaces of the capacitor body 110, and optionally, it is also applied to portions of the first, second, fifth, and / or sixth surfaces on which the first and second external electrodes are formed.

[0159] Organometallic decomposition (MOD) inks may include metal ligand materials, amine compounds, binders, antioxidants, and solvents.

[0160] Metal ligand materials may include conductive metal formate formed by reacting a conductive metal precursor with formic acid.

[0161] The conductive metal precursor may be a precursor comprising a conductive metal, including at least one selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof. Examples of such conductive metal precursors may include metal oxides, metal hydroxides, metal nitrates, metal carbonates, metal sulfates, metal chlorides, metal acetates, or combinations thereof.

[0162] Based on the total amount of the metal-organic decomposition (MOD) ink, the metal ligand material may be included in an amount of about 20% to about 40% by weight.

[0163] Examples of amine compounds may include butylamine, hexylamine, octylamine, dibutylamine, triethylamine, diethylenetriamine, ethylenediamine, cyclohexylamine, aminomethylpropanol, 2-amino-2-methyl-1-propanol (AMP), or combinations thereof.

[0164] Based on the total amount of the organometallic decomposition (MOD) ink, amine compounds may be included in an amount of about 20% to about 60% by weight.

[0165] The adhesive may include at least one selected from the group consisting of thermoplastic resins, thermosetting resins, natural polymers, and combinations thereof. Examples of thermoplastic resins may include at least one selected from the group consisting of acrylic resins, cellulose resins, aliphatic or copolyester resins, vinyl resins, polyamide resins, polyurethane resins, polyether resins, urea resins, alkyd resins, silicone resins, fluoropolymers, and olefin resins. Acrylic resins may be, for example, polyacrylic acid, polyacrylates, etc. Examples of thermosetting resins may include at least one selected from the group consisting of epoxy resins, unsaturated or vinyl polyester resins, diallyl phthalate resins, phenolic resins, oxetane resins, oxazine resins, bismaleimide resins, modified silicone resins, and melamine resins. Examples of natural polymers may include at least one selected from the group consisting of ethylene-propylene rubber (EPR), styrene-butadiene rubber (SBR), starch, and gelatin.

[0166] Based on the total weight of the metal-organic decomposition (MOD) ink, the binder may be included in an amount from about 0.1% to about 5% by weight.

[0167] Antioxidants can include organic acids, such as oleic acid.

[0168] Based on the total weight of the metal-organic decomposition (MOD) ink, antioxidants may be included in an amount of about 0.1% to about 5% by weight.

[0169] Solvents may include at least one selected from the group consisting of: water; alcohol solvents, such as methanol, ethanol, isopropanol, 1-methoxypropanol, butanol, ethylhexanol, and terpineol; glycol solvents, such as ethylene glycol and glycerol; acetate solvents, such as ethyl acetate, butyl acetate, methoxypropyl acetate, carbitol acetate, and ethyl carbitol acetate; ether solvents, such as methyl cellosolve, butyl cellosolve, diethyl ether, tetrahydrofuran, and dioxane; ketone solvents, such as methyl ethyl ketone, acetone, dimethylformamide, and 1-methyl-2-pyrrolidone; hydrocarbon solvents, such as hexane, heptane, dodecane, paraffin oil, and mineral oil; aromatic solvents, such as benzene, toluene, and xylene; and halogen-substituted solvents, such as chloroform, dichloromethane, and carbon tetrachloride.

[0170] Based on the total amount of organometallic decomposition (MOD) ink, the remaining amount may include solvent.

[0171] The metal-organic decomposition (MOD) ink can be coated with a thickness of about 50 μm to about 400 μm, for example, a thickness of about 80 μm to about 350 μm. When the metal-organic decomposition (MOD) ink is coated within the above thickness range, an inner layer of appropriate thickness can be formed after firing, thereby enhancing the contact between the inner electrode layer and the outer electrode.

[0172] Reduction can be performed in a nitrogen atmosphere at a temperature of about 170°C to about 300°C (e.g., at a temperature of about 180°C to about 250°C) for about 30 minutes to about 3 hours (e.g., about 40 minutes to about 2 hours). When reduction is performed under conditions within the above range, the contact between the inner electrode layer and the outer electrode can be strengthened due to the formation of the inner layer.

[0173] When metal-organic decomposition (MOD) ink is coated onto the surface of capacitor body 110 and reduced, a metal particle film comprising very small and uniform metal nanoparticles can be formed. For example, the metal particle film may comprise metal nanoparticles with a size (particle size) of about 10 nm to about 50 nm, such as metal nanoparticles with a size of about 15 nm to about 45 nm.

[0174] Subsequently, the paste is applied to the surface of the capacitor body 110 on which a metal particle film is formed, and then it is fired.

[0175] The paste comprises a composition of conductive metals and glass.

[0176] Based on the total amount of the paste, the glass composition may be included in an amount of about 10% to about 30% by weight (e.g., about 12% to about 28% by weight or about 14% to about 26% by weight).

[0177] Since the description of the conductive metal and glass composition is the same as that of the conductive metal and glass described above, its description is omitted here.

[0178] Ointments may also include adhesives, solvents, dispersants, plasticizers, oxide powders, etc.

[0179] The adhesive may include, for example, ethyl cellulose, acrylic resin or butyral resin, and the solvent may include, for example, organic solvents (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, toluene, etc.) or aqueous solvents.

[0180] Methods for applying paste to the surface of capacitor body 110 may include: dipping, various printing methods (such as screen printing), coating methods using a dispenser, and spraying methods using a sprayer. The paste may be applied to at least the third and fourth surfaces of capacitor body 110, and optionally, to portions of the first, second, fifth, and / or sixth surfaces on which the first and second external electrodes are formed.

[0181] The firing can be carried out at a temperature of about 700°C to about 800°C (for example, about 720°C to about 740°C) for about 0.5 hours to about 3 hours (for example, about 1 hour to about 2 hours).

[0182] Optionally, a paste for forming a conductive resin layer is applied to the outer surface of the capacitor body 110 on which the outer layers 20 and 40 are formed on the inner layers 10 and 30, and then cured to form a conductive resin layer.

[0183] The paste used to form the conductive resin layer may include conductive metals and resins, and optionally, may include non-conductive fillers. Since the descriptions of the conductive metals and resins are the same as those described above, repeated descriptions will be omitted. Additionally, the paste used to form the conductive resin layer may optionally include binders, solvents, dispersants, plasticizers, oxide powders, etc. Binders may be, for example, ethyl cellulose, acrylic acid, butyral, etc., and solvents may be organic solvents (such as terpineol, butyl carbitol, ethanol, methyl ethyl ketone, acetone, and toluene) or aqueous solvents.

[0184] For example, the conductive resin layer can be formed by immersing the capacitor body 110 in a paste for forming the conductive resin layer and then curing it, or by printing the paste for forming the conductive resin layer onto the surface of the capacitor body 110 by screen printing or gravure printing and then curing it, or by applying the paste for forming the conductive resin layer onto the surface of the capacitor body 110 and then curing it.

[0185] Next, a plating layer can be formed on the outer surface of the conductive resin layer.

[0186] For example, a coating can be formed by plating methods (such as electroplating) or sputtering.

[0187] The embodiments are illustrated in more detail below with reference to examples. However, these examples are exemplary, and the scope of the claims is not limited thereto.

[0188] (Manufacturing of multilayer ceramic capacitors) Example 1 Dielectric green sheets are fabricated using BaTiO3 powder. A conductive paste layer including Ni is printed on the surface of the dielectric green sheets, and the dielectric green sheets with the conductive paste layer formed thereon are stacked and pressed to fabricate a dielectric green sheet stack. The capacitor body is fabricated by calcining the dielectric green sheet stack at a temperature of 400°C or lower in a nitrogen atmosphere, followed by firing at a firing temperature of less than or equal to 1300°C and under conditions of hydrogen (H2) concentration of less than or equal to 1.0%.

[0189] A metal-organic decomposition (MOD) ink comprising 30 wt% copper formate (Cu formate), 25 wt% octylamine, 25 wt% 2-amino-2-methyl-1-propanol (AMP), 0.5 wt% oleic acid, 0.5 wt% acrylic resin (SPB80), and the balance dihydroterpineol (DHT) was coated onto the surface of the capacitor body until a thickness of 100 μm was achieved. The coating was then reduced at 200 °C for 1 hour under a nitrogen atmosphere to form a Cu particle film composed of Cu nanoparticles with an average size (particle size) of less than or equal to 50 nm.

[0190] On the surface of the capacitor body where a Cu particle film is formed, a paste comprising 70 wt% Cu, 20 wt% glass composition, 5 wt% acrylic resin (SPB80), and the balance dihydroterpineol (DHT) is coated, and then fired at 730°C for 70 minutes to form the external electrode. Here, the glass composition comprises 9.1 mol% lithium oxide (Li₂O), 10 mol% sodium oxide (Na₂O), 1.5 mol% iron(III) oxide (Fe₂O₃), 6.3 mol% zinc oxide (ZnO), 21 mol% barium oxide (BaO), 11 mol% silicon dioxide (SiO₂), 8 mol% calcium oxide (CaO), 12 mol% aluminum oxide (Al₂O₃), 20.2 mol% boron trioxide (B₂O₃), and 1 mol% tin(IV) oxide (SnO₂).

[0191] Next, a coating is formed through processes such as plating, thereby manufacturing a multilayer ceramic capacitor.

[0192] Comparative Example 1 A paste comprising 70% by weight Cu, 20% by weight glass composition, 5% by weight acrylic resin (SPB80) and the balance dihydroterpineol (DHT) is coated on the surface of the capacitor body, and then fired at 730°C for 70 minutes to form the external electrode.

[0193] Next, a coating is formed through processes such as plating, thereby manufacturing a multilayer ceramic capacitor.

[0194] Evaluation 1: SEM Analysis The multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 were analyzed by scanning electron microscopy (SEM) using the following methods, and the results are shown in Figures 6 to 7. Figure 8 middle.

[0195] Each multilayer ceramic capacitor was mounted on adhesive tape with its L-axis and T-axis surfaces (LT surfaces) facing upwards, and then immersed in an epoxy resin mixture for curing. Next, the LT surface of the capacitor body was ground to half its length along the W-axis, obtaining a cross-sectional sample with the LT surface for observation of the external electrodes. Subsequently, one side of the obtained cross-sectional sample was measured using SEM to observe the capacitor body and external electrodes. SEM measurements were performed at an accelerating voltage of 20 kV and a magnification of 10 kV.

[0196] Figure 6A and Figure 6B The images are low-magnification scanning electron microscope (SEM) images of the external electrodes of the multilayer ceramic capacitors in Comparative Example 1 and Example 1, respectively. Figure 7A and Figure 7B The images were analyzed using high-magnification scanning electron microscopy (SEM) of the external electrodes of the multilayer ceramic capacitors in Comparative Example 1 and Example 1, respectively. Figure 8 The images are scanning electron microscope (SEM) analysis images of the external electrodes of the multilayer ceramic capacitor according to Example 1.

[0197] Reference Figures 6A to 7B Comparative Example 1 has an external electrode structure in which no inner layer is formed at the interface between the external electrode and the capacitor body; instead, a large amount of glass is dispersed at the interface between the external electrode and the inner electrode layer (see reference). Figure 6A and Figure 7A Furthermore, in the external electrode of Comparative Example 1, since glass with a size of 1 μm to 3 μm and Cu flakes with a size of 3 μm or larger are mixed together with Cu particles, the connection between the external electrode and the internal electrode layer deteriorates further as the thickness of the internal electrode layer decreases.

[0198] On the other hand, according to Example 1, the external electrode manufactured using the MOD method includes an inner layer and an outer layer. The inner layer is connected to an inner electrode layer on one side of the effective region of the capacitor body and is formed of a Cu particle film. The outer layer covers the inner layer, and the external electrode has the following structure: the inner layer is mainly made of Cu, but a small amount of glass is present only at the interface between the inner layer and the dielectric layer (i.e., on the dielectric layer) (see...). Figure 6B and Figure 7B In other words, compared to Comparative Example 1, in Example 1, since the inner layer with the structure described is formed on one side of the effective region, glass dispersion on the inner electrode layer is prevented, ensuring excellent connectivity between the outer electrode and the inner electrode layer.

[0199] Specifically, refer to Figure 8 In Example 1, in the cross-section of the inner layer, the area occupied by glass in the inner layer was measured to be 3.795% of the total area of ​​the inner layer. Here, the inner layer is defined as: the region extending from the interface between the inner electrode layer and the outer electrode on the surface of the effective region of the capacitor body toward the outer electrode to a depth of 3 μm from the interface, in a direction perpendicular to the stacking direction. Figure 8 The inner area is marked with a dashed line.

[0200] Furthermore, in the SEM images obtained above, the bonding surface between the external electrode and the capacitor body was divided into three parts (such as the upper, central, and lower parts) in the stacking direction (i.e., in the thickness (T-axis) direction of the multilayer ceramic capacitor) to measure the connectivity in each part, and then the average value was calculated. The connectivity in each part was obtained according to Equation 1.

[0201] [Equation 1] Connectivity between outer and inner electrode layers (%) = (Number of inner electrode layers connected to the outer electrode / Total number of inner electrode layers) × 100% As a result of the measurements, in Comparative Example 1, the connectivity between the outer electrode and the inner electrode layer was 40% or less, but in Example 1, the connectivity between the outer electrode and the inner electrode layer was 90% or greater.

[0202] Therefore, the outer electrode according to the embodiment has an inner layer in which Cu is the main component, but a small amount of glass is only thinly distributed on the surface of the dielectric layer in the effective region, thus exhibiting excellent connectivity between the outer electrode and the inner electrode layer.

[0203] Evaluation 2: EPMA Measurement Electron probe microanalysis (EPMA) was performed on the multilayer ceramic capacitors according to Example 1 and Comparative Example 1 using the method described below, and the results are presented in... Figures 9A to 11B middle.

[0204] Using the cross-sectional sample of Evaluation 1, EPMA was performed at an accelerating voltage of 20 kV and a magnification of 2 k to examine the diffusion of Cu and Ni elements by analyzing the peaks of Cu and Ni elements, and to examine the glass distribution by analyzing the peaks of O elements.

[0205] Figure 9A and Figure 9B , Figure 10A and Figure 10B as well as Figure 11A and Figure 11B These are electron probe microanalysis (EPMA) images of the external electrodes of the multilayer ceramic capacitors of Comparative Example 1 and Example 1, showing Cu diffusion, Ni diffusion, and glass distribution, respectively.

[0206] Reference Figure 9A and Figure 9B Because the portion of the external electrode in Comparative Example 1 that connects to the inner electrode layer is blocked, Cu did not diffuse into the inner electrode layer (see reference). Figure 9A However, in Example 1, because the outer electrode and the inner electrode layer are integrally connected, Cu diffuses uniformly into the inner electrode layer (see [reference]). Figure 9B ). Reference Figure 10A and Figure 10B In Comparative Example 1, Ni did not diffuse into the outer electrode, and the connection between the inner electrode layer and the outer electrode deteriorated (see reference). Figure 10A However, in Example 1, Ni diffuses throughout the entire external electrode (see reference). Figure 10B Therefore, since the outer electrode including the inner layer and the inner electrode layer according to the embodiment have excellent connectivity, Cu not only diffuses into the inner electrode layer, but Ni also diffuses uniformly into the outer electrode.

[0207] Additionally, refer to Figure 11A and Figure 11B Comparative Example 1 exhibits glass clusters at the interface between the outer electrode and the inner electrode layer. These glass clusters degrade the connectivity between the outer electrode and the inner electrode layer, thereby degrading the electrical properties of the multilayer ceramic capacitor. On the other hand, in Example 1, no glass clusters were found at the interface between the outer electrode and the inner electrode layer; instead, a small amount of glass was present only on the dielectric layer. The outer electrode, including the inner layer, according to the embodiment exhibits excellent connectivity with the inner electrode layer.

[0208] Evaluation 3: EBSD Analysis Electron backscattering diffraction (EBSD) analysis was performed on the multilayer ceramic capacitors according to Example 1 and Comparative Example 1, and the results are presented below. Figure 12 middle.

[0209] Using the cross-sectional sample from Evaluation 1, EBSD analysis was performed with an accelerating voltage of 15 kV, a step size of 0.025 μm, a scan area of ​​16 μm × 4 μm, a grain boundary deorientation of 10°, and a magnification of 3 k. In the obtained EBSD images, the grain size of Cu was calculated according to Equation 2 when straight lines of equal length were plotted.

[0210] [Equation 2] Grain size (μm) = (Total length of all straight lines) / (Total number of intersections between the straight lines and the grains) Figure 12 The images are electron backscatter diffraction (EBSD) images of the external electrodes of the multilayer ceramic capacitors of Comparative Example 1 and Example 1.

[0211] The Cu used to form the external electrode of Comparative Example 1 is a mixture of spherical particles of 500 nm and sheet-like particles of 7 μm or larger. On the other hand, the Cu nanoparticles included in the Cu particle film formed in Example 1 are fine spherical particles with an average size of 50 nm or smaller. This size difference of Cu particles results in different grain sizes of Cu after sintering.

[0212] In other words, refer to Figure 12 The Cu in the outer electrode of Comparative Example 1 has a grain size of about 1.8 μm, but the Cu in the inner layer of the outer electrode of Example 1 manufactured by the MOD method has a grain size of about 0.83 μm, which is reduced by about 50%.

[0213] Evaluation 4: Capacitor Characteristics Regarding capacitance and dielectric loss (DF), measurements were performed on the multilayer ceramic capacitors according to Example 1 and Comparative Example 1 at 120 Hz and 0.5 V, and the results are shown below. Figure 13 middle.

[0214] Figure 13 This is a graph showing the capacitance characteristics of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1.

[0215] Reference Figure 13 Compared with the multilayer ceramic capacitor of Comparative Example 1, in the multilayer ceramic capacitor of Example 1 in which the inner layer of the outer electrode is formed by the MOD method, problems caused by contact deterioration between the outer electrode and the inner electrode layer are reduced. For example, the capacitance distribution is reduced, the capacitance defects exceeding the specified specifications are significantly improved, and the distribution of dielectric loss DF is also reduced.

[0216] Evaluation 5: Electrical Characteristics The equivalent series resistance (ESR) and DC resistance (Rdc) were measured for the multilayer ceramic capacitors according to Example 1 and Comparative Example 1, and the results are shown below. Figure 14and Figure 15 middle.

[0217] The equivalent series resistance (ESR) and DC resistance (Rdc) were measured under 1MHz conditions.

[0218] Figure 14 This is a graph showing the equivalent series resistance (ESR) of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1, and Figure 15 This is a graph showing the DC resistance (Rdc) of the multilayer ceramic capacitors according to Comparative Example 1 and Example 1.

[0219] Reference Figure 14 Compared to the multilayer ceramic capacitor of Comparative Example 1, the equivalent series resistance (ESR) in the multilayer ceramic capacitor of Example 1 is reduced by approximately 15% to approximately 20%. Additionally, refer to... Figure 15 Compared to the multilayer ceramic capacitor of Comparative Example 1, the multilayer ceramic capacitor of Example 1 exhibits a lower DC resistance (Rdc) at both the upper and lower portions. Therefore, the multilayer ceramic capacitor according to the embodiment, having an inner layer with an outer electrode manufactured by the MOD method, exhibits excellent electrical characteristics.

[0220] Evaluation 6: Moisture Resistance Reliability The moisture resistance reliability of the multilayer ceramic capacitors manufactured in Example 1 and Comparative Example 1 was evaluated, and the results are presented in... Figures 16A to 16C middle.

[0221] Moisture resistance reliability was evaluated using an ESPEC (PR-3J, 8585) device at 85°C, 85% relative humidity (RH), and for 24 hours.

[0222] Figure 16A This is a graph showing the moisture resistance reliability of the multilayer ceramic capacitor according to Comparative Example 1. Figure 16B This is a graph showing the moisture resistance reliability of the multilayer ceramic capacitor according to Example 1, and Figure 16C The photograph shows the occurrence of defects in the multilayer ceramic capacitor according to Comparative Example 1 and Example 1.

[0223] Reference Figures 16A to 16C Comparative Example 1 exhibits an arc burn-out defect, a reliability failure caused by deterioration of the connection between the outer electrode and the inner electrode layer. However, Example 1 does not exhibit an arc burn-out defect. Therefore, the multilayer ceramic capacitor manufactured in Example 1 according to some embodiments of this disclosure has an inner layer of outer electrodes formed by the MOD method, thereby improving the connection between the outer electrode and the inner electrode layer and thus exhibiting excellent moisture-proof reliability.

[0224] While this disclosure has been described in conjunction with embodiments now considered practical, it should be understood that this disclosure is not limited to the disclosed embodiments, but is intended, by comparison, to cover various modifications and equivalents included within the spirit and scope of the appended claims.

[0225] <Explanation of reference numerals in the attached drawings> 100: Multilayer ceramic capacitor 110: Capacitor body 111: Dielectric layer 121: First inner electrode layer 122: Second inner electrode layer 131: First external electrode 132: Second external electrode 10: First Inner Layer 20: First outer layer 30: Second inner layer 40: Second outer layer.

Claims

1. A multilayer ceramic capacitor, comprising: A capacitor body includes multiple dielectric layers and multiple internal electrode layers, wherein the multiple internal electrode layers are stacked such that the dielectric layers are located between the multiple internal electrode layers; as well as External electrodes are disposed on the outer surface of the capacitor body. The capacitor body includes an effective region where the dielectric layer and the inner electrode layer are alternately disposed, and a covering region where the dielectric layer is disposed on the upper and lower surfaces of the effective region along the stacking direction. The external electrode includes an inner layer and an outer layer. The inner layer is disposed on the surface of the effective region and connected to the inner electrode layer, and the outer layer covers the inner layer. The inner layer comprises a first conductive metal and a first glass, and In the cross-section of the inner layer, the area occupied by the first glass is greater than 0% and less than or equal to 6% of the total area of ​​the inner layer.

2. The multilayer ceramic capacitor as described in claim 1, wherein, Based on the total amount of the inner layer, the first glass of the inner layer is included in an amount greater than 0% by weight and less than or equal to 5% by weight.

3. The multilayer ceramic capacitor as described in claim 1, wherein, Based on the total amount of the inner layer, the first conductive metal of the inner layer is included in an amount greater than 95% by weight and less than 100% by weight.

4. The multilayer ceramic capacitor as described in claim 1, wherein, The first conductive metal of the inner layer includes at least one selected from the group consisting of copper (Cu), nickel (Ni), silver (Ag), palladium (Pd), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), lead (Pb), and alloys thereof.

5. The multilayer ceramic capacitor as described in claim 1, wherein, The first conductive metal of the inner layer includes copper (Cu) and nickel (Ni).

6. The multilayer ceramic capacitor as described in claim 1, wherein, The first glass of the inner layer comprises at least one selected from the group consisting of aluminum oxide (Al2O3), silicon dioxide (SiO2), lithium oxide (Li2O), sodium oxide (Na2O), iron oxide (Fe2O3), zinc oxide (ZnO), barium oxide (BaO), calcium oxide (CaO), boron trioxide (B2O3), and tin oxide (SnO2).

7. The multilayer ceramic capacitor as described in claim 1, wherein, The inner layer extends into the interior of the capacitor body and connects to the inner electrode layer.

8. The multilayer ceramic capacitor as claimed in claim 1, wherein, The multilayer ceramic capacitor includes a Cu-Ni alloy located at the interface between the inner layer of the outer electrode and the inner electrode layer.

9. The multilayer ceramic capacitor as claimed in claim 1, wherein, The first glass of the inner layer exists on the surface of the dielectric layer in the effective region.

10. The multilayer ceramic capacitor as claimed in claim 1, wherein, The thickness of the inner layer is in the range of 1 μm to 5 μm.

11. The multilayer ceramic capacitor as claimed in claim 1, wherein, The grain size of the first conductive metal in the inner layer is 0.5 μm to 1 μm.

12. The multilayer ceramic capacitor as claimed in claim 1, wherein, The outer layer comprises a second conductive metal and a second glass. The second conductive metal of the outer layer may be the same as or different from the first conductive metal of the inner layer, and The second glass in the outer layer may be the same as or different from the first glass in the inner layer.

13. The multilayer ceramic capacitor as claimed in claim 12, wherein, Based on the total amount of the outer layer, the outer layer comprises 70% to 90% by weight of the second conductive metal and 10% to 30% by weight of the second glass.

14. The multilayer ceramic capacitor as claimed in claim 1, wherein, The inner electrode layer comprises nickel (Ni) and copper (Cu).

15. A method for manufacturing a multilayer ceramic capacitor, comprising: Metal-organic decomposition (MOD) ink is coated onto the surface of a capacitor body and reduced to form a metal particle film for the inner layer. The capacitor body includes multiple dielectric layers and multiple inner electrode layers, the multiple inner electrode layers being stacked such that the dielectric layer is located between the multiple inner electrode layers. A paste comprising a conductive metal and a glass composition is applied to the surface of the capacitor body on which the metal particle film is formed to form an outer layer; and The paste is fired to form an external electrode, the external electrode comprising an inner layer formed of the metal particle film and an outer layer covering the inner layer and formed of the paste. The inner layer comprises a conductive metal and glass, and In the cross-section of the inner layer, the area occupied by the glass is greater than 0% and less than or equal to 6% of the total area of ​​the inner layer.

16. The method according to claim 15, wherein, The metal-organic decomposition (MOD) ink comprises metal ligand materials, amine compounds, binders, antioxidants, and solvents.

17. The method according to claim 15, wherein, Perform the coating step of the metal-organic decomposition (MOD) ink until the thickness is 50 μm to 400 μm.

18. The method according to claim 15, wherein, Reduction is carried out at a temperature of 170°C to 300°C for 30 minutes to 3 hours.

19. The method according to claim 15, wherein, The metal particle film comprises metal nanoparticles with a particle size ranging from 10 nm to 50 nm.

20. The method of claim 15, wherein, The glass composition is included in an amount of 10% to 30% by weight, based on the total amount of the paste.

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