Semiconductor laser and packaging method thereof

Abstract

The application provides a semiconductor laser and a packaging method thereof. The packaging method of the semiconductor laser comprises the following steps: forming a solder structure on one side of a heat sink along a first direction, wherein the solder structure comprises a first solder layer, a porous barrier layer and a second solder layer which are sequentially stacked away from the heat sink along the first direction, the melting point of the first solder layer is greater than that of the second solder layer; the eutectic temperature of the material of the second solder layer and the material of the porous barrier layer is greater than the eutectic temperature of the material of the second solder layer and the first solder layer; arranging a substrate-free semiconductor laser chip on the side of the solder structure away from the heat sink, and performing soldering, wherein the soldering temperature is greater than the melting point of the second solder layer and less than the melting point of the first solder layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor laser and its packaging method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) possess characteristics such as low divergence angle, circular output beam, low threshold current, high efficiency, and high reliability, leading to their applications in time-of-flight, pumping, and medical fields. Due to the relatively low output power of a single emission column, large-size, two-dimensional, densely integrated emission column arrays are required to achieve power outputs exceeding 100 watts under continuous / quasi-continuous operation conditions. During operation, the high heat density of high-power VCSEL chips can easily lead to temperature rise, thus affecting the device's performance and reliability. VCSEL chips primarily dissipate heat through conduction from the substrate to the heat sink, making the substrate a major obstacle in the heat transfer path. To improve the heat dissipation capabilities of high-power VCSEL chips, researchers have employed a special substrate removal process to peel off the substrate. Summary of the Invention

[0003] The technical problem to be solved by the present invention is how to reduce the blank soldering rate, thereby providing a semiconductor laser and its packaging method.

[0004] This application provides a method for packaging a semiconductor laser, comprising: forming a solder structure on one side of a heat sink along a first direction, the solder structure comprising a first solder layer, a porous barrier layer, and a second solder layer sequentially stacked in the first direction away from the heat sink, wherein the melting point of the first solder layer is greater than the melting point of the second solder layer; the eutectic temperature of the materials of the second solder layer and the porous barrier layer is greater than the eutectic temperature of the materials of the second solder layer and the first solder layer; and placing a substrate-free semiconductor laser chip on the side of the solder structure away from the heat sink and performing soldering, wherein the soldering temperature is greater than the melting point of the second solder layer and less than the melting point of the first solder layer.

[0005] Optionally, the welding process includes: the second solder layer melting and wetting the welding surface of the semiconductor laser chip; the molten second solder layer diffusing through the pores of the porous barrier layer to contact the first solder layer and undergoing a eutectic reaction with the first solder layer to form molten solder, wherein the first element of the first solder layer and the second element of the second solder layer enter the molten solder; during the eutectic reaction, the composition of the first element in the molten solder increases, and the melting point of the molten solder rises; when the melting point of the molten solder rises to above the welding temperature, the molten solder solidifies.

[0006] Optionally, before soldering, the dimension of the first solder layer in the direction perpendicular to the first direction is larger than the dimension of the porous barrier layer in the direction perpendicular to the first direction and larger than the dimension of the second solder layer in the direction perpendicular to the first direction.

[0007] Optionally, before soldering, the dimensional difference between the first solder layer and the second solder layer in the direction perpendicular to the first direction is greater than or equal to 0.5 mm, and the dimensional difference between the first solder layer and the porous barrier layer in the direction perpendicular to the first direction is greater than or equal to 0.5 mm.

[0008] Optionally, prior to soldering, the dimensional difference between the second solder layer and the semiconductor laser chip in the direction perpendicular to the first direction is greater than or equal to 0.1 mm and less than or equal to 0.5 mm.

[0009] Optionally, the melting point of the second solder layer +20℃ ≤ welding temperature < melting point of the second solder layer +150℃.

[0010] Optional, curing time t g Curing time t is less than or equal to 25 seconds. g The interval between the start of the melting of the second solder layer and the end of the solidification of the molten solder in the direction directly opposite the porous barrier layer in the first direction.

[0011] Optionally, the curing time t can be adjusted by regulating the porosity P of the porous barrier layer and the welding temperature T. g ;in, Among them, the curing time t g T1 is the time interval between the start of the melting of the second solder layer and the end of the solidification of the molten solder directly opposite the porous barrier layer in the first direction; T2 is the melting point of the second solder layer; k is the overtemperature coefficient; t0 is the time required for the eutectic reaction of the first solder layer and the second solder layer to solidify without the porous barrier layer.

[0012] Optionally, prior to soldering, the second solder layer has a dimension greater than or equal to 2 micrometers in the first direction.

[0013] Optionally, the elements of the first solder layer are first elements, and the elements of the second solder layer are second elements; Where H1 is the dimension of the first solder layer in the first direction before welding. H1 represents the density of the first solder layer, and H2 represents the dimension of the second solder layer in the first direction before soldering. The density of the second solder layer; in the eutectic phase diagram of the materials of the first solder layer and the second solder layer, m represents the distance of the feature point from the first vertical axis along the horizontal axis, n represents the distance of the feature point from the second vertical axis along the horizontal axis, the feature point is the point in the solidus line corresponding to the welding temperature, the horizontal axis of the first vertical axis represents that the composition of the second element in the binary system of the eutectic phase diagram is 100%, and the horizontal axis of the second vertical axis represents that the composition of the first element in the binary system of the eutectic phase diagram is 100%.

[0014] Optionally, prior to welding, the porous barrier layer has a size of 50 nm to 500 nm in the first direction.

[0015] Optionally, before soldering, the first solder layer has a dimension of 2μm to 5μm in the first direction, and the second solder layer has a dimension of 2μm to 10μm in the first direction.

[0016] Optionally, prior to welding, the porosity of the porous barrier layer is 1% to 10%.

[0017] Optionally, the welding temperature is 250℃~350℃.

[0018] Optionally, the formation process of the porous barrier layer includes a rotating grazing angle deposition method.

[0019] This application also provides a semiconductor laser, comprising: a heat sink; a substrate-free semiconductor laser chip located on one side of the heat sink along a first direction; and a weld body located between the heat sink and the substrate-free semiconductor laser chip; wherein the weld body comprises a first hypereutectic layer and a porous blocking layer; the first hypereutectic layer is located on both sides of the porous blocking layer in the first direction and passes through the holes of the porous blocking layer; the melting point of the first hypereutectic layer is lower than the melting point of the porous blocking layer.

[0020] Optionally, the welded body further includes a second hypereutectic layer, the melting point of which is lower than that of the porous barrier layer and the melting point of which is lower than that of the first hypereutectic layer, and the second hypereutectic layer is located on the side of the porous barrier layer and the first hypereutectic layer in a direction perpendicular to the first direction.

[0021] The technical solution of this invention has the following beneficial effects:

[0022] The semiconductor laser packaging method provided by this invention has a eutectic temperature greater than that of the materials of the second solder layer and the porous barrier layer. The materials of the second solder layer and the first solder layer are more prone to eutectic reaction compared to the materials of the porous barrier layer. The porous barrier layer slows down the eutectic reaction rate between the first and second solder layers facing the porous barrier layer in the first direction, prolonging the solidification time of the eutectic reaction. This extends the wetting and spreading time of the second solder layer on the soldering surface of the semiconductor laser chip during melting, reducing the risk of cold solder joints. The soldering temperature is greater than the melting point of the second solder layer. During the process of heating from the melting point of the second solder layer to the soldering temperature, the materials of the first and second solder layers facing the porous barrier layer in the first direction gradually undergo a eutectic reaction. After melting, the material of the second solder layer can pass through the pores in the porous barrier layer and contact the first solder layer, causing a eutectic reaction to occur in the first solder layer. As the composition of the first element in the first solder layer increases during the eutectic reaction, the melting point of the molten solder rises, and the molten solder solidifies to form the first hypereutectic layer. This solidified hypereutectic layer is located between the semiconductor laser chip and the heat sink, and the heat sink and the solidified hypereutectic layer provide good mechanical confinement and fixation for the semiconductor laser chip. Even after a certain holding time, the mechanically confined and fixed semiconductor laser chip is less prone to significant thermal deformation, reducing the risk of open solder joints. Attached Figure Description

[0023] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart of a semiconductor laser packaging method according to an embodiment of this application;

[0025] Figures 2 to 5 This is a schematic diagram of the packaging process of a semiconductor laser in one embodiment of this application;

[0026] Figure 6 This is a eutectic phase diagram of the materials of the first solder layer and the second solder layer in one embodiment of this application. Detailed Implementation

[0027] By peeling away the substrate of a vertical-cavity surface-emitting laser (VCSEL) chip, the thickness of the chip along the cavity length can be reduced from approximately 150 μm to below 10 μm, significantly lowering the thermal resistance. Therefore, developing large-size, ultra-thin VCSEL chips is of great practical significance.

[0028] Research has revealed that the packaging process for semiconductor laser chips faces the following key technical challenges:

[0029] 1. During the soldering process between semiconductor laser chips and heat sinks, open solder joints are prone to occur. Specifically, after removing the substrate of the semiconductor laser chip, a back electrode is formed on the back side. Due to the small cavity length of the substrate-free semiconductor laser chip, during the soldering process, the back and front electrodes of the semiconductor laser chip experience asymmetric thermal stress due to stress relaxation and grain recrystallization. This leads to wrinkles and warping thermal deformation of the semiconductor laser chip exceeding 20 μm. The semiconductor laser chip and heat sink are soldered using a eutectic bonding process, which requires high-temperature heating. During the high-temperature heating and holding process of eutectic bonding, the solder melts and fills the gap between the semiconductor laser chip and the heat sink. The semiconductor laser chip and heat sink are in a relatively free state, without significant mechanical restraint or fixation. As the holding time increases, the semiconductor laser chip inevitably undergoes the aforementioned significant thermal deformation, creating a gap between the semiconductor laser chip and the heat sink that is far greater than the solder thickness, ultimately resulting in an open solder joint.

[0030] 2. During the soldering process between semiconductor laser chips and heat sinks, leakage and short circuits in the semiconductor laser chip are easily caused. Specifically, during the soldering process, a certain amount of auxiliary pressure is required to ensure good adhesion between the semiconductor laser chip and the heat sink. When the solder melts, under pressure, the molten solder is squeezed out of the soldering surface, forming an arc-shaped solder bulge of a certain height around the soldering surface. When this solder bulge climbs onto the front electrode of the substrate-free semiconductor laser chip, it can cause leakage and short circuits, affecting the packaging yield and reliability of the semiconductor laser chip.

[0031] Based on this, embodiments of this application provide a semiconductor laser and a packaging method thereof to solve at least some of the above-mentioned technical problems.

[0032] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0034] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0035] This application provides a packaging method for a semiconductor laser, with reference to... Figure 1 ,include:

[0036] S1: A solder structure is formed on one side of the heat sink along a first direction. The solder structure includes a first solder layer, a porous barrier layer, and a second solder layer stacked sequentially in the first direction away from the heat sink. The melting point of the first solder layer is greater than the melting point of the second solder layer. The eutectic temperature of the material of the second solder layer and the material of the porous barrier layer is greater than the eutectic temperature of the material of the second solder layer and the first solder layer.

[0037] S2: A substrate-free semiconductor laser chip is placed on the side of the solder structure away from the heat sink and soldered, wherein the soldering temperature is greater than the melting point of the second solder layer and less than the melting point of the first solder layer.

[0038] In this embodiment, the eutectic temperature of the materials of the second solder layer and the porous barrier layer is greater than the eutectic temperature of the materials of the second solder layer and the first solder layer. Therefore, the materials of the second solder layer and the first solder layer are more prone to eutectic reaction compared to the materials of the second solder layer and the porous barrier layer. The porous barrier layer slows down the eutectic reaction rate of the first and second solder layers facing the porous barrier layer in the first direction, prolonging the solidification time of the eutectic reaction. This extends the wetting and spreading time of the second solder layer on the soldering surface of the semiconductor laser chip during the melting process, reducing the risk of cold solder joints. Since the soldering temperature is higher than the melting point of the second solder layer, during the process of heating from the melting point of the second solder layer to the soldering temperature, the materials of the first and second solder layers facing the porous barrier layer in the first direction gradually undergo a eutectic reaction. After melting, the material of the second solder layer can pass through the pores in the porous barrier layer and contact the first solder layer, causing a eutectic reaction to occur in the first solder layer. As the composition of the first element in the first solder layer increases during the eutectic reaction, the melting point of the molten solder rises, and the molten solder solidifies to form the first hypereutectic layer. This solidified hypereutectic layer is located between the semiconductor laser chip and the heat sink, and the heat sink and the solidified hypereutectic layer provide good mechanical confinement and fixation for the semiconductor laser chip. Even after a certain holding time, the mechanically confined and fixed semiconductor laser chip is less prone to significant thermal deformation, reducing the risk of open solder joints.

[0039] refer to Figures 2 to 5 This article provides a detailed introduction to the packaging methods for semiconductor lasers.

[0040] refer to Figure 2 This forms a substrate-free semiconductor laser chip 100.

[0041] The substrate-free semiconductor laser chip 100 includes multiple light-emitting pillars, which improves the light-emitting power.

[0042] In some embodiments, the substrate-free semiconductor laser chip 100 has a dimension greater than or equal to 5 mm in the direction perpendicular to the first direction Z. The substrate-free semiconductor laser chip 100 also has a dimension greater than or equal to 5 mm in the second direction X and a dimension greater than or equal to 5 mm in the third direction Y. The large area and large size of the substrate-free semiconductor laser chip 100 result in a greater number of light-emitting pillars, effectively improving the luminous power.

[0043] Wherein, the first direction Z is perpendicular to the second direction X, the first direction Z is perpendicular to the third direction Y, and the second direction X is perpendicular to the third direction Y.

[0044] In some embodiments, the substrate-free semiconductor laser chip 100 is a vertical-cavity surface-emitting laser chip. The substrate-free semiconductor laser chip 100 includes a first Bragg mirror, a plurality of light-emitting pillars, a front electrode layer, and a back electrode layer. The plurality of light-emitting pillars are located on one side of the first Bragg mirror along a first direction Z, and are arranged in an array along a direction perpendicular to the first direction Z. Each light-emitting pillar includes an active layer and a second Bragg mirror located on the side of the active layer opposite to the first Bragg mirror along the first direction Z. The light-emitting pillar may also include a current-limiting layer, which is located between the active layer and the second Bragg mirror and / or between the active layer and the first Bragg mirror. The front electrode layer is located on the side of the second Bragg mirror opposite to the active layer, and may be a ring-shaped structure. The back electrode layer is located on the side of the first Bragg mirror opposite to the active layer and is in contact with the first Bragg mirror.

[0045] In some embodiments, forming a substrate-free semiconductor laser chip 100 includes: forming a first Bragg mirror, a plurality of light-emitting pillars, and a front electrode layer on one side of a substrate along a first direction, wherein the plurality of light-emitting pillars are located on the side of a portion of the first Bragg mirror facing away from the substrate along the first direction Z, the plurality of light-emitting pillars are arranged in an array along a direction perpendicular to the first direction Z, and each light-emitting pillar includes an active layer and a second Bragg mirror located on the side of the active layer facing away from the first Bragg mirror along the first direction Z; the light-emitting pillar may also include a current-limiting layer located between the active layer and the second Bragg mirror and / or between the active layer and the first Bragg mirror; removing the substrate; and after removing the substrate, forming a back electrode layer on the side of the first Bragg mirror facing away from the active layer.

[0046] Wherein, the first direction Z is the cavity length direction.

[0047] In some embodiments, the substrate-free semiconductor laser chip 100 has a dimension of less than or equal to 10 micrometers in the first direction Z, which greatly reduces the thermal resistance between the substrate-free semiconductor laser chip 100 and the subsequent heat sink. The heat in the substrate-free semiconductor laser chip 100 can be transferred to the heat sink more quickly, thus improving the heat dissipation effect.

[0048] In some embodiments, the back electrode layer can be a multilayer structure, for example, the back electrode layer includes a first sub-electrode layer, a second sub-electrode layer, and a third sub-electrode layer in the first direction Z. The first sub-electrode layer is used for better adhesion to the first Bragg mirror, the second sub-electrode layer is used to block diffusion between the first and third sub-electrode layers, and the third sub-electrode layer is used for wetting contact with the solder. For example, the material of the first sub-electrode layer is Ti, the material of the second sub-electrode layer is Pt, and the material of the third sub-electrode layer is Au.

[0049] In some embodiments, the back electrode layer is a single-layer structure, and the material of the back electrode layer includes TiAu, TiNiAu, or PdGeTiAu.

[0050] refer to Figure 3 A solder structure 300 is formed on one side of the heat sink 200 along the first direction Z. The solder structure 300 includes a first solder layer 301, a porous barrier layer 303, and a second solder layer 302 stacked sequentially away from the heat sink 200 in the first direction Z. The melting point of the first solder layer 301 is greater than the melting point of the second solder layer 302. The eutectic temperature of the materials of the second solder layer 302 and the porous barrier layer 303 is greater than the eutectic temperature of the materials of the second solder layer 302 and the first solder layer 301.

[0051] In some embodiments, the heat sink 200 may be selected from copper-clad aluminum nitride, aluminum-clad diamond, copper-clad diamond, copper-clad silicon carbide, or copper tungsten.

[0052] In some embodiments, a wetting layer may be provided on the surface of the heat sink 200. The material of the wetting layer may be Au. The dimension of the wetting layer in the first direction Z may be 0.1 μm to 2 μm, for example 0.5 μm.

[0053] After the first solder layer 301 is formed, the first solder layer 301 can come into contact with the wetting layer.

[0054] In some embodiments, the process of forming the first solder layer 301 includes a deposition process or electroplating, such as a physical vapor deposition process.

[0055] In some embodiments, the process for forming the porous barrier layer 303 includes a spin-grazing deposition method. Specifically, a large-angle jig with a spin function is used to hold the heat sink 200. The deposition surface of the first solder layer 301 is approximately parallel to the deposition direction, away from the heat sink 200. The roughness and protrusions of the deposition surface create a shielding effect, resulting in a large number of uniform pores in the deposited porous barrier layer 303. The pores in the porous barrier layer 303 can be micron-sized. By controlling the surface roughness of the heat sink 200, the jig angle, and the deposition time, the porosity P of the porous barrier layer 303 can be relatively easily controlled.

[0056] In some embodiments, the surface roughness of the first solder layer 301 facing away from the heat sink 200 is set to a certain roughness. The roughness of the surface of the first solder layer 301 facing away from the heat sink 200 is less than the roughness of the surface of the heat sink 200. For example, the surface roughness of the heat sink 200 is 0.5 micrometers to 5 micrometers. The roughness of the surface of the first solder layer 301 facing away from the heat sink 200 is 0.5 micrometers to 3 micrometers, for example, 0.5 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, or 3 micrometers.

[0057] The surface roughness of the first solder layer 301 facing away from the heat sink 200 is greater than or equal to 0.5 micrometers, which is beneficial to the formation of pores in the porous barrier layer 303. The surface roughness of the first solder layer 301 facing away from the heat sink 200 is less than or equal to 3 micrometers, which is beneficial to improving the flatness of the substrate-free semiconductor laser chip 100 on the heat sink 200 after soldering.

[0058] In some embodiments, during the formation of the porous barrier layer 303 using the rotating grazing angle deposition method, the angle between the deposition surface of the first solder layer 301 away from the heat sink 200 and the deposition direction is 80°~90°, for example 85°.

[0059] In some embodiments, the melting point of the porous barrier layer 303 is higher than that of the first solder layer 301.

[0060] In some embodiments, the difference between the melting point of the first solder layer 301 and the melting point of the second solder layer 302 is greater than or equal to 300 degrees, for example: 300 degrees, 400 degrees, 500 degrees, 600 degrees, 700 degrees, 800 degrees, or 850 degrees. The greater the difference between the melting point of the first solder layer 301 and the melting point of the second solder layer 302, the more beneficial it is to expand the process window for subsequent soldering temperatures.

[0061] In some embodiments, the porosity of the porous barrier layer 303 is 1% to 10%, for example, 1%, 3%, 5%, 8%, or 10%. The porosity of the porous barrier layer 303 is not too small, which can extend the curing time of the eutectic reaction between the first solder layer 301 and the second solder layer 302, which are directly opposite the porous barrier layer 303 in the first direction Z, to a certain extent during subsequent soldering. The melting process of the second solder layer 302 extends the wetting and spreading time on the soldering surface of the semiconductor laser chip 100, effectively reducing the risk of poor soldering. The porosity of the porous barrier layer 303 is not too large, ensuring that the curing time of the eutectic reaction between the first solder layer 301 and the second solder layer 302, which are directly opposite the porous barrier layer 303 in the first direction Z, is not too long, effectively reducing the thermal deformation of the substrate-free semiconductor laser chip 100 during subsequent soldering.

[0062] In some embodiments, the process of forming the second solder layer 302 includes a deposition process or electroplating, such as a physical vapor deposition process.

[0063] In some embodiments, the material of the second solder layer 302 includes any one of Sn, In, Pb and Bi.

[0064] In some embodiments, the material of the first solder layer 301 includes any one of Au, Ag, Zn, Sb and Cu.

[0065] In some embodiments, the porous barrier layer 303 is made of a metal or an intermetallic compound, and the material of the porous barrier layer 303 includes any one of TiW, Ti, W, Mo, TiW, TiNi, TiN, and TiC. The materials of the second solder layer 302 and the first solder layer 301 are more prone to eutectic reaction than the materials of the second solder layer 302 and the porous barrier layer 303. That is, the porous barrier layer 303 and the second solder layer 302 are less prone to eutectic reaction than the materials of the second solder layer 302 and the first solder layer 301.

[0066] In some embodiments, due to limitations in the temperature resistance of the substrate-free semiconductor laser chip 100, the melting point of the second solder layer 302 should not exceed 300°C. This reduces the thermal impact on the substrate-free semiconductor laser chip 100.

[0067] In some embodiments, before soldering, the first solder layer 301 has a dimension of 2μm to 5μm in the first direction Z, for example, 3μm. Before soldering, the second solder layer 302 has a dimension of 2μm to 10μm in the first direction Z, for example, 4μm.

[0068] In some embodiments, the size of the second solder layer 302 in the first direction Z is greater than the size of the first solder layer 301 in the first direction Z, and the size ratio of the second solder layer 302 to the first solder layer 301 in the first direction Z is 1:5 to 2:1, for example 4 / 3.

[0069] In some embodiments, the dimension of the porous barrier layer 303 in the first direction Z is smaller than that of the second solder layer 302 in the first direction Z and smaller than that of the first solder layer 301 in the first direction Z. The smaller dimension of the porous barrier layer 303 in the first direction Z makes it less difficult for the material of the second solder layer 302 to pass through the pores in the porous barrier layer 303. Furthermore, the material composition of the porous barrier layer 303 required for the eutectic reaction between the porous barrier layer 303 and the second solder layer 302 can be very small; therefore, the dimension of the porous barrier layer 303 in the first direction Z can be designed to be smaller.

[0070] In some embodiments, prior to welding, the porous barrier layer 303 has a dimension of 50 nm to 500 nm in the first direction Z, for example, 100 nm.

[0071] In some embodiments, prior to soldering, the dimension of the first solder layer 301 in the direction perpendicular to the first direction Z is greater than the dimension of the porous barrier layer 303 in the direction perpendicular to the first direction Z and greater than the dimension of the second solder layer 302 in the direction perpendicular to the first direction Z. For example, the dimension of the first solder layer 301 in the second direction X is greater than the dimension of the porous barrier layer 303 in the second direction X and greater than the dimension of the second solder layer 302 in the second direction X; the dimension of the first solder layer 301 in the third direction Y is greater than the dimension of the porous barrier layer 303 in the third direction Y and greater than the dimension of the second solder layer 302 in the third direction Y.

[0072] In some embodiments, prior to soldering, the dimensional difference between the first solder layer 301 and the second solder layer 302 in the direction perpendicular to the first direction Z is greater than or equal to 0.5 mm, and the dimensional difference between the first solder layer 301 and the porous barrier layer 303 in the direction perpendicular to the first direction Z is greater than or equal to 0.5 mm. For example, the dimensional difference between the first solder layer 301 and the second solder layer 302 in the second direction X is greater than or equal to 0.5 mm, and the dimensional difference between the first solder layer 301 and the second solder layer 302 in the third direction Y is greater than or equal to 0.5 mm. The dimensional difference between the first solder layer 301 and the porous barrier layer 303 in the second direction X is greater than or equal to 0.5 mm, and the dimensional difference between the first solder layer 301 and the porous barrier layer 303 in the third direction Y is greater than or equal to 0.5 mm. The edge region of the first solder layer 301 that does not contact the porous barrier layer 303 is sized as described above, allowing the edge region of the first solder layer 301 to provide a larger area for contact with the solder extruded during subsequent soldering.

[0073] In some embodiments, the dimensional difference between the first solder layer 301 and the second solder layer 302 in the direction perpendicular to the first direction Z is less than or equal to 2 mm, and the dimensional difference between the first solder layer 301 and the porous barrier layer 303 in the direction perpendicular to the first direction Z is less than or equal to 2 mm. This reduces the area of ​​the first solder layer 301, saving its area. For example, the dimensional difference between the first solder layer 301 and the second solder layer 302 in the second direction X is less than or equal to 2 mm, and the dimensional difference between the first solder layer 301 and the second solder layer 302 in the third direction Y is less than or equal to 2 mm; the dimensional difference between the first solder layer 301 and the porous barrier layer 303 in the second direction X is less than or equal to 2 mm, and the dimensional difference between the first solder layer 301 and the second solder layer 302 in the third direction Y is less than or equal to 2 mm.

[0074] The semiconductor laser chip 100 has a dimension in the direction perpendicular to the first direction Z that is smaller than the dimension of the second solder layer 302 in the same direction and smaller than the dimension of the porous barrier layer 303 in the same direction. This allows for sufficient soldering of the bonding surfaces of the semiconductor laser chip 100. For example, the semiconductor laser chip 100 has a dimension in the second direction X that is smaller than the dimension of the second solder layer 302 in the same direction and smaller than the dimension of the porous barrier layer 303 in the same direction X; the semiconductor laser chip 100 also has a dimension in the third direction Y that is smaller than the dimension of the second solder layer 302 in the same direction and smaller than the dimension of the porous barrier layer 303 in the same direction Y.

[0075] In some embodiments, prior to soldering, the dimensional difference between the second solder layer 302 and the semiconductor laser chip 100 in the direction perpendicular to the first direction Z is greater than or equal to 0.1 mm and less than or equal to 0.5 mm. For example, the dimensional difference between the second solder layer 302 and the semiconductor laser chip 100 in the second direction X is greater than or equal to 0.1 mm and less than or equal to 0.5 mm, and the dimensional difference between the second solder layer 302 and the semiconductor laser chip 100 in the third direction Y is greater than or equal to 0.1 mm and less than or equal to 0.5 mm.

[0076] In some embodiments, prior to soldering, the second solder layer 302 has a dimension greater than or equal to 2 micrometers in the first direction Z, such as 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 8 micrometers, or 10 micrometers. This ensures that the second solder layer 302 provides sufficient molten solder during subsequent soldering, reducing the risk of incomplete soldering.

[0077] refer to Figure 4 A substrate-free semiconductor laser chip 100 is placed on the side of the solder structure 300 away from the heat sink 200 and soldered, wherein the soldering temperature is greater than the melting point of the second solder layer 302 and less than the melting point of the first solder layer 301.

[0078] In some embodiments, the difference between the welding temperature and the melting point of the second solder layer 302 is smaller than the difference between the welding temperature and the melting point of the first solder layer 301. This prevents the welding temperature from becoming excessively high, which helps reduce the thermal impact on the substrate-free semiconductor laser chip 100.

[0079] A substrate-free semiconductor laser chip 100 is disposed on the side of the solder structure 300 away from the heat sink 200, wherein the back electrode layer is in contact with the second solder layer 302. The surface of the back electrode layer away from the first Bragg mirror serves as the bonding surface of the substrate-free semiconductor laser chip 100.

[0080] The welding process includes a series of sequential heating, holding, and cooling processes. The heating process raises the temperature of the chamber to the welding temperature, the holding process maintains the temperature at the welding temperature, and the cooling process lowers the temperature of the chamber from the welding temperature to room temperature.

[0081] In some embodiments, the soldering process includes: the second solder layer 302 melting and wetting the soldering surface of the semiconductor laser chip 100; the molten second solder layer 302 diffusing through the pores of the porous barrier layer 303 to contact the first solder layer 301 and undergoing a eutectic reaction with the first solder layer 301 to form molten solder, wherein the first element of the first solder layer 301 and the second element of the second solder layer 302 enter the molten solder; during the eutectic reaction, the composition of the first element in the molten solder increases, and the melting point of the molten solder rises; when the melting point of the molten solder rises to above the soldering temperature, the molten solder solidifies, and after solidification, a first hypereutectic layer 304 is formed (see reference). Figure 5 ).

[0082] The porous barrier layer 303 slows down the eutectic reaction rate of the first solder layer 301 and the second solder layer 302, prolonging the curing time required for the eutectic reaction of the first solder layer 301 and the second solder layer 302, which are directly opposite the porous barrier layer 303 in the first direction Z. This extends the wetting and spreading time of the second solder layer 302 on the soldering surface of the semiconductor laser chip 100 during the melting process, reducing the risk of cold solder joints. The soldering temperature is higher than the melting point of the second solder layer. During the heating process, the materials of the first solder layer 301 and the second solder layer 302, which are directly opposite the porous barrier layer 303 in the first direction Z, gradually undergo a eutectic reaction. After melting, the material of the second solder layer 302 can pass through the pores in the porous barrier layer 303 and contact the first solder layer 301, causing a eutectic reaction in the first solder layer 301. As the composition of the first element in the eutectic reaction of the first solder layer 301 increases, the melting point of the molten solder increases, and the molten solder solidifies to form a first hypereutectic layer. The first pereutectic layer, after curing, is located between the semiconductor laser chip 100 and the heat sink 200. The heat sink 200 and the first pereutectic layer provide good mechanical confinement and fixation for the semiconductor laser chip 100. Even after a certain period of heat preservation, the semiconductor laser chip 100, which is mechanically confined and fixed, is unlikely to undergo significant thermal deformation, reducing the risk of open circuits.

[0083] In some embodiments, the dimension of the first solder layer 301 in the direction perpendicular to the first direction Z is larger than the dimension of the porous barrier layer 303 in the direction perpendicular to the first direction Z and larger than the dimension of the second solder layer 302 in the direction perpendicular to the first direction Z. This allows excess molten material of the second solder layer 302 to be squeezed out to the edge region of the first solder layer 301 under pressure during the soldering process. The edge region of the first solder layer 301 does not contact the porous barrier layer 303. The molten material of the second solder layer 302 rapidly seeps into the edge region of the first solder layer 301, causing a eutectic reaction between the material of the second solder layer 302 and the edge region of the first solder layer 301. As elements from the edge region of the first solder layer 301 continuously diffuse into the molten solder of the second solder layer 302, the material of the second solder layer 302 and the edge region of the first solder layer 301 undergo a eutectic reaction and rapidly solidify, forming a second hypereutectic layer 305 (see reference). Figure 5 This reduces the accumulation of solder on the soldering surface of the semiconductor laser chip 100 along the periphery perpendicular to the first direction Z, thereby reducing leakage and short circuits in the semiconductor laser chip 100 and improving the packaging yield and reliability of the semiconductor laser chip 100.

[0084] In some embodiments, the melting point of the second solder layer +20°C ≤ welding temperature < melting point of the second solder layer +150°C. This ensures that the material of the second solder layer 302 effectively wets the welding surface of the semiconductor laser chip 100, while reducing the increased thermal deformation of the semiconductor laser chip 100 caused by overheating.

[0085] In some embodiments, the curing time t is adjusted by regulating the porosity P of the porous barrier layer 303 and the welding temperature T. g ;in, Among them, the curing time t g T1 is the time interval between the start of melting of the second solder layer 302 and the end of solidification of the molten solder opposite the porous barrier layer 303 in the first direction Z; T2 is the melting point of the second solder layer 302; k is the overtemperature coefficient; t0 is the time required for the eutectic reaction solidification of the first solder layer 301 and the second solder layer 302 without the porous barrier layer 303. The value of t0 is a constant for the dimensions of the second solder layer 302 and the first solder layer 301 in the first direction Z, as well as the welding temperature, for the determined welding temperature, the determined composition of the second solder layer 302, the determined composition of the first solder layer 301, the determined dimension of the first solder layer 301 in the first direction Z, and the determined dimension of the second solder layer 302 in the first direction Z.

[0086] In some embodiments, the curing time t g Less than or equal to 25 seconds. Curing time t gThe size is not too large, so that the semiconductor laser chip 100 can be mechanically bound and fixed by the first hypereutectic layer earlier during the welding process, reducing thermal deformation.

[0087] In some embodiments, the curing time t g The end time is before the end time of the heating process, or the curing time t. g The end time coincides with the end time of the heating process.

[0088] In some embodiments, the curing time t g The end time is after the end of the heating process, and the curing time is t. g The interval between the end of the curing process and the end of the heating process is less than or equal to 15 seconds. That is, the curing time t... g The interval between the end time of the heat preservation process and the start time of the heat preservation process is less than or equal to 15 seconds.

[0089] In some embodiments, the elements of the first solder layer 301 are first elements, and the elements of the second solder layer 302 are second elements; Where H1 is the dimension of the first solder layer 301 in the first direction Z before welding. H1 represents the density of the first solder layer 301, and H2 represents the dimension of the second solder layer 302 in the first direction Z before soldering. The density of the second solder layer 302; the eutectic phase diagram of the materials of the first solder layer 301 and the second solder layer 302 (reference). Figure 6 In the diagram, m represents the distance of feature point S from the first vertical axis along the horizontal axis, and n represents the distance of feature point S from the second vertical axis along the horizontal axis. Feature point S is the point in the solidus line corresponding to the welding temperature. The horizontal axis of the first vertical axis represents that the composition of the second element in the binary system of the eutectic phase diagram is 100%, and the horizontal axis of the second vertical axis represents that the composition of the first element in the binary system of the eutectic phase diagram is 100%. The above dimensional settings allow all the material of the second solder layer 302 to participate in the eutectic reaction.

[0090] In some embodiments, the welding temperature is 250°C to 350°C, for example, 300°C. Due to the temperature resistance of the substrate-free semiconductor laser chip 100, the welding temperature should not exceed 400°C. The holding time can be 120s to 1800s, for example, 480s.

[0091] Comparative Example 1: A SnAu solder layer was placed between a substrate-free semiconductor laser chip and a heat sink. During the soldering process, the substrate-free semiconductor laser chip suffered severe thermal deformation, and solder accumulated at the edges of the substrate-free semiconductor laser chip, resulting in a high risk of short circuit.

[0092] Comparative Example 2: The first solder layer is made of Au, and the second solder layer is made of Sn. The first solder layer has a dimension of 3 μm in the first Z direction, and the second solder layer has a dimension of 4 μm in the first Z direction. No porous barrier layer is provided, and the first and second solder layers are in contact. Because there is no porous barrier layer between the first and second solder layers, the first and second solder layers rapidly undergo a eutectic reaction and solidify. The solder fails to completely wet the edge area of ​​the substrate-free semiconductor laser chip, resulting in a void between the edge area of ​​the substrate-free semiconductor laser chip and the heat sink.

[0093] Comparative Example 3: The first solder layer is made of Au, and the second solder layer is made of Sn. The dimensions of the first solder layer in the Z-direction are 3 μm and 4 μm, respectively. A dense barrier layer made of TiW is placed between the first and second solder layers, with a dimension of 200 nm in the Z-direction. Due to the excessive density of the barrier layer, no significant eutectic reaction occurred between the first and second solder layers. Soldering was primarily achieved using the second solder layer. The substrate-less semiconductor laser chip exhibited severe thermal deformation, and solder accumulation at the edges led to a high risk of short circuits.

[0094] Test Example: The first solder layer was made of Au, and the second solder layer was made of Sn. The dimensions of the first solder layer in the Z-direction were 3 μm and 4 μm, respectively. A porous barrier layer with a Z-direction dimension of 200 nm was placed between the first and second solder layers. The intended objective was achieved. During eutectic bonding, the first solder layer fully wetted the bonding surface of the substrate-free semiconductor laser chip. The material of the second solder layer contacted the first solder layer through the pores of the porous barrier layer, resulting in a significant eutectic reaction between the two layers, followed by curing. The measured curing time was approximately 25 seconds. No significant thermal deformation or open solder joints were observed in the substrate-free semiconductor laser chip during the subsequent heat treatment period after eutectic bonding, demonstrating excellent packaging performance.

[0095] First, the substrate-free semiconductor laser chip prepared by this invention has a low void soldering rate, which can avoid the thermal failure problem caused by void soldering and improve the reliability of the semiconductor laser chip. Second, the substrate-free semiconductor laser chip prepared by this invention has low warpage, which can improve the poor directivity problem caused by thermal deformation and improve the beam quality of the semiconductor laser chip. Finally, the substrate-free semiconductor laser chip prepared by this invention has a low risk of edge short circuits, which can significantly improve the packaging yield and reduce the packaging cost.

[0096] This application also provides a semiconductor laser, referenced... Figure 5The device includes: a heat sink 200; a substrate-free semiconductor laser chip 100 located on one side of the heat sink 200 along the first direction Z; and a weld body located between the heat sink 200 and the substrate-free semiconductor laser chip 100. The weld body includes a first hypereutectic layer 304 and a porous barrier layer 303. The first hypereutectic layer 304 is located on both sides of the porous barrier layer 303 along the first direction Z and passes through the holes of the porous barrier layer 303. The melting point of the first hypereutectic layer 304 is lower than the melting point of the porous barrier layer 303.

[0097] The first eutectic layer 304 is located between the semiconductor laser chip 100 and the heat sink 200. The heat sink 200 and the first eutectic layer 304 provide good mechanical confinement and fixation for the semiconductor laser chip 100. Even after a certain period of heat preservation, the semiconductor laser chip, which is mechanically confined and fixed, is unlikely to undergo significant thermal deformation, reducing the risk of open solder joints.

[0098] Semiconductor lasers are formed using the methods described above.

[0099] The first hypereutectic layer 304 is located on both sides of the porous barrier layer 303 in the first direction Z and passes through the pores of the porous barrier layer 303. Specifically, a first portion of the first hypereutectic layer 304 is located on one side of the porous barrier layer 303 in the first direction Z, a second portion of the first hypereutectic layer 304 is located on the other side of the porous barrier layer 303 in the first direction Z, and a third portion of the first hypereutectic layer 304 is located within the pores of the porous barrier layer 303. The third portion is in contact with the first portion and also in contact with the second portion.

[0100] In some embodiments, the weld body further includes a second hypereutectic layer 305, the melting point of which is lower than that of the porous barrier layer 303, and the melting point of the second hypereutectic layer 305 is lower than that of the first hypereutectic layer 304. The second hypereutectic layer 305 is located on the side of the porous barrier layer 303 and the first hypereutectic layer 304 perpendicular to the first direction Z.

[0101] The second hypereutectic layer 305 and the semiconductor laser chip 100 are spaced apart in the first direction Z. The second hypereutectic layer 305 does not contact the semiconductor laser chip 100, thus reducing the risk of leakage current in the semiconductor laser chip 100.

[0102] In some embodiments, the size of the second hypereutectic layer 305 in the first direction Z is smaller than the size of the first hypereutectic layer 304 between the porous barrier layer 303 and the semiconductor laser chip 100 in the first direction Z.

[0103] In some embodiments, the semiconductor laser further includes a first solder layer 301a, which is located between the solder body and the heat sink 200. A second hypereutectic layer 305 is in contact with a portion of the first solder layer 301a. The first solder layer 301a includes a first element and a second element, and the second hypereutectic layer 305 also includes a first element and a second element. The ratio of the first element to the second element in the first solder layer 301a is greater than the ratio of the first element to the second element in the second hypereutectic layer 305. The melting point of the metal corresponding to the first element is greater than the melting point of the metal corresponding to the second element.

[0104] In some embodiments, the porous barrier layer 303 is made of a metal or an intermetallic compound, and the porous barrier layer 303 is made of any one of TiW, Ti, W, Mo, TiW, TiNi, TiN and TiC.

[0105] In some embodiments, the dimension of the porous barrier layer 303 in the first direction Z is smaller than the dimension of the first hypereutectic layer 304 on one side of the porous barrier layer 303 in the first direction Z.

[0106] In some embodiments, the porous barrier layer 303 has a dimension of 50 nm to 500 nm in the first direction Z, for example, 100 nm.

[0107] In some embodiments, the porosity of the porous barrier layer 303 is 1% to 10%, for example 1%, 3%, 5%, 8% or 10%.

[0108] In some embodiments, the surface roughness of the heat sink 200 is 0.5 micrometers to 5 micrometers, for example 0.5 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 3 micrometers, 4 micrometers or 5 micrometers.

[0109] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for packaging a semiconductor laser, characterized in that, include: A solder structure is formed on one side of the heat sink along a first direction. The solder structure includes a first solder layer, a porous barrier layer, and a second solder layer stacked sequentially in the first direction away from the heat sink. The melting point of the first solder layer is greater than the melting point of the second solder layer. The eutectic temperature of the materials of the second solder layer and the porous barrier layer is greater than the eutectic temperature of the materials of the second solder layer and the first solder layer. A substrate-free semiconductor laser chip is disposed on the side of the solder structure away from the heat sink and soldered thereon, wherein the soldering temperature is greater than the melting point of the second solder layer and less than the melting point of the first solder layer.

2. The packaging method for a semiconductor laser according to claim 1, characterized in that, The welding process includes: The second solder layer melts and wets the solder surface of the semiconductor laser chip; The molten second solder layer diffuses through the pores of the porous barrier layer and contacts the first solder layer, and undergoes a eutectic reaction with the first solder layer to form molten solder. The first element of the first solder layer and the second element of the second solder layer enter the molten solder. During the eutectic reaction, the proportion of the first element in the molten solder increases, and the melting point of the molten solder rises. When the melting point of the molten solder rises above the welding temperature, the molten solder solidifies.

3. The packaging method for a semiconductor laser according to claim 1, characterized in that, Before soldering, the dimension of the first solder layer in the direction perpendicular to the first direction is greater than the dimension of the porous barrier layer in the direction perpendicular to the first direction and greater than the dimension of the second solder layer in the direction perpendicular to the first direction.

4. The packaging method for a semiconductor laser according to claim 3, characterized in that, Before soldering, the dimensional difference between the first solder layer and the second solder layer in the direction perpendicular to the first direction is greater than or equal to 0.5 mm, and the dimensional difference between the first solder layer and the porous barrier layer in the direction perpendicular to the first direction is greater than or equal to 0.5 mm.

5. The packaging method for a semiconductor laser according to claim 1 or 3, characterized in that, Before welding, the dimensional difference between the second solder layer and the semiconductor laser chip in the direction perpendicular to the first direction is greater than or equal to 0.1 mm and less than or equal to 0.5 mm.

6. The packaging method for a semiconductor laser according to claim 1, characterized in that, Melting point of the second solder layer +20℃ ≤ welding temperature < melting point of the second solder layer +150℃.

7. The packaging method for a semiconductor laser according to claim 2, characterized in that, Curing time t g Curing time t is less than or equal to 25 seconds. g The interval between the start of the melting of the second solder layer and the end of the solidification of the molten solder in the direction directly opposite the porous barrier layer in the first direction.

8. The packaging method for a semiconductor laser according to claim 2, characterized in that, The curing time t is adjusted by regulating the porosity P of the porous barrier layer and the welding temperature T. g ; in, ; Among them, curing time t g T1 is the time interval between the start of the melting of the second solder layer and the end of the solidification of the molten solder directly opposite the porous barrier layer in the first direction; T2 is the melting point of the second solder layer; k is the overtemperature coefficient; t0 is the time required for the eutectic reaction of the first solder layer and the second solder layer to solidify without the porous barrier layer.

9. The packaging method for a semiconductor laser according to claim 1, characterized in that, Prior to welding, the second solder layer has a dimension greater than or equal to 2 micrometers in the first direction.

10. The packaging method for a semiconductor laser according to claim 1, characterized in that, The elements of the first solder layer are first elements, and the elements of the second solder layer are second elements; Where H1 is the dimension of the first solder layer in the first direction before welding. H1 represents the density of the first solder layer, and H2 represents the dimension of the second solder layer in the first direction before soldering. The density of the second solder layer; in the eutectic phase diagram of the materials of the first solder layer and the second solder layer, m represents the distance of the feature point from the first vertical axis along the horizontal axis, n represents the distance of the feature point from the second vertical axis along the horizontal axis, the feature point is the point in the solidus line corresponding to the welding temperature, the horizontal axis of the first vertical axis represents that the composition of the second element in the binary system of the eutectic phase diagram is 100%, and the horizontal axis of the second vertical axis represents that the composition of the first element in the binary system of the eutectic phase diagram is 100%.

11. The packaging method for a semiconductor laser according to claim 1, characterized in that, Before welding, the porous barrier layer has a size of 50nm~500nm in the first direction.

12. The packaging method for a semiconductor laser according to claim 1, characterized in that, Before soldering, the first solder layer has a size of 2μm to 5μm in the first direction, and the second solder layer has a size of 2μm to 10μm in the first direction.

13. The packaging method for a semiconductor laser according to claim 1, characterized in that, Before welding, the porosity of the porous barrier layer is 1% to 10%.

14. The packaging method for a semiconductor laser according to claim 1, characterized in that, The welding temperature is 250℃~350℃.

15. The packaging method for a semiconductor laser according to claim 1, characterized in that, The formation process of the porous barrier layer includes a rotating grazing angle deposition method.

16. A semiconductor laser, characterized in that, include: Heat sink; A substrate-free semiconductor laser chip is located on one side of the heat sink along the first direction; The weld body is located between the heat sink and the substrate-free semiconductor laser chip; The welded body includes a first hypereutectic layer and a porous barrier layer; the first hypereutectic layer is located on both sides of the porous barrier layer in the first direction and passes through the pores of the porous barrier layer; the melting point of the first hypereutectic layer is lower than the melting point of the porous barrier layer.

17. The semiconductor laser according to claim 16, characterized in that, The welded body further includes a second hypereutectic layer, the melting point of which is lower than that of the porous barrier layer and the melting point of which is lower than that of the first hypereutectic layer. The second hypereutectic layer is located on the side of the porous barrier layer and the first hypereutectic layer in a direction perpendicular to the first direction.

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