Onboard bus message transmission method
By combining data linked lists with DMA caching technology, the problem of poor universality in airborne bus driver design was solved, enabling reuse and performance improvement across bus platforms.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA HELICOPTER RES & DEV INST
- Filing Date
- 2025-12-24
- Publication Date
- 2026-04-28
AI Technical Summary
Airborne high-speed bus driver designs vary greatly across different types of networks, have poor versatility, are complex to process, and are costly. Furthermore, the driver layer has a complex way of processing received bus data.
A general high-speed bus-driven data processing method is formed by combining data linked lists and DMA caching technology, and the onboard bus message transmission is managed through message linked lists.
It enables the reuse of airborne bus drivers across bus platforms, reducing design complexity and improving communication performance.
Smart Images
Figure CN121940237A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of airborne avionics system bus communication network technology, and particularly relates to an airborne bus message transmission method. Background Technology
[0002] Airborne bus networks are the foundation for achieving high integration and information sharing in avionics systems. As the nerve center of various devices within the avionics system, they are responsible for information exchange between subsystems. With the rapid development of computer technology, communication technology, and network construction technology, network interconnection technology has evolved from traditional low-speed inter-subsystem bus interconnection to high-speed switched networks. Currently, the mainstream high-speed switched airborne buses mainly include several types such as AFDX, FC, TTE, TSN, and lossless Ethernet.
[0003] The main shortcomings and problems of the current mainstream high-speed switching airborne buses are reflected in the following aspects: 1) Different types of airborne network drivers have very different architectures in terms of design and development. The processing of bus data is closely coupled with the bus type, and a unified high-speed bus data processing architecture has not been formed. The versatility is poor, and the personnel development, design and maintenance costs are high. 2) The driver layer has a complex and diverse way of processing the received bus data, and it has failed to break free from the constraints of the bus protocol itself. Summary of the Invention
[0004] The purpose of this invention is to address the design flaws in the aforementioned airborne high-speed bus drivers by proposing an airborne bus message transmission and processing method. This method aims to extract the common characteristics of data processing for various types of high-speed airborne buses and combine data linked lists with DMA caching technology to form a universal design method for high-speed bus driver data processing, thereby achieving the goal of reusing airborne high-speed bus drivers across bus platforms.
[0005] This application provides an airborne bus message transmission method, the method comprising: Step 1: The application requests a cache from the terminal, establishes a message list, and inserts the cache into the message list; wherein, the cache is used to store airborne bus messages; the message list includes a send A list, a send B list, a receive A list, a receive B list, and a receive C list; Step 2: Obtain the airborne bus message from the buffers in the sending A linked list and the sending B linked list, and send the airborne bus message; Step 3: Receive the airborne bus message and store the airborne bus message in the buffers of the receive A linked list, receive B linked list, and receive C linked list.
[0006] Preferably, step 1 includes: 1) Based on the system design bus communication resource requirements, create the following message linked lists according to the number of message channels and message priority: a) Messages are sent using a shared linked list, i.e., linked list A is sent; b) Send the channel message pending list, i.e., send the B list; c) Message priority receiving list, i.e., receiving list A; d) The message channel has received the linked list, i.e., it has received linked list B; e) The message channel waiting list, i.e., the receiving C list; 2) Based on the system design bus communication resource requirements, request transmit / receive DMA cache information from the operating system during device initialization, including the size, sequence number, priority, and physical address of each transmit / receive cache, and register the cache sequence number and physical address to the corresponding register of the peripheral FPGA; 3) According to the priority of the transmit / receive DMA buffer, insert the allocated transmit / receive DMA buffers into the tail of the transmit A linked list and the receive B linked list respectively in order; 4) In accordance with the requirements of system and bus protocol constraints, register the message channel priority, channel type, channel number, message source / destination information, and channel ID information to the corresponding registers of the peripheral FPGA.
[0007] Preferably, step 2 includes: Retrieve transmit bus data buffer; Encapsulate and send the message; Release the send buffer.
[0008] Preferably, the step of acquiring the transmit bus data buffer includes: a) Obtain the corresponding message sending channel based on the message sending ID parameter input by the user in the sending API interface; b) Retrieve the head node buffer from the B-list. If the buffer is valid, it indicates that there are still bus messages in the list that have not been sent. Exit the send API and return the corresponding error. c) Calculate the number of buffers to be sent based on the sending length input by the user, and start from the head node to take out the valid buffers from the sending A linked list and insert them into the tail of the sending B linked list; d) Retrieve the head node buffer of the B linked list. If the send length defined in the DMA buffer control header is not 0, it means that there are messages in the buffer that have not been sent. Then return the "Send Busy" error. e) Record the number of valid B-buffer entries obtained and their corresponding DMA buffer numbers.
[0009] Preferably, the encapsulation and transmission of the message includes: Based on the obtained number of valid transmit buffers and the corresponding DMA buffer sequence number, the DMA buffer control header and application information are sequentially filled into the corresponding transmit buffer.
[0010] Preferably, releasing the send buffer includes: a) Starting from the head node of the B-linked list, take out the B-linked list and retrieve the send buffer. As long as the send buffer is not empty, write the corresponding buffer number and priority to the peripheral FPGA and notify the peripheral FPGA to send the message. After the FPGA finishes sending, it will clear the message length in the DMA control header of the buffer to zero. b) Recycle the sent buffers to the end of the sending A linked list in the order they were retrieved, so as to enable the recycling of DMA buffer resources.
[0011] Preferably, step 3 includes: 1) Extract bus messages: a) In the periodic task, the head node of the message receiving A linked list is traversed in a loop according to the message priority. The message length in the control header field of the receiving DMA cache is extracted to determine whether a new message has been received. If the length is >0, it means that there is a new message to be received. The corresponding receiving message channel number is obtained by extracting the priority field in the DMA cache control header. b) Determine whether the entire message reception is complete by parsing the message end flag (EOF) bit in the DMA cache control header field. If EOF is 1, it means that the message has been received completely. Then, insert the received message cache into the tail of the received message B linked list in sequence. 2) Call the Message Receiving API to receive application messages: The application calls the driver's message receiving API interface, using the following parameters: device handle pointer, message ID, application message cache pointer, and received message length pointer. 3) Get the number of messages to be read from the cache: a) Lock the message receiving channel based on the priority of the user-input message; b) Retrieve the head node cache from the received message C linked list. If the cache is not empty, it indicates that the current cache has not been fully read, and return the corresponding error. c) If the number of messages in the receiving channel is 0, it means that no data has been received and the corresponding error is returned; d) Starting from the head node, traverse the B linked list of received messages corresponding to this channel, and insert the above unread received buffers into the tail of the C linked list in turn, while recording the number of buffered messages to be read; 4) Parse the receive buffer: Traverse the message C linked list starting from the head node, and record the sequence number and quantity of the buffer to be read; 5) Fill the application receive buffer: Based on the received quantity and buffer sequence number obtained in step 4), the sequence number of the receive buffer is obtained in a loop, the corresponding original receive buffer is locked, the contents of the buffer are parsed, and the received message payload is extracted from the buffer according to the message length and message reception integrity flag in the DMA receive control header field. The received message payload is copied and filled into the application receive buffer for the user to retrieve the received message. 6) Release the receive buffer: Traverse the entire received message C linked list and complete the preset operations.
[0012] Preferably, traversing the entire received message C linked list and completing the preset operation includes: a) Clear the received DMA cache control header field; b) Notify the peripheral FPGA of the sequence number and message priority of the received DMA buffer by writing to the corresponding register of the FPGA; c) Reclaim the received DMA cache to the end of the received message A linked list to enable the recycling of DMA cache resources.
[0013] The beneficial technical effects of this application are as follows: The airborne bus message processing method proposed in this invention combines DMA caching with data linked list management and scheduling technology, which effectively solves the problem of information transmission between airborne communication terminals for various types of airborne bus messages. It largely solves the problem of the universality of the design architecture for message processing of airborne multi-type bus drivers, greatly reduces the complexity of airborne bus communication system design, improves airborne bus communication performance, and is applicable to various airborne high-speed bus communication platform scenarios. Attached Figure Description
[0014] Figure 1 This is a flowchart of a message sending process provided in an embodiment of this application; Figure 2 This is a flowchart of a message receiving process provided in an embodiment of this application. Detailed Implementation
[0015] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0016] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings, but the embodiments of the present invention are not limited thereto.
[0017] The present invention is implemented using the following technical solution: Please see Figures 1-1 This paper provides a general processing method for high-speed bus-driven message transmission, which mainly includes the following steps: a) The application requests a cache from the terminal, establishes a message list, and inserts the cache into the message list; wherein, the cache is used to store airborne bus messages; the message list includes a send A list, a send B list, a receive A list, a receive B list, and a receive C list.
[0018] 1) Based on the system design bus communication resource requirements, create the following message linked lists according to the number of message channels and message priority: a) A message sending shared linked list, hereinafter referred to as the sending A linked list; b) Send channel message pending list, hereinafter referred to as the B-list; c) Message priority receiving list, hereinafter referred to as the receiving A list; d) The message channel has received the B list, hereinafter referred to as the B receiving list; e) Message channel waiting list, hereinafter referred to as the receiving C list.
[0019] 2) Based on the system design bus communication resource requirements, request transmit / receive DMA cache information from the operating system during device initialization. This mainly includes the size, sequence number, priority, and physical address of each transmit / receive cache. Register the cache sequence number and physical address to the corresponding register of the peripheral FPGA. 3) According to the priority of the send / receive DMA buffer, insert the allocated send / receive DMA buffers into the tail of the send A linked list and the receive B linked list respectively.
[0020] 4) In accordance with the requirements of system and bus protocol constraints, register the message channel priority, channel type, channel number, message source / destination information, channel ID and other information to the corresponding registers of the peripheral FPGA.
[0021] b) Obtain airborne bus messages from the buffers in the sending A list and the sending B list, and send the airborne bus messages; Upper-layer applications send application messages by calling the driver interface - Send Bus Message API. The API interface parameters include device handle pointer, message ID, message buffer address, message length, and other parameters.
[0022] 1) Obtain the transmit bus data buffer a) Obtain the corresponding message sending channel based on the message sending ID parameter input by the user in the sending API interface; b) Retrieve the head node buffer from the B-list. If the buffer is valid, it indicates that there are still bus messages in the list that have not been sent. Exit the send API and return the corresponding error. c) Calculate the number of buffers to be sent based on the sending length input by the user, and start from the head node to take out the valid buffers from the sending A linked list and insert them into the tail of the sending B linked list; d) Retrieve the head node buffer of the B linked list. If the send length defined in the DMA buffer control header is not 0, it means that there are messages in the buffer that have not been sent. Then return the "Send Busy" error. e) Record the number of valid B-buffer entries obtained and their corresponding DMA buffer numbers.
[0023] 2) Encapsulate and send messages: Based on the number of valid send buffers and the corresponding DMA buffer sequence number obtained in step 1), fill the DMA buffer control header and application information into the corresponding send buffers in sequence.
[0024] 3) Release the send buffer a) Starting from the head node of the B-linked list, take out the B-linked list and retrieve the send buffer. As long as the send buffer is not empty, write the corresponding buffer number, priority and other parameters to the peripheral FPGA and notify the peripheral FPGA to send the message. After the FPGA finishes sending, it will clear the message length in the DMA control header of the buffer to zero.
[0025] b) Recycle the sent buffers to the end of the sending A linked list in the order they were retrieved, so as to enable the recycling of DMA buffer resources.
[0026] If any error occurs during the above steps, the application's sent message API will return the corresponding error result. c) Receive the airborne bus message and store the airborne bus message in the buffers of the receive A linked list, receive B linked list and receive C linked list; 1) Extract bus messages a) In the periodic task, the head node of the message receiving A linked list is traversed in a loop according to the message priority. The message length in the control header field of the receiving DMA cache is extracted to determine whether a new message has been received (if the length > 0, it means there is a new message to be received). The corresponding receiving message channel number is obtained by extracting the priority field in the DMA cache control header. b) Determine whether the entire message reception is complete by parsing the message end flag (EOF) bit in the DMA cache control header field. If EOF is 1, it means that the message has been completely received, and the received message cache is inserted into the tail of the received message B linked list in sequence. 2) Call the message receiving API to receive application messages. The application calls the driver's message receiving API interface, using the following parameters: device handle pointer, message ID, application message cache pointer, and received message length pointer.
[0027] 3) Get the number of messages to be read from the cache a) Lock the message receiving channel based on the priority of the user-input message; b) Retrieve the head node cache from the received message C linked list. If the cache is not empty, it indicates that the current cache has not been fully read, and return the corresponding error. c) If the number of messages in the receiving channel is 0, it means that no data has been received and the corresponding error is returned; d) Starting from the head node, traverse the B linked list of received messages corresponding to this channel, and insert the above unread received buffers into the tail of the C linked list in turn, while recording the number of buffered messages to be read; 4) Parse the receive buffer Traverse the message C linked list starting from the head node, recording the sequence number and quantity of the cache to be read.
[0028] 5) Populate the application receive cache Based on the received quantity and buffer sequence number obtained in step 4), the sequence number of the received buffer is obtained in a loop, the corresponding original received buffer is locked, the contents of the buffer are parsed, and the received message payload is extracted from the buffer according to the message length and EOF (whether the message reception is complete) flag in the DMA receive control header field. The received message payload is copied and filled into the application receive buffer for the user to retrieve the received message. 6) Release the receive buffer: Traverse the entire received message C linked list and perform the following operations: a) Clear the received DMA cache control header field; b) Notify the peripheral FPGA of the sequence number and message priority of the received DMA buffer by writing to the corresponding register of the FPGA; c) Reclaim the received DMA cache to the end of the received message A linked list to enable the recycling of DMA cache resources.
[0029] If any error occurs during the above steps, the API for receiving messages called by the application will return the corresponding error result.
[0030] The airborne bus message processing method proposed in this invention combines DMA caching with data linked list management and scheduling technology, which effectively solves the problem of information transmission between airborne communication terminals for various types of airborne bus messages. It largely solves the problem of the universality of the design architecture for message processing of airborne multi-type bus drivers, greatly reduces the complexity of airborne bus communication system design, improves airborne bus communication performance, and is applicable to various airborne high-speed bus communication platform scenarios.
[0031] Table 1. Message Sending and Receiving Control Header Field Definitions
[0032] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.
Claims
1. An airborne bus message transmission method, characterized in that, The method includes: Step 1: The application requests a cache from the terminal, establishes a message list, and inserts the cache into the message list; wherein, the cache is used to store airborne bus messages; the message list includes a send A list, a send B list, a receive A list, a receive B list, and a receive C list; Step 2: Obtain the airborne bus message from the buffers in the sending A linked list and the sending B linked list, and send the airborne bus message; Step 3: Receive the airborne bus message and store the airborne bus message in the buffers of the receive A linked list, receive B linked list, and receive C linked list.
2. The method according to claim 1, characterized in that, Step 1 includes: 1) Based on the system design bus communication resource requirements, create the following message linked lists according to the number of message channels and message priority: a) Messages are sent using a shared linked list, i.e., linked list A is sent; b) Send the channel message pending list, i.e., send the B list; c) Message priority receiving list, i.e., receiving list A; d) The message channel has received the linked list, i.e., it has received linked list B; e) The message channel waiting list, i.e., the receiving C list; 2) Based on the system design bus communication resource requirements, request transmit / receive DMA cache information from the operating system during device initialization, including the size, sequence number, priority, and physical address of each transmit / receive cache, and register the cache sequence number and physical address to the corresponding register of the peripheral FPGA. 3) According to the priority of the transmit / receive DMA buffer, insert the allocated transmit / receive DMA buffers into the tail of the transmit A linked list and the receive B linked list respectively in order; 4) In accordance with the requirements of system and bus protocol constraints, register the message channel priority, channel type, channel number, message source / destination information, and channel ID information to the corresponding registers of the peripheral FPGA.
3. The method according to claim 1, characterized in that, Step 2 includes: Retrieve transmit bus data buffer; Encapsulate and send the message; Release the send buffer.
4. The method according to claim 3, characterized in that, The acquisition of the transmit bus data buffer includes: a) Obtain the corresponding message sending channel based on the message sending ID parameter input by the user in the sending API interface; b) Retrieve the head node buffer from the B-list. If the buffer is valid, it indicates that there are still bus messages in the list that have not been sent. Exit the send API and return the corresponding error. c) Calculate the number of buffers to be sent based on the sending length input by the user, and start from the head node to take out the valid buffers from the sending A linked list and insert them into the tail of the sending B linked list; d) Retrieve the head node buffer of the B linked list. If the send length defined in the DMA buffer control header is not 0, it means that there are messages in the buffer that have not been sent. Then return the "Send Busy" error. e) Record the number of valid B-buffer entries obtained and their corresponding DMA buffer numbers.
5. The method according to claim 3, characterized in that, The encapsulation and transmission of the message includes: Based on the obtained number of valid transmit buffers and the corresponding DMA buffer sequence number, the DMA buffer control header and application information are sequentially filled into the corresponding transmit buffer.
6. The method according to claim 3, characterized in that, The release of the send buffer includes: a) Starting from the head node of the B-linked list, take out the B-linked list and retrieve the send buffer. As long as the send buffer is not empty, write the corresponding buffer number and priority to the peripheral FPGA and notify the peripheral FPGA to send the message. After the FPGA finishes sending, it will clear the message length in the DMA control header of the buffer to zero. b) Recycle the sent buffers to the end of the sending A linked list in the order they were retrieved, so as to enable the recycling of DMA buffer resources.
7. The method according to claim 1, characterized in that, Step 3 includes: 1) Extract bus messages: a) In the periodic task, the head node of the message receiving A linked list is traversed in a loop according to the message priority. The message length in the control header field of the receiving DMA cache is extracted to determine whether a new message has been received. If the length is >0, it means that there is a new message to be received. The corresponding receiving message channel number is obtained by extracting the priority field in the DMA cache control header. b) Determine whether the entire message reception is complete by parsing the message end flag (EOF) bit in the DMA cache control header field. If EOF is 1, it means that the message has been received completely. Then, insert the received message cache into the tail of the received message B linked list in sequence. 2) Call the Message Receiving API to receive application messages: The application calls the driver's message receiving API interface, and receives messages through the following parameters: device handle pointer, message ID, application message cache pointer, and received message length pointer; 3) Get the number of messages to be read in the cache: a) Lock the message receiving channel based on the priority of the user-input message; b) Retrieve the head node cache from the received message C linked list. If the cache is not empty, it indicates that the current cache has not been fully read, and return the corresponding error. c) If the number of messages in the receiving channel is 0, it means that no data has been received and the corresponding error is returned; d) Starting from the head node, traverse the B linked list of received messages corresponding to this channel, and insert the above unread received buffers into the tail of the C linked list in turn, while recording the number of buffered messages to be read; 4) Parse the receive buffer: Traverse the message C linked list starting from the head node, and record the sequence number and quantity of the buffer to be read; 5) Fill the application receive buffer: Based on the received quantity and buffer sequence number obtained in step 4), the sequence number of the receive buffer is obtained in a loop, the corresponding original receive buffer is locked, the contents of the buffer are parsed, and the received message payload is extracted from the buffer according to the message length and message reception integrity flag in the DMA receive control header field. The received message payload is copied and filled into the application receive buffer for the user to retrieve the received message. 6) Release the receive buffer: Traverse the entire received message C linked list and complete the preset operations.
8. The method according to claim 7, characterized in that, The step of traversing the entire received message C linked list and completing the preset operations includes: a) Clear the received DMA cache control header field; b) Notify the peripheral FPGA of the sequence number and message priority of the received DMA buffer by writing to the corresponding register of the FPGA; c) Reclaim the received DMA cache to the end of the received message A linked list to enable the recycling of DMA cache resources.