Communication system, node device, and communication method

Abstract

The invention discloses a communication system, node equipment and a communication method, and the communication system comprises at least two pieces of node equipment with a first port and a second port, the first port and the second port of the node equipment are configured in a way that the first port and the second port of the node equipment send data to another node equipment or receive data sent by the other node equipment; the node equipment comprises a synchronization unit and an integration unit, the synchronization unit is used for performing clock recovery and data synchronization on two paths of data received by the first port and the second port of the node equipment, and the integration unit is used for integrating the two paths of data output by the synchronization unit and outputting the integrated data to external equipment. According to the communication system and the communication method provided by the invention, the first port and the second port of the node equipment are configured, so that the input and output directions of the ports can be flexibly configured, two channels can directly and simultaneously carry out half-duplex data transmission, and the transmission bandwidth is improved.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a communication system, node device, and communication method. Background Technology

[0002] In multi-device wired transmission systems, to reduce the number of ports on the main device and the number of cables used for signal transmission, a daisy-chain connection method is typically used to build the system, such as... Figure 1 As shown, data from the host is distributed to the various node devices (Slave1 and Slave2) for processing via the master node device. Data to be uploaded by the peripherals of each node device is uploaded level by level from the previous node device to the master node device, and then transmitted to the host for further processing via an interface. Each node device has two data ports, TRXA and TRXB. Normally, TRXA is the uplink port, and TRXB is the downlink port. While transmitting data required by the peripherals, the master node device also embeds a synchronization signal. After passing through the clock recovery circuit (CDR), the clock synchronization of all node devices is ensured.

[0003] In some special applications, such as the transmission of high-fidelity audio, it is necessary to increase the transmission bandwidth of the bus. Due to channel conditions, changing the encoding method will greatly increase the complexity of the design. Increasing the transmission rate of the channel will have a serious impact on the EMI (electromagnetic interference) and EMC (electromagnetic compatibility) performance of the system.

[0004] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a communication system, node device, and communication method that can increase the transmission bandwidth of the bus without changing the encoding method or increasing the rate.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution: A communication system includes at least two node devices having a first port and a second port, namely a first node device and a second node device. The first port and the second port of the first node device are connected to the first port and the second port of the second node device via a communication cable. The first port and the second port of the node device are configured to: send data to or receive data sent by the second node device from the first node device; or send data to or receive data sent by the second node device from the first node device and receive data sent by the second node device from the second node device from the first node device; or send data to or receive data sent by the second node device from the first node device and send data to the second node device from the second node device from the first node device; or send data to or receive data sent by the second node device from the first node device and receive data sent by the second node device from the first node device from the first node device from the first node device; or send data to or receive data sent by the second node device from the first node device and send data to the second node device from the first node device from the first node device from the second node device.

[0007] The node device includes a synchronization unit and an integration unit. The synchronization unit is used to synchronize two data streams received by the first port and the second port of the node device. The integration unit is used to integrate the two data streams output by the synchronization unit and output the integrated data to an external device.

[0008] In one or more embodiments of the present invention, the synchronization unit includes a first buffer circuit, which is used to synchronize two data streams received by the first port and the second port of the node device and transmit them to the integration unit; or

[0009] The synchronization unit includes a first clock recovery circuit, a second clock recovery circuit, and a first buffer circuit. The first clock recovery circuit is used to restore the clock of one data channel received by the first port of the node device. The second clock recovery circuit is used to restore the clock of one data channel received by the second port of the node device. The first buffer circuit is connected to the first clock recovery circuit and the second clock recovery circuit. The first buffer circuit is used to synchronize the two data channels and send them to the integration unit.

[0010] In one or more embodiments of the present invention, the synchronization unit includes a clock recovery circuit, a phase detection circuit, a numerically controlled delay line, and a sampler. The clock recovery circuit is used to recover the clock of the first data received by the node device to obtain the system clock. The phase detection circuit is used to detect the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The numerically controlled delay line performs phase compensation on the second data based on the phase difference signal. The sampler samples the compensated second data based on the system clock. The integration unit is connected to the sampler and the clock recovery circuit to integrate the sampled two data streams; or

[0011] The synchronization unit includes a clock recovery circuit, a phase detection circuit, a phase interpolator, and a sampler. The clock recovery circuit is used to recover the clock of the first data received by the node device to obtain the system clock. The phase detection circuit is used to detect the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The phase interpolator is used to adjust the phase of the system clock and the first data based on the phase difference signal. The sampler samples the second data based on the phase-adjusted system clock. The integration unit is connected to the sampler and the phase interpolator to integrate the two data streams.

[0012] In one or more embodiments of the present invention, the node device includes an allocation unit for allocating external data received by the node device to each port of the node device.

[0013] In one or more embodiments of the present invention, the node device further includes a third port, a third clock recovery circuit, and a second buffer circuit. The third clock recovery circuit is used to restore the clock of the data received by the third port of the node device and write it into the second buffer circuit. The integration unit of the node device is used to integrate the data output by the synchronization unit and the second buffer circuit of the node device.

[0014] The third port of the node device is used to connect with subsequent node devices via communication cables to form a daisy-chain cascade structure.

[0015] In one or more embodiments of the present invention, the first buffer circuit is used to store the first received data and simultaneously output the two data streams when the other data stream is received.

[0016] In one or more embodiments of the present invention, the node device further includes a mapping unit, a first cache unit, a second cache unit, and a data exchange unit. The mapping unit is used to sort the integrated data based on the mapping relationship and alternately write it into the first cache unit and the second cache unit. The data exchange unit is used to alternately read the data in the first cache unit and the second cache unit and transmit it to one or more external devices.

[0017] The present invention also discloses a node device, which includes a first port and a second port. The first port and the second port of the node device are connected to another node device via a communication cable. The first port and the second port of the node device are configured to: send data to or receive data from the other node device; or send data to or receive data from the other node device via the first port and receive data from the other node device via the second port; or send data to or receive data from the other node device via the first port and send data to the other node device via the second port; or send data to or receive data from the other node device via the second port and receive data from the other node device via the first port; or send data to or receive data from the other node device via the second port and send data to the other node device via the first port.

[0018] In one or more embodiments of the present invention, the node device further includes a third port, which is connected to subsequent node devices via communication cables to form a daisy-chain cascade structure.

[0019] The present invention also discloses a communication method, characterized in that, based on the aforementioned communication system, the communication method includes:

[0020] The first and second ports of the node device are configured to receive or send data to the second node device through the first and second ports of the first node device, or send or receive data to the second node device through the first port of the first node device and receive data sent by the second node device through the second port of the first node device, or send or receive data sent by the first node device through the first port of the first node device and send data to the second node device through the second port of the first node device, or send or receive data sent by the second node device through the second port of the first node device and receive data sent by the second node device through the first port of the first node device, or send or receive data sent by the second node device through the second port of the first node device and send data to the second node device through the first port of the first node device;

[0021] After receiving two data streams at the first and second ports of the current node device, the two data streams are synchronized.

[0022] The synchronized data is integrated and output.

[0023] In one or more embodiments of the present invention, synchronizing two data streams includes:

[0024] Data is synchronized through the first buffer circuit; or

[0025] The clock is restored to the two data streams using a clock recovery circuit, and the restored data is synchronized using a first buffer circuit; or

[0026] The system clock is obtained by restoring the clock of the first data stream using a clock recovery circuit. A phase difference signal is obtained by detecting the phase difference between the second data stream and the system clock using a phase detection circuit. Phase compensation is performed on the second data stream based on the phase difference signal using a digitally controlled delay line. Finally, the compensated second data stream is sampled based on the system clock using a sampler.

[0027] The system clock is obtained by restoring the clock of the first data channel through a clock recovery circuit. The phase difference signal is obtained by detecting the phase difference between the second data channel and the system clock through a phase detection circuit. The phase difference signal is used to adjust the phase of the system clock and the first data channel through a phase interpolator. The second data channel is sampled by a sampler based on the phase-adjusted system clock.

[0028] In one or more embodiments of the present invention, the communication method includes:

[0029] Configure the link to work in full-duplex or half-duplex mode by configuring the first node device;

[0030] When the device is selected to work in full-duplex mode, the first node device selects either its first port or its second port as the downlink port and sends data through that port. The second node device receives data through one of its first port and its second port, and sends a response frame to the first node device through the other port. After the first node device receives the response frame, it confirms that the handshake is complete, and the two node devices can communicate normally in full-duplex mode.

[0031] When the device is selected to work in half-duplex mode, data is sent synchronously through the first port and the second port of the first node device. Data is received simultaneously through the first port and the second port of the second node device, and a response frame is sent synchronously. After the first node device receives the response frame, it confirms that the handshake is complete, and the two node devices can communicate normally in half-duplex mode.

[0032] Compared with existing technologies, the communication system, node device, and communication method of this invention can flexibly configure the input and output directions of the first and second ports of the node device, enabling two channels to directly and simultaneously perform half-duplex data transmission, thereby increasing transmission bandwidth. Configuring a third port allows for network expansion to support data transmission in normal daisy-chain communication systems. Based on a daisy-chain system for multi-device wired transmission, without changing the encoding method or increasing the rate, it can perform hybrid networking of dual-line and single-line transmission, improving the data transmission rate between devices. Furthermore, the system can be configured to full-duplex operation or one path to be half-duplex while the other path has a fixed transmission direction to meet the needs of other systems for different uplink and downlink bandwidths. An optional initialization method is also proposed to complete the protocol handshake for half-duplex or full-duplex modes. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a system diagram of a daisy chain system in the prior art.

[0035] Figure 2 This is a schematic diagram of the system circuit of the communication system in Embodiment 1 of the present invention.

[0036] Figure 3This is a schematic diagram of the first circuit for data allocation in Embodiment 1 of the present invention.

[0037] Figure 4 This is a circuit diagram of data synchronization and integration in Embodiment 1 of the present invention.

[0038] Figure 5 This is a schematic diagram of data synchronization in Embodiment 1 of the present invention.

[0039] Figure 6 This is a circuit diagram of the output unit in Embodiment 1 of the present invention.

[0040] Figure 7 This is a circuit diagram illustrating data integration in Embodiment 1 of the present invention.

[0041] Figure 8 This is a schematic diagram of the second circuit for data allocation in Embodiment 1 of the present invention.

[0042] Figure 9 This is a flowchart of the communication method in Embodiment 1 of the present invention.

[0043] Figure 10 This is a schematic diagram of the data synchronization circuit in Embodiment 2 of the present invention.

[0044] Figure 11 This is a schematic diagram of the data synchronization circuit in Embodiment 3 of the present invention.

[0045] Figure 12 This is a circuit diagram illustrating the configuration of ports in other embodiments of the present invention for simultaneous one-way and two-way communication.

[0046] Figure 13 Another circuit diagram illustrating the configuration of ports in other embodiments of the present invention for simultaneous one-way and two-way communication. Detailed Implementation

[0047] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0048] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0049] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0050] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0051] For the purposes of this disclosure, the phrase “A and / or B” means (A), (B), or (A and B). For the purposes of this disclosure, the phrase “A, B and / or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0052] Various components and devices may be referred to or shown in the singular (e.g., “transistor”, “transistor”, “switch”, etc.) in this document, but only for the convenience of discussion, and any element referred to in the singular may include multiple such elements as taught herein.

[0053] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which may refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this disclosure are synonymous.

[0054] like Figure 2As shown, a communication system according to one embodiment of the present invention includes: at least two node devices having a first port TRXA and a second port TRXB. The first port TRXA and the second port TRXB of the node devices are configured to send data to or receive data sent by the other node device. That is, the first port TRXA and the second port TRXB of the node devices are simultaneously configured as uplink ports or downlink ports to realize two-line half-duplex data transmission and expand bandwidth.

[0055] When the host needs to transmit data to an external device connected to another node device via the current node device, the first port TRXA and the second port TRXB of the current node device are simultaneously configured as downlink ports to send data to the other node device. At the same time, the first port TRXA and the second port TRXB of the other node device are also simultaneously configured as downlink ports to receive data. When the external device connected to the other node device needs to return data to the host, the first port TRXA and the second port TRXB of that other node device are simultaneously configured as uplink ports to send data to the node device connected to the host. At the same time, the first port TRXA and the second port TRXB of the node device connected to the host are also simultaneously configured as uplink ports to receive data. This half-duplex communication method allows data to be transmitted in both directions, but not simultaneously; downlink and uplink data share the bus bandwidth. In one embodiment, the bandwidth occupied by downlink and uplink data is also configurable. When the amount of data transmitted from the host to the external device is greater than the amount of data transmitted from the external device to the host, the bandwidth occupied by downlink data can be increased as needed. Conversely, when the amount of data transmitted from the host to the external device is less than the amount of data transmitted from the external device to the host, the bandwidth occupied by the uplink data can be increased as needed.

[0056] In other embodiments, such as Figure 12 As shown, the first port TRXA and the second port TRXB of the node device are configured such that: the second port TRXB of the first node device sends (UP) data to the second node device or receives (DN) data sent by the second node device, and the first port TRXA of the first node device receives (UP) data sent by the second node device. In other embodiments, such as Figure 13 As shown, the first port TRXA and the second port TRXB of the node device are configured such that the second port TRXB of the first node device sends data to or receives data from the second node device, and the first port TRXA of the first node device sends data to the second node device. It should be noted that the port configuration for receiving or sending data on the node device can be changed as needed.

[0057] In one embodiment, such as Figure 2As shown, two node devices are configured, namely a first node device and a second node device. In other embodiments, the number of node devices can be configured as needed. The first port TRXA and the second port TRXB of the first node device are wiredly connected to the first port TRXA and the second port TRXB of the second node device via communication cables. The first port TRXA and the second port TRXB of the first node device are configured to: send data to the first port TRXA and the second port TRXB of the first node device, or receive data sent by the first port TRXA and the second port TRXB of the second node device. Specifically, the first port TRXA of the first node device is connected to the second port TRXB of the second node device, and the second port TRXB of the first node device is connected to the first port TRXA of the second node device. In other embodiments, the first port TRXA of the first node device is connected to the first port TRXA of the second node device, and the second port TRXB of the first node device is connected to the second port TRXB of the second node device.

[0058] In other embodiments, the first port TRXA and the second port TRXB of the first node device, as well as the first port TRXA and the second port TRXB of the second node device, can also be configured such that: the first port TRXA of the first node device sends data to or receives data sent by the second port TRXB of the second node device, and the second port TRXB of the first node device sends data to the first port TRXA of the second node device; or it can be configured such that: the first port TRXA of the first node device sends data to or receives data sent by the second port TRXB of the second node device, and the second port TRXB of the first node device receives data sent by the first port TRXA of the second node device.

[0059] In one embodiment, the first node device is the master device, and the second node device is the slave device. The second port TRXB of the first node device is connected to the first port TRXA of the second node device for downlink DN or uplink UP data transmission, and the first port TRXA of the first node device is connected to the second port TRXB of the second node device for downlink DN or uplink UP data transmission. Downlink DN data transmission or uplink UP data transmission occurs simultaneously between the two pairs of ports, achieving a half-duplex transmission mode. In other embodiments, the two pairs of ports can respectively perform downlink DN and uplink UP data transmission, achieving a full-duplex transmission mode.

[0060] like Figure 2As shown, each node device includes an allocation unit, a synchronization unit, an integration unit, and an output unit.

[0061] The allocation unit is used to allocate received external data to the ports of the node device when the node device receives external data. For example, the first node device is connected to the host, and the host sends and receives data through the first node device. When the first node device receives external data sent by the host (in one embodiment, the external data is time-division multiplexing (TDM) data; time-division multiplexing (TDM) is a core communication technology that allows multiple data streams to share the same physical channel. By dividing time into small segments, different signals take turns using the channel, thereby enabling the simultaneous transmission of multiple information streams on a single line. In other embodiments, the external data can be other forms of data), the allocation unit of the first node device allocates the external data to the first port TRXA and the second port TRXB of the first node device in a two-line manner according to parity bytes. Figure 3 The diagram illustrates how, for example, the allocation unit BUF allocates the odd byte (Odd byte) of time-division multiplexed data (TDM data) to the first port TRXA of the first node device, and the even byte (Even byte) of time-division multiplexed data (TDM data) to the second port TRXB of the first node device. The second node device is connected to external device 1, which is a device in the system requiring high-bandwidth data transmission. External device 1 sends and receives data through the second node device. The second node device receives external data (TDM data) sent by external device 1, and its allocation unit allocates the external data to both the first port TRXA and the second port TRXB of the second node device according to the odd and even bytes. Other allocation methods may also be used in other embodiments.

[0062] Because dual-wire transmission involves two data paths transmitting simultaneously, with each port receiving data independently, the clock phases of the two data paths differ due to cable delay variations. The node receiving the data from both paths needs to reconstruct a unified clock and use it to correctly sample the data from both paths, or perform phase alignment on the data from each path separately.

[0063] Taking the second node device as an example (the same applies to the first node device), the synchronization unit of the second node device performs clock recovery and data synchronization on the two data streams received from the first port TRXA and the second port TRXB of the second node device (these two data streams were sent by the first node device). The integration unit of the second node device integrates the two data streams output by the synchronization unit and outputs the integrated data to the output unit, which then outputs the data to external device 1. The two data streams are: data Aport data and data Bport data. In other embodiments, clock recovery can be performed without a synchronization unit, and data acquisition can be performed using a local clock.

[0064] like Figure 4 As shown, the synchronization unit includes a first clock recovery circuit CDR_A, a second clock recovery circuit CDR_B, and a first buffer circuit FIFO1. The first clock recovery circuit CDR_A is used to restore the clock of one data Aport data received from the first port TRXA of the second node device. The second clock recovery circuit CDR_B is used to restore the clock of one data Bport data received from the second port TRXB of the second node device. The first buffer circuit FIFO1 is connected to the first clock recovery circuit CDR_A and the second clock recovery circuit CDR_B. The first buffer circuit FIFO1 is used to synchronize the two data Aport data and Bport data and send them to the integration unit. The first buffer circuit FIFO1 stores the first received data and synchronously outputs the two data when the other data is received to synchronize the data. The integration unit integrates the synchronized data to ensure the synchronization and integrity of the data, and outputs the integrated data to the output unit. The output unit then outputs the data to the external device 1.

[0065] like Figure 5 As shown, when the first node device transmits data to the second node device, the first port TRXA and the second port TRXB of the first node device send data simultaneously using the same clock. However, due to the different cable lengths, the two data streams arrive at the second node device at different times, namely Delay1 and Delay2. In the second node device, the two data streams, Aport data and Bport data, are sent to the first clock recovery circuit CDR_A and the second clock recovery circuit CDR_B, respectively. The clock recovery circuit extracts the synchronization signal from the data frame header to generate a system clock, which samples the data from this channel. However, since the first time Delay1 and the second time Delay2 may be inconsistent, the two recovered system clocks may also have a phase difference, and the sampled data may also be misaligned, which will affect subsequent data processing.

[0066] In one embodiment, combined with Figure 4 and Figure 5 The first arriving data is stored in the first buffer circuit FIFO1. If the first time delay (Delay1) is less than the second time delay (Delay2), the first received data (Aport data) will be stored in the first buffer circuit FIFO1. Only after the frame header of the later received data (Bport data) is received will the first buffer circuit FIFO1 release the data (Aport data), synchronizing the data (Aport data) and data (Bport data). Conversely, if data (Bport data) is received first, it will be stored in the first buffer circuit FIFO1. Only after the frame header of data (Aport data) is received will the first buffer circuit FIFO1 release the data (Bport data), synchronizing the data (Aport data) and data (Bport data). The integration unit can integrate uplink and downlink data separately according to the current configuration to ensure data synchronization and integrity. The integrated data is sent to peripherals through the output unit; the number of peripherals is configurable.

[0067] In other embodiments, the synchronization unit includes a first sampling circuit, a second sampling circuit, and a first buffer circuit. The first sampling circuit samples one channel of data received from the first port of the node device based on the local clock of the node device. The second sampling circuit samples one channel of data received from the second port of the node device based on the local clock of the node device. The first and second sampling circuits can adjust the local clock according to the phase of the data they are sampling to accurately sample the data. The first buffer circuit is connected to the first and second sampling circuits and is used to synchronize the two channels of data sampled by the first and second sampling circuits and send them to the integration unit.

[0068] like Figure 6As shown, the output unit includes a mapping unit, a first buffer unit SRAM0, a second buffer unit SRAM1, and a data exchange unit TDM_TX. The mapping unit sorts the data integrated by the integration unit based on the mapping relationship and alternately writes it to the first buffer unit SRAM0 and the second buffer unit SRAM1. The data exchange unit TDM_TX alternately reads data from the first buffer unit SRAM0 and the second buffer unit SRAM1; that is, when received data is written to the first buffer unit SRAM0, the data to be sent is read from the second buffer unit SRAM1. The next frame of received data is written to the second buffer unit SRAM1, and the next frame of sent data is read from the first buffer unit SRAM0, and so on. This ping-pong operation ensures that data reading is not interfered with by data writing. The data exchange unit TDM_TX is responsible for data exchange with external devices. The number of channels TX0~TXn of the data exchange unit TDM_TX can be configured according to the number of external devices to connect one or more external devices.

[0069] like Figure 2 As shown, the communication system also includes node devices as downstream devices, each having a first port TRXA and a second port TRXB, such as a third node device and a fourth node device. The third node device is connected to external device 2, and the fourth node device is connected to external device 3. External device 2 and external device 3 do not require high-bandwidth data transmission. In other embodiments, the number of downstream node devices can be set as needed.

[0070] like Figure 7 and Figure 2 As shown, in one embodiment, the first node device and the second node device further include a third port TRXC, a third clock recovery circuit CDR_C, and a second buffer circuit FIFO2, which are used for single-line expansion. The third node device and the fourth node device, as subsequent node devices, are connected to the third port TRXC of the first node device and the third port TRXC of the second node device respectively through communication cables, forming a daisy-chain cascade structure, thereby enabling hybrid networking through communication between the first node device and the second node device.

[0071] In one embodiment, taking the second and fourth node devices as examples (the first and third node devices are similar), the third port TRXC of the second node device is connected to the second port TRXB of the fourth node device to configure downlink or uplink data transmission between them. The third clock recovery circuit CDR_C of the second node device is used to restore the clock of one data channel Cport data (issued by the fourth node device) received by the third port TRXC of the second node device and write it into the second buffer circuit FIFO2 of the second node device. The integration unit of the second node device is used to integrate the data output by the synchronization unit and the second buffer circuit FIFO2 of the second node device. The first port TRXA of the fourth node device is connected to the ports of other subsequent node devices to further extend the daisy-chain cascade structure. In other embodiments, the third port TRXC of the second node device can be connected to the second port TRXB of the fourth node device.

[0072] like Figure 8 As shown, after setting up the third port TRXC for single-line extension, the allocation unit BUF allocates part of the data to the first port TRXA and the second port TRXB of the node device in odd bytes and even bytes, and also allocates another part of the data to the third port TRXC to send to subsequent node devices.

[0073] Each node device extends the network through the third port TRXC to support the transmission of the normal daisy-chain communication system. The third port TRXC is a relatively independent port compared to the first port TRXA and the second port TRXB. When the first node device (master node) sends data, it first needs to package and distribute the data to the second and third node devices respectively. When receiving data, the first node device will receive data from the second and third node devices. The two parts of the data are relatively independent, so after being buffered by the corresponding buffer circuit, the integration unit can integrate and process the data.

[0074] This embodiment also discloses a communication method. Based on the above-described communication system, the communication method includes:

[0075] Configure the first port TRXA and the second port TRXB of the node device to receive data from another node device or send data to another node device to enter two-wire half-duplex mode.

[0076] In other embodiments, the first port TRXA and the second port TRXB of the node device can also be configured such that the first port TRXA of the node device sends data to or receives data from another node device, and the second port TRXB of the node device receives data from another node device; or the first port TRXA and the second port TRXB of the node device can be configured such that the first port TRXA sends data to or receives data from another node device, and the second port TRXB of the node device sends data to another node device, wherein the configuration of the first port TRXA and the second port TRXB can be replaced.

[0077] After receiving two data streams at the first port TRXA and the second port TRXB of the node device, clock recovery and data synchronization are performed on the two data streams.

[0078] The synchronized data is integrated and output.

[0079] In one embodiment, there are four methods for clock recovery and data synchronization of two data streams, including:

[0080] Method 1: The sampling circuit samples the two data streams based on the local clock of the node device, and the first buffer circuit synchronizes the sampled data. The sampling circuit can adjust the phase of the local clock to accurately sample the data.

[0081] Method 2: The clock recovery circuit restores the clock of the two data channels, and the first buffer circuit FIFO1 synchronizes the data after clock recovery. Specifically, the first buffer circuit FIFO1 stores the first received data channel and outputs the two data channels when the other data channel is received to achieve synchronization of the two data channels.

[0082] Method 3: A clock recovery circuit restores the clock of the first data stream to obtain the system clock. A phase detection circuit detects the phase difference between the second data stream and the system clock to obtain a phase difference signal. A numerically controlled delay line performs phase compensation on the second data stream based on the phase difference signal. A sampler samples the compensated second data stream based on the system clock. Ultimately, the data obtained by clock recovery of the first data stream through the clock recovery circuit and the data obtained by sampling the compensated second data stream based on the system clock through the sampler are synchronized.

[0083] Method 4: A clock recovery circuit restores the clock of the first data stream to obtain the system clock. A phase detection circuit detects the phase difference between the second data stream and the system clock to obtain a phase difference signal. A phase interpolator adjusts the phase of the system clock and the first data stream based on the phase difference signal. A sampler samples the second data stream based on the phase-adjusted system clock. Ultimately, the data obtained by phase adjustment of the system clock and the first data stream using the phase interpolator and the sampler are synchronized with the data obtained by sampling the second data stream based on the phase-adjusted system clock.

[0084] In one embodiment, the communication of data transmission from the host to the external device 1 is taken as an example (the communication of data transmission from the external device 1 to the host is in the opposite direction to the communication of data transmission from the host to the external device 1).

[0085] Combination Figure 9 and Figure 1 As shown, the signal sent by the host is divided into two data streams by the distribution unit of the first node device and transmitted to the first port TRXA and the second port TRXB of the first node device.

[0086] The two data streams are transmitted from the first node device to the second node device via the first port TRXA and the second port TRXB.

[0087] The two data streams, Aport data and Bport data, are transmitted to the synchronization unit of the second node device through the first port TRXA and the second port TRXB.

[0088] The synchronization unit of the second node device performs clock recovery and data synchronization for the two data streams, Aport data and Bport data. The specific clock recovery and synchronization method for the two data streams, Aport data and Bport data, is described above.

[0089] The synchronized data is integrated by the integration unit of the second node device, and the integrated data is sent to the external device 1 through the output unit.

[0090] Additionally, the distribution unit of the first node device will distribute the signal sent by the host into another path and transmit it to the third port TRXC of the first node device. The third port TRXC of the first node device will then transmit the data to the third node device.

[0091] Combination Figure 7As shown, when the third port TRXC of the first node device receives the data Cport data sent by the third node device, it will be clocked through the third clock recovery circuit CDR_C and sent to the integration unit for integration processing through the second buffer circuit FIFO2.

[0092] In one embodiment, different communication methods can be configured between the first node device and the second node device. When initiating initialization, the first node device can configure the link to operate in full-duplex or half-duplex mode. When operating in full-duplex mode, the first node device can select either the first port TRXA or the second port TRXB as the downlink port to send data. At this time, one of the first port TRXA and the second port TRXB of the second node device will receive data, while the other port will not receive data. The second node device then determines that data has been received on a single line, which indicates full-duplex mode. Data transmission is carried out synchronously on both cables, one uplink and one downlink. The second node device then sends a response frame through the other cable that has not received data. After receiving the signal, the first node device can confirm that the handshake is complete, and the two node devices can then conduct normal full-duplex communication.

[0093] When operating in half-duplex mode, the first node device will synchronously send data through its first port TRXA and second port TRXB. At the same time, the second node device will receive data simultaneously through its first port TRXA and second port TRXB. The second node device then determines that data has been received on both lines, thus entering half-duplex mode. The two cables synchronously transmit uplink and downlink data in a time-division manner. The second node device will synchronously send response frames through both cables. After receiving the signal, the first node device can confirm that the handshake is complete, and the two nodes can then communicate normally in half-duplex mode.

[0094] Example 2

[0095] In one embodiment, such as Figure 10As shown, the synchronization unit includes a clock recovery circuit (CDR), a phase detector circuit (Phase detector), a digitally controlled delay line (DCDL), and a sampler. The CDR recovers the clock from the first data received by the node device to obtain the system clock. The Phase detector detects the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The DCDL performs phase compensation on the second data based on the phase difference signal. The sampler samples the compensated second data based on the system clock. The data combiner unit is connected to the sampler and the CDR to combine the two data streams. In one embodiment, data Aport data is selected as the first data stream, and data Bport data is selected as the second data stream. In other embodiments, data Bport data is selected as the first data stream, and data Aport data is selected as the second data stream.

[0096] In half-duplex mode, any data channel can be selected as the main channel, or a data channel with better signal quality can be selected. The clock recovery circuit (CDR) locks to the data rate of the main channel, generating a stable system clock. The phase detector detects the phase of the data from the other data channel and obtains the phase difference between the data and the system clock. The digitally controlled delay line (DCDL) compensates for the phase of the data, and after sampling by the system clock, the data is integrated with the data from the main channel.

[0097] Example 3

[0098] In one embodiment, such as Figure 11As shown, the synchronization unit includes a clock recovery circuit (CDR), a phase detection circuit (Phasedetector), a phase interpolator, and a sampler. The CDR recovers the clock from the first data received by the node device to obtain the system clock. The Phase Detector detects the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The Phase Interpolator adjusts the phase of the system clock and the first data based on the phase difference signal. The Sampler samples the second data based on the phase-adjusted system clock. The Data Combiner unit is connected to the Sampler and the Phase Interpolator to combine the two data streams. In one embodiment, data Aport data is selected as the first data stream, and data Bport data is selected as the second data stream. In other embodiments, data Bport data is selected as the first data stream, and data Aport data is selected as the second data stream.

[0099] In half-duplex mode, either data channel can be selected as the main channel, or a data channel with better signal quality can be selected. The clock recovery circuit (CDR) locks to the data rate of the main channel, generating a stable system clock. The phase detector detects the phase of the data from the other data channel and obtains the phase difference between the data and the system clock. The phase interpolator delays the system clock and the data on the main channel to obtain a clock signal that can accurately sample the data from the other channel. After sampling by the sampler, the data from the two channels are integrated.

[0100] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0101] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A communication system, characterized in that, include: At least two node devices, each having a first port and a second port, are designated as a first node device and a second node device, respectively. The first and second ports of the first node device are connected to the first and second ports of the second node device via communication cables. The first and second ports of the node devices are configured to: send data to or receive data from the second node device via the first and second ports of the first node device; or send data to or receive data from the second node device via the first port of the first node device and receive data from the second node device via the second port of the first node device; or send data to or receive data from the second node device via the first port of the first node device and send data to the second node device via the second port of the first node device; or send data to or receive data from the second node device via the first port of the first node device and receive data from the second node device via the second port of the first node device; or send data to or receive data from the second node device via the first port of the first node device and send data to the second node device via the first port of the first node device. The node device includes a synchronization unit and an integration unit. The synchronization unit is used to synchronize two data streams received by the first port and the second port of the node device. The integration unit is used to integrate the two data streams output by the synchronization unit and output the integrated data to an external device.

2. The communication system according to claim 1, characterized in that, The synchronization unit includes a first sampling circuit, a second sampling circuit, and a first buffer circuit. The first sampling circuit samples one channel of data received from the first port of the node device based on the local clock. The second sampling circuit samples one channel of data received from the second port of the node device based on the local clock. The first buffer circuit is connected to the first sampling circuit and the second sampling circuit. The first buffer circuit is used to synchronize the two channels of data sampled by the first sampling circuit and the second sampling circuit and send them to the integration unit. or The synchronization unit includes a first clock recovery circuit, a second clock recovery circuit, and a first buffer circuit. The first clock recovery circuit is used to restore the clock of one data channel received by the first port of the node device. The second clock recovery circuit is used to restore the clock of one data channel received by the second port of the node device. The first buffer circuit is connected to the first clock recovery circuit and the second clock recovery circuit. The first buffer circuit is used to synchronize the two data channels and send them to the integration unit.

3. The communication system according to claim 1, characterized in that, The synchronization unit includes a clock recovery circuit, a phase detection circuit, a numerically controlled delay line, and a sampler. The clock recovery circuit is used to recover the clock of the first data received by the node device to obtain the system clock. The phase detection circuit is used to detect the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The numerically controlled delay line performs phase compensation on the second data based on the phase difference signal. The sampler performs clock sampling on the compensated second data based on the system clock. The integration unit is connected to the sampler and the clock recovery circuit to integrate the two sampled data streams. or The synchronization unit includes a clock recovery circuit, a phase detection circuit, a phase interpolator, and a sampler. The clock recovery circuit is used to recover the clock of the first data received by the node device to obtain the system clock. The phase detection circuit is used to detect the phase difference between the second data received by the node device and the system clock to obtain a phase difference signal. The phase interpolator is used to adjust the phase of the system clock and the first data based on the phase difference signal. The sampler samples the second data based on the phase-adjusted system clock. The integration unit is connected to the sampler and the phase interpolator to integrate the two data streams.

4. The communication system according to claim 1, characterized in that, The node device includes an allocation unit, which is used to allocate external data received by the node device to each port of the node device.

5. The communication system according to claim 1, characterized in that, The node device also includes a third port, a third clock recovery circuit, and a second buffer circuit. The third clock recovery circuit is used to restore the clock of the data received by the third port of the node device and write it into the second buffer circuit. The integration unit of the node device is used to integrate the data output by the synchronization unit and the second buffer circuit of the node device. The third port of the node device is used to connect with subsequent node devices via communication cables to form a daisy-chain cascade structure.

6. The communication system according to claim 2, characterized in that, The first buffer circuit is used to store the first received data and simultaneously output the two data streams when the second data stream is received.

7. The communication system according to claim 1, characterized in that, The node device further includes a mapping unit, a first cache unit, a second cache unit, and a data exchange unit. The mapping unit is used to sort the integrated data based on the mapping relationship and alternately write it to the first cache unit and the second cache unit. The data exchange unit is used to alternately read the data in the first cache unit and the second cache unit and send it to one or more external devices.

8. A node device, characterized in that, The node device includes a first port and a second port. The first port and the second port of the node device are connected to another node device via a communication cable. The first port and the second port of the node device are configured to: send data to or receive data from the other node device; or send data to or receive data from the other node device via the first port and receive data from the other node device via the second port; or send data to or receive data from the other node device via the first port and send data from the other node device via the second port; or send data to or receive data from the other node device via the second port and send data from the other node device via the first port; or send data to or receive data from the other node device via the second port and send data from the first port.

9. The node device according to claim 8, characterized in that, The node device also includes a third port, which is connected to subsequent node devices via communication cables to form a daisy-chain cascade structure.

10. A communication method, characterized in that, Based on the communication system according to any one of claims 1 to 7, the communication method includes: The first and second ports of the node device are configured to receive or send data to the second node device through the first and second ports of the first node device, or send or receive data to the second node device through the first port of the first node device and receive data sent by the second node device through the second port of the first node device, or send or receive data sent by the first node device through the first port of the first node device and send data to the second node device through the second port of the first node device, or send or receive data sent by the second node device through the second port of the first node device and receive data sent by the second node device through the first port of the first node device, or send or receive data sent by the second node device through the second port of the first node device and send data to the second node device through the first port of the first node device; After receiving two data streams at the first and second ports of the current node device, the two data streams are synchronized. The synchronized data is integrated and output.

11. The communication method according to claim 10, characterized in that, Synchronizing the two data streams includes: The sampling circuit samples data from two channels based on a local clock, and the sampled data is synchronized by the first buffer circuit; or The clock is restored to the two data streams using a clock recovery circuit, and the restored data is synchronized using a first buffer circuit; or The system clock is obtained by restoring the clock of the first data stream using a clock recovery circuit. A phase difference signal is obtained by detecting the phase difference between the second data stream and the system clock using a phase detection circuit. Phase compensation is performed on the second data stream based on the phase difference signal using a digitally controlled delay line. Finally, the compensated second data stream is sampled based on the system clock using a sampler. The system clock is obtained by restoring the clock of the first data channel through a clock recovery circuit. The phase difference signal is obtained by detecting the phase difference between the second data channel and the system clock through a phase detection circuit. The phase difference signal is used to adjust the phase of the system clock and the first data channel through a phase interpolator. The second data channel is sampled by a sampler based on the phase-adjusted system clock.

12. The communication method according to claim 10, characterized in that, The communication method includes: Configure the link to work in full-duplex or half-duplex mode by configuring the first node device; When the device is selected to work in full-duplex mode, the first node device selects either its first port or its second port as the downlink port and sends data through that port. The second node device receives data through one of its first port and its second port, and sends a response frame to the first node device through the other port. After the first node device receives the response frame, it confirms that the handshake is complete, and the two node devices can communicate normally in full-duplex mode. When the device is selected to work in half-duplex mode, data is sent synchronously through the first port and the second port of the first node device. Data is received simultaneously through the first port and the second port of the second node device, and a response frame is sent synchronously. After the first node device receives the response frame, it confirms that the handshake is complete, and the two node devices can communicate normally in half-duplex mode.

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