Data unloading and frame reconstruction optimization method and system for high-speed Ethernet

Abstract

The invention is suitable for the technical field of high-speed Ethernet communication, and provides a data unloading and frame reconstruction optimization method and system for a high-speed Ethernet, and the method comprises the steps: packaging to-be-transmitted data into a UDP frame in an FPGA, calculating a checksum, and forming a complete UDP frame; packaging the UDP frame into an IP data packet, then packaging the IP data packet into an Ethernet frame, and controlling splicing of the frames; the packaged Ethernet frame is cached in a Frame FIFO (First In First Out); the format is further converted through a data format conversion module; scrambling the data, and carrying out serial transmission; at a receiving end, descrambling the received data and converting the format; analyzing the Ethernet frame layer by layer through a receiving state machine, and separating IP data or ARP data; the IP data are further analyzed, and UDP data are extracted and transmitted to the data processing module; according to the invention, the Ethernet transmission rate can be greatly improved, and the dependence on hardware is reduced.

Description

Technical Field

[0001] This invention relates to the field of high-speed Ethernet communication technology, specifically a method and system for optimizing data offloading and frame reconstruction in high-speed Ethernet. Background Technology

[0002] In the field of high-speed Ethernet communication technology, the 10G Ethernet Subsystem is widely used for receiving, parsing, and transmitting Ethernet data. This system encapsulates the Physical Layer (PHY) and the Media Access Control (MAC) layer, which communicate via the XGMII bus. The PHY layer includes the Physical Coding Sublayer (PCS) and the Physical Media Adaptor (PMA). The MAC standardizes the user-side interface, providing an AXI4-Stream interface for user-side Ethernet data transmission and reception control, and also an AXI4-Lite interface for protocol conversion of the MDIO management interface. Users can configure the PHY layer through this interface. The system selects 10GBASE-R (optical module interface). The Ethernet receiver module includes 10gEth_RX, DATA_FIFO, and TKEEP_FIFO. The 10gEth_RX submodule parses Ethernet data through finite state machine transitions. This module's finite state machine includes five states. Based on the states of the finite state machine, the effective Ethernet data length is counted, and it is determined whether the length meets the service data length requirements. If the requirements are met, the calculated frame length is stored in FIFO_LEN for use in encapsulating AOS frames; otherwise, the Ethernet packet is discarded. When calculating the Ethernet frame length, the data is stored in RAM_DATA.

[0003] The Ethernet data frame header is determined based on the enable signal for received data, and frame length counting begins. The 10 Gigabit Ethernet receiver module receives 64 bits of data per clock cycle, with a frame length equal to eight times the length of a gigabit data frame in the same cycle. Therefore, the frame length count result of the 10 Gigabit receiver module needs to be shifted. After reception, it is also determined whether the service data exceeds the AOS frame length range. If it does, the Ethernet data packet is cleared; otherwise, the Ethernet data and TKEEP data value are stored. During downlink data transmission, the Ethernet transmitter module primarily handles the transmission of Ethernet data from the FPGA to the PC. The 10 Gigabit transmitter module includes a 10gDATA_TX module and three FIFOs. The FIFO is used to buffer data. 10gFIFO_TX_DATA primarily stores Ethernet data after AOS frame decapsulation, 10gFIFO_TX_LEN primarily stores the current Ethernet frame length, and 10gFIFO_TX_TKEEP primarily stores the TKEEP value of the last time period of the current Ethernet frame. This module, upon detecting the completion of the AOS frame decapsulation operation, reads data from one clock cycle in 10gFIFO_TX_LEN and uses this data to read the stored data in 10gFIFO_TX_DATA, ensuring the transmission of a complete Ethernet data frame. According to the timing design of the 10G EthernetSubsystem transmitter AXI4-Stream interface, when the transmitter module detects the presence of Ethernet data in 10gFIFO_TX_DATA (i.e., when the FIFO empty signal is high), it begins reading data from one clock cycle in 10gFIFO_TX_LEN and 10gFIFO_TX_TKEEP and assigns the data from the output port to the register variable. Based on the register frame length variable, Ethernet data is correctly sent to the 10G Ethernet Subsystem core via the tx_data[63:0] interface. Simultaneously, tx_data_valid is set high, and tx_data_tkeep is assigned the value "FF". When sending the last valid Ethernet data byte, tx_data_tlast is set high, and the TKEEP register variable is assigned to the tx_data_tkeep interface. User data enters the MAC layer through the AXI4-Stream at the 10G Ethernet Subsystem core's transmitter, then enters the PCS / PMA sublayer module via the XGMII bus, and finally transmits data to the external SFP 10 Gigabit optical port module via the GTX transceiver, ultimately achieving high-speed transmission of 10 Gigabit Ethernet data.

[0004] However, current Ethernet systems are limited in processing speed and cannot be used for higher-speed Ethernet data transmission. They are also highly dependent on hardware and lack portability. Therefore, there is an urgent need to provide a data offloading and frame reconstruction optimization method and system for high-speed Ethernet to overcome the shortcomings in current practical applications. Summary of the Invention

[0005] The purpose of this invention is to provide a method and system for optimizing data offloading and frame reconstruction in high-speed Ethernet, effectively solving the problems mentioned in the background art.

[0006] This invention is implemented as follows: a data offloading and frame reconstruction optimization method for high-speed Ethernet, the method comprising the following steps: Inside the FPGA, the data to be transmitted is encapsulated into UDP frames, the checksum is calculated, and a complete UDP frame is formed. The UDP frame is encapsulated into an IP packet, then into an Ethernet frame, and the splicing is controlled by sending a state machine. The encapsulated Ethernet frames are buffered in a Frame FIFO; The data format conversion module converts AXIS format data to XGMII format, and then further converts it to 64B / 66B format; The 64B / 66B format data is scrambled and then serialized and transmitted via a high-speed transceiver. At the receiving end, the received data is descrambled and converted to XGMII format, and then converted to AXIS format; By receiving the state machine, Ethernet frames are parsed layer by layer to separate IP data or ARP data; The IP data is further parsed to extract UDP data and transmit it to the data processing module.

[0007] As a further aspect of the present invention: the calculation steps of the checksum are as follows: The pseudo header, UDP header, and UDP data are added together in 16-bit format. If a carry occurs, 1 is added. The final result is inverted to obtain the checksum.

[0008] As a further aspect of the present invention: the transmitting state machine includes the following states: Initial state, write header state, write load state, and write final load state; The initial state waits for the UDP frame header to arrive. After the frame header arrives, it jumps to the write header state, in which the IP header is formed. Then it jumps to the write payload state, which is used to encapsulate the UDP layer data into IP data. After receiving data, it jumps to the write last payload state, waiting for the arrival of the last frame of data. After receiving the last frame of data, it jumps back to the initial state.

[0009] As a further aspect of the present invention: the data format conversion module uses a linear feedback shift register (LFSR) and cyclic redundancy check (CRC) to scramble and descramble 64B / 66B format data.

[0010] As a further aspect of the present invention: the linear rate calculation formula for the high-speed transceiver is as follows: ; in, For 10Gbps, the calculated It is 10.3125Gbps.

[0011] As a further aspect of the present invention: the reference clock frequency of the high-speed transceiver is determined by the following formula: ; The data rate is 10Gbps, and the calculated Requested reference clock is 156.25MHz. The actual reference clock is: ; The requested reference clock is 156.25MHz, and the calculated actual reference clock is 161.1328125MHz.

[0012] As a further aspect of the present invention: the receiving state machine includes the following states: Initial state, read header state, read load state, read last load state, and waiting for last data state; In the initial state, based on the valid header signal, the system waits to receive the Ethernet frame header. After receiving the frame header, it jumps to the read header state. In the read header state, read the IP header information and calculate the checksum. If the version and length information of the IP header are correct, jump to the read payload state. If it is a bad frame, jump to the read last payload state. The load status is used to read the data portion of the IP and calculate the checksum, and then form an AXI-format IP packet for transmission. After detecting the last data of the payload in the Read Last Payload state, the system stops receiving new payloads, starts transmitting IP data, and jumps to the initial state. If the last data is not detected, the system returns to the Read Last Payload state until the last data is detected. If an error occurs but the data frame has not been completely received, the system jumps to the Wait for Last Data state until the last data of the payload is received, and then jumps to the IDLE state.

[0013] A data offloading and frame reconstruction optimization system for high-speed Ethernet, for implementing the above method, the system comprising: The transmitting FPGA is used for data encapsulation and format conversion. The receiving FPGA is used for data parsing and format conversion. Optical fiber transmission medium, connecting the transmitting end and the receiving end; The photoelectric conversion module enables the mutual conversion between optical signals and electrical signals.

[0014] As a further aspect of the present invention: the transmitting FPGA includes a UDP encapsulation module, an IP encapsulation module, an Ethernet encapsulation module, a data format conversion module, a scrambling module, and a high-speed transceiver module.

[0015] As a further aspect of the present invention: the receiving FPGA includes a descrambling module, a data format reverse conversion module, an Ethernet parsing module, an IP parsing module, a UDP parsing module, and a high-speed receiver module.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention improves the data frame receiving and sending modules within an FPGA by processing data in layers according to the data frame structure, which significantly increases Ethernet transmission speed. Furthermore, all modules are implemented in Verilog, reducing hardware dependency. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 A top-level design block diagram for an existing 10G Ethernet network; Figure 2 For the existing 10 Gigabit receiver module state machine; Figure 3 Design a block diagram for an existing 10 Gigabit Ethernet transmission module; Figure 4 The existing submodule MAC_TX is a finite state machine; Figure 5 This is a block diagram of the Ethernet transmission system in this invention; Figure 6 This is the state machine for sending IP modules in this invention; Figure 7 This is the receiving state machine of the receiving IP module in this invention. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The present invention will be further explained below with reference to specific embodiments.

[0021] Please see Figures 4-7 This invention provides a method and system for optimizing data offloading and frame reconstruction in high-speed Ethernet. The method includes the following steps: Inside the FPGA, the data to be transmitted is encapsulated into UDP frames, the checksum is calculated, and a complete UDP frame is formed. The UDP frame is encapsulated into an IP packet, then into an Ethernet frame, and the splicing is controlled by sending a state machine. The encapsulated Ethernet frames are buffered in a Frame FIFO; The data format conversion module converts AXIS format data to XGMII format, and then further converts it to 64B / 66B format; The 64B / 66B format data is scrambled and then serialized and transmitted via a high-speed transceiver. At the receiving end, the received data is descrambled and converted to XGMII format, and then converted to AXIS format; By receiving the state machine, Ethernet frames are parsed layer by layer to separate IP data or ARP data; The IP data is further parsed to extract UDP data and transmit it to the data processing module.

[0022] In this embodiment, after the data to be transmitted is generated inside the FPGA, it is encapsulated into a UDP frame in the data module and a checksum is calculated. The pseudo header, UDP header, and UDP data are added in 16-bit format. If a carry occurs, 1 needs to be added. The final value is inverted to obtain the checksum. The calculated checksum is filled into the corresponding positions to form a complete UDP frame to be sent. Then, the sending UDP module concatenates the data according to the corresponding positions of the fields, using the sending state machine to combine the UDP header and UDP data into IP data, and then adds the IP header to form the IP layer data. The sending state machine is as follows: Figure 6As shown, the initial state waits for the arrival of the UDP frame header; after the frame header arrives, it jumps to the write header state, in which the IP header is formed; then it jumps to the write payload state, which is used to encapsulate the UDP layer data into IP data; after receiving begins, it jumps to the write last payload state, waiting for the arrival of the last frame of data, and after receiving is completed, it jumps back to the initial state. Then, in the IP sending module, the IP header and IP data are merged into Ethernet data and an Ethernet frame header is added. The data encapsulation method is the same as... Figure 6 The state machine is similar. Then, a complete Ethernet frame is formed in the transmit eth module, and subsequently buffered in the transmit FIFO. This FIFO uses a frame FIFO mode, storing data in units of frames. Then, the data format conversion module adds SFD, PRB, and FCS to the sent data frame to encapsulate it into MAC layer data, and converts the AXIS format data into XGMII format data. The data then enters the data format conversion module to convert the XGMII format data into 64B / 66B format data, and the scrambling module scrambles the 64B / 66B format data using a linear feedback shift register (LFSR) and cyclic redundancy check (CRC). The scrambled data is transmitted through a high-speed transceiver, where SerDes (Serializer / Deserializer) performs serial-to-parallel conversion and clock recovery, corresponding to the PMA (Physical Medium Attachment) layer in an Ethernet system. Within the FPGA, the UltraScale FPGAs Transceivers Wizard IP core simplifies the configuration and use of the GTH high-speed transceiver. Finally, the serial data is output to the optoelectronic conversion module. This optoelectronic conversion module replaces the PMD (Physical Media Dependent) layer in the Ethernet system to achieve optoelectronic / electro-optical conversion, enabling high-speed data transmission over optical fiber. The formula for calculating the linear rate of the high-speed transceiver is as follows: ; in, For 10Gbps, the calculated It is 10.3125Gbps; The reference clock frequency of the high-speed transceiver is determined by the following formula: ; The data rate is 10Gbps, and the calculated Requested reference clock is 156.25MHz. The actual reference clock is: ; The requested reference clock is 156.25MHz, and the calculated actual reference clock is 161.1328125MHz. Data is transmitted via optical fiber to the receiving FPGA board, where a photoelectric conversion module converts the optical signal into an electrical signal, which is then transmitted to the FPGA chip. The receiving FPGA then parses the Ethernet data layer by layer. In the FPGA chip, serial data is converted into parallel data for reception through a high-speed transceiver, and 64B / 66B format data is output. The 64B / 66B format data is descrambled by the descrambling module using a linear feedback shift register (LFSR) and cyclic redundancy check (CRC). Then, the 64B / 66B format data is converted into XGMII format data by the data format conversion module. The data format conversion module removes SFD, PRB, and FCS from the received data and converts the XGMII format data to AXIS format data. After the conversion is completed, the data is buffered in the receiving FIFO, which also adopts the FrameFIFO mode. The eth module decomposes the Ethernet frame header and outputs Ethernet data, determining whether it is IP data or ARP data. If it is ARP data, it then enters the arp module to decompose the ARP header and output the ARP data to the data processing module for processing; if it is IP data, it enters the ip module to decompose the IP header and output the IP data. The state machine inside the receiving IP module, such as Figure 7As shown, there are five states in total: In the initial state, based on the valid header signal, it waits to receive the Ethernet frame header (destination MAC address, source MAC address, and type). After receiving the header, it jumps to the read header state. In the read header state, it reads the IP header information and calculates the checksum. If the IP header version and length information are correct, it jumps to the read payload state; if it is a bad frame, it jumps to the read last payload state. The read payload state is used to read the IP data portion, calculate the checksum, and form an AXI-format IP packet for subsequent transmission. In the read last payload state, after detecting the last data in the payload, it stops receiving new payloads, starts transmitting IP data, and jumps back to the initial state. If the last data is not detected, it returns to the read last payload state until the last data is detected. If an error occurs (IP version and length mismatch, checksum error) but the current frame data has not been completely received, it jumps to the wait for last data state until the last data in the payload is received, and then jumps to the IDLE state. Then, the receiving UDP module decomposes the UDP header and transmits the UDP data to the data processing module for processing.

[0023] This method is used for Ethernet frame composition, data transmission, and data offloading. It enables data transmission between FPGAs at rates up to 100Gbps. This transmission method requires optical fiber as the transmission medium, and its maximum transmission rate is affected by the type of optical module and the FPGA chip model. The method processes data hierarchically according to the Ethernet data frame structure, converting common Ethernet hardware circuits into Verilog modules that run internally within the FPGA. It has less dependence on external hardware circuits, is applicable to various FPGA board models, and offers higher portability. Figure 5 This is a block diagram of an Ethernet transmission system.

[0024] Please see Figures 4-7 This invention also provides a data offloading and frame reconstruction optimization system for high-speed Ethernet, used to implement the above-described method. The system includes: The transmitting FPGA is used for data encapsulation and format conversion. The receiving FPGA is used for data parsing and format conversion. Optical fiber transmission medium, connecting the transmitting end and the receiving end; The photoelectric conversion module enables the mutual conversion between optical signals and electrical signals.

[0025] The transmitting FPGA includes a UDP encapsulation module, an IP encapsulation module, an Ethernet encapsulation module, a data format conversion module, a scrambling module, and a high-speed transceiver module; the receiving FPGA includes a descrambling module, a data format reverse conversion module, an Ethernet parsing module, an IP parsing module, a UDP parsing module, and a high-speed receiver module.

[0026] In summary, this invention improves the data frame receiving and sending modules within the FPGA by processing data in layers according to the structure of the data frames, which greatly increases the Ethernet transmission rate. Furthermore, all modules are implemented in Verilog, reducing the dependence on hardware.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for optimizing data offloading and frame reconstruction in high-speed Ethernet, characterized in that, The method includes the following steps: Inside the FPGA, the data to be transmitted is encapsulated into UDP frames, the checksum is calculated, and a complete UDP frame is formed. The UDP frame is encapsulated into an IP packet, then into an Ethernet frame, and the splicing is controlled by sending a state machine. The encapsulated Ethernet frames are buffered in a Frame FIFO; The data format conversion module converts AXIS format data to XGMII format, and then further converts it to 64B / 66B format; The 64B / 66B format data is scrambled and then serialized and transmitted via a high-speed transceiver. At the receiving end, the received data is descrambled and converted to XGMII format, and then converted to AXIS format; By receiving the state machine, Ethernet frames are parsed layer by layer to separate IP data or ARP data; The IP data is further parsed to extract UDP data and transmit it to the data processing module.

2. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The steps for calculating the checksum are as follows: The pseudo header, UDP header, and UDP data are added together in 16-bit format. If a carry occurs, 1 is added. The final result is inverted to obtain the checksum.

3. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The sending state machine includes the following states: Initial state, write header state, write load state, and write final load state; The initial state waits for the UDP frame header to arrive. After the frame header arrives, it jumps to the write header state, in which the IP header is formed. Then it jumps to the write payload state, which is used to encapsulate the UDP layer data into IP data. After receiving data, it jumps to the write last payload state, waiting for the arrival of the last frame of data. After receiving the last frame of data, it jumps back to the initial state.

4. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The data format conversion module uses a linear feedback shift register and cyclic redundancy check to scramble and descramble 64B / 66B format data.

5. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The formula for calculating the linear rate of the high-speed transceiver is as follows: ； in, The calculated value is 10Gbps. It is 10.3125Gbps.

6. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The reference clock frequency of the high-speed transceiver is determined by the following formula: ； The data rate is 10Gbps, and the calculated Requested reference clock is 156.25MHz. The actual reference clock is: ； The requested reference clock is 156.25MHz, and the calculated actual reference clock is 161.1328125MHz.

7. The data offloading and frame reconstruction optimization method for high-speed Ethernet according to claim 1, characterized in that, The receiving state machine includes the following states: Initial state, read header state, read load state, read last load state, and waiting for last data state; In the initial state, based on the valid header signal, the system waits to receive the Ethernet frame header. After receiving the frame header, it jumps to the read header state. In the read header state, read the IP header information and calculate the checksum. If the version and length information of the IP header are correct, jump to the read payload state. If it is a bad frame, jump to the read last payload state. The load status is used to read the data portion of the IP and calculate the checksum, and then form an AXI-format IP packet for transmission. After detecting the last data of the payload in the Read Last Payload state, the system stops receiving new payloads, starts transmitting IP data, and jumps to the initial state. If the last data is not detected, the system returns to the Read Last Payload state until the last data is detected. If an error occurs but the data frame has not been completely received, the system jumps to the Wait for Last Data state until the last data of the payload is received, and then jumps to the IDLE state.

8. A data offloading and frame reconstruction optimization system for high-speed Ethernet, characterized in that, For implementing the method of any one of claims 1-7, the system is characterized in that it comprises: The transmitting FPGA is used for data encapsulation and format conversion. The receiving FPGA is used for data parsing and format conversion. Optical fiber transmission medium, connecting the transmitting end and the receiving end; The photoelectric conversion module enables the mutual conversion between optical signals and electrical signals.

9. The data offloading and frame reconstruction optimization system for high-speed Ethernet according to claim 8, characterized in that, The transmitting FPGA includes a UDP encapsulation module, an IP encapsulation module, an Ethernet encapsulation module, a data format conversion module, a scrambling module, and a high-speed transceiver module.

10. The data offloading and frame reconstruction optimization system for high-speed Ethernet according to claim 8, characterized in that, The receiving FPGA includes a descrambling module, a data format inversion conversion module, an Ethernet parsing module, an IP parsing module, a UDP parsing module, and a high-speed receiver module.

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