Method for processing ultra-flat silicon wafer and silicon wafer
By constructing a morphology feedback control loop and a chemical mechanical polishing equipment with multi-region adjustable pressure control, the problem of poor global flatness consistency of silicon wafers was solved, and high-yield production of ultra-flat silicon wafers was achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- QL ELECTRONICS SCI QUZHOU CO LTD
- Filing Date
- 2026-04-01
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, the poor global flatness consistency of silicon wafers leads to low yield of ultra-flat silicon wafers, which cannot meet the requirements of large-scale mass production.
By constructing a morphology feedback control loop, the initial morphology consistency is actively shaped, and precise correction is made in stages and zones. A chemical mechanical polishing device with multi-zone adjustable pressure control is used to achieve active compensation polishing of the global morphology.
It significantly improved the processing yield of ultra-flat silicon wafers from less than 1% to over 50%, enabling large-scale, economical production.
Smart Images
Figure CN121946286B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, specifically to a processing method and a silicon wafer for an ultra-flat silicon wafer, particularly to an ultra-flat silicon wafer with a global flatness (GBIR) of <60nm. Background Technology
[0002] With the development of advanced semiconductor processes (such as 5 nanometers and below), chip manufacturing has placed extremely stringent requirements on the global back surface referenced ideal plane range (GBIR) and the site front surface referenced least sQuares range (SFQR) of silicon substrates. Among these, the demand for ultra-flat silicon wafers (usually referring to global back surface referenced ideal plane range < 60nm) has increased dramatically.
[0003] Currently, the standardized process flow for 12-inch polished wafers typically employs a double-sided polishing (DSP) followed by single-sided chemical mechanical polishing (CMP). In existing technologies, especially in silicon wafer development for advanced processes, there exists a prevalent and deeply ingrained technical bias: the belief that the core optimization goal of the DSP process should prioritize ensuring optimal surface flatness (SFQR) to meet the extreme requirements of uniform topography within minute areas in processes such as photolithography. Guided by this bias, process developers tend to use a single, fixed recipe in the DSP stage designed to minimize SFQR.
[0004] However, the inventors' in-depth research revealed that this "prioritizing SFQR optimization" strategy often sacrifices control over the overall silicon wafer topography (GBIR) consistency. Due to inherent fluctuations in silicon wafer material, stress distribution, and equipment conditions, a DSP process that prioritizes optimizing local SFQR may achieve good local flatness in some wafers, but the overall topography (such as bowl-shaped or saddle-shaped) of the processed wafers exhibits significant inconsistencies and unpredictability. Specifically, this manifests as huge differences in GBIR values and their radial profiles between different wafers, and even between wafers in the same batch.
[0005] The inconsistency in the overall morphology of the silicon wafers after DSP (Digital Semiconductor Processing) presents a fundamental challenge to the subsequent critical CMP (Chemical Mechanical Polishing) correction process. Existing CMP processes typically employ a fixed, single-pressure formulation. When a fixed CMP removal profile is applied to a batch of silicon wafers with varying initial global morphologies and discrete GBIR (GBIR) values (typically scattered across a wide range of 100nm to 300nm), its correction effect is inevitably limited and random. As a result, the proportion of silicon wafers ultimately meeting the ultra-flat GBIR < 60nm specification is extremely low, with a yield typically around 0.5%, failing to meet the economic requirements for large-scale mass production.
[0006] Therefore, there is an urgent need in this field for a new method that can overcome the above-mentioned technical biases and solve the problem of global morphology consistency control of silicon wafers from a system level, so as to achieve high yield and stable production of ultra-flat silicon wafers. Summary of the Invention
[0007] The purpose of this invention is to overcome the biases and shortcomings of existing technologies and provide a method for processing ultra-flat silicon wafers and the resulting ultra-flat silicon wafers. This method constructs a topography feedback control loop, abandoning the traditional priority optimization SFQR, and builds a silicon substrate flatness control model that achieves initial topography uniformity in the early stage and precise correction by grading and partitioning in the later stage, thereby achieving an order-of-magnitude improvement in the yield of ultra-flat silicon wafer processing.
[0008] To achieve the above-mentioned objectives, the present invention adopts the following technical solution.
[0009] A method for processing ultra-flat silicon wafers, the core of which lies in constructing a feedback control system that achieves high-yield ultra-flat silicon wafers through morphology stabilization, digital parameter grading, and finally customized grading and precise regional correction. First, a stable and predictable initial morphology is actively shaped in the DSP stage. Then, "feedforward" identification is performed through measurement grading. Finally, in the CMP stage, a preset "feedback" correction formula that precisely matches the identification results is invoked to achieve active compensation polishing of the global morphology. Specifically, the following steps are performed sequentially:
[0010] Step 1, Active formation of the initial morphology:
[0011] Double-sided polishing (DSP) is performed on the silicon wafer. In this step, the traditional parameter settings aimed at optimizing a single local flatness (SFQR) are abandoned, and instead, the priority is to obtain a highly consistent standard bowl-shaped global morphology. By synergistically adjusting the two key process parameters, polishing pad gap (GAP) and silicon wafer back pressure (SK), the overall deformation and material removal distribution of the silicon wafer are controlled, so that the DSP-processed silicon wafer not only forms a standard bowl-shaped morphology where the central region is slightly lower than the edge region (as shown in the attached figure). Figure 1The diagram shown illustrates the ideal bowl-shaped morphology of a silicon wafer after DSP processing in an embodiment of the present invention. Furthermore, the Global Flatness Indicator (GBIR) value is stably controlled within a preset, relatively wide first range, i.e., the GBIR value of the silicon wafer after DSP processing is within a certain range. min To GBIR max Within the range, where 60≤GBIR min <GBIR max The initial morphology should be ≤140nm to ensure a relatively consistent initial morphology; preferably, the GBIR value of the silicon wafer processed by DSP should be between 60 nm and 120 nm. This step aims to provide a batch of silicon wafers with consistent initial morphology characteristics for subsequent processing, laying a predictable and consistent morphology foundation for subsequent precise correction of differences.
[0012] Step 2, Quantitative identification and classification of morphological parameters:
[0013] After the initial morphology shaping step and before the final chemical mechanical polishing (CMP), a 100% inspection geometric parameter measurement step is introduced. A non-contact optical morphology measuring instrument is used to quantify and obtain the global flatness (GBIR) value of each silicon wafer. Subsequently, based on the different GBIR values, the silicon wafers are sorted to different CMP process paths. Specifically, multiple grading intervals are established based on the magnitude of the GBIR value. For example, silicon wafers with GBIR values in the range of 60nm to 120nm are divided into at least two, preferably four, consecutive and non-overlapping grading intervals, according to the values from smallest to largest.
[0014] First level (A level): GBIR value is 60 nm≤GBIR≤75 nm;
[0015] Second setting (B setting): GBIR value at 75 nm <GBIR ≤ 90 nm;
[0016] Third level (C level): GBIR value at 90 nm <GBIR≤105 nm;
[0017] Fourth setting (D setting): GBIR value at 105 nm <GBIR≤120 nm。
[0018] This sorting step quantifies and classifies the initial morphological differences of silicon wafers, providing precise input conditions for subsequent customized processing.
[0019] Step 3, Customized morphology correction based on grading:
[0020] This step is crucial for achieving ultra-flat silicon wafers. A chemical mechanical polishing (CMP) system equipped with multi-zone, independently pressure-controlled polishing heads is used. For each specific zone determined in the above-mentioned grading steps, a uniquely corresponding multi-zone pressure formula is pre-set and stored.
[0021] Each pressure formulation defines a specific combination of pressures applied to multiple pressure control zones (e.g., zones Z5 to Z1) of the polishing head from the center region to the edge region. All pressure formulations share the characteristic that their set pressure values increase progressively from the center region to the edge region of the polishing head, thereby gradually increasing the material removal rate of the silicon wafer during the CMP process from the center to the edge, achieving targeted compensatory polishing of the standard bowl-shaped morphology.
[0022] Furthermore, for wafers with higher initial GBIR values (i.e., more pronounced bowl-shaped morphology), the pressure formulation applied to the edge region of the polishing head exerts a higher pressure than the formulation used for wafers with lower initial GBIR values. For example, the fourth pressure formulation designed for fourth-grade (D-grade) wafers has a higher set pressure in the outermost edge zone (Z1) than the first pressure formulation designed for first-grade (A-grade) wafers in the corresponding edge zone. This differentiated pressure setting results in differentiated edge removal, ensuring that wafers with different initial morphologies can be corrected to the same ultra-flat specification with GBIR < 60 nm.
[0023] The present invention also provides an ultra-flat silicon wafer prepared according to the above processing method, wherein the ultra-flat silicon wafer is a polished silicon wafer with a GBIR value of less than 60nm, especially a large-size polished silicon wafer of 12 inches.
[0024] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:
[0025] This invention proactively compensates for fluctuations in materials and previous processes through a control logic of "morphology shaping - identification and grading - grading and zoning with multi-formula customization and correction," thus solving the fundamental problem that traditional fixed-formula processes cannot cope with morphological differences.
[0026] The technical effect is improved by orders of magnitude: This method increases the processing yield of ultra-flat silicon wafers from less than 1% to more than 50%, making large-scale and economical production of ultra-flat silicon wafers possible.
[0027] Synergistic effect of front and back processes: The "stability" of step 1 is the premise of effective "grading" in step 2, and the "precise grading" of step 2 is the basis for achieving "precise correction" in step 3. The three constitute an organic whole, producing a synergistic effect far exceeding the simple superposition of each part. Attached Figure Description
[0028] Figure 1This is a schematic diagram of the ideal bowl-shaped morphology of the silicon wafer after DSP processing in various embodiments of the present invention.
[0029] Figure 2 This is a pressure response curve diagram of the multi-zone adjustable pressure polishing head used in the CMP step of various embodiments of the present invention. In the figure, the horizontal axis "radial position of silicon wafer" refers to the distance from the center of the silicon wafer; the vertical axis "removal amount" refers to the amount of material removed from the surface of the silicon wafer by polishing; the title "Pressure Response Curve" refers to the pressure response curve of the polishing head area.
[0030] Figure 3 This is a comparison chart of the radial standardized removal rate curves of silicon wafers corresponding to four different CMP pressure formulations in Example 1 of the present invention. In the figure, "Recipe 1", "Recipe 2", "Recipe 3" and "Recipe 4" refer to "first pressure formulation", "second pressure formulation", "third pressure formulation" and "fourth pressure formulation", respectively.
[0031] Figure 4 A schematic diagram of the morphology of the silicon wafer after CMP processing in Embodiment 1 of the present invention. Detailed Implementation
[0032] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. The following embodiments are provided to better understand the present invention, but not to limit its scope of protection.
[0033] Example 1
[0034] This embodiment employs the method of preparing ultra-flat silicon wafers based on morphology grading and pressure control using multiple formulations, as described in this invention, to perform a polishing process on the silicon wafer. The goal of this embodiment is to process a 12-inch (300mm) ultra-flat silicon wafer with a final GBIR value of less than 60nm. The specific steps are as follows:
[0035] Step 1, DSP fabrication and shape control:
[0036] Prepare silicon wafers that have undergone previous processing steps, including slicing, grinding, chamfering, and cleaning. Use a double-sided polishing machine (DSP) to perform double-sided polishing on the silicon wafers. By adjusting the GAP and SK values of the DSP machine, the output pressure of the fixed platen is kept within the range of UPAC: 28-30 bar and LPAC: 0.83-0.87 bar. This ensures that the polished silicon wafers have a standard bowl-shaped morphology and GBIR < 120 nm. Figure 1The diagram illustrates the ideal bowl-shaped morphology of the silicon wafer obtained after DSP processing in various embodiments of the present invention. The key to this step lies in adjusting the process parameters polishing pad gap (GAP) and silicon wafer back pressure (SK), abandoning the traditional approach of pursuing only the optimal single indicator, and instead prioritizing ensuring that the silicon wafer forms a stable and consistent standard bowl-shaped morphology. At this stage, the consistency of the bowl-shaped morphology is far more important than the specific value of GBIR, as it forms the basis for subsequent precise compensation.
[0037] Step 2, Geometric parameter testing and classification:
[0038] Following the DSP process, a high-precision silicon wafer topography measuring instrument is used. In this embodiment, a KLA Surfscan is used to test the geometric parameters of each silicon wafer, employing 100% inspection to obtain its GBIR value. Based on the GBIR measurement results, the silicon wafers are precisely divided into four grades:
[0039] First level (A level): GBIR value is 60 nm≤GBIR≤75 nm;
[0040] Second setting (B setting): GBIR value at 75 nm <GBIR ≤ 90 nm;
[0041] Third level (C level): GBIR value at 90 nm <GBIR≤105 nm;
[0042] Fourth setting (D setting): GBIR value at 105 nm <GBIR≤120 nm。
[0043] Step 3, Customized CMP Processing (Core Invention Point)
[0044] This step is crucial for achieving ultra-flat silicon wafers. In this step, CMP processing employs a multi-zone adjustable polishing head. By adjusting the output pressure of each zone of the polishing head, different radial removal curves of the silicon wafer can be obtained, ensuring that the removal amount gradually increases from the center to the edge of the silicon wafer. Its principle is based on... Figure 2 The device characteristics shown Figure 2 The figure shows the pressure response curves of the multi-zone adjustable pressure polishing head used in the CMP step of various embodiments of the present invention. The figure shows the effect of applying high pressure (Z1 high pressure, Z2 high pressure, Z3 high pressure, Z4 high pressure, Z5 high pressure) and low pressure (Z1 low pressure, Z2 low pressure, Z3 low pressure, Z4 low pressure, Z5 low pressure) to different radial positions of silicon wafers (i.e., the "pressure response" characteristics of the equipment) when each zone (a total of 5 zones, Z1, Z2, Z3, Z4, Z5) of the AMAT multi-zone polishing head used in this embodiment is applied individually.
[0045] Based on the aforementioned "pressure response" characteristics of the CMP equipment, four different pressure recipes were designed. Each pressure recipe corresponds to a different GBIR setting in step two. Each setting's recipe progressively increases the edge removal rate, and the increase in edge removal rate must be differentiated from the corresponding setting. Specific parameters are shown in the table below (pressure unit: psi):
[0046]
[0047] When the pressure formulation in the table above is applied to the polishing head, it will form as shown in the table above. Figure 3 The four different radial removal curves are shown. It can be seen that from Recipe 1 to Recipe 4, the relative removal rate (the increase in edge removal amount) at the silicon wafer edge (>100mm from the center) increases significantly. Specifically, Recipe 1 shows a slight increase in edge removal, used to correct the flattest A-grade silicon wafer, avoiding overcorrection. Recipe 4 shows the largest edge removal, used to strongly correct the most pronounced bowl-shaped D-grade silicon wafer, effectively removing its "raised" edges and making the overall shape flatter.
[0048] The graded silicon wafers (A, B, C, and D) were processed using Recipes 1, 2, 3, and 4, respectively, via CMP. The resulting wafer morphology is shown in the diagram below. Figure 4 As shown in the figure, after selecting a suitable CMP recipe, the silicon wafer edge changed from a raised shape to a collapsed shape, and the lowest point of the edge was not lower than the lowest point of the center, ensuring the minimum GBIR value. The statistical results after processing are as follows:
[0049] Grade A silicon wafers can ultimately achieve a GBIR of approximately 37.18nm.
[0050] B-grade silicon wafers can ultimately achieve a GBIR of approximately 43.37nm.
[0051] C-grade silicon wafers can ultimately achieve a GBIR of approximately 49.88nm.
[0052] The final GBIR of D-grade silicon wafers can be reduced to approximately 56.62nm.
[0053] All silicon wafers processed by the method in this embodiment consistently achieve a final GBIR value of less than 60nm, meeting the requirements for ultra-flat silicon wafers. The overall yield is improved from approximately 0.5% using traditional methods to 55%~65%, demonstrating the remarkable effectiveness of this invention.
[0054] Simultaneously, the local flatness (SFQR) and (ESFQR) of the aforementioned silicon wafers after CMP processing were tested. The average SFQR was 16.22nm (26*8mm, EE3mm), and the average ESFQR was 14.36nm (72 sectors@15mm), both showing improvement compared to the average SFQR of 20.28nm and the average ESFQR of 17.71nm after conventional processing. This is because although this processing method prioritizes stable GBIR values during the DSP stage, it maintains a smaller GBIR while ensuring the wafer edges remain flat and do not curl, resulting in a smaller local flatness compared to conventional processing. In the CMP stage, the need to reduce GBIR and the higher edge pressure lead to wafer edge curling, causing some deterioration in local flatness. However, due to the precise control provided by graded processing, the degree of curling is manageable, and the parameter deterioration is limited. Ultimately, the statistical data still outperforms conventional processing.
[0055] Meanwhile, this ultra-flat silicon wafer processing method also provides a solution for silicon wafer processing with ultra-small local flatness requirements. The aforementioned DSP processing method and grading method remain unchanged; only the pressure distribution curve needs to be adjusted during the CMP processing stage to reduce GBIR while ensuring that the edges do not curl (as shown in the attached figure). Figure 4 (If the middle edge is still in a raised state), the SFQR value can be kept as small as possible, making it possible to mass-produce products with SFQR and ESFQR less than 10nm.
[0056] Example 2
[0057] This embodiment employs a simplified and efficient processing method based on two-level partitioning. For certain production lines with high requirements for cost and control efficiency, a simplified partitioning strategy can be adopted. The specific steps are as follows:
[0058] Step 1, DSP processing: Same as in Example 1, the silicon wafer to be processed is a 12-inch silicon wafer that has undergone previous processes such as slicing, grinding, chamfering and cleaning. In this step, the silicon wafer is controlled to form a standard bowl-shaped morphology with GBIR of 60-120nm.
[0059] Step 2, Geometric Parameter Testing and Grading: In this embodiment, the silicon wafers are divided into only two grades:
[0060] Low value range (L range): GBIR values are between 60 nm and 90 nm.
[0061] High value range (H range): GBIR value at 90 nm <GBIR ≤ 120 nm。
[0062] Step 3, CMP processing: The same CMP equipment is used as in Example 1, therefore it is also based on... Figure 2The pressure response characteristics of the equipment shown are designed with two pressure formulations for L and H settings respectively. The design principle is still that the pressure increases from the center to the edge, and the edge pressure (Z1 zone) of the H-set formulation is higher than that of the L-set formulation in this zone.
[0063] L-range formulation: Z5=1.0psi, Z4=1.04psi, Z3=1.08psi, Z2=1.13psi, Z1=2.54psi;
[0064] H-grade formulation: Z5=1.0psi, Z4=1.08psi, Z3=1.18psi, Z2=1.23psi, Z1=2.88psi.
[0065] After processing using this method, the final GBIR of both L-grade and H-grade silicon wafers can be corrected to <60nm. Although the overall yield (approximately 50%) is slightly lower than the four-grade classification in Example 1, it is still a significant improvement compared to the 0.5% yield of the traditional fixed-formula method, proving that even with simplified classification, the method of this invention can still achieve significantly better results than traditional technologies.
[0066] Example 3
[0067] This embodiment employs a more refined grading system to meet the specific customer's requirement for ultra-high yield (>70%) of ultra-flat silicon wafers with GBIR < 50nm. The implementation steps are as follows.
[0068] DSP fabrication: Same as in Example 1, the distribution range of GBIR is narrowed to 60-120nm to ensure the consistency of the initial morphology.
[0069] Geometric parameter testing and grading: More refined six-grading: Grade 1 (60-70nm), Grade 2 (70-80nm), Grade 3 (80-90nm), Grade 4 (90-100nm), Grade 5 (100-110nm), Grade 6 (110-120nm).
[0070] CMP processing: Six pressure gradient formulations, divided into Z1 to Z5 zones, were designed for each gear level. The Z1 zone pressures for gears 1 to 6 were set as follows: 2.40 psi, 2.53 psi, 2.66 psi, 2.80 psi, 2.92 psi, and 3.05 psi, respectively. This embodiment achieves "micron-level" correction of the morphology through more precise matching, enabling accurate control of edge collapse after processing.
[0071] Through the more refined graded matching process in this embodiment, more than 60% of the silicon wafers finally meet the stringent requirement of GBIR < 50nm, and the overall yield of meeting GBIR < 60nm is improved to over 75%.
[0072] It should be noted that the specific pressure parameters in the above embodiments are merely examples. Those skilled in the art can make adaptive adjustments based on the actual equipment model, polishing fluid type, and other conditions, while adhering to the core inventive concept of "gradually increasing pressure from the center area to the edge area, and using a recipe with higher edge pressure for silicon wafers with larger initial GBIR." All such adjustments should fall within the protection scope of this invention.
[0073] The above embodiments are intended to illustrate the essential content of the present invention, but are not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the essence and scope of protection of the present invention.
Claims
1. A method for processing ultra-flat silicon wafers, characterized in that, Includes the following steps: Step S1: Perform double-sided polishing (DSP) on the incoming silicon wafer. Adjust the process parameters to form a bowl-shaped morphology on the silicon wafer, and control the global flatness (GBIR) of the double-sided polished silicon wafer within the GBIR range. min To GBIR max Within the range; where 60≤GBIR min <GBIR max ≤140nm; the incoming silicon wafer refers to the wafer to be polished that has at least completed the cutting and grinding process; Step S2: Measure the geometric parameters of the silicon wafer after the processing in step S1, and divide the silicon wafer into at least two grades according to the measured GBIR values. Step S3: Based on the silicon wafer grading results, chemical mechanical polishing (CMP) is performed using a corresponding multi-zone pressure formulation. The multi-zone pressure formulation refers to controlling the pressure of the polishing heads in different zones to make the material removal amount at the edge of the silicon wafer greater than that in the center zone, thereby correcting the bowl-shaped morphology and ultimately ensuring that the silicon wafer meets the requirements of an ultra-flat silicon wafer after CMP processing, i.e., the GBIR value of the silicon wafer is less than 60nm. In step S3, different multi-zone pressure formulations are used to process silicon wafers of different grades using different grades; and the edge removal capability of the multi-zone pressure formulations corresponding to grades with GBIR values from small to large also increases accordingly.
2. The method of processing an ultra flat silicon wafer of claim 1, wherein, The global flatness (GBIR) of the double-sided polished silicon wafer is controlled between 60nm and 120nm.
3. The method of processing an ultraflat silicon wafer of claim 2 wherein, In step S2, the silicon wafers are divided into four grades based on their GBIR values: Category A: 60nm ≤ GBIR ≤ 75nm; Category B: 75nm < GBIR ≤ 90nm; Category C: 90nm <GBIR ≤ 105nm; D-mode: 105nm < GBIR ≤ 120nm.
4. The processing method for ultra-flat silicon wafers according to claim 3, characterized in that, In step S3, for silicon wafers of grades A, B, C, and D, the first pressure formulation, the second pressure formulation, the third pressure formulation, and the fourth pressure formulation with increasing edge removal capability are respectively adopted.
5. The method of processing an ultra flat silicon wafer of claim 4, wherein, The multi-zone polishing head has at least five independent pressure control zones distributed from the center to the edge, namely Z5, Z4, Z3, Z2, and Z1; the first pressure formula to the fourth pressure formula all satisfy the following: the set pressure increases stepwise from zone Z5 to zone Z1.
6. The method of processing an ultra flat silicon wafer of claim 5, wherein, The pressure set in the Z1 region for the fourth pressure formulation is greater than the pressure set in the Z1 region for the first pressure formulation.
7. The method for processing ultra-flat silicon wafers according to claim 1, characterized in that, In step S1, the adjusted process parameters include the polishing pad gap (GAP) and the silicon wafer back pressure (SK).
8. The method of claim 1, wherein the thickness of the silicon wafer is 50- 200 μm. The ultra-flat silicon wafers processed by the method are 12-inch silicon wafers.
9. The method of claim 1, wherein the thickness of the silicon wafer is 50- 200 μm. After processing using the method described above, the processing yield of ultra-flat silicon wafers with GBIR values less than 60nm reaches over 50%.
10. A silicon wafer, characterized by, The silicon wafer is an ultra-flat silicon wafer prepared by the processing method according to any one of claims 1-9, wherein the GBIR value of the silicon wafer is less than 60nm.