Quantum capacitor chip testing device and system for testing state density and manufacturing method
By designing a quantum capacitor chip testing device and constructing an electrolytic cell on a substrate using photolithography and etching techniques, the problem of measuring the density of states of materials at room temperature and pressure using traditional testing methods has been solved, achieving efficient and low-cost measurement of the density of states of materials.
Patent Information
- Application Number
- CN202610103050.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-26
- Publication Date
- 2026-05-01
AI Technical Summary
Traditional methods for testing the density of states of materials have limitations in conventional research and production fields, including stringent conditions, cumbersome processes, and limited applicability. They cannot efficiently test the density of states of materials at room temperature and pressure.
Design a quantum capacitor chip testing device, including a substrate, metal electrodes, an insulating layer and an electrolytic cell structure. The metal electrodes are formed on the substrate by photolithography or etching, and an insulating layer is deposited on it. An electrolytic cell is constructed to contain the electrolyte to realize the measurement of the material density of states.
It simplifies the material density of states testing process, reduces testing costs and pollution risks, and enables high-throughput density of states testing at room temperature and pressure, capable of measuring complete information on conduction band, valence band, Fermi surface and defect states.
Smart Images
Figure CN121955658A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of material characterization device technology, and in particular to a quantum capacitor chip testing device, system, and fabrication method for testing the density of states. Background Technology
[0002] Traditional methods for testing the density of states in materials primarily utilize large-scale equipment such as angle-resolved photoelectron spectroscopy (ARPES) and scanning tunneling spectroscopy (STS). While these methods provide high-resolution electronic structure density of states information, they suffer from limitations such as demanding sample preparation requirements and harsh testing environments (e.g., ultra-high vacuum, low temperature), restricting their widespread application in routine research and production. Furthermore, some research fields can combine general-purpose equipment such as UPS ultraviolet photoelectron spectroscopy, X-ray photoelectron spectroscopy, and photoluminescence spectroscopy for testing and comprehensive analysis. However, these methods are cumbersome, carry a high risk of damage, and are difficult to test at the same point on the same material. They also only provide information on the conduction band, valence band, and Fermi level, failing to obtain defect state information.
[0003] In summary, traditional testing methods are subject to stringent conditions, involve cumbersome processes, have high requirements for test materials, and are applicable to limited scenarios. Therefore, there is an urgent need for a material density of states testing technology suitable for normal temperature and pressure operating environments. Summary of the Invention
[0004] The main objective of this invention is to provide a quantum capacitor chip testing device, system, and manufacturing method for testing the density of states, aiming to enable the testing of material density of states at room temperature and pressure.
[0005] To achieve the above objectives, the present invention provides a quantum capacitance chip testing device for testing the density of states, comprising a substrate, metal electrodes, an insulating layer, and an electrolytic cell structure, wherein, One side surface of the substrate is used to deposit the test material. The metal electrode is made of metal and is formed on top of the test material by photolithography or etching. One end of the metal electrode is connected to the test material. The insulating layer is deposited on top of the metal electrode and the test material, covering all the test material and some metal electrodes. A test window is formed in the middle of the insulating layer. No insulating layer is set at the test window. The test window is located on top of the test material. The electrolytic cell structure is bonded to the insulating layer and accommodates the test window inside it. The interior of the electrolytic cell structure is hollow to accommodate the electrolyte.
[0006] Preferably, the substrate includes a base layer and a surface insulating layer located on the surface of the base layer. The base layer is a monocrystalline silicon substrate, an optically transparent rigid insulating substrate, or a flexible polymer substrate, and the surface insulating layer is an insulating layer composed of silicon oxide or silicon nitride.
[0007] Preferably, the metal electrode adopts a single metal layer or a stacked structure of two metals selected from Au, V, Cr, Cu, Ti, Ga, In, and Ag. The fabrication of the metal electrode includes patterning and metal deposition. Patterning is performed by ultraviolet lithography or electron beam etching, and metal deposition is achieved by physical vapor deposition.
[0008] Preferably, the thickness of the metal electrode is 2 nm to 10 µm; and the thickness of the insulating layer is 10 nm to 500 µm.
[0009] Preferably, the material to be tested includes graphene or transition metal dichalcogenides, and the material to be tested is prepared by mechanical exfoliation, chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition.
[0010] Preferably, when the insulating layer is made of an organic material, its preparation process includes: spin coating, pre-baking curing, ultraviolet exposure through a mask, development to form the insulating layer and test window, and post-baking to finally cure the insulating layer; when the insulating layer is made of an inorganic material, the preparation process adopts a stripping method: first, a temporary mask is covered in the area where the test window is to be formed; then, inorganic insulating material is deposited by magnetron sputtering on the entire substrate surface to form an insulating layer; finally, the temporary mask is removed by dissolution, and the inorganic insulating material on top of it is stripped off, thereby forming an insulating layer structure with a test window.
[0011] The present invention also proposes a quantum capacitor chip testing system for testing density of states, including the aforementioned quantum capacitor chip testing device for testing density of states, and further including electrodes and an external testing circuit electrically connected thereto. The electrodes include a working electrode, a counter electrode, and a reference electrode. The counter electrode and the reference electrode are inserted into the electrolyte of the quantum capacitor chip testing device, and the working electrode is electrically connected to the metal electrode of the quantum capacitor chip testing device.
[0012] The present invention further proposes a method for fabricating a quantum capacitance chip testing device for testing state density based on the above, comprising the following steps: The test material is transferred to the central region of the substrate surface, and a metal electrode is formed on the test material by photolithography or etching so that the metal electrode is deposited on the substrate surface and one end of the metal electrode is connected to the test material. An insulating layer is formed above the metal electrode, covering all the test material and the local metal electrode. A test window is formed by removing part of the insulating layer through photolithography or etching in the middle of the insulating layer. The test window is located above the material to be tested, and the area of the test window is smaller than the flat area of the material to be tested. An electrolytic cell structure is bonded above the insulating layer, and the electrolytic cell structure encloses the test window in its internal chamber.
[0013] Preferably, the step of forming a metal electrode on the test material by photolithography or etching, so that the metal electrode is deposited on the substrate surface and one end of the metal electrode is connected to the test material specifically includes: spin-coating a release agent and a photoresist onto the test material in sequence, performing photolithography and development by ultraviolet light, depositing metal in sequence, using a solvent to dissolve the photoresist and peel off the excess metal to form a metal electrode, and connecting one end of the metal electrode to the test material.
[0014] Preferably, the material to be tested is transferred to the substrate surface by mechanical exfoliation or chemical vapor deposition; the electrolyte is sulfuric acid, hydroxymethyl ferrocene solution or ionic liquid, and the electrolyte volume is 0.01 ml to 300 ml.
[0015] The quantum capacitance chip testing device for testing state density proposed in this invention has the following beneficial effects: 1. This quantum capacitance chip testing device can measure the quantum capacitance and convert it into the density of states of the material by photolithography and deposition of test circuits on a chip loaded with material, constructing an electrolytic cell and connecting it to an external test circuit; 2. This quantum capacitor chip testing device can also measure complete information on the conduction band, valence band, Fermi surface, and defect states. It can also incorporate various external field control analyses such as electrical, mechanical, optical, thermal, magnetic, and electrochemical fields, which greatly simplifies the material density of states testing process, reduces testing costs, shortens the testing cycle, and avoids the risk of processing contamination, thus realizing high-throughput working condition density of states testing technology.
[0016] 3. This quantum capacitor chip testing device has the advantages of simple structure, easy and convenient manufacturing, and stable operation. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the quantum capacitor chip testing device for testing the density of states according to the present invention; Figure 2 The graph shows the quantum capacitance curves obtained by testing graphene materials using the quantum capacitance chip testing device for testing the density of states according to the present invention. Figure 3a This is a schematic diagram of the structure of the quantum capacitance chip testing device for testing state density of the present invention when transferring the material to be tested on the substrate; Figure 3b This is a schematic diagram of the structure of the quantum capacitance chip testing device for testing the density of states of the present invention when metal electrodes are formed on the substrate. Figure 3c This is a schematic diagram of the quantum capacitor chip testing device for testing state density of the present invention when an insulating layer is formed on the substrate; Figure 3dThis is a schematic diagram of the structure of the quantum capacitance chip testing device for testing state density of the present invention when a test window is formed on the insulating layer; Figure 3e This is a schematic diagram of the structure of the quantum capacitor chip testing device for testing the density of states of the present invention when an electrolytic cell structure is installed on the insulating layer; Figure 3f This is a schematic diagram of the structure of the quantum capacitor chip testing device for testing the density of states according to the present invention after the electrodes are inserted.
[0018] In the figure, 1-substrate; 2-external test circuit; 3-material under test; 4-metal electrode; 5-insulating layer; 6-test window; 7-electrolyte; 8-electrolytic cell structure; 9-counter electrode; 10-reference electrode; 11-working electrode.
[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation
[0020] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
[0021] It should be noted that in the description of this invention, the terms "lateral," "longitudinal," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0022] This invention proposes a quantum capacitor chip testing device for testing the density of states.
[0023] In this preferred embodiment, a quantum capacitance chip testing device for testing state density includes a substrate 1, a metal electrode 4, an insulating layer 5, and an electrolytic cell structure 8, wherein... One side surface of substrate 1 is used to deposit the test material 3. A metal electrode 4, made of metal and formed on top of the test material 3 using photolithography or etching, has one end connected to the test material 3. An insulating layer 5 is deposited on top of the metal electrode 4 and the test material 3, covering all of the test material 3 and parts of the metal electrode 4. A test window 6 (i.e., an electrochemical reaction window) is formed in the middle of the insulating layer 5. No insulating layer 5 is present at the test window 6, which is located above the test material 3. An electrolytic cell structure 8 is bonded to the insulating layer 5 and houses the test window 6 within it. The interior of the electrolytic cell structure 8 is hollow and used to accommodate the electrolyte 7. The area of the test window 6 is smaller than the area of the test material 3, and the vertical projection area of the test window 6 towards substrate 1 is all located on the test material 3.
[0024] Specifically, in this embodiment, the substrate 1 includes a substrate layer and a surface insulating layer located on the surface of the substrate layer. The substrate layer is a single-crystal silicon substrate, an optically transparent rigid insulating substrate, or a flexible polymer substrate, and the surface insulating layer is an insulating layer composed of silicon oxide or silicon nitride.
[0025] The test material 3 includes graphene or transition metal dichalcogenides, and is prepared by mechanical exfoliation, chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition. Before testing, the structure and defects of the test material 3 can be engineered using processes such as van der Waals force stacking, heat treatment, plasma etching, heavy metal ion bombardment, and ion implantation. The test material 3 can be transferred onto the substrate 1 using dry transfer, wet transfer, or other processes for subsequent processing and testing.
[0026] Specifically, in this embodiment, the metal electrode 4 adopts a single metal layer or a stacked structure of two metals selected from Au, V, Cr, Cu, Ti, Ga, In, and Ag. The fabrication of the metal electrode 4 includes patterning and metal deposition. Patterning is achieved using ultraviolet lithography or electron beam etching, and metal deposition is achieved using physical vapor deposition (PVD). The size and pattern of the metal electrode 4 can be independently designed according to different materials.
[0027] Furthermore, the thickness of the metal electrode 4 is 2 nm to 10 µm; the thickness of the insulating layer 5 is 10 nm to 500 µm. The size of the substrate 1 is 1 cm. 2 Any size between 2 inches is acceptable. In this embodiment, substrate 1 is cut into 4 cm pieces. 2 A square.
[0028] Electrolyte 7 is sulfuric acid (which can be 0.5 mol / L), hydroxymethyl ferrocene solution, or ionic liquid, and the volume of electrolyte 7 is 0.01 ml to 300 ml.
[0029] In this embodiment, the insulating layer 5 can be made of PMMA, SU-8 type photoresist, silicon oxide, or silicon nitride type inorganic insulating layer 5. The insulating layer 5 needs to cover the material to be tested 3 and part of the metal electrode 4. When the insulating layer 5 is made of organic material, its preparation process includes: spin coating, pre-baking curing, ultraviolet exposure through a mask, development to form the insulating layer 5 and the test window 6, and post-baking to finally cure the insulating layer 5. When the insulating layer 5 is made of inorganic material, the preparation process adopts the stripping method: first, a temporary mask is covered in the area where the test window 6 is to be formed; then, inorganic insulating material is deposited by magnetron sputtering on the entire surface of the substrate 1 to form the insulating layer 5; finally, the temporary mask is removed by dissolution, and the inorganic insulating material on top of it is stripped off, thereby forming the insulating layer 5 structure with the test window 6.
[0030] Specifically, in this embodiment, the electrolytic cell structure 8 is a PDMS annular gasket with an outer diameter of 1 cm to 2 cm, an inner diameter of 0.3 cm to 1 cm, and a thickness of 5 mm to 20 mm. The PDMS annular gasket is placed on the substrate 1 and pressed tightly with a glass plate to ensure a leak-free seal with the substrate 1 and that the reaction window is located at the center of the PDMS annular gasket. After pressing, the glass plate is removed. The PDMS annular gasket has inherent adhesiveness, thus adhering to the substrate 1. The quantum capacitance curve obtained by testing the graphene material using this quantum capacitance chip testing device is shown below. Figure 2 As shown.
[0031] The quantum capacitance chip testing device for testing state density proposed in this invention has the following beneficial effects: 1. This quantum capacitance chip testing device can measure the quantum capacitance and convert it into the density of states of the material by photolithography and deposition of test circuits on the chip loaded with material, constructing an electrolytic cell and connecting it to an external test circuit 2. 2. This quantum capacitor chip testing device can also measure complete information on the conduction band, valence band, Fermi surface, and defect states. It can also incorporate various external field control analyses such as electrical, mechanical, optical, thermal, magnetic, and electrochemical fields, which greatly simplifies the material density of states testing process, reduces testing costs, shortens the testing cycle, and avoids the risk of processing contamination, thus realizing high-throughput working condition density of states testing technology.
[0032] 3. This quantum capacitor chip testing device has the advantages of simple structure, easy and convenient manufacturing, and stable operation.
[0033] The present invention also proposes a quantum capacitor chip testing system for testing the density of states.
[0034] In this preferred embodiment, a quantum capacitor chip testing system for testing state density includes a quantum capacitor chip testing device for testing state density, and further includes electrodes and an external testing circuit 2 electrically connected thereto. The electrodes include a working electrode 11, a counter electrode 9, and a reference electrode 10. The counter electrode 9 and the reference electrode 10 are inserted into the electrolyte 7 of the quantum capacitor chip testing device, and the working electrode 11 is electrically connected to the metal electrode 4 of the quantum capacitor chip testing device. The specific structure and beneficial effects of the quantum capacitor chip testing device are the same as those in the above embodiment, and will not be repeated here.
[0035] Specifically, the working electrode 11 can be bonded using a tungsten carbide probe or wire bonding; the counter electrode 9 can be a Pt metal electrode or a carbon rod; the reference electrode 10 can be Ag / AgCl or other reference electrodes. The Ag / AgCl electrode is obtained through constant current electrodeposition, specifically by immersing a pure Ag wire as the working electrode 11 in an HCl solution and using a commercial Pt electrode as the counter electrode 9 to perform constant current electrodeposition to prepare the Ag / AgCl reference electrode 10. The external testing circuit 2 can be a high-precision electrochemical workstation or a source meter.
[0036] The working process of this quantum capacitor chip testing system for testing the density of states is as follows: 3 mL of electrolyte 7 is injected into the electrolytic cell structure 8. Plating the platinum wire and the homemade Ag / AgCl wire into the electrolyte 7 ensures that neither the platinum wire nor the homemade Ag / AgCl wire comes into contact with the test material 3 and is not short-circuited with the metal electrode 4. A tungsten probe is connected to the metal electrode 4 as the working electrode 11 (WE) and then to the electrochemical workstation; the platinum wire or carbon rod serves as the counter electrode 9 (CE); and the Ag / AgCl serves as the reference electrode 10 (RE). The test can then begin. The bare metal electrode 4 is gently touched with the tungsten probe, and a high-resolution digital camera is used to confirm good contact and the absence of scratches.
[0037] The present invention also proposes a method for fabricating a quantum capacitor chip testing device for testing state density.
[0038] In this preferred embodiment, a method for fabricating a quantum capacitance chip testing device for testing state density, as described above, includes the following steps: Step S10: Transfer the test material 3 to the central region of the surface of the substrate 1, such as... Figure 3a As shown, the area of the test material 3 is smaller than the area of the substrate 1. Then, a metal electrode 4 is formed on the test material 3 by photolithography or etching, so that the metal electrode 4 is deposited on the surface of the substrate 1 and one end of the metal electrode 4 is connected to the test material 3, as shown. Figure 3b As shown; Step S20: An insulating layer 5 is formed above the metal electrode 4. The insulating layer 5 covers all the test material 3 and a portion of the metal electrode 4 (the metal electrode 4 is partially exposed away from the test material 3 for connection with the electrode). Figure 3c As shown; Step S30: A portion of the insulating layer 5 is removed by photolithography or etching to form a test window 6. The test window 6 is located above the material to be tested 3, and the area of the test window 6 is smaller than the flat area of the material to be tested 3 (thus exposing the surface of the material to be tested 3). Figure 3d As shown; In step S40, an electrolytic cell structure 8 is bonded above the insulating layer 5, and the electrolytic cell structure 8 encloses the test window 6 in its internal chamber.
[0039] After installation, electrolyte 7 can be injected into the electrolytic cell structure 8, such as... Figure 3e As shown. During the test, the counter electrode 9 and the reference electrode 10 are inserted into the electrolyte 7, as follows. Figure 3d As shown.
[0040] Specifically, in step S10, the step of forming a metal electrode 4 on the test material 3 by photolithography or etching, so that the metal electrode 4 is deposited on the surface of the substrate 1 and one end of the metal electrode 4 is connected to the test material 3 includes: spin-coating a release agent and a photoresist on the test material 3 in sequence, performing photolithography and development by ultraviolet light, depositing metal in sequence, using solvents such as acetone to dissolve the photoresist and peel off the excess metal to form the metal electrode 4, and connecting one end of the metal electrode 4 to the test material 3.
[0041] The specific parameters for forming the metal electrode 4 are as follows: A release agent is spin-coated onto the substrate 1 containing the transferred material, and the spin-coating speed and time are adjusted to obtain a suitable thickness. Photoresist is then spin-coated onto the dried release agent, while controlling the photoresist thickness, and dried again to prepare for subsequent operations. The patterns of the metal electrode 4 are designed independently for different materials, and then exposed using 405 nm ultraviolet light on a lithography machine. The exposed substrate is then immersed in a developer for 10 seconds to remove the photoresist in the exposed areas and the underlying release agent, forming an undercut structure. Physical vapor deposition (PVD) is used to first deposit 10 nm of Ti to enhance the adhesion between the metal and the SiO2 surface, followed by the deposition of 90 nm of Au to provide the main conductive layer. After deposition, the metallized substrate is immersed in acetone for 1 hour to dissolve the photoresist in the unexposed areas and remove the metal above it, completing the release process. Residual release agent is then removed using NMD-2.38%, ultimately forming the metal electrode 4 with a specific pattern.
[0042] Specifically, the test material 3 is transferred to the surface of the substrate 1 by mechanical exfoliation or chemical vapor deposition. The electrolyte 7 is sulfuric acid, hydroxymethyl ferrocene solution, ionic liquid or other liquid, and the volume of the electrolyte 7 is 0.01 ml to 300 ml.
[0043] When forming the test window 6, if a 4 µm² test window 6 can be designed, first spin-coat SU-8 photoresist onto the patterned metal electrode 4, control the thickness, and dry to form the insulating layer 5. Then, perform a second exposure with 385 nm ultraviolet light, immerse the exposed SU-8 substrate 1 in the developer to expose the reaction window, and bake at 90 °C for 5 min to crosslink the unexposed SU-8 to form an inert insulating layer 5, which is used to isolate the metal electrode 4 from the electrolyte 7 during subsequent electrochemical testing.
[0044] The preparation method proposed in this invention is simple, convenient, and easy to operate. At the same time, the quantum capacitor chip testing device produced has low requirements for testing materials.
[0045] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. Any equivalent structural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A quantum capacitance chip testing device for testing the density of states, characterized in that, It includes a substrate, metal electrodes, an insulating layer, and an electrolytic cell structure, among which, One side surface of the substrate is used to deposit the test material. The metal electrode is made of metal and is formed on top of the test material by photolithography or etching. One end of the metal electrode is connected to the test material. The insulating layer is deposited on top of the metal electrode and the test material, covering all the test material and some metal electrodes. A test window is formed in the middle of the insulating layer. No insulating layer is set at the test window. The test window is located on top of the test material. The electrolytic cell structure is bonded to the insulating layer and accommodates the test window inside it. The interior of the electrolytic cell structure is hollow to accommodate the electrolyte.
2. The quantum capacitance chip testing device for testing state density as described in claim 1, characterized in that, The substrate includes a base layer and a surface insulating layer located on the surface of the base layer. The base layer is a monocrystalline silicon substrate, an optically transparent rigid insulating substrate, or a flexible polymer substrate, and the surface insulating layer is an insulating layer composed of silicon oxide or silicon nitride.
3. The quantum capacitance chip testing device for testing state density as described in claim 1, characterized in that, The metal electrode adopts a single metal layer or a stacked structure of two metals selected from Au, V, Cr, Cu, Ti, Ga, In, and Ag. The fabrication of the metal electrode includes patterning and metal deposition. Patterning is performed by ultraviolet lithography or electron beam etching, and metal deposition is achieved by physical vapor deposition.
4. The quantum capacitance chip testing device for testing state density as described in claim 1, characterized in that, The thickness of the metal electrode is 2 nm to 10 µm; the thickness of the insulating layer is 10 nm to 500 µm.
5. The quantum capacitance chip testing device for testing state density as described in claim 1, characterized in that, The test material includes graphene or transition metal dichalcogenides, and is prepared by mechanical exfoliation, chemical vapor deposition, molecular beam epitaxy, or atomic layer deposition.
6. The quantum capacitance chip testing apparatus for testing state density as described in any one of claims 1 to 5, characterized in that, When the insulating layer is made of organic materials, its preparation process includes: spin coating, pre-baking curing, ultraviolet exposure through a mask, development to form the insulating layer and test window, and post-baking to finally cure the insulating layer. When the insulating layer is made of inorganic materials, the preparation process adopts a stripping method: first, a temporary mask is covered on the area where the test window is to be formed; then, inorganic insulating material is deposited by magnetron sputtering on the entire substrate surface to form an insulating layer; finally, the temporary mask is removed by dissolution, and the inorganic insulating material on top of it is stripped off, thereby forming an insulating layer structure with a test window.
7. A quantum capacitance chip testing system for testing the density of states, characterized in that, The quantum capacitor chip testing device for testing the density of states as described in any one of claims 1 to 6 further includes electrodes and an external testing circuit electrically connected thereto. The electrodes include a working electrode, a counter electrode, and a reference electrode. The counter electrode and the reference electrode are inserted into the electrolyte of the quantum capacitor chip testing device, and the working electrode is electrically connected to the metal electrode of the quantum capacitor chip testing device.
8. A method for fabricating a quantum capacitance chip testing device for testing state density according to any one of claims 1 to 6, characterized in that, Includes the following steps: The test material is transferred to the central region of the substrate surface, and a metal electrode is formed on the test material by photolithography or etching. The metal electrode is laid on the substrate surface and one end of the metal electrode is connected to the test material. An insulating layer is formed above the metal electrode, covering all the test material and the local metal electrode. A test window is formed by removing part of the insulating layer through photolithography or etching in the middle of the insulating layer. The test window is located above the material to be tested, and the area of the test window is smaller than the flat area of the material to be tested. An electrolytic cell structure is bonded above the insulating layer, and the electrolytic cell structure encloses the test window in its internal chamber.
9. The preparation method according to claim 8, characterized in that, The step of forming a metal electrode on the test material by photolithography or etching, depositing the metal electrode on the substrate surface, and connecting one end of the metal electrode to the test material specifically includes: sequentially spin-coating a release agent and a photoresist on the test material, performing photolithography and development by ultraviolet light, depositing metal sequentially, using a solvent to dissolve the photoresist and peel off excess metal to form a metal electrode, and connecting one end of the metal electrode to the test material.
10. The preparation method according to claim 8, characterized in that, The test material is transferred to the substrate surface by mechanical exfoliation or chemical vapor deposition; the electrolyte is sulfuric acid, hydroxymethyl ferrocene solution or ionic liquid, and the electrolyte volume is 0.01 ml to 300 ml.