Closed-loop calibration method, equipment and system for channel delay of digital board card of automatic test equipment

Abstract

The invention relates to a closed-loop calibration method, equipment and system for channel delay of a digital board card of automatic test equipment, and relates to the field of automatic test equipment. Aiming at the problems of high cost, low precision and difficulty in large-scale expansion of the existing calibration scheme, the method comprises the following steps of: establishing electrical connection between a to-be-calibrated channel and an isomorphic reference channel; carrying out multiple self-loop and cross-channel cross transmit-receive measurements on the two to obtain a relative time value; respectively calculating a sending delay deviation and a receiving delay deviation of the to-be-calibrated channel relative to the reference channel based on the measured values; and respectively adjusting the programmable delay units on the channel receiving and transmitting paths according to the deviation so as to align the reference. The device is mainly used for high-speed testing of an integrated circuit, picosecond-level high-precision independent alignment of large-scale channels can be achieved in a closed loop mode in equipment without an external instrument, and the resource utilization rate is high.

Description

Closed-loop calibration method, equipment and system for delay of digital board channels in automated test equipment Technical Field

[0001] This invention belongs to the field of integrated circuit automatic test (ATE) technology, specifically relating to a closed-loop calibration method, equipment, and system for the delay of digital board channels in an automatic test device. Background Technology

[0002] As digital chips evolve towards higher integration and higher operating frequencies, the requirements for signal time-domain alignment accuracy become increasingly stringent. To meet the testing needs of high-speed chips (DUTs), the clock frequency of digital boards in Automatic Test Equipment (ATE) is constantly increasing. However, inherent factors such as the physical size, circuit layout, and cable length of digital boards inevitably lead to differences in signal delay between channels. Without precise AC calibration of the transmission and reception timing between these channels, the overall testing accuracy of the equipment will be severely limited.

[0003] Currently, the commonly used AC calibration solutions in the industry mainly fall into the following three categories:

[0004] The first approach involves cascading multiple independent high-precision signal sources to calibrate the ATE's transmit and receive channels separately. While this method can achieve extremely high precision at the tens of picosecond level, it relies on dedicated equipment costing hundreds of thousands of yuan per unit, and each unit only supports a very limited number of channels, making it completely unsuitable for the large-scale expansion needs of modern ATEs with hundreds or thousands of channels.

[0005] The second method involves calibrating the transmitting channel first using an external oscilloscope, and then using this as a reference to calibrate the receiving channel. While this serial calibration mode improves channel coverage, it is extremely cumbersome and time-consuming. Furthermore, calibration errors at the transmitting end, often in the hundreds of picosecond range, are directly introduced into the calibration at the receiving end, amplifying the error and failing to meet the stringent requirements of high-speed testing.

[0006] The third approach is based on Time Domain Reflectometry (TDR), which uses a Time-to-Digital Converter (TDC) to measure the reflection time difference to compensate for the offset. While this approach offers excellent accuracy, the high-resolution TDC logic consumes a significant amount of critical FPGA resources, limiting the channel density of the digital board and significantly increasing the complexity of the system's underlying design.

[0007] In summary, existing ATE channel delay calibration technologies cannot simultaneously balance calibration channel size, calibration accuracy, resource utilization, and system cost, making it difficult to meet the application requirements of modern high-speed ATE equipment for multi-channel, high-precision, and low-cost timing calibration. Summary of the Invention

[0008] The purpose of this invention is to address the aforementioned problems in the prior art by providing a closed-loop calibration method, device, and system for the channel delay of an automatic test equipment digital board. By establishing an electrical connection between the channel to be calibrated and the isomorphic reference channel within the ATE system, and combining a relative delay algorithm based on four-step interactive timing with a native adjustable delay unit, the independent decoupling and fully closed-loop automatic and accurate alignment of the transmission and reception channel delays are achieved.

[0009] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: A closed-loop calibration method for channel delay of an automatic test equipment digital board includes the following steps: establishing an electrical connection between the channel to be calibrated and a reference channel, wherein the reference channel and the channel to be calibrated have the same hardware architecture; performing multiple self-loop transmit / receive measurements and cross-channel cross-transmit / receive measurements on the channel to be calibrated and the reference channel to obtain multiple relative time measurement values; calculating the transmit delay deviation and receive delay deviation of the channel to be calibrated relative to the reference channel based on the relative time measurement values; and adjusting the programmable delay units on the transmit path and receive path of the channel to be calibrated according to the transmit delay deviation and receive delay deviation, so as to align the timing of multiple channels to be calibrated to a unified reference.

[0010] Furthermore, the steps of performing multiple self-loop transceiver measurements and cross-channel transceiver measurements on the channel to be calibrated and the reference channel specifically include: controlling the channel to be calibrated to send a test signal and receiving it itself to obtain a first measurement value; controlling the reference channel to send a test signal and receiving it itself to obtain a second measurement value; controlling the channel to be calibrated to send a test signal and receiving it from the reference channel to obtain a third measurement value; and controlling the reference channel to send a test signal and receiving it from the channel to be calibrated to obtain a fourth measurement value.

[0011] Further, based on relative time measurements, the steps of calculating the transmission delay deviation and reception delay deviation of the channel to be calibrated relative to the reference channel specifically include: assuming that the transmission delay from the channel to be calibrated to the reference channel is equal to the transmission delay from the reference channel to the channel to be calibrated, half of the difference obtained by subtracting the sum of the second and fourth measurements from the sum of the first and third measurements is used as the transmission delay deviation of the channel to be calibrated relative to the reference channel; and half of the difference obtained by subtracting the sum of the second and third measurements from the sum of the first and fourth measurements is used as the reception delay deviation of the channel to be calibrated relative to the reference channel.

[0012] Furthermore, when there is a situation where the transmission delay from the channel to be calibrated to the reference channel is not equal to the reverse transmission delay, the method also includes obtaining the bidirectional transmission delay difference and introducing the bidirectional transmission delay difference for compensation and correction when calculating the transmission delay deviation and the reception delay deviation.

[0013] Furthermore, the receiving paths of both the channel to be calibrated and the reference channel include a receiver and a comparator. Before performing multiple self-loop transceiver measurements and cross-channel cross-transceiver measurements, the method also includes: aligning and calibrating the high-level output delay and low-level output delay of the comparator in the channel to be calibrated.

[0014] Furthermore, the step of aligning and calibrating the high-level output delay and low-level output delay of the comparator in the channel to be calibrated specifically includes: controlling the channel to be calibrated to automatically transmit and receive high-level pulse signals, adjusting the first delay unit on the receiving path until the receiver successfully captures the high level, and recording the first tap value; controlling the channel to be calibrated to automatically transmit and receive low-level pulse signals, adjusting the first delay unit on the receiving path until the receiver successfully captures the low level, and recording the second tap value; comparing the first tap value and the second tap value, and compensating the independent delay unit corresponding to the high-level output pin or low-level output pin of the comparator according to the difference between the two.

[0015] Furthermore, both the channel to be calibrated and the reference channel are equipped with receivers containing triggers and asynchronous first-in-first-out queues. During the acquisition of relative time measurement values, the method for determining successful reception is as follows: gradually increase the delay amount of the programmable delay unit on the reception path until the results read from the asynchronous first-in-first-out queue are all specific logic levels indicating successful reception. Then, successful reception is determined, and the delay amount at this time is recorded as the corresponding relative time measurement value.

[0016] Furthermore, in the step of adjusting the programmable delay units on the transmission path and reception path of the channel to be calibrated according to the transmission delay deviation and reception delay deviation, the programmable delay units on the transmission path of all channels to be calibrated are adjusted to make the transmission delay deviation values ​​of each channel to be calibrated relative to the reference channel equal; and the programmable delay units on the reception path of all channels to be calibrated are adjusted to make the reception delay deviation values ​​of each channel to be calibrated relative to the reference channel equal.

[0017] An automatic test equipment digital board channel delay calibration system includes: a reference channel module, whose hardware architecture is the same as that of the channel module to be calibrated, and which is electrically connected to the channel module to be calibrated; a measurement control module, used to perform multiple self-loop transmit / receive measurements and cross-channel transmit / receive measurements on the channel module to be calibrated and the reference channel module to obtain multiple relative time measurement values; a deviation calculation module, used to calculate the transmit delay deviation and receive delay deviation of the channel module to be calibrated relative to the reference channel module based on the relative time measurement values; and a delay alignment module, used to adjust the programmable delay units on the transmit path and receive path of the channel module to be calibrated according to the transmit delay deviation and receive delay deviation, so as to align the timing of multiple channel modules to be calibrated to a unified reference.

[0018] An automated test device includes a digital test board and a digital test board channel delay calibration system as described above.

[0019] Compared with the prior art, the present invention has the following significant advantages: 1. Strong channel expansion capability and high testing efficiency: It gets rid of the dependence on external high-precision signal sources or the physical number of oscilloscope channels. It can support parallel and rapid calibration of extremely large-scale (such as 128 channels or more) ATE systems only through internal electrical connections and automated programs, and the expansion capability is exponentially increased.

[0020] 2. Extremely high calibration accuracy and suppression of error accumulation: An innovative relative measurement model completely decouples and independently calibrates the transmit and receive paths, avoiding error propagation and amplification found in traditional oscilloscope solutions. Utilizing the FPGA's native high-resolution delay unit, nanosecond-level channel deviations can be precisely compressed to within ±4.2ps, perfectly meeting the stringent timing requirements of high-speed digital chips.

[0021] 3. Extremely low hardware cost and high resource utilization: The entire calibration process is completed in a closed loop within the ATE, saving hundreds of thousands of yuan in external instrument procurement costs; at the same time, it cleverly reuses idle resources in the FPGA that are usually used for interface fine-tuning (such as IDELAY3), without consuming a lot of core logic (such as LUT, carry chain) to reconstruct complex TDC modules, thus freeing up the channel design density of digital boards.

[0022] 4. Excellent environmental immunity and stability: Utilizing the built-in self-calibration engine (BISC) of the internal delay unit, automatic temperature and voltage drift compensation can be achieved without additional intervention. Even under wide temperature and pressure fluctuations, the channel delay drift can still be strictly controlled within 35ps, which greatly improves the long-term operational consistency in industrial environments. Attached Figure Description

[0023] Figure 1 is an architecture diagram of a high-precision signal source cascade calibration scheme; Figure 2 is an architecture diagram of a serial calibration scheme based on an oscilloscope; Figure 3 is an architecture diagram of a calibration scheme based on TDC and TDR; Figure 4 is an overall architecture diagram of the ATE equipment inter-channel calibration system of the present invention; Figure 5 is a schematic diagram of the transmit / receive path delay principle of the calibration scheme of the present invention; Figure 6 is a hardware architecture diagram of the channel to be calibrated / reference channel of the present invention; Figure 7 is a matching architecture diagram of the IDELAY3 delay unit and IDELAYCTRL; Figure 8 is a linear correspondence curve between IDELAY3 delay value and tap value; Figure 9 is a hardware architecture diagram of the receiver of the present invention; Figure 10 is a flowchart of the working timing and reception determination of the receiver of the present invention; Figure 11 is a simplified flowchart of the ATE digital board channel delay calibration method of the present invention. Detailed Implementation

[0024] This specific embodiment provides a method and system for calibrating the channel delay of an automated test equipment (ATE) digital board. It is applied to the multi-channel timing synchronization calibration of ATE equipment used for mass production testing of high-speed digital chips. It can achieve picosecond-level precision delay calibration for hundreds of channels without relying on external high-precision test instruments, while having extremely low FPGA resource consumption and hardware cost.

[0025] The technical solution, hardware architecture, calibration process, and specific embodiments of the present invention will be described in detail and completely below with reference to the accompanying drawings. Those skilled in the art to which this invention pertains can implement the technical solution of the present invention without creative effort based on the content disclosed in this specification.

[0026] I. Existing Technical Solutions and Core Defects Figure 1 is an architecture diagram of a high-precision signal source cascade calibration scheme. This scheme uses synchronous trigger signals to cascade multiple independent high-precision signal sources, corresponding to channels 0 to N-1 to be calibrated, to achieve transmission edge synchronization. However, its channel expansion capability is limited by the number of signal sources. A single device only supports 2-4 channels, and the hardware cost is as high as hundreds of thousands of yuan per unit, which cannot adapt to the large-scale calibration needs of hundreds or thousands of channels in modern ATE systems.

[0027] Figure 2 shows the architecture of the serial calibration scheme based on an oscilloscope. This scheme first completes the calibration of all the transmitting channels to be calibrated through the oscilloscope calibration system, and then uses the calibrated transmitting channels as a reference to serially calibrate the receiving channels. The calibration process is executed serially, which is cumbersome and time-consuming. Moreover, the calibration error of the transmitting channel on the order of hundreds of picoseconds will be introduced and amplified in the receiving calibration. In the end, the system-level error cannot meet the test accuracy requirements of high-speed digital chips.

[0028] Figure 3 shows the architecture of the calibration scheme based on TDC and TDR. This scheme builds a TDC measurement module and a TDC calibration module in the FPGA. It calculates the channel delay by measuring the round-trip time difference of the reflected signal through time-domain reflection technology. However, its high-resolution TDC module consumes a lot of core logic resources such as LUTs and registers in the FPGA, which directly limits the channel density of the digital board. Moreover, the calibration process of absolute time measurement is highly complex and difficult to implement in engineering.

[0029] II. Hardware Architecture of the Calibration System of the Invention Figure 4 shows the overall architecture of the ATE equipment inter-channel calibration system of the present invention. The calibration system of the present invention is completely deployed inside the ATE equipment, including at least one reference channel and several channels to be calibrated. Channels to be calibrated 0, 1 to N-1 are functional channels on the ATE digital board used for testing the chip under test. Each channel to be calibrated is equipped with a pin electronic unit (PE). The reference channel is also equipped with a pin electronic unit (PE) with hardware parameters and circuit architecture completely identical to the channel to be calibrated. The pin electronic units (PE) of each channel to be calibrated are bidirectionally electrically connected to the pin electronic units (PE) of the reference channel via coaxial lines, forming a complete calibration loop capable of self-loop transmission and reception and cross-channel transmission and reception.

[0030] Figure 5 is a schematic diagram of the transmit / receive path delay principle of the calibration scheme of the present invention. The present invention decomposes the transmission delay of each channel into independent transmit and receive paths, wherein: the transmission delay of the driver in the channel to be calibrated is D. dut The propagation delay of the comparator is C. dut The propagation delay of the driver within the reference channel is D. ref The propagation delay of the comparator is C. ref The signal transmission delay from the channel to be calibrated to the reference channel is T. d_r The signal transmission delay from the reference channel to the channel to be calibrated is T. r_d This invention uses multi-path combined transmit and receive measurements to decouple and calculate the transmission delay deviation (D) of the channel to be calibrated relative to the reference channel. dut With D ref The difference between the received delay and the received delay deviation (C) dut With C ref The difference between the two values ​​is used as a benchmark to complete the timing alignment of the entire channel.

[0031] Figure 6 shows the hardware architecture of the calibration channel / reference channel of the present invention. The calibration channel and the reference channel adopt the same hardware architecture, which mainly includes two parts: FPGA and pin electronics unit (PE). The FPGA contains a transmit timing generator, a receive timing generator, multiple programmable delay units, and a receiver; the pin electronics unit (PE) integrates a driver for signal driving and a comparator for signal acquisition.

[0032] The specific connection relationships are as follows: the output of the transmitting timing generator is connected to the input of the transmitting delay calibration unit IDELAY3_D, and the output of IDELAY3_D is connected to the input of the driver inside the PE; the output of the driver is shorted to the input of the comparator in the same channel, forming a self-loop transceiver circuit, and is also electrically connected to the PE unit of the opposite channel, forming a cross-channel transceiver circuit; the high-level output VOH of the comparator is connected to the input of the high-level delay calibration unit IDELAY3_VOH, and the low-level output VOL of the comparator is connected to the input of the low-level delay calibration unit IDELAY3_VOL; the outputs of both IDELAY3_VOH and IDELAY3_VOL are connected to the input of the receiver, the sampling clock of the receiver is connected to the output of the receiving main delay calibration unit IDELAY3_R, and the input of IDELAY3_R is connected to the output of the receiving timing generator. Through this architecture, pre-calibration of the comparator's high and low level paths, delay adjustment of the transmitting and receiving paths, and accurate measurement can be achieved respectively.

[0033] Figure 7 shows the architecture diagram of the IDELAY3 delay unit and IDELAYCTRL. All programmable delay units in this invention use the IDELAY3 unit built into the Xilinx Ultrascale series FPGA, and are equipped with the IDELAYCTRL calibration control module.

[0034] The IDELAY3 unit is a 512-level programmable delay line that supports delay adjustment for any input signal except the clock signal. Its input ports include the clock signal CLK, input data signal DATAIN, voltage and temperature compensation enable signal EN_VTC, load signal LOAD, 9-bit tap value input signal CNTVALUEIN[8:0], and reset signal RST. The output port is the delayed output data signal DATAOUT. The input ports of the IDELAYCTRL unit are the reference clock signal REFCLK and the reset signal RST. The output port is the ready signal RDY. The IDELAY3 unit operates in TIME-VAR_LOAD mode with a tap value adjustment step of 1. By loading the target tap value through the CNTVALUEIN[8:0] port, the corresponding signal delay can be achieved. The delay resolution of a single tap can be calculated by the formula "delay = single tap resolution × tap value". Meanwhile, the IDELAYCTRL unit drives the built-in self-calibrating BISC engine through REFCLK, which runs continuously in the background to compensate for delay drift caused by voltage and temperature changes, ensuring the long-term stability of delay parameters.

[0035] Figure 8 shows the linear relationship between the IDELAY3 delay value and the tap value. The horizontal axis represents the IDELAY3 tap number, and the vertical axis represents the corresponding actual delay value (Delay value), in ps. The figure clearly shows a strict linear positive correlation between the actual delay value and the tap number. As the tap number increases from 0 to 200, the delay value increases linearly from 0 to approximately 900 ps. This excellent linearity ensures the accuracy and predictability of delay adjustment, providing a reliable hardware foundation for high-precision delay calibration.

[0036] Figure 9 shows the hardware architecture of the receiver of this invention. The receiver is used to determine whether the target pulse signal has been successfully captured, providing a stable basis for delay measurement. Its core components include a D flip-flop (DFF), an asynchronous FIFO, a FIFO controller, and a read interface. The input data port of the D flip-flop is connected to the output signal of the comparator, the sampling clock port of the D flip-flop is connected to the output signal of the receiving timing generator, and the output of the D flip-flop is connected to the data write port Din of the asynchronous FIFO. The write enable port WriteEn, the clear port Clear, and the write clock port Wclk of the asynchronous FIFO are all connected to the corresponding output ports of the FIFO controller. The read enable port ReadEn and the read clock port Rclk of the asynchronous FIFO are connected to the corresponding output ports of the read interface. The data output port Dout and the empty flag port Empty of the asynchronous FIFO are connected to the corresponding input ports of the read interface. The driving clock of the FIFO controller is the system clock, and the output of the read interface is the receiver response output, used to output the FIFO read result.

[0037] Figure 10 is a flowchart of the receiver's operating timing and reception determination process. From top to bottom, the figures show the comparator output signal, IDELAY3_R tap value, IDELAY3_R output signal, and asynchronous FIFO readout result. Initially, the IDELAY3_R tap value is 0, and the sampling edge of its output signal is not aligned with the effective level window of the comparator output signal. The asynchronous FIFO readout result is all 0, indicating a reception failure. Subsequently, the IDELAY3_R tap value is gradually increased, delaying the phase of the sampling clock. When the tap value increases to 4, the sampling edge of the IDELAY3_R output signal is aligned with the high-level window of the comparator output signal, and the asynchronous FIFO readout result is all 1. At this point, the reception is determined to be successful, and the current IDELAY3_R tap value is recorded as the total delay parameter for the corresponding path.

[0038] III. Specific Implementation Steps of the Calibration Method of the Present Invention As shown in Figure 11, the ATE digital board channel delay calibration method of the present invention specifically includes the following steps: Step 1: System Initialization and Electrical Connection Construction Configure one reference channel and N channels to be calibrated in the ATE digital board, ensuring that the hardware architecture and component parameters of the reference channel and all channels to be calibrated are completely consistent; establish a bidirectional electrical connection between the pin electronic unit PE of each channel to be calibrated and the pin electronic unit PE of the reference channel through a coaxial cable, forming a self-loop and cross-channel transmit / receive circuit. Simultaneously, perform a system reset operation, clearing the tap values ​​of all programmable delay units IDELAY3 to zero, and setting the delay codes of the transmit timing generator and receive timing generator to 0, completing the initialization preparation before calibration.

[0039] Step 2: Comparator High and Low Level Output Path Pre-calibration. For each channel to be calibrated, the high-level and low-level output paths of the comparator are first aligned to eliminate inherent process deviations in the two outputs. Specifically, this includes: controlling the transmit timing generator of the channel to be calibrated to generate a high-level pulse signal with a frequency of 200MHz and an amplitude of 3.3V, which is then output by the driver in the PE through the transmit delay calibration unit IDELAY3_D and fed into the input of the comparator through a self-loop loop; gradually adjusting the tap values ​​of the receive main delay calibration unit IDELAY3_R until the asynchronous FIFO readout results of the receiver are all high-level, which is considered a successful high-level reception, and recording the tap value of IDELAY3_R at this time as the first tap value T. VOH (X)=IDELAY3_R(Dut=D dut (X)+C dut_H (X); Control the timing generator of the channel to be calibrated to generate a low-level pulse signal with a frequency of 200MHz and an amplitude of 3.3V. Similarly, gradually adjust the tap value of IDELAY3_R until the receiver stably captures the low-level signal. Record the tap value of IDELAY3_R at this time as the second tap value T. VOL (X)=IDELAY3_R(Dut=D dut (X)+C dut_L (X); Compare the first tap value T VOH (X) and the second tap value T VOL The magnitude of (X): If T VOH (X)>T VOL (X), then set the tap value of IDELAY3_VOL on the comparator low-level path to T. VOH (X)-T VOL (X), the tap value of IDELAY3_VOH on the high-level path is 0, i.e., IDELAY3 VOH (Dut)=0; if T VOL (X)>TVOH (X), then set the tap value of IDELAY3_VOH to T. VOL (X)-T VOH (X), the tap value of IDELAY3_VOL is 0, that is, IDELAY3 VOL (Dut)=0, thus completing the time delay alignment of the high and low level output paths of the comparator.

[0040] Step 3: Multipath Relative Delay Measurement. For each channel to be calibrated after pre-calibration, the corresponding total delay parameter is measured using four different transmit / receive path combinations. Specifically, this includes: First Path Measurement: Control the channel to be calibrated to send a pulse test signal and receive it itself, i.e., the channel to be calibrated transmits and receives itself. Gradually adjust the IDELAY3_R tap value of the channel to be calibrated until successful reception, and record the tap value at this time as the first measurement value T1(X)=IDELAY3_R(Dut)=D dut (X)+C dut T1(X) corresponds to the total delay of the transmission and reception paths of the channel to be calibrated; Second path measurement: Control the reference channel to send a pulse test signal and receive it itself, that is, the reference channel transmits and receives itself, and gradually adjusts the IDELAY3_R tap value of the reference channel until successful reception. Record the tap value at this time as the second measurement value T2, which corresponds to the total delay of the transmission and reception paths of the reference channel; Third path measurement: Control the channel to be calibrated to send a pulse test signal and receive it from the reference channel. Gradually adjust the IDELAY3_R tap value of the reference channel until successful reception. Record the tap value at this time as the third measurement value T3(X)=IDELAY3_R(Ref)=D dut (X)+T d_r (X)+C ref T3(X) corresponds to the total delay of the transmission path of the channel to be calibrated, the cross-channel transmission path, and the reception path of the reference channel; Fourth path measurement: Control the reference channel to send a pulse test signal, which is received by the channel to be calibrated. Gradually adjust the IDELAY3_R tap value of the channel to be calibrated until successful reception, and record the tap value at this time as the fourth measurement value T4(X)=IDELAY3_R(Ref)=D ref +T r_d (X)+C dut (X), T4(X) corresponds to the total delay of the reference channel transmission path, the reverse cross-channel transmission path, and the channel to be calibrated reception path.

[0041] If, during the measurement process, the IDELAY3_R tap value is adjusted to the maximum value of 512 and a valid signal is still not captured, the tap value will be cleared and the measurement process of the corresponding path will be re-executed to avoid measurement failure caused by unstable electrical connection.

[0042] Step 4: Decoupling Calculation of Transmit / Receive Path Delay Deviation. Based on the symmetry of bidirectional transmission on coaxial cables, it is assumed that the transmission delay from the channel to be calibrated to the reference channel is equal to the reverse transmission delay, i.e., T. d_r (X)=T r_d Based on the four sets of measured values ​​T1(X), T2, T3(X), and T4(X), the transmission delay deviation and reception delay deviation of the channel to be calibrated relative to the reference channel are obtained through decoupling calculation: Transmission delay deviation ΔD = D dut (X)-D ref =(T1(X)-T2+T3(X)-T4(X)) / 2; Receive delay deviation ΔC=C dut (X)-C ref =(T1(X)-T2-T3(X)+T4(X)) / 2.

[0043] If the bidirectional transmission delay is unequal due to PCB routing asymmetry or differences in connection structure, the bidirectional transmission delay difference Δt=T can be measured in advance using a vector network analyzer. d_r (X)-T r_d (X), the calculation results are compensated and corrected based on the time delay difference. The corrected formula is: Transmission delay deviation ΔD=(T1(X)-T2+T3(X)-T4(X)-Δt) / 2; Reception delay deviation ΔC=(T1(X)-T2-T3(X)+T4(X)+Δt) / 2.

[0044] Step 5: Multi-channel timing alignment calibration. Based on the calculated transmit delay deviation and receive delay deviation, adjust the programmable delay units of the corresponding channels to be calibrated to align the timing of all channels to be calibrated to the unified reference of the reference channel. Specifically, this includes: Transmit channel alignment: Adjust the tap value of the transmit delay calibration unit IDELAY3_D of each channel to be calibrated to make the transmit delay deviation ΔD of all channels to be calibrated relative to the reference channel equal, so that the transmit path delay of all channels to be calibrated is consistent with the reference channel, completing the timing alignment of all transmit channels; Receive channel alignment: Adjust the tap value of the receive main delay calibration unit IDELAY3_R of each channel to be calibrated to make the receive delay deviation ΔC of all channels to be calibrated relative to the reference channel equal, so that the receive path delay of all channels to be calibrated is consistent with the reference channel, completing the timing alignment of all receive channels.

[0045] At this point, the transmission and reception path delay calibration of all channels to be calibrated is completed, achieving high-precision timing synchronization of multiple channels on the ATE digital board.

[0046] IV. Specific Implementation Examples Example 1 (Typical Mass Production Application Scenario) This example is the standard configuration for mass production of ATE equipment. The specific parameter settings are as follows: The number of channels to be calibrated is N=128, and the number of reference channels is 1; the IDELAY3 unit works in TIME-VAR_LOAD mode, the tap value adjustment step size is 1, the reference clock REFCLK frequency of IDELAYCTRL is configured to 200MHz, and the measured single tap resolution of IDELAY3 is 4.2ps; the frequency of the test pulse signal is 200MHz, and the amplitude is 3.3V; the write and read thresholds of the asynchronous FIFO are both 512. Before calibration, the delay deviation between the 128 channels to be calibrated ranged from -1.38ns to +2.13ns; after calibration, the delay deviation between all channels to be calibrated and the reference channel was controlled within ±4.2ps; within a temperature range of 10℃ to 70℃ and a voltage fluctuation range of 0.95V to 1.05V, the delay drift of the calibrated channels was ≤35ps, which fully meets the mass production testing requirements of consumer-grade and industrial-grade high-speed digital chips.

[0047] Example 2 (High-Resolution Extreme Application Scenarios) This example demonstrates an extreme scenario for testing ultra-high-speed chips. Specific parameter settings are as follows: the number of channels to be calibrated, N=32, and the number of reference channels, =1; the IDELAY3 unit operates in TIME-VAR_LOAD mode, the reference clock REFCLK frequency of IDELAYCTRL is configured to 800MHz, and the measured single-tap resolution of IDELAY3 is 2.5ps; the frequency of the test pulse signal is 400MHz, and the amplitude is 3.3V; the write and read thresholds of the asynchronous FIFO are both 1024. Before calibration, the delay deviation between the 32 channels to be calibrated ranges from -0.8ns to +1.2ns; after calibration, the delay deviation between all channels to be calibrated and the reference channel is controlled within ±2.5ps; under a stable environment of 25℃ room temperature and a rated voltage of 1.0V, the channel delay drift is ≤10ps, suitable for high-precision testing scenarios of ultra-high-speed RF digital chips and high-end processor chips.

[0048] Example 3 (Wide Temperature and Voltage Industrial Application Scenarios) This example demonstrates a wide-environment application scenario for industrial-grade ATE equipment. Specific parameter settings are as follows: the number of channels to be calibrated, N=64, and the number of reference channels, =1; the IDELAY3 unit operates in TIME-VAR_LOAD mode, the reference clock REFCLK frequency of IDELAYCTRL is configured to 400MHz, and the measured single-tap resolution of IDELAY3 is 15ps; the frequency of the test pulse signal is 100MHz, and the amplitude is 3.3V; the write and read thresholds of the asynchronous FIFO are both 256. Before calibration, the delay deviation range between the 64 channels to be calibrated is -2.0ns to +3.0ns; after calibration, the delay deviation between all channels to be calibrated and the reference channel is controlled within ±15ps; within an industrial-grade temperature range of -40℃ to 85℃ and a wide voltage fluctuation range of 0.9V to 1.1V, the channel delay drift is ≤80ps, suitable for wide-environment testing scenarios of industrial-grade and automotive-grade chips.

[0049] The parts of this invention not described in detail are prior art, therefore they are not described in detail here.

[0050] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0051] Although this document uses a considerable amount of technical terminology, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.

[0052] This invention is not limited to the preferred embodiments described above. Anyone can derive other products in various forms under the guidance of this invention. However, regardless of any changes made to their shape or structure, any technical solution that is the same as or similar to this invention falls within the protection scope of this invention.

Claims

1. A method for calibrating the channel delay of an automatic test equipment digital board, characterized in that, Includes the following steps: An electrical connection is established between the channel to be calibrated and a reference channel, which have the same hardware architecture as the channel to be calibrated. Multiple self-loop transceiver measurements and cross-channel transceiver measurements are performed on the channel to be calibrated and the reference channel to obtain multiple relative time measurements. Based on the relative time measurements, the transmission delay deviation and reception delay deviation of the channel to be calibrated relative to the reference channel are calculated respectively. According to the transmission delay deviation and reception delay deviation, the programmable delay units on the transmission path and reception path of the channel to be calibrated are adjusted respectively to align the timing of multiple channels to be calibrated to a unified reference.

2. The automatic test equipment digital board channel delay calibration method according to claim 1, characterized in that, The steps for performing multiple self-loop transceiver measurements and cross-channel transceiver measurements on the channel to be calibrated and the reference channel specifically include: controlling the channel to be calibrated to send a test signal and receiving it itself to obtain a first measurement value; controlling the reference channel to send a test signal and receiving it itself to obtain a second measurement value; controlling the channel to be calibrated to send a test signal and receiving it from the reference channel to obtain a third measurement value; and controlling the reference channel to send a test signal and receiving it from the channel to be calibrated to obtain a fourth measurement value.

3. The automatic test equipment digital board channel delay calibration method according to claim 2, characterized in that, Based on the relative time measurements, the steps of calculating the transmission delay deviation and reception delay deviation of the channel to be calibrated relative to the reference channel include: assuming that the transmission delay from the channel to be calibrated to the reference channel is equal to the transmission delay from the reference channel to the channel to be calibrated, half of the difference obtained by subtracting the sum of the second and fourth measurements from the sum of the first and third measurements is taken as the transmission delay deviation of the channel to be calibrated relative to the reference channel; and half of the difference obtained by subtracting the sum of the second and third measurements from the sum of the first and fourth measurements is taken as the reception delay deviation of the channel to be calibrated relative to the reference channel.

4. The automatic test equipment digital board channel delay calibration method according to claim 3, characterized in that, When the transmission delay from the channel to be calibrated to the reference channel is not equal to the reverse transmission delay, the method further includes obtaining the bidirectional transmission delay difference and incorporating the bidirectional transmission delay difference for compensation and correction when calculating the transmission delay deviation and the reception delay deviation.

5. The automatic test equipment digital board channel delay calibration method according to claim 1, characterized in that, The receiving paths of both the channel to be calibrated and the reference channel include a receiver and a comparator. Before performing multiple self-loop transceiver measurements and cross-channel cross-transceiver measurements, the method further includes: aligning and calibrating the high-level output delay and low-level output delay of the comparator in the channel to be calibrated.

6. The automatic test equipment digital board channel delay calibration method according to claim 5, characterized in that, The steps for aligning and calibrating the high-level output delay and low-level output delay of the comparator in the channel to be calibrated specifically include: controlling the channel to be calibrated to automatically transmit and receive high-level pulse signals, adjusting the first delay unit on the receiving path until the receiver successfully captures the high level, and recording the first tap value; controlling the channel to be calibrated to automatically transmit and receive low-level pulse signals, adjusting the first delay unit on the receiving path until the receiver successfully captures the low level, and recording the second tap value; comparing the first tap value and the second tap value, and compensating the independent delay unit corresponding to the high-level output pin or low-level output pin of the comparator according to the difference between the two.

7. The automatic test equipment digital board channel delay calibration method according to claim 1, characterized in that, Both the channel to be calibrated and the reference channel are equipped with receivers containing triggers and asynchronous first-in-first-out queues. During the acquisition of relative time measurement values, the method for determining successful reception is as follows: gradually increase the delay amount of the programmable delay unit on the reception path until the results read by the asynchronous first-in-first-out queue are all specific logic levels indicating successful reception. Then, successful reception is determined, and the delay amount at this time is recorded as the corresponding relative time measurement value.

8. The automatic test equipment digital board channel delay calibration method according to claim 1, characterized in that, In the step of adjusting the programmable delay units on the transmission path and reception path of the channel to be calibrated according to the transmission delay deviation and reception delay deviation, the programmable delay units on the transmission path of all channels to be calibrated are adjusted to make the transmission delay deviation values ​​of each channel to be calibrated relative to the reference channel equal; and the programmable delay units on the reception path of all channels to be calibrated are adjusted to make the reception delay deviation values ​​of each channel to be calibrated relative to the reference channel equal.

9. An automatic test equipment digital board channel delay calibration system, characterized in that, include: The reference channel module has the same hardware architecture as the channel module to be calibrated and is electrically connected to the channel module to be calibrated. The measurement control module is used to perform multiple self-loop transceiver measurements and cross-channel cross-transceiver measurements on the channel module to be calibrated and the reference channel module to obtain multiple relative time measurement values. The deviation calculation module is used to calculate the transmission delay deviation and reception delay deviation of the channel module to be calibrated relative to the reference channel module based on the relative time measurement value. The delay alignment module is used to adjust the programmable delay units on the transmission path and reception path of the channel module to be calibrated according to the transmission delay deviation and reception delay deviation, so as to align the timing of multiple channel modules to be calibrated to a unified reference.

10. An automatic testing device, characterized in that, It includes digital test boards and the automatic test equipment digital board channel delay calibration system as described in claim 9.

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