Equal-proportion wafer detection method and system based on visual perception and application of equal-proportion wafer detection method and system

Abstract

The invention provides an equal-proportion wafer detection method and system based on visual perception and application of the equal-proportion wafer detection method and system, and belongs to the technical field of chip detection. According to the method, an equal-proportion line-scanning integrated camera is used as core hardware, a Dysample sampling template is introduced into Neck, meanwhile, an MCA mechanism is fused, LAE is introduced to replace part of standard convolution, and the detection precision is improved; wafer defects are trained and tested in different environments, and defect detection of wafers is realized. The system is realized based on the detection method. According to the method, three technologies are adopted for cooperation in the aspects of hardware, software, algorithm and model, high-quality images are provided through the CIS integration technology, high-precision imaging is guaranteed through compound eye bionics, and the model is improved to be endowed to an intelligent brain. According to the invention, an integrated system, a double-linear-array lens and a compound eye bionic imaging technology are designed, an advanced target detection model and the like are fused, and the system has obvious advantages in detection precision, speed and intelligent level. The limitation of the traditional detection equipment in the aspects of precision, efficiency and intelligence can be broken through; and the wafer manufacturing yield is obviously improved.

Description

Visual perception-based proportional wafer inspection method, system and its application Technical Field

[0001] This invention relates to the field of chip inspection technology, specifically a method, system, and application of proportional wafer inspection based on visual perception. Background Technology

[0002] As semiconductor processes move towards 3nm and more advanced nodes, detection technology faces both challenges and opportunities, focusing on three major directions: accuracy improvement, speed optimization, and intelligence, and showing a trend of multi-technology integration.

[0003] In the field of wafer inspection, optical inspection has long held a dominant position due to its high efficiency and non-destructive characteristics, mainly using high-resolution optical microscopes combined with bright-field and dark-field illumination to identify surface defects. However, as semiconductor processes evolve towards 3nm and below nodes, traditional optical inspection faces severe challenges: limited by the diffraction limit of light, its detection accuracy for tiny defects below 50nm is insufficient; simultaneously, the multi-layer stacking of complex chip structures and the introduction of new materials exacerbate optical signal interference, significantly increasing both false positive and false negative rates.

[0004] Problems with traditional detection methods:

[0005] (1) Optical detection method

[0006] Limited by the wavelength of light, it is difficult to break through the 200nm resolution bottleneck and cannot detect nanoscale defects in advanced processes; it has low sensitivity to surface flat defects (such as uneven film thickness and photoresist residue), and is easy to miss; the uniformity of illumination and the difference in wafer reflectivity will cause fluctuations in image contrast, increasing the difficulty of defect identification; if a high-resolution lens is used, the field of view is reduced, and multiple image stitching is required, which is time-consuming and prone to stitching errors; it has insufficient ability to handle the shadow effect of complex three-dimensional structures (such as FinFET fins), affecting the detection accuracy.

[0007] (2) Scanning electron microscopy detection method

[0008] It can generate high-resolution images, but the efficiency of single-beam point-by-point scanning is extremely low. It takes several hours to inspect a single wafer, and the equipment purchase and maintenance costs are extremely high. It also requires a vacuum environment to operate.

[0009] (3) Laser scattering detection method

[0010] It is only sensitive to raised / depressed particles and cannot detect defects on flat surfaces. Differences in wafer surface texture and reflectivity can easily trigger more than 90% of invalid alarms. The detection limit of conventional systems is about 50nm, which is difficult to meet the requirements of advanced processes. In addition, the laser parameters need to be strictly calibrated and environmental fluctuations affect stability.

[0011] (4) Metallographic analysis

[0012] The limitations are: it is a destructive test, and the samples cannot be reused after testing, making it unsuitable for full inspection on mass production lines; the process is lengthy, taking several hours to several days from sample preparation to imaging, making it difficult to provide rapid feedback; and the detection range is limited, only able to analyze local areas (usually a few square millimeters), and cannot cover the entire wafer.

[0013] (5) Ultrasonic testing method diagram

[0014] The detection resolution is limited by the wavelength of the sound wave, and conventional ultrasonic systems have difficulty distinguishing tiny defects smaller than 1μm; they have low sensitivity to surface and near-surface defects (such as oxide layer cracks) and are more suitable for internal delamination, voids and other problems; they require a coupling agent (such as water or gel) to ensure sound wave transmission, which may introduce the risk of secondary contamination. Summary of the Invention

[0015] The technical objective of this invention is to overcome the shortcomings of existing technologies and provide a method, system, and application for proportional wafer inspection based on visual perception.

[0016] The technical solution of the present invention is implemented in the following manner: the present invention provides a visual perception-based proportional wafer inspection method, system and application, wherein the method uses a proportional line scan integrated camera as the core hardware, introduces a Dysample sampling template in the Neck, integrates the MCA mechanism, introduces LAE to replace part of the standard convolution, trains and tests wafer defects in different environments, and realizes wafer defect detection.

[0017] This method includes the following aspects:

[0018] (1) Integration of CIS components: including the layout and packaging of cylindrical lenses, light sources, and photosensitive chips, optimizing the hardware structure, and improving the integration and stability of the system;

[0019] Hardware integration and software development integration;

[0020] Single-strand wide-format CIS replaces the traditional multi-strand CIS splicing;

[0021] Hardware and testing software integration;

[0022] Quickly acquire high-definition images; reduce warm-up time and lower energy consumption;

[0023] (2) Compound eye bionics:

[0024] Develop a multi-channel AD high-speed image signal acquisition card, study the selection and application of linear array lenses, and combine compound eye bionic imaging technology to solve the imaging distortion problem;

[0025] Linear lenses replace optical reduction systems;

[0026] Using perfunctory biomimetic technology;

[0027] Image acquisition and A / D conversion;

[0028] Achieving 1:1 distortion-free imaging technology improves image clarity;

[0029] (3) Improved YOLOv11 model:

[0030] Introducing LAE to replace part of the standard convolution reduces the number of parameters and lowers computational costs;

[0031] Introducing the Dysample sampling template into Neck improves the detection effect of chip surface defects;

[0032] Integrating the MCA mechanism into Neck improves detection capabilities.

[0033] The beneficial effects of this invention compared to the prior art are:

[0034] The present invention relates to a visual perception-based proportional wafer inspection method, system, and its application. By developing a proportional wafer inspection system based on YOLOv11n, it addresses the shortcomings of traditional wafer inspection equipment in terms of efficiency, accuracy, and algorithm generalization ability.

[0035] At the hardware level, advanced imaging technology is employed to improve image stitching steps and optimize the detection process, significantly increasing detection efficiency. An innovative optical solution is introduced, which not only effectively corrects system distortion but also achieves high-precision imaging, thereby significantly improving detection accuracy. The independently developed high-speed signal acquisition system, through the use of advanced parallel processing technology and low-latency design, ensures real-time and efficient image acquisition, providing stable and high-quality image processing results even in complex or high-noise environments.

[0036] At the software level, multiple deep learning technologies are integrated, and the wafer surface defect detection algorithm is comprehensively optimized through refined feature extraction and pattern recognition. This not only enhances the algorithm's ability to identify complex defects but also significantly improves detection accuracy and speed. Through training and validation on large-scale datasets, combined with data augmentation and transfer learning techniques, the algorithm effectively reduces false positives and false negatives.

[0037] This invention achieves a breakthrough through the synergistic application of three major technical modules:

[0038] Developing CIS integration technology: Starting from the hardware level, this approach achieves integrated hardware and software development, abandoning traditional multi-module stitching and adopting a single-module-level CIS to optimize the image sensor packaging structure and fabrication. This increases the CIS frame rate, boosting detection speed, enabling rapid acquisition of high-definition images, reducing stitching time and energy consumption, and laying a solid hardware foundation for efficient detection.

[0039] Compound eye bionic technology: Simulating biological compound eyes, this technology replaces the optical reduction system with a defective lens, integrates sampling superpixels, A / D conversion, and other technologies to construct a lunar array-style proportional cylindrical stereoscopic imaging system. The introduction of compound eye bionics and other technologies significantly improves detection accuracy. It overcomes three major distortion challenges, achieving 1:1 distortion-free imaging, greatly improving clear viewing distance, accurately capturing minute wafer features, and solving the pain point of low accuracy.

[0040] Improved YOLOv11 model: Algorithm-level optimizations include the introduction of lightweight LA ​​convolution, Dysample sampling templates, and the integration of MCA mechanism, coupled with a dedicated deep learning detection algorithm. The improved model achieves an accuracy and extremely low false positive rate of 99.9%, using intelligent algorithms to accurately identify defects and overcome the challenge of difficult detection.

[0041] The three technologies work together: CIS provides high-quality images, compound eye bionics ensures high-precision imaging, and the improved YOLOv11 provides an intelligent "brain." Through assembly, debugging, and experimentation of the complete system, and verification of stability through integrated modules, the system has made great strides in the transition from theoretical to practical testing, contributing to the upgrading of the semiconductor wafer inspection industry.

[0042] The device of this invention consists of a light source, a lens, a signal acquisition board, and a display, and is integrated with a detection algorithm software package. It has the advantages of dimensional measurement and distortion-free graphics, more stable accuracy, small installation space, fast detection speed, no need for focusing time, and no need for image stitching.

[0043] This invention features an integrated system, dual-line array lenses, compound eye bionic imaging technology, and incorporates the advanced target detection model YOLOv11, which offers significant advantages in detection accuracy, speed, and intelligence, while also providing a higher cost-performance ratio.

[0044] Technically, this invention overcomes the limitations of traditional inspection equipment in terms of accuracy, efficiency, and intelligence by using proportional line scanning imaging and deep learning algorithms. Secondly, in terms of economic benefits, it achieves cost reduction and efficiency improvement, while significantly reducing reliance on manual labor and substantially improving wafer manufacturing yield.

[0045] The present invention relates to a visual perception-based proportional wafer inspection method, system, and its application, which are reasonably designed, simple in structure, safe and reliable, easy to use and maintain, and have great potential for widespread application. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the overall process of wafer defect detection according to the present invention;

[0047] Figure 2 is a proportional line scan camera configuration diagram of the present invention;

[0048] Figure 3 is a comparison diagram of the CIS camera-based imaging of the present invention and the general CCD imaging;

[0049] Figure 4 is a schematic diagram illustrating the image processing principle of the present invention;

[0050] Figure 5 is a schematic diagram illustrating the multi-size defects in a wafer and the size variation of defects on different sized grains of the present invention.

[0051] Figure 6 is a diagram of the YOLOv11 network structure of the present invention;

[0052] Figure 7 is a framework diagram of the YOLOv11n invention;

[0053] Figure 8 shows the detection results of various methods for pits, glass spots, and gold plating defects at different scales.

[0054] Figure 9 shows the detection results of oxide film residue and gold plating defects at different scales using various methods. Detailed Implementation

[0055] The following detailed description of the visual perception-based proportional wafer inspection method, system, and its applications, in conjunction with the accompanying drawings, provides a comprehensive overview of the present invention.

[0056] As shown in the attached diagram, in wafer inspection scenarios, low inspection speed, insufficient accuracy, and difficulty in defect identification are the core pain points of this invention. This technical approach revolves around a "vision-based proportional wafer inspection system," using three major technical modules to collaboratively overcome these pain points:

[0057] Independently developed CIS integration technology: This technology revolutionizes hardware from the ground up, achieving integrated hardware and software development. It abandons traditional multi-module stitching and adopts a single-module-level CIS, optimizing the image sensor packaging structure and fabrication. This technology increases the CIS frame rate, boosting detection speed by 35%, enabling rapid acquisition of high-definition images, reducing stitching time and energy consumption, and laying a solid hardware foundation for efficient detection.

[0058] Compound eye bionic technology: Simulating biological compound eyes, this technology replaces the optical reduction system with a defective lens, integrates sampling superpixels, A / D conversion, and other technologies to construct a lunar array-style proportional cylindrical stereoscopic imaging system. The introduction of compound eye bionics and other technologies improves detection accuracy by 3 times. It overcomes three major distortion challenges, achieving 1:1 distortion-free imaging, increasing clear viewing distance by 50%, accurately capturing minute wafer features, and solving the pain point of low accuracy.

[0059] Improved YOLOv11 model: Algorithm-level optimizations include the introduction of lightweight LA ​​convolution, Dysample sampling templates, and the integration of MCA mechanism, coupled with a dedicated deep learning detection algorithm. The improved model achieves an accuracy and extremely low false positive rate of 99.9%, using intelligent algorithms to accurately identify defects and overcome the challenge of difficult detection.

[0060] The three technologies work together: CIS provides high-quality images, compound eye bionics ensures high-precision imaging, and the improved YOLOv11 provides an intelligent "brain." Through assembly, debugging, and experimentation of the complete equipment, and verification of stability of integrated modules, the technology has been transformed from theory into practical testing equipment, contributing to the upgrading of the semiconductor wafer inspection industry.

[0061] System integration and testing:

[0062] A complete wafer inspection system is constructed by integrating CIS overall integration technology, a proportional line scan integrated imaging system, and optimized detection algorithms. The system undergoes comprehensive testing, including hardware performance testing, software function testing, and detection accuracy testing. Based on the test results, optimizations and improvements are made to ensure the system meets design requirements.

[0063] Application expansion and optimization:

[0064] The system's adaptability will be studied in various application scenarios, such as semiconductor manufacturing, chip packaging and testing, and wafer inspection and analysis in research institutions. The system will be optimized and adjusted according to the needs of different application scenarios to improve its versatility and practicality. User feedback will be collected to continuously improve system performance and enhance the user experience.

[0065] Technological breakthroughs have solved three core challenges:

[0066] (1) Efficiency Breakthrough: High-Speed ​​Imaging and Real-Time Processing Technology Breakthroughs. Traditional inspection equipment is limited by data acquisition bandwidth and algorithm inference speed, making it difficult to meet the inspection requirements of 15 wafers per minute on a 12-inch wafer production line. To address this issue, a multi-channel parallel acquisition technology was developed. Through time-division multiplexing circuit design, single-channel noise was suppressed to 0.2μVrms, effectively improving data transmission efficiency by 27%, breaking through the data transmission bottleneck of 3.75GB / s of traditional equipment, and achieving an ultra-high-speed data acquisition of 5.4GB / s. This technology adopts a multi-level cache architecture and DMA direct memory access technology to ensure no data loss during high-speed scanning, laying a solid foundation for subsequent real-time processing.

[0067] At the algorithm deployment level, LAE is introduced to replace part of the standard convolution, reducing the number of parameters and lowering the computational cost; Dysample sampling template is introduced in Neck to improve the detection effect of chip surface defects; MCA mechanism is integrated in Neck to significantly improve the detection capability and fully meet the production line's detection speed requirement of 15 wafers per minute, with a 40% improvement in inference speed compared to traditional algorithms, achieving a significant improvement in efficiency while ensuring detection accuracy.

[0068] (2) Precision Breakthrough: Distortion-Free Detection and Cross-Scale Recognition Technology. To address the inspection challenges of complex wafer structures (such as 3D stacked chips), a precision calibration technology for optical systems was developed. A checkerboard calibration algorithm was used to perform pixel-level coordinate mapping calibration of over 200 points, establishing a high-precision optical distortion correction model. Actual measurement data shows that the wafer size measurement error is <1μm, and the defect location accuracy reaches 0.1nm. Even for 3D stacked chips with more than 10 layers, precise location of defects in each layer can be achieved, completely solving the problem of insufficient accuracy of traditional equipment for inspecting complex wafer structures.

[0069] For cross-scale defect detection, a multi-resolution feature fusion module was designed, which achieves the detection of 100nm particles and 5μm cracks through pyramid feature extraction and a self-attention mechanism. This module first extracts multi-resolution features using convolutional kernels of different scales, and then uses a self-attention layer to dynamically focus on the tiny defect region, suppressing background noise interference. In a defect database test at a certain institution, this technology reduced the false negative rate by 75% compared to traditional algorithms, and improved the detection recall rate to 99.2%, effectively identifying even weak defects with a signal-to-noise ratio below 3.

[0070] (3) Intelligent Breakthrough: Data-Driven Defect Detection Technology. To address the pain point of traditional equipment being able to "only identify known defects," a million-level defect sample library was constructed, with a total of 6 million wafer images annotated, covering 12 typical defects such as scratches, edge chipping, and voids, as well as 20 types of complex background noise. Through data augmentation techniques (such as rotation, scaling, and Gaussian noise addition), the sample size was expanded to 18 million images, forming the industry's first multimodal database. Based on this database, the algorithm achieves automatic weekly iterative optimization, shortening the new defect identification cycle from 3 months in traditional methods to 2 weeks, significantly improving the equipment's adaptability to new defects.

[0071] In the field of unknown defect detection, a self-supervised anomaly detection technique is employed. By training the model on unlabeled data through comparative learning, a Generative Adversarial Network (GAN) is constructed to generate 100,000 simulated defects. This technique enables the model to learn the feature distribution of normal wafers and detect unknown defects through anomaly score calculation, achieving a measured accuracy of 99.9%. In TSMC's blind testing, three novel unlabeled defects were successfully detected, filling a gap in the field of unknown defect detection for traditional equipment.

[0072] The proportional silicon wafer inspection device of the present invention is a device that uses a proportional line scan integrated camera as the core hardware, introduces a Dysample sampling template in the Neck, integrates the MCA mechanism, introduces LAE to replace part of the standard convolution, and trains and tests wafer defects under different environments to achieve wafer defect detection.

[0073] The product consists of a light source, lens, signal acquisition board, and display, integrated with a detection algorithm software package. It has advantages such as distortion-free size measurement and graphics, more stable accuracy, small installation space, fast detection speed, no need for focusing time, and no need for image stitching.

[0074] The core of the visual perception-based proportional wafer inspection method, system, and application of this invention is:

[0075] 1. CIS Overall Integration Technology

[0076] Principle: The integrated CIS technology is an innovative solution that optimally packages components such as cylindrical lenses, light sources, and photosensitive chips. The principle is as follows: the light source emits light that illuminates the wafer surface. After reflection from surface features, the cylindrical lens precisely focuses the light onto the photosensitive chip. The photoelectric effect converts the light signal into an electrical signal, which is then amplified, filtered, and converted by an AD converter through a readout circuit to form a digital signal for subsequent analysis. Thanks to its highly integrated design, this technology achieves "plug-and-play" functionality through standardized interfaces, eliminating the warm-up process required for traditional CCD scanning. The 1:1 imaging mode reduces image scaling calculations, and combined with optimized circuit response and data transmission efficiency, it achieves a maximum scanning speed of 26.79 m / s. Furthermore, it overcomes the technical bottleneck of multi-CIS splicing, integrating all components into a unified control system. Intelligent circuits synchronize the workflow of the light source and photosensitive chip, reducing the complexity of hardware connections and software debugging, improving system integration and collaborative control capabilities, and providing an efficient and accurate front-end solution for wafer inspection.

[0077] The core advantage of CIS integrated technology lies in its plug-and-play capability, eliminating the long warm-up time required for traditional CCD scanning and enabling rapid startup and high-speed scanning, with a maximum scanning speed of 26.79 m / s. This technology significantly improves the efficiency and convenience of silicon wafer inspection, making the inspection process smoother and more efficient.

[0078] The CIS camera integrates its light source, lens, signal acquisition board, and display with the detection algorithm software package, forming a compact system structure. This facilitates close-range integration with the object being inspected, saving space and reducing adjustment and maintenance procedures. The image acquisition card's multiple input interfaces support flexible single-channel or multi-channel image acquisition, further enhancing the system's applicability and convenience.

[0079] As shown in the attached diagram, the integrated CIS technology demonstrates its compact structure and efficient design, intuitively showcasing the significant performance advantages of CIS cameras compared to traditional CCD cameras. This not only improves the accuracy and efficiency of silicon wafer inspection but also provides strong support for the popularization of industrial vision imaging inspection and the simplification of engineering applications.

[0080] Second: Introducing multiple technologies such as compound eye bionics to achieve distortion-free imaging.

[0081] Line scan cameras and area scan cameras differ in their mechanical structure. The main difference lies in the fact that a line scan camera consists of photosensitive wafers arranged in rows. Through continuous triggering of images, each line is captured and a new image is constructed in the image acquisition card. Due to its working principle, the object being measured and the camera must be in relative motion. This places extremely high demands on the hardware; otherwise, longitudinal stretching or compression of the image may occur. This system utilizes a novel calibration board, and during camera calibration, both the calibration board and the line scan camera remain stationary. This significantly reduces the hardware requirements, simplifies the calibration process, and improves calibration accuracy.

[0082] To improve the measurement accuracy of the system, the camera underwent flat field correction, flat field compensation, and radiometric calibration. The radiometric calibration and compensation made the images captured by the camera more realistically reflect the physical information of the measured object, providing the most ideal image for the algorithm.

[0083] (1) High-speed image acquisition capability: This technology uses a self-developed multi-channel AD high-speed image signal acquisition card, which can quickly detect tiny defects on the surface of silicon wafers, with a detection speed of up to 5.4 GB / s, as shown in the attached figure. This ensures that every silicon wafer can be clearly imaged even in a high-speed production environment, improving production efficiency and product quality.

[0084] (2) Integrated system design: The proportional line scan integrated camera technology integrates the CIS image sensor module, AD conversion module, FPGA logic control module, ARM image processing module and stepper motor drive module to reduce external connection and data processing time delay and improve system stability.

[0085] (3) Image Data Processing and Optimization: The CIS image sensor is responsible for capturing image data from the silicon wafer and converting analog signals into digital signals via an AD conversion module. The FPGA logic control module processes the received data and then buffers it in external SDRAM. The ARM processor further performs image data correction, filtering, compression encoding, and other processing.

[0086] (4) High imaging accuracy: Compared with traditional CCD image sensors, CIS image sensors have the advantages of high accuracy and simple structure, which can effectively reduce image noise and improve imaging quality. By adopting a linear array lens, the distortion problem of traditional optical reduction systems is overcome, achieving 1:1 distortion-free imaging.

[0087] (5) Wide-span imaging and precision measurement: This technology has significant advantages in wide-span applications, enabling WYSIWYG imaging and precision measurement of critical dimensions in defect detection, as well as highly integrated wide-span scanning. This greatly facilitates the production and quality control of silicon wafers.

[0088] 3. Optimization of Wafer Surface Defect Detection Algorithm

[0089] Object detection is a core area of ​​computer vision, with its main task being object localization and classification. Traditional object detection approaches include target region selection, manual extraction of target features, and classifier classification. However, manual feature extraction methods have inherent limitations that prevent them from accommodating the diversity of target features.

[0090] Deep learning models include various basic models such as classification, segmentation, object detection, and keypoint localization, capable of completing the entire process of image annotation, preprocessing, training, inference, and visualization. Based on the image processing platform, algorithms can be quickly customized to meet specific industrial inspection needs. Simple application training for engineers allows for seamless switching between different products and inspection or measurement functions. Algorithms compatible with the deep learning framework include particle array segmentation algorithms, Dysample sampling templates introduced into Neck, and optimized algorithms incorporating the MCA mechanism.

[0091] Utilizing the principles of professional image processing systems, a Dysample sampling template is introduced into Neck. Simultaneously, the MCA mechanism is integrated, and LAE is introduced to replace part of the standard convolution to train and test wafer defects under different environments. The training data is monitored, the model performance is continuously evaluated, and the model version is managed to ensure the reliability of the model.

[0092] The comparison results between the YoLov11 system of this invention and Faster R-CNN are shown below:

[0093] Comparative experimental results

[0094]

[0095] Accuracy advantages: mAP@0.5 improves accuracy by 1.7% compared to YOLOv11s, and mAP@small improves detection accuracy by 6.9%, especially in the recognition rate of 40-100nm particle defects, which is improved from 82% to 91% (defect category confusion matrix).

[0096] Speed ​​advantage: The detection speed reaches 45.2 FPS with a single RTX 3090 card, meeting the industrial-grade real-time detection requirements (≥20 FPS), which is 2.6 times faster than Faster R-CNN.

[0097] Reliability: The false negative rate and false positive rate have been reduced to 0.1% and 0.8% respectively, which are lower than the industry standard (false negative rate ≤5%, false positive rate ≤3%).

[0098] Actual production verification (tested on a 12-inch wafer production line of a certain technology company):

[0099] ① The detection accuracy for metal layer scratches (50nm width) reaches 99.99%, which is 14.2% higher than manual visual inspection (85% accuracy);

[0100] ② The defect location error is ≤ ±8μm, which meets the precision screening requirements of the wafer before packaging (SEMI standard ±10μm);

[0101] ③ The system runs continuously for 24 hours without missing detections, and the number of false alarms is less than 3 per 10,000 pieces, which is much lower than imported equipment (such as the KLAeSL series, which has 15 false alarms per 10,000 pieces).

[0102] Main technical specifications of the proportional wafer inspection system:

[0103] The proportional wafer inspection system integrates CIS overall integration technology, a proportional line scan imaging system, and the YOLOv11n algorithm to achieve end-to-end collaboration of "high-precision imaging - high-speed acquisition - intelligent recognition." Its main technical indicators cover imaging performance, inspection accuracy, equipment efficiency, and environmental adaptability. Details are as follows:

[0104]

[0105]

[0106] Core advantages:

[0107] Leading precision: 5μm resolution, 0.1% distortion rate, breaking through the bottleneck of small defect (40nm level) detection;

[0108] Efficiency Improvement: The testing speed is 30% faster than imported equipment, with a daily processing capacity of 8,000 pieces;

[0109] Stable and reliable: Industrial-grade environmental adaptability, MTBF exceeding 10,000 hours, and a false negative rate as low as 0.1%.

[0110] Compliance and compatibility:

[0111] ①SEMI standard: Meets SEMI E122 accuracy requirements, with critical dimension measurement error ≤ ±10μm;

[0112] ② Data interface: Supports GigE Vision, Camera Link, PCIe 3.0, and is compatible with MES systems;

[0113] ③ Software support: Cross-Windows / Linux systems, providing a secondary development SDK.

[0114] The key technical problem to be solved by this invention:

[0115] Addressing the core pain points of traditional wafer inspection equipment, such as insufficient accuracy, low efficiency, and poor environmental adaptability, this invention overcomes the following five key technical challenges, achieving end-to-end innovation from hardware integration to algorithm optimization:

[0116] I. Challenges in High-Precision Hardware Integration and Uniform Imaging

[0117] (1) Technical challenges:

[0118] Traditional multi-CIS sensor splicing results in image seam errors (>±50μm) and uneven illumination in edge areas (uniformity <80%), making it difficult to meet the requirements of full-area high-precision inspection of 12-inch wafers.

[0119] (2) Solution:

[0120] ①Develop a single wide-width CIS integrated component that integrates a 20k pixel linear array sensor, cylindrical lens, and LED light source into a single package, covering a width of 300mm in a single scan and eliminating splicing errors (≤±5μm);

[0121] ② By adopting coaxial optical path design and light homogenizer technology, the uniformity of illumination on the wafer surface is >95%. Combined with the air-floating motion platform (positioning accuracy ±1μm), the consistency of detection between the edge and center areas is ensured.

[0122] (3) Technological breakthrough:

[0123] The hardware integration is improved by 40%, the size is reduced by 30%, and the edge detection accuracy is improved by 5 times compared with the traditional solution, meeting the Class A detection requirements in the SEMI standard.

[0124] II. Bottlenecks in Scaling Imaging and Geometric Distortion Correction Techniques

[0125] (1) Technical challenges:

[0126] Traditional optical systems rely on lenses to reduce image size (such as 20× objectives), resulting in radial distortion >1% in the edge region. Furthermore, they cannot directly obtain information about the actual wafer size, and the critical dimension (CD) measurement error is >±50μm, making it difficult to meet the accuracy requirements of the 28nm process.

[0127] (2) Solution:

[0128] ① A compound eye bionic linear array lens group was designed, which achieves 1:1 proportional imaging through 16 microlens arrays. Combined with FPGA real-time distortion correction algorithm, the distortion rate of the entire field of view is controlled within 0.1%.

[0129] ② A laser displacement sensor is introduced to calibrate the wafer height in real time, and combined with Z-axis compensation of the motion platform (accuracy ±2μm), the defocusing problem caused by wafer warping (±50μm) is solved.

[0130] (3) Technological breakthrough:

[0131] Achieving WYSIWYG scale imaging with a critical dimension measurement error of ≤±10μm, it is the first time that it has reached an advanced level among existing equipment (KLA-Tencor's similar equipment has an error of ±15μm).

[0132] III. The Challenges of Small Defect Detection and Complex Background Interference

[0133] (1) Technical challenges:

[0134] Tiny defects at the 40nm level (such as photoresist particles) are difficult to identify against a low-contrast background, and traditional algorithms (such as edge detection) have a false detection rate of >10%; metallization layer reflections, photoresist textures, etc. lead to a false detection rate of >5%, which cannot meet the yield control requirements of advanced processes.

[0135] (2) Solution:

[0136] ① Constructing a YoLov11n deep learning model introduces LAE to replace some standard convolutions, reducing the number of parameters and lowering computational costs.

[0137] ② Introduce the Dysample sampling template into Neck to improve the detection effect of chip surface defects; integrate the MCA mechanism into Neck to significantly improve detection capability.

[0138] (3) Technological breakthrough:

[0139] For the first time, industrial-grade detection of 40nm-level defects has been achieved, with an overall false negative rate of ≤0.1%, reaching the leading level of KLA-eSL series equipment (false negative rate of 1.2%-1.8%).

[0140] IV. Bottlenecks in High-Speed ​​Detection and Real-Time Data Processing Efficiency

[0141] (1) Technical challenges:

[0142] The data volume of a 12-inch wafer reaches 36GB. Traditional equipment relies on CPU serial processing, with a detection time of more than 4 minutes per wafer and a data transmission latency of more than 50ms, which cannot meet the real-time quality control requirements of the production line.

[0143] (2) Solution:

[0144] ① Design an 8-channel parallel AD acquisition card with a data throughput of 5.4GB / s. Combined with FPGA real-time filtering preprocessing (denoising and edge enhancement), the CPU load is reduced.

[0145] ②Based on GPU-accelerated inference (RTX 3090 single card 45.2FPS), it achieves end-to-end processing capability from image acquisition to defect report generation in ≤10 seconds.

[0146] (3) Technological breakthrough:

[0147] The detection speed is increased by 40%, the daily processing capacity reaches 8,000 wafers, and the data processing latency is reduced by 70% compared with the traditional solution, meeting the real-time closed-loop control requirements of "detection-feedback-adjustment" in semiconductor production lines.

[0148] V. Industrial-grade environmental adaptability and long-term stability

[0149] (1) Technical challenges:

[0150] Fluctuations in temperature and humidity (0-40℃, 20%-80%RH), vibration (10G), and wafer warpage (±50μm) in semiconductor workshops can easily cause drift in equipment testing accuracy. Traditional equipment has an MTBF (Mean Time Between Failures) of less than 5000 hours and requires frequent calibration (>1 time / week), making it difficult to meet the needs of 24 / 7 uninterrupted production.

[0151] (2) Solution:

[0152] ① Adaptive temperature and humidity control: The device uses a combination of temperature-controlled fan and semiconductor cooling chip to automatically adjust the internal temperature (±1℃) according to the ambient temperature; a moisture-proof coating is applied to the surface of key optical components, and combined with the sealed cavity design, the internal humidity is controlled at 30%-60%RH to ensure stable optical performance.

[0153] ② Vibration resistance design and compensation: The design incorporates air-bearing guide rails and shock-absorbing bases to effectively isolate workshop floor vibrations (attenuation rate > 90%); and uses laser displacement sensors to monitor the vibration offset of the motion platform in real time, combined with algorithm-level coordinate compensation, to control the impact of vibration on detection accuracy within ±5μm.

[0154] ③ Adaptive wafer warpage detection: Utilizing multi-sensor fusion technology (laser displacement + visual imaging), the wafer surface height information is acquired in real time, and the detection focal length and imaging parameters are dynamically adjusted to ensure that the detection accuracy is not affected when the wafer warpage is ±50μm.

[0155] ④ Redundancy design and self-diagnostic function: The hardware adopts dual power supply and dual sensor backup, and automatically switches to the backup equipment when the main equipment fails; the software develops a self-diagnostic algorithm to monitor the equipment operating status in real time, give early warning of potential faults, and realize rapid fault recovery (<30 minutes).

[0156] (3) Technological breakthrough:

[0157] ① The equipment's MTBF is increased to >10,000 hours, and the fault recovery time is shortened by 80% compared to traditional equipment, meeting the 24 / 7 uninterrupted operation requirements of semiconductor production lines.

[0158] ② In complex industrial environments, the detection accuracy remains stable over a long period of time, and the fluctuation range of key dimension measurement error is controlled within ±3μm, which is 3 times more accurate and stable than traditional equipment.

[0159] Innovation:

[0160] 1. Achieving high-speed image acquisition using an integrated system.

[0161] (1) Principle: Integrated packaging of key components can reduce space occupation and energy consumption, and improve system stability. The single wide-width component design can reduce the number of components and splicing links. Plug and play combined with high-speed scanning technology can realize rapid start-up and efficient operation of the equipment.

[0162] (2) Innovation: Integrated hardware and software development. A single wide-format CIS is used instead of the traditional multi-CIS stitching method. Camera components and detection algorithm software packages are integrated into one unit.

[0163] (3) Results: Quickly acquires high-definition images and processes image data in real time. Optimizes the detection process and reduces time delays. Reduces energy consumption and extends equipment lifespan.

[0164] Second: Linear array lens incorporating compound eye bionic technology

[0165] By employing a dual-line array lens and compound eye bionic imaging technology, the detection accuracy is improved by 3 times.

[0166] (1) Principle: The linear array lens optical design directly focuses light onto the linear photosensitive element, eliminating the complex process of traditional optical reduction technology; the compound eye structure is arranged to form an integrated imaging system, which can simultaneously capture light from different directions. Rod Lens Array is used, replacing the traditional optical reduction system with a linear array lens, and compound eye bionic imaging technology is adopted; CIS image sensor module, AD conversion module, etc. are used.

[0167] (2) Results: It has overcome three major distortion problems and achieved a 40%-50% improvement in image clarity with 1:1 distortion-free imaging.

[0168] III: Research on Optimization of Wafer Surface Defect Detection Algorithms

[0169] Based on a deep learning framework, a 3D collaborative detection model is constructed by introducing LAE to replace part of the standard convolution, incorporating the Dysample sampling template in the Neck, and integrating the MCA mechanism. This model uses...

[0170] LAE feature extraction allows the model to extract more contextual information and high-resolution details from multi-scale feature maps, forming a multimodal feature representation system. For wafer defect detection, LAE is introduced to replace some standard convolutions, reducing the number of parameters and computational cost. A Dysample template is introduced in the Neck to improve the detection effect of chip surface defects. The MCA mechanism is integrated into the Neck to significantly improve detection capabilities. During the training phase, a strategy combining contrastive learning and self-supervised learning is adopted. Pre-training is performed using massive amounts of unlabeled data, and fine-tuning is done using a small number of labeled samples to alleviate the data shortage problem. A dynamic model ensemble framework is established to improve accuracy and robustness, and a full-link evaluation system covering multi-dimensional indicators is constructed.

[0171] Features and advantages of this invention:

[0172] I. System Integration and Intelligent Control

[0173] (1) Features: It adopts CIS integrated technology to optimally package components such as cylindrical lens, light source, and photosensitive chip to achieve "plug and play" function, eliminating the warm-up time of traditional CCD scanning, and the maximum scanning speed can reach 26.79m / s.

[0174] (2) Advantages: It breaks through the technical bottleneck of multi-CIS splicing mode, improves system integration and intelligent control capabilities, and reduces equipment debugging complexity.

[0175] II. Wafer Imaging Technology

[0176] (1) Features: By using a single wide-width CIS scanning component, it overcomes three major challenges: radial distortion, centrifugal distortion and thin prism distortion, and achieves 1:1 scale imaging without image distortion.

[0177] (2) Advantages: Reduces space occupation by 64%, reduces energy consumption, improves battery life, and enhances imaging accuracy and speed.

[0178] III. Wafer Defect Detection Algorithm

[0179] (1) Features: Construct a deep learning model based on YOLOv11n, introduce the Dysample sampling template in Neck, and integrate the MCA mechanism to improve detection accuracy and generalization ability.

[0180] (2) Advantages: The algorithm has an accuracy of 99.9%, which is significantly better than traditional algorithms and effectively reduces the false detection rate and false negative rate.

[0181] The core technology of this invention:

[0182] (1) The CIS integrated technology adopts a single wide-width CIS component to replace the traditional multi-span splicing mode, integrating a 12K resolution photosensitive chip, a cylindrical uniform light lens and an LED light source. Through optical simulation to optimize the optical path, it achieves 1:1 distortion-free imaging, reduces the edge brightness uniformity error from 12% to below 3%, reduces the volume by 30%, and improves the detection efficiency by 40%-50%.

[0183] (2) The integrated imaging system of linear scanning is developed with a multi-channel AD high-speed acquisition card (data throughput 5.4GB / s). By combining dual linear array lens and compound eye bionic technology, optical problems such as radial distortion (<0.02%) are overcome, the minimum detection defect is 40nm, and the false negative rate is reduced from 6% to less than 0.1%.

[0184] (3) Based on the YOLOv11n deep learning algorithm, LAE is introduced to replace part of the standard convolution, reducing the number of parameters and the computational cost; Dysample sampling template is introduced in Neck to improve the detection effect of chip surface defects; MCA mechanism is integrated in Neck to significantly improve the detection capability, which is 1.7% higher than the original YOLO-v11s model and 23% higher for defects below 100nm.

[0185] The proportional silicon wafer inspection system uses a dynamic adaptive algorithm to calibrate inspection parameters in real time, combined with an industrial-grade environmental adaptability design (IP65 protection, MTBF>10,000 hours) to meet the high-speed, high-precision inspection requirements of semiconductor production lines. This technology breaks through the bottlenecks of traditional optical inspection, achieving end-to-end collaboration of "high-precision imaging - high-speed acquisition - intelligent recognition".

[0186] Experimental testing and data calculation of this invention:

[0187] I. Performance Coefficient Study

[0188] In wafer inspection systems, imaging performance is a core factor affecting inspection accuracy and reliability. To achieve high-precision wafer defect detection, a comprehensive and in-depth study of the system's imaging performance was conducted, focusing on a systematic analysis of key indicators such as resolution, sharpness, distortion rate, accuracy, and false negative rate.

[0189] (1) Resolution

[0190] In the experiment, a variety of lenses of different specifications were selected, covering different focal lengths from low to high magnification, and various light source types, such as ring light sources and coaxial light sources, as well as different models of image sensors with varying pixel densities and sensitivities. A large number of image samples were obtained through testing these different combinations.

[0191] (2) Clarity

[0192] To assess sharpness, a subjective visual evaluation method was used, with professionals meticulously observing and scoring the imaging results. An image sharpness evaluation algorithm was then employed to conduct an objective quantitative analysis across multiple dimensions, including edge sharpness and texture detail richness. During the experiment, it was found that while some lenses could capture sufficient light at large apertures, this resulted in blurred image edges and reduced sharpness; uneven illumination from some light sources also affected the sharpness of localized areas of the image. By continuously adjusting the lens aperture, optimizing the light source layout, and selecting a suitable image sensor, image sharpness was gradually improved.

[0193] (3) Distortion rate

[0194] The experiment used test templates with standard geometric shapes. After the imaging system acquired the images, image processing software was used to measure the deviation between the actual shape of the object in the image and the standard shape, thereby calculating the distortion rate. Experimental results showed that some lenses produced significant barrel distortion at the wide-angle end, while some lenses exhibited pincushion distortion at the telephoto end. To achieve 1:1 distortion-free imaging, lenses were rigorously screened, and software algorithms were used to correct image distortion. After repeated testing and optimization, the optimal combination of lens, light source, and image sensor was finally determined, effectively eliminating the impact of distortion on the detection results.

[0195] (4) Accuracy

[0196] With the optimized combination of imaging system parameters, the detection accuracy reached 99.9%. Further analysis revealed that the accuracy was closely related to resolution and sharpness. High-resolution and sharp images can provide more accurate feature information for the detection algorithm, thereby improving the recognition accuracy. Low distortion rate ensured the accurate representation of the defect location and shape, which also played a positive role in improving the accuracy.

[0197] Through extensive experimental comparisons and parameter optimization, the system has achieved significant results in imaging performance. This provides a solid and reliable image foundation for subsequent defect detection work, greatly improves the accuracy and reliability of wafer inspection, and provides strong support for quality control in the semiconductor manufacturing process.

[0198] In the simulation environment, various types of wafer defects are accurately simulated. Based on the common scratch length, width, and depth ranges in actual production, scratch samples of different sizes are generated. Different scratch shapes are considered. For crack defects, cracks of different lengths, widths, and orientations are simulated, as well as their distribution at different locations on the wafer surface. For particle contamination defects, particles of different sizes, shapes, and materials are set to simulate their random distribution on the wafer surface. Following the size distribution patterns of defects in actual production, the generated defect samples are ensured to be representative.

[0199] The effects of different lighting conditions on defect detection were simulated. Regarding lighting intensity, multiple gradients from low to high intensity were set. Regarding lighting angle, the angle between the light source and the wafer surface was varied to observe the imaging effect of defects in the image under different lighting angles. Irradiation by different colored light sources was simulated to study the influence of different colors of light on defect feature extraction.

[0200] Considering the inevitable noise interference during actual testing, different levels of noise interference are set in the simulated environment. Gaussian white noise generated by the sensor is simulated with different noise intensities; the impact of background noise in a production workshop on image acquisition is simulated by adding random noise to mimic this interference.

[0201] In real-world industrial scenarios, each defect atlas often exhibits diversity. Addressing the challenges of dealing with multiple types of defects, this invention aims to improve the model's ability to identify and locate various defects, providing more reliable quality assurance for industrial production. It can also identify the algorithm's response methods to different situations based on simulation results.

[0202] II. Simulation Experiment

[0203] In the simulation environment, various types of wafer defects are accurately simulated. Based on the common scratch length, width, and depth ranges in actual production, scratch samples of different sizes are generated. Different scratch shapes are considered. For crack defects, cracks of different lengths, widths, and orientations are simulated, as well as their distribution at different locations on the wafer surface. For particle contamination defects, particles of different sizes, shapes, and materials are set to simulate their random distribution on the wafer surface. Following the size distribution patterns of defects in actual production, the generated defect samples are ensured to be representative.

[0204] The effects of different lighting conditions on defect detection were simulated. Regarding lighting intensity, multiple gradients from low to high intensity were set. Regarding lighting angle, the angle between the light source and the wafer surface was varied to observe the imaging effect of defects in the image under different lighting angles. Irradiation by different colored light sources was simulated to study the influence of different colors of light on defect feature extraction.

[0205] Considering the inevitable noise interference during actual testing, different levels of noise interference are set in the simulated environment. Gaussian white noise generated by the sensor is simulated with different noise intensities; the impact of background noise in a production workshop on image acquisition is simulated by adding random noise to mimic this interference.

[0206] In real-world industrial scenarios, each defect atlas often exhibits diversity, as shown in the attached figure, encompassing various training wafer defects. Addressing the practical challenge of detecting multiple types of defects, the proposed deep learning-based wafer defect detection method is particularly important. Its innovative design aims to improve the model's ability to identify and locate various defects, providing more reliable quality assurance for industrial production. Based on simulation results, the advantages and disadvantages of the algorithm under different conditions are identified.

[0207] III. Experimental Study on the Test Bench

[0208] A practical wafer defect inspection test bench was constructed. A high-resolution industrial camera was selected for image acquisition to ensure clear image capture of the wafer surface. The motion control system employed high-precision servo motors and precision lead screws to ensure smooth wafer movement during inspection. A ring light source providing stable and uniform illumination was chosen to meet the lighting requirements of different defect inspections. The camera lens and light source were connected according to the design specifications.

[0209] The wafer samples were actually inspected using a test bench. During the inspection process, key data such as inspection time, inspection accuracy, and system stability were recorded in detail. The time required for the entire process from image acquisition to output of inspection results was accurately recorded, and the impact of different sample numbers and defect complexity on inspection time was analyzed. By comparing the results with manual inspection, the detection accuracy of different types of defects was statistically analyzed. For missed detections, the defects were either too small, and the image acquisition equipment failed to clearly capture their features, or the detection algorithm had insufficient ability to identify certain special types of defects.

[0210] Based on the test bench experimental results, targeted optimizations and improvements were made to the detection system. These included optimizing the algorithm's computational flow, improving its operational efficiency, or upgrading hardware to enhance the reliability and accuracy of the detection system in practical applications. This ensured the system met the stringent requirements for wafer defect detection in industrial production, providing reliable quality assurance for semiconductor manufacturing companies.

[0211] (1) Integrate the CIS overall integration technology, the proportional line scan integrated imaging system, and the optimized detection algorithm to build a complete wafer inspection system. Conduct comprehensive testing on the system, including hardware performance testing, software function testing, and detection accuracy testing. Optimize and improve the system based on the test results to ensure that the system meets the design requirements.

[0212] (2) Study the system's adaptability in different application scenarios, such as semiconductor manufacturing, chip packaging and testing, and wafer inspection and analysis in research institutions. Optimize and adjust the system according to the needs of different application scenarios to improve its versatility and practicality. Collect user feedback to continuously improve system performance and enhance user experience.

[0213] IV. Analysis of Detection Methods for Wafer Surface Defects

[0214] During the system development process, a series of theoretical calculations were performed to ensure the system's performance and reliability. In terms of hardware design, theoretical calculations and analyses were conducted on the optical performance of the CIS camera, the transmission rate of the signal acquisition card, and the computing power of the image processing chip to ensure that the hardware components could meet the overall performance requirements of the system. In terms of algorithm design, theoretical calculations and optimizations were performed on the complexity, training time, and convergence speed of the deep learning model, improving the efficiency and accuracy of the algorithm. These theoretical calculations provided a theoretical basis for the system's design and optimization, ensuring the smooth progress of the project.

[0215] Wafer surface defects vary considerably in spatial scale, and this variation is reflected in multiple levels. The attached figure shows some wafer defects of various sizes and the size variation of defects on different sized grains.

[0216] (1) YOLOv11 network

[0217] The YOLOv11 network inherits the framework of the YOLO series of algorithms. The network structure mainly consists of three parts: Backbone, Neck, and Head, as shown in the attached figure.

[0218] The backbone is the fundamental component of the model, primarily used for feature extraction. The neck is designed to fuse feature information from different levels, with the key being to simultaneously retain richer spatial and semantic information. The head is responsible for directly predicting the target's location and category.

[0219] (2) Overall architecture of YOLOv11n object detection model

[0220] The architecture of the multi-scale detection model MYOLOv11n is shown in the attached figure. In the backbone part, local and global feature extraction layers (LGLayer) are designed to enhance the model's modeling capabilities.

[0221] Introducing the Dysample sampling template into Neck improves the detection effect of chip surface defects; integrating the MCA mechanism into Neck significantly enhances detection capabilities.

[0222] (3) Dataset Construction The details of the wafer multi-scale defect detection dataset are shown in the table below. The image size ranges from 280×280 to 842×842, and the input size for network training is set to 640×640. The dataset contains a total of 12,860 images, which are randomly divided into training set, validation set, and test set of 882, 294, and 294 images respectively.

[0224] Wafer multi-scale defect detection data:

[0225]

[0226] (4) Experimental Results and Analysis

[0227] The experiment selected six models for comparison: YOLOv5-s, PPYOLOE-s, YOLOv6-s, YOLOv11-s, YOLOv11-l, and RT-DETR-L. The experimental data are shown below.

[0228]

[0229] The visualization of the comparative experimental results is shown in the attached figure. Each row of images represents the recognition results of different methods, and the first column is the label image.

[0230] The results show that YOLOv11n outperforms the comparative methods in both overdetection and missed detection. For typical small-scale defects, such as small pits, the original YOLOv5 and YOLOv11 cannot detect them correctly, while the improved model can locate small-scale defects more accurately. However, for irregularly shaped, highly deformed corner gold plating and oxide film residue defects, the YOLOv11 model has a higher detection accuracy than YOLOv5, but missed detection and overdetection issues still exist. Nevertheless, the improved YOLOv11n network has strong multi-scale feature extraction capabilities, can balance the processing of spatial detail features and semantic features of the target, and can accurately detect defects that were missed or overdetected in other comparative methods.

[0231] V. Simulation Control Strategy Experiment

[0232] In wafer defect detection systems, various control strategies have a significant impact on the detection results. To determine the optimal combination of control strategies, experiments simulating different control strategies were designed and implemented.

[0233] Consider adjusting the exposure time of the image acquisition equipment. Set different exposure time gradients: short exposure time, medium exposure time, and long exposure time. During the simulated inspection process, use the same batch of representative wafer samples to observe the quality of wafer images acquired at different exposure times.

[0234] With short exposure times, images may lose detail due to underexposure, making the edges and textures of defects unclear; with long exposure times, images may become too bright, causing information saturation in some areas, which is also not conducive to defect recognition; while moderate exposure times can balance the brightness and detail of the image to a certain extent, making defect features more obvious, and the detection algorithm analyzes the detection results based on these images.

[0235] Different movement speeds, such as low, medium, and high, were set up. During the simulated detection process, the images acquired by the detection equipment at different movement speeds and the detection results of the detection algorithm were observed. At low speeds, the image acquisition stability was high, but the detection efficiency was low. Although high-speed movement could improve detection efficiency, it might lead to a decrease in image quality due to motion blur, affecting the accuracy of defect detection.

[0236] Through multiple comparative experiments on various control strategies, including exposure time, motion speed, and data transmission frequency, the impact of each strategy on the overall performance of the detection system was observed in detail. The advantages and disadvantages of different control strategies were comprehensively evaluated, and the optimal combination of control strategies was selected to improve the stability and efficiency of the detection system, ensuring that the system can operate efficiently and accurately in practical applications.

Claims

1. A method for inspecting scaled wafers based on visual perception, characterized in that... This method uses a proportional line scan integrated camera as the core hardware, introduces the Dysample sampling template in the Neck, integrates the MCA mechanism, introduces LAE to replace part of the standard convolution, trains and tests wafer defects in different environments, and realizes wafer defect detection.

2. The method for proportional wafer inspection based on visual perception according to claim 1, characterized in that... The method includes the following aspects: (1) Integration of CIS components: including the layout and packaging of cylindrical lenses, light sources, and photosensitive chips, optimizing the hardware structure, improving the system integration and stability; hardware integration and software development integration; single wide-width CIS replacing traditional multi-CIS splicing; hardware and detection software integration; rapid acquisition of high-definition images; reduction of warm-up time and energy consumption; (2) Compound eye bionics: developing multi-channel AD high-speed image signal acquisition cards, studying the selection and application of linear array lenses, combining compound eye bionic imaging technology to solve the imaging distortion problem; linear lenses replacing optical reduction systems; adopting perfunctory bionic technology; image acquisition AD conversion; achieving 1:1 distortion-free imaging technology to improve clarity; (3) Improved YOLOv11 model: introducing LAE to replace part of the standard convolution, reducing the number of parameters and reducing computational costs; introducing Dysample sampling template in Neck to improve the detection effect of chip surface defects; integrating MCA mechanism in Neck to improve detection capability.

3. The proportional wafer inspection method based on visual perception according to claim 1, characterized in that... The method includes the following mechanisms: (1) CIS overall integration: Starting from the hardware bottom layer, the software and hardware development is integrated, abandoning the traditional multi-module splicing, adopting single-module level CIS, optimizing the image sensor packaging structure and preparation; making the CIS frame rate help improve the detection speed, quickly acquire high-definition images, reduce splicing time and energy consumption, and build a solid hardware foundation for detection. (2) Compound eye bionics: Simulates biological compound eyes, replaces optical reduction system with defect lens, integrates sampling superpixel and A / D conversion technology, constructs lunar array equal scale columnar stereo imaging system, introduces compound eye bionic technology to greatly improve detection accuracy; overcomes distortion, achieves 1:1 distortion-free imaging, improves clear viewing distance, accurately captures wafer fine features, and solves the pain point of low accuracy; (3) Wafer surface defect detection algorithm optimization: improves model, optimizes algorithm level, introduces LA lightweight convolution, Dysample sampling template, integrates MCA mechanism, and matches exclusive deep learning detection algorithm; after improvement, the model accuracy and extremely low false detection rate both reach 99.9%, accurately identify defects with intelligent algorithm, and solve the difficulty of identification; the above (1)(2)(3) work together, CIS provides high quality images, compound eye bionics ensures high precision imaging, and improved YOLOv11 gives intelligent brain; after the whole equipment assembly, debugging, experimentation, integration module verification stability, vigorously promotes from theoretical to practical detection, and helps the semiconductor wafer detection industry upgrade; the wafer detection system is constructed with hardware-algorithm-system collaboration.

4. The proportional wafer inspection method based on visual perception according to claim 1, characterized in that... The method includes the following aspects: (1) Overall CIS integration: High-precision hardware integration and uniform imaging adopt a single wide-width CIS integrated component, which integrates a 20k pixel linear array sensor, cylindrical lens and LED light source into a single package, covering a width of 300mm in a single scan, eliminating splicing error, or controlling the error within ≤±5μm; using a coaxial optical path and light homogenizer to achieve a wafer surface illumination uniformity of >95%, and with the air-floating motion platform, the positioning accuracy range is ±1μm, ensuring the consistency of edge and center area detection; (2) Compound eye bionics: proportional imaging and geometric distortion correction adopt a compound eye bionic linear array lens group, which achieves 1:1 proportional imaging through 16 microlens arrays, combined with FPGA real-time distortion correction. The algorithm controls the full field-of-view distortion rate to within 0.1%; a laser displacement sensor is introduced to calibrate the wafer height in real time, and the Z-axis compensation of the motion platform is used to control the accuracy range to ±2μm, overcoming the defocusing problem caused by wafer warping; (3) Small defect detection and anti-complex background interference: constructing a YoLov11n deep learning model, introducing LAE to replace part of the standard convolution, reducing the number of parameters and reducing the computational cost; introducing Dysample sampling template in Neck to improve the detection effect of chip surface defects; integrating MCA mechanism in Neck to improve detection capability; (4) High-speed detection and real-time data processing efficiency: the bottleneck of high-speed detection and real-time data processing efficiency is to use an 8-channel parallel AD acquisition card, data According to the throughput of 5.4GB / s, combined with FPGA real-time filtering preprocessing, noise reduction, edge enhancement, and CPU load reduction; based on GPU accelerated inference, it realizes the end-to-end processing capability from image acquisition to defect report generation ≤10 seconds; (5) Industrial-grade environmental adaptability and long-term stability temperature and humidity adaptive control: adopting the combination of temperature control fan and semiconductor cooling chip, the internal temperature of the equipment is automatically adjusted to ±1℃ according to the ambient temperature; a moisture-proof coating is applied to the surface of key optical components, combined with the sealed cavity design, the internal humidity is controlled at 30%-60%RH to ensure stable optical performance; anti-vibration design and compensation: the design of air-floating guide rail and shock-absorbing base effectively isolates the vibration of the workshop floor, and the attenuation rate is >9 0%; and by using a laser displacement sensor to monitor the vibration offset of the motion platform in real time, combined with algorithm-level coordinate compensation, the impact of vibration on detection accuracy is controlled within ±5μm; Wafer warpage adaptive detection: Utilizing multi-sensor fusion technology, laser displacement + visual imaging, real-time acquisition of wafer surface height information is obtained, and the detection focal length and imaging parameters are dynamically adjusted to ensure that the detection accuracy is not affected even when the wafer warpage is ±50μm; Redundant design and self-diagnostic function: The hardware adopts dual power supply and dual sensor backup, and automatically switches to the backup equipment when the main equipment fails; The software develops a self-diagnostic algorithm to monitor the equipment operating status in real time, provide early warning of potential faults, and achieve rapid fault recovery within <30 minutes.

5. The method for proportional wafer inspection based on visual perception according to claim 1, characterized in that... The method includes: <1> Hardware integration: The system employs a single, wide-format CIS module with integrated encapsulation. This module innovatively integrates a 12K resolution high-sensitivity photosensitive chip, a customized cylindrical uniform light lens, and a low-heat LED light source. Through over 300 optical path optimizations using the optical simulation software LightTools, it achieves 1:1 distortion-free imaging. It utilizes a dual-line array lens + compound eye bionic technology solution. The industrial-grade dual-line array lens employs a CMOS sensor with a 5μm pixel pitch. Combined with a compound eye bionic optical structure, it decomposes the incident light into 128 independent optical paths for parallel imaging by mimicking the multi-lens array principle of insect compound eyes. This avoids three major optical distortions: radial distortion, centrifugal distortion, and thin prism distortion, enabling the system to achieve a minimum detectable defect size of 40nm, reducing the false negative rate to below 0.1%, and improving detection accuracy. <2> Intelligent Algorithms: Based on the YOLOv11 framework, a multi-scale feature enhancement network, YOLOv11n, was developed through deep optimization. This model incorporates LAE to replace some standard convolutions, reducing the number of parameters and computational costs. A Dysample sampling template is introduced into the Neck to improve the detection effect of chip surface defects. The MCA mechanism is integrated into the Neck to improve detection capabilities, especially improving the accuracy of identifying tiny defects below 100nm, effectively solving the problem of insufficient detection capability of traditional algorithms for nanoscale defects. For the detection needs of wafers with different materials such as silicon-based and silicon carbide-based wafers, a dynamic adaptive detection algorithm is matched. This algorithm collects 12-dimensional environmental parameters, including light source illuminance and wafer material reflectivity, in real time through an environmental perception module. Based on the Bayesian optimization algorithm, a parameter matching model is constructed, which automatically completes the optimal configuration of key parameters such as light source wavelength of 450nm / 525nm and scanning speed of 15-25m / s within 50ms. <3> System Engineering: A high-speed data acquisition system is adopted, which integrates an 8-channel AD high-speed acquisition card and uses a PCIe 4.0 interface to achieve ultra-high-speed data transmission of 5.4GB / s. Combined with a 12000fps CIS camera, it eliminates equipment warm-up time and achieves plug-and-play quick start-up. In terms of system architecture design, a modular and scalable architecture is adopted, matching CIS line scanning systems that support 6-12 inch wafers. The magnetic quick-change structure enables the system to be quickly changed within 5 minutes. At the software level, a standardized API interface has been developed, which is fully compatible with the SEMIE100 communication protocol and can be seamlessly integrated into the customer's MES system to realize real-time uploading and analysis of detection data.

6. The method for proportional wafer inspection based on visual perception according to claim 1, characterized in that... This method includes the following aspects: Regarding efficiency: To avoid limitations imposed by data acquisition bandwidth and algorithm inference speed, high-speed imaging and real-time processing are achieved by employing multi-channel parallel acquisition technology. Through time-division multiplexing circuitry, single-channel noise is suppressed to 0.2μVrms, effectively improving data transmission efficiency and breaking through the traditional equipment's 3.75GB / s data transmission bottleneck, thus achieving ultra-high-speed data acquisition. A multi-level caching architecture and DMA direct memory access technology are adopted to ensure no data loss during high-speed scanning, laying the foundation for subsequent real-time processing. At the algorithm deployment level, LAE is introduced to replace part of the standard convolution, reducing the number of parameters and lowering computational costs; a Dysample sampling template is introduced into the Neck to improve the detection effect of chip surface defects; the MCA mechanism is integrated into the Neck to improve detection capabilities and meet the production line's detection speed requirement of 15 wafers per minute, achieving a significant improvement in efficiency while ensuring detection accuracy; in terms of accuracy, this method employs distortion-free detection and cross-scale recognition technology to solve the detection challenges of complex 3D stacked chip wafer structures, and develops precise optical system calibration technology; combined with checkerboard pattern... The calibration algorithm performs pixel-level coordinate mapping calibration at more than 200 points to establish a high-precision optical distortion correction model. Real-world data shows that the wafer size measurement error is <1μm, and the defect location accuracy reaches 0.1nm. For 3D stacked chips with more than 10 layers, it can also achieve accurate location of defects in each layer, completely solving the problem of inspection accuracy for complex wafer structures. In cross-scale defect detection, a multi-resolution feature fusion module is designed, using pyramid feature extraction and a self-attention mechanism to detect 100nm particles and 5μm cracks. This module first uses different scales... Convolutional kernels extract multi-resolution features, and then a self-attention layer dynamically focuses on minute defect regions, suppressing background noise interference. In defect database testing, this significantly reduces the false negative rate, effectively identifying even weak defects with a signal-to-noise ratio below 3. In terms of intelligence, this method employs data-driven defect detection technology. To address the limitation of traditional equipment that "can only identify known defects," a million-level defect sample library has been constructed, with 6 million wafer images annotated, covering 12 typical defects including scratches, chipping, and voids, as well as 20 types of complex background noise. Through methods such as rotation and scaling... Data augmentation techniques, including the addition of Gaussian noise, expand the sample size to 18 million images, forming a multimodal database. Based on this database, the algorithm automatically iterates and optimizes every week, significantly shortening the new defect identification cycle and improving the equipment's adaptability to novel defects. In the field of unknown defect detection, a self-supervised anomaly detection technique is adopted. By comparing and learning unlabeled data, a Generative Adversarial Network (GAN) is constructed to generate defects 100,000 times. This technique enables the model to learn the feature distribution of normal wafers and detect unknown defects through anomaly score calculation, achieving a measured accuracy rate.

7. The method for proportional wafer inspection based on visual perception according to claim 1, characterized in that... This method includes:

1. Utilizing an integrated system to integrate and package key components for high-speed image acquisition, reducing space occupation and energy consumption, and improving system stability; single-width component design reduces the number of components and splicing steps; employing plug-and-play combined with high-speed scanning technology enables rapid device startup and efficient operation; integrating hardware and software development; replacing the traditional multi-CIS splicing mode with a single-width CIS; integrating camera components and detection algorithm software packages; rapidly acquiring high-definition images and processing image data in real time; optimizing the detection process and reducing time delay; reducing energy consumption and extending equipment lifespan; 2. Introducing a compound eye bionic technology linear array lens: employing a dual-line array lens and compound eye bionic imaging technology, doubling detection accuracy; using a dual-line array lens optical design to directly focus light onto the linear photosensitive element, eliminating the complex process of traditional optical reduction technology; the compound eye structure arrangement forms an integrated imaging system, capable of simultaneously capturing light from different directions; employing RodLens... The array uses a linear array lens to replace the traditional optical reduction system and employs compound eye bionic imaging technology; it uses a CIS image sensor module and an AD conversion module; it overcomes the three major optical distortions and achieves 1:1 distortion-free imaging, thus improving clarity; 3. Optimization of wafer surface defect detection algorithm: Based on the deep learning framework, a 3D collaborative detection model is constructed by introducing LAE to replace part of the standard convolution, introducing the Dysample sampling template in the Neck, and integrating the MCA mechanism. By using LAE feature extraction, the model can obtain more contextual information and high-resolution details from multi-scale feature maps, forming a multi-modal feature representation system. For wafer defect detection, LAE is introduced to replace part of the standard convolution, reducing the number of parameters and computational cost; Dysample sampling template is introduced into the Neck to improve the detection effect of chip surface defects; MCA mechanism is integrated into the Neck to significantly improve detection capability; a strategy combining contrastive learning and self-supervised learning is adopted in the training phase, using massive unlabeled data for pre-training and combining a small number of labeled samples for fine-tuning to alleviate the problem of insufficient data; a dynamic model integration framework is established to improve accuracy and robustness, and a full-link evaluation system covering multi-dimensional indicators is constructed.

8. A vision-based proportional wafer inspection system, characterized in that... The system is implemented based on the visual perception-based proportional wafer inspection method as described in any one of claims 1 to 7.

9. The application of the visual perception-based proportional wafer inspection method as described in any one of claims 1 to 7 in chip manufacturing processes.

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