Display device and electronic device including the same

Abstract

A display device and an electronic apparatus including the same are disclosed. The display device includes: a display panel including pixels; a scan driver configured to supply a first scan signal and a second scan signal to the pixels; and a power management circuit configured to supply the first power voltage and the second power voltage to the pixel. The second scan signal includes an active pulse in an active period having a constant time length and a plurality of dummy pulses in a vertical blank period having a variable time length. A width of each of the plurality of dummy pulses is less than a width of the active pulse. An interval between the plurality of dummy pulses is smaller than an interval between the active pulse and a first dummy pulse of the plurality of dummy pulses.

Description

Display device and electronic device including the display device Technical Field

[0001] The example embodiments relate to display devices. More specifically, the example embodiments relate to display devices driven by variable refresh rates and / or electronic devices including such display devices. Background Technology

[0002] The display device may include a display panel, a scan driver, and power management circuitry. The display panel may include pixels for displaying images. The scan driver provides scan signals to the pixels. The power management circuitry provides electrical voltage to the pixels.

[0003] The display device can be driven in a variable refresh rate (VRR) mode, in which the driving frequency of the display panel can be changed. When the display device displays moving images, the driving frequency of the display panel can be increased to relatively improve the image quality of the display device. When the display device displays still images, the driving frequency of the display panel can be decreased to reduce the power consumption of the display device. Summary of the Invention

[0004] Some example embodiments provide a display device with improved image quality and an electronic device including the display device.

[0005] A display device according to some example embodiments includes: a display panel including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; and a power management circuit configured to provide a first power voltage and a second power voltage to the pixels, wherein the second scan signal includes a valid pulse in an effective time period having a constant duration and a plurality of dummy pulses in a vertical blank time period having a variable duration, wherein the width of each of the plurality of dummy pulses is less than the width of the valid pulse, and wherein the interval between the plurality of dummy pulses is less than the interval between the valid pulse and the first dummy pulse among the plurality of dummy pulses.

[0006] In some example embodiments, the widths of multiple dummy pulses may be equal to each other.

[0007] In some example embodiments, the intervals between multiple dummy pulses can be equal to each other.

[0008] In some example embodiments, a pixel may include: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power voltage, and a second terminal connected to a second node; a second transistor including a second gate configured to receive a first scan signal, a third terminal configured to receive a data voltage, and a fourth terminal connected to the first node; a third transistor including a third gate configured to receive a second scan signal, a fifth terminal configured to receive a reference voltage, and a sixth terminal connected to the second node; a capacitor including a seventh terminal connected to the first node and an eighth terminal connected to the second node; and a light-emitting diode including a ninth terminal connected to the second node and a tenth terminal configured to receive a second power voltage.

[0009] In some example embodiments, in response to a pulse of the first scan signal and a valid pulse of the second scan signal during a valid time period, the capacitor may be configured to store the difference between the data voltage and the reference voltage, and wherein the third transistor may be configured to apply the reference voltage to the second node in response to a plurality of dummy pulses.

[0010] In some example embodiments, the reference voltage level may be lower than the threshold voltage level of the light-emitting diode.

[0011] In some example embodiments, the first scan signal may include a pulse during the active period and a deactivation level during the vertical blank period.

[0012] In some example embodiments, the first power voltage may have a constant high voltage level, and the second power voltage may have a constant low voltage level below the constant high voltage level.

[0013] A display device according to some example embodiments includes: a display panel including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; and a power management circuit configured to provide a power voltage to the pixels, wherein the second scan signal includes a valid pulse in an effective time period having a constant duration, the power voltage includes a plurality of pulses in a vertical blank time period having a variable duration, each of the widths of the plurality of power voltage pulses is less than the width of the valid pulse, and the interval between the plurality of power voltage pulses is less than the interval between the valid pulse and the first pulse of the plurality of power voltage pulses.

[0014] In some example embodiments, the widths of the multiple pulses of the electrical voltage can be equal to each other.

[0015] In some example embodiments, the intervals between multiple pulses of electrical voltage can be equal to each other.

[0016] In some example embodiments, a pixel may include: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power voltage, and a second terminal connected to a second node; a second transistor including a second gate configured to receive a first scan signal, a third terminal configured to receive a data voltage, and a fourth terminal connected to the first node; a third transistor including a third gate configured to receive a second scan signal, a fifth terminal configured to receive a reference voltage, and a sixth terminal connected to the second node; a capacitor including a seventh terminal connected to the first node and an eighth terminal connected to the second node; and a light-emitting diode including a ninth terminal connected to the second node and a tenth terminal configured to receive a second power voltage, wherein the power voltage may be either the first power voltage or the second power voltage.

[0017] In some example embodiments, the power voltage may be a first power voltage and may have a constant high voltage level during the effective period, and multiple pulses of the power voltage may have low voltage levels below the constant high voltage level.

[0018] In some example embodiments, the power voltage may be a second power voltage and may have a constant low voltage level during the effective period, and multiple pulses of the power voltage may have a high voltage level higher than the constant low voltage level.

[0019] In some example embodiments, the first scan signal may include a pulse during the active period and a deactivation level during the vertical blank period.

[0020] In some example embodiments, the second scan signal may have a deactivation level during the vertical blank period.

[0021] An electronic device according to some example embodiments includes: a display device; and a processor configured to control the display device, wherein the display device includes: a display panel including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; and a power management circuit configured to provide a first power voltage and a second power voltage to the pixels, wherein the second scan signal includes a valid pulse in an effective time period having a constant duration and a plurality of dummy pulses in a vertical blank time period having a variable duration, each of the widths of the plurality of dummy pulses being less than the width of the valid pulse, and the interval between the plurality of dummy pulses being less than the interval between the valid pulse and the first dummy pulse among the plurality of dummy pulses.

[0022] In some example embodiments, the widths of multiple dummy pulses may be equal to each other.

[0023] In some example embodiments, the intervals between multiple dummy pulses can be equal to each other.

[0024] In some example embodiments, a pixel may include: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power voltage, and a second terminal connected to a second node; a second transistor including a second gate configured to receive a first scan signal, a third terminal configured to receive a data voltage, and a fourth terminal connected to the first node; a third transistor including a third gate configured to receive a second scan signal, a fifth terminal configured to receive a reference voltage, and a sixth terminal connected to the second node; a capacitor including a seventh terminal connected to the first node and an eighth terminal connected to the second node; and a light-emitting diode including a ninth terminal connected to the second node and a tenth terminal configured to receive a second power voltage.

[0025] In display devices and electronic devices according to some example embodiments, i) the width of each of the dummy pulses of the second scan signal is less than the width of the effective pulse of the second scan signal, and the interval between the dummy pulses of the second scan signal is less than the interval between the effective pulse of the second scan signal and the first dummy pulse, or ii) the width of each of the pulses of the power voltage is less than the width of the effective pulse of the second scan signal, and the interval between the pulses of the power voltage is less than the interval between the effective pulse of the second scan signal and the first pulse of the power voltage, such that the brightness deviation between frequencies can be reduced, and accordingly, the image quality of the display device can be improved. Attached Figure Description

[0026] The illustrative and non-limiting exemplary embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram illustrating a display device according to some example embodiments.

[0028] Figure 2 is a circuit diagram of the pixel shown in Figure 1.

[0029] Figure 3 is a diagram illustrating the variable refresh rate mode of the display device in Figure 1.

[0030] Figure 4 is a timing diagram used to describe the operation of the pixels according to the comparison example at the first and second frequencies.

[0031] Figure 5 is a timing diagram illustrating the brightness of the display device according to the comparative example at the first and second frequencies.

[0032] Figure 6 is a diagram illustrating the operation of a pixel at a second frequency when using a dummy cutoff drive.

[0033] Figure 7 is a timing diagram illustrating the brightness of the display device at a second frequency when using a dummy cutoff drive.

[0034] Figure 8 is a graph illustrating the relationship between the frequency and brightness of a display device when using dummy cutoff drive and when not using dummy cutoff drive.

[0035] Figure 9 is a graph illustrating the number of cutoffs and brightness of the LED at the first to fifth frequencies when using dummy cutoff drive.

[0036] Figure 10 is a timing diagram illustrating a first scan signal, a second scan signal, a first power voltage, a second power voltage, and brightness according to some example embodiments.

[0037] Figure 11 is a graph illustrating the relationship between the frequency and brightness of a display device when using dummy cutoff drive and when using split dummy cutoff drive.

[0038] Figure 12 is a graph illustrating the brightness of the display device at the same frequency when using dummy cutoff drive and when using split dummy cutoff drive.

[0039] Figure 13 is a timing diagram illustrating a first scan signal, a second scan signal, a first power voltage, a second power voltage, and brightness according to some example embodiments.

[0040] Figure 14 is a timing diagram illustrating a first scan signal, a second scan signal, a first power voltage, a second power voltage, and brightness according to some example embodiments.

[0041] Figure 15 is a block diagram illustrating an electronic device according to some example embodiments.

[0042] Figure 16 is a diagram illustrating an example in which the electronic device of Figure 15 is implemented as a computer monitor. Detailed Implementation

[0043] In the following description, display devices and electronic devices according to some exemplary embodiments will be described in more detail with reference to the accompanying drawings. The same or similar reference numerals will be used for the same elements in the drawings.

[0044] It will be understood that elements and / or their attributes may be stated herein as “identical” or “equal” to other elements and / or their attributes, and it will be further understood that elements and / or their attributes stated herein as “completely identical,” “identical,” or “equal” to other elements and / or their attributes may be “completely identical,” “identical,” or “equal” to those other elements and / or their attributes, or “substantially identical,” “substantially identical,” or “substantially equal.” Elements and / or their attributes that are “substantially identical,” “substantially identical,” or “substantially equal” to other elements and / or their attributes will be understood to include elements and / or their attributes that are completely identical, identical, or equal to those other elements and / or their attributes within manufacturing tolerances and / or material tolerances. Elements and / or their attributes that are completely identical or substantially identical to other elements and / or their attributes may be structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical.

[0045] It will be understood that elements and / or attributes described herein as "substantially" identical and / or completely identical include elements and / or attributes having a relative amplitude difference of equal to or less than 10%. Furthermore, regardless of whether an element and / or attribute is modified to "substantially," it will be understood that these elements and / or attributes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated elements and / or attributes.

[0046] When the terms “approximately” or “basically” are used in conjunction with numerical values ​​in this specification, it means that the associated numerical value includes a tolerance of ±10% around the stated numerical value. When a range is specified, the range includes all values ​​in increments such as 0.1%. Furthermore, regardless of whether numerical values ​​or shapes are modified to “approximately” or “basically”, it will be understood that these numerical values ​​and shapes should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​or shapes.

[0047] Figure 1 is a block diagram illustrating a display device 100 according to some example embodiments.

[0048] Referring to FIG1, the display device 100 may include a display panel 110, a data driver 120, a scan driver 130, a power management circuit 140, and / or a controller 150.

[0049] The display panel 110 may include multiple data lines, multiple first scan lines, multiple second scan lines, and / or multiple pixels PX. The data lines can provide a data voltage DV to the pixels PX. The first scan lines can provide a first scan signal S1 to the pixels PX. The second scan lines can provide a second scan signal S2 to the pixels PX. The pixels PX can emit light in response to the data voltage DV, the first scan signal S1, and / or the second scan signal S2.

[0050] The display panel 110 may further include multiple reference voltage lines. These reference voltage lines can provide a reference voltage to the pixel PX. In some example embodiments, the reference voltage lines can be used as sensing lines for sensing characteristics of the pixel PX.

[0051] Data driver 120 can provide a data voltage DV to pixel PX via a data line. Data driver 120 can generate the data voltage DV based on a data control signal DCTRL and output image data ODAT. In some example embodiments, the data control signal DCTRL may include an output data enable signal, a level start signal, and / or a load signal. In some example embodiments, data driver 120 can receive output image data ODAT at a drive frequency DF that is variable within a selected range.

[0052] In some example embodiments, the data driver 120 and the controller 150 may be implemented as a single integrated circuit, and such an integrated circuit may be referred to as a timing controller embedded data driver (TED). In some example embodiments, the data driver 120 and the controller 150 may be implemented as separate integrated circuits.

[0053] The scan driver 130 can sequentially provide a first scan signal S1 to pixel PX via a first scan line on a pixel-row basis, and can sequentially provide a second scan signal S2 to pixel PX via a second scan line on a pixel-row basis. The scan driver 130 can generate the first scan signal S1 and / or the second scan signal S2 based on the scan control signal SCTRL.

[0054] In some example embodiments, the scan driver 130 may be formed and / or mounted in the peripheral area of ​​the display panel 110. In some example embodiments, the scan driver 130 may be implemented as at least one integrated circuit.

[0055] The power management circuit 140 can provide a first power voltage ELVDD and / or a second power voltage ELVSS to the pixel PX. The power management circuit 140 can generate the first power voltage ELVDD and / or the second power voltage ELVSS based on the power control signal PCTRL.

[0056] Controller 150 can control the operation (or drive) of data driver 120, scan driver 130, and / or power management circuit 140. Controller 150 can provide output image data ODAT and data control signal DCTRL to data driver 120, scan control signal SCTRL to scan driver 130, and power control signal PCTRL to power management circuit 140. Controller 150 can generate output image data ODAT, data control signal DCTRL, scan control signal SCTRL, and / or power control signal PCTRL based on input image data IDAT and / or control signal CTRL. In some example embodiments, input image data IDAT may include red image data, green image data, and / or blue image data. In some example embodiments, control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, and / or a master clock signal. Controller 150 can receive input image data IDAT and / or control signal CTRL from an external host processor (e.g., processor 1010 shown in FIG. 15).

[0057] The host processor can change the length of the vertical blanking intervals in each frame segment or one or more frame segments to provide input image data IDAT to the controller 150 at a variable input frame rate (VIFF) that varies within a selected range. The controller 150 can control the data driver 120, the scan driver 130, and / or the power management circuitry 140 to drive the display panel 110 at a drive frequency DF corresponding to the variable input frame rate (VIFF). For example, the drive frequency DF of the display panel 110 can be determined as the variable input frame rate (VIFF). In some example embodiments, the mode in which the display device 100 drives the display panel 110 with the variable input frame rate (VIFF) can be referred to as a variable refresh rate (VRR) mode. The variable refresh rate mode can be a free synchronization mode, a G-synchronization mode, etc., but is not limited to these.

[0058] Figure 2 is a circuit diagram of pixel PX in Figure 1.

[0059] Referring to Figures 1 and 2, a pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a capacitor CST, and / or a light-emitting diode (LED). The pixel PX may receive a first scan signal S1, a second scan signal S2, a data voltage DV, a reference voltage VREF, a first power voltage ELVDD, and / or a second power voltage ELVSS. In some example embodiments, the voltage level of the first power voltage ELVDD may be higher than the voltage level of the second power voltage ELVSS. In some example embodiments, the voltage level of the reference voltage VREF may be lower than the threshold voltage level of the LED.

[0060] The first transistor T1 can generate a drive current corresponding to the voltage difference between the first node NG and the second node NS. The first transistor T1 may include a gate connected to the first node NG, a first terminal (e.g., drain) receiving a first power voltage ELVDD, and / or a second terminal (e.g., source) connected to the second node NS.

[0061] The second transistor T2 can transmit the data voltage DV to the first node NG in response to the first scan signal S1. The second transistor T2 may include a gate that receives the first scan signal S1, a first terminal (e.g., drain) connected to the data line DL that transmits the data voltage DV, and / or a second terminal (e.g., source) connected to the first node NG.

[0062] The third transistor T3 can transmit the reference voltage VREF to the second node NS in response to the second scan signal S2. The third transistor T3 may include a gate receiving the second scan signal S2, a first terminal (e.g., drain) connected to the reference voltage line VREFL through which the reference voltage VREF is transmitted, and / or a second terminal (e.g., source) connected to the second node NS. In some example embodiments, the third transistor T3 can transmit the voltage of the second node NS, reflecting the characteristics of the first transistor T1 and / or the characteristics of the light-emitting diode (LED), to the reference voltage line VREFL in response to the second scan signal S2.

[0063] In some example embodiments, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be an NMOS transistor. In some example embodiments, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be a PMOS transistor.

[0064] A capacitor CST can be connected between a first node NG and a second node NS. The capacitor CST may include a first terminal connected to the first node NG and / or a second terminal connected to the second node NS.

[0065] The light-emitting diode (LED) may include a first terminal (e.g., anode) connected to the second node NS and / or a second terminal (e.g., cathode) receiving a second power voltage ELVSS. The LED may emit light with a brightness corresponding to the drive current generated by the first transistor T1.

[0066] Figure 3 is a diagram illustrating the variable refresh rate mode of the display device 100 of Figure 1.

[0067] Referring to Figures 1 and 3, the period or frequency of the rendering 210 and 220 of the host processor may not be constant, and the host processor can provide input image data IDAT (e.g., frame data FD1 and / or FD2) to the display device 100 in a variable refresh rate mode in synchronization with the non-constant period or frequency of the rendering 210 and 220. In the variable refresh rate mode, at least one frame period FP1 and / or FP2 may have effective periods AP1 and / or AP2 with constant duration, and the host processor can provide frame data FD1 and / or FD2 to the display device 100 at a variable input frame rate VIFF by changing the duration of the vertical blank periods VBP1 and / or VBP2 of at least one frame period FP1 and / or FP2.

[0068] As illustrated in Figure 3, during the first frame period FP1, when rendering the second frame data FD2 at the first frequency FRQ1, the host processor can provide the first frame data FD1 to the display device 100 at a variable input frame rate (VIFF) of the first frequency FRQ1. Furthermore, the host processor can output the second frame data FD2 during the effective period AP2 of the second frame period FP2, and can continue the vertical blank period VBP2 of the second frame period FP2 until the rendering of the third frame data FD3 is completed. Correspondingly, during the second frame period FP2, when rendering the third frame data FD3 at a second frequency FRQ2 lower than the first frequency FRQ1, the host processor can increase the duration of the vertical blank period VBP2 of the second frame period FP2, thereby providing the second frame data FD2 to the display device 100 at a variable input frame rate (VIFF) of the second frequency FRQ2.

[0069] In variable refresh rate mode, at least one frame period FP1 and FP2 may include effective periods AP1 and / or AP2 with a constant duration regardless of the variable input frame rate VIFF, and vertical blank periods VBP1 and / or VBP2 with a variable duration corresponding to the variable input frame rate VIFF. For example, in variable refresh rate mode, as the variable input frame rate VIFF decreases, the duration of the vertical blank periods VBP1 and / or VBP2 may increase. In variable refresh rate mode, controller 150 may output input image data IDAT received at the variable input frame rate VIFF as output image data ODAT to data driver 120 at a drive frequency DF substantially equal to the variable input frame rate VIFF. Accordingly, the display device 100 supporting variable refresh rate mode can display images synchronously with the variable input frame rate VIFF to reduce or prevent tearing caused by frame rate mismatch.

[0070] Figure 4 is a timing diagram describing the operation of pixel PX according to the comparison example at the first frequency FRQ1 and the second frequency FRQ2.

[0071] Referring to Figures 2 and 4, pixel PX can simultaneously receive pulses of the first scan signal S1 and the second scan signal S2 during at least one effective time period AP1 and / or AP2. When the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, the data voltage DV can be applied to the first node NG (e.g., the first terminal of capacitor CST), and the reference voltage VREF can be applied to the second node NS (e.g., the second terminal of capacitor CST). Accordingly, when the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, capacitor CST can store the difference between the data voltage DV and the reference voltage VREF. When the pulses of the first scan signal S1 and the second scan signal S2 are applied to pixel PX, the light-emitting diode LED may not emit light because the second node NS, connected to the first terminal of the light-emitting diode LED, has the reference voltage VREF.

[0072] The duration of the vertical blank periods VBP1 and / or VBP2 can vary depending on the driving frequency DF of the display panel 110. The duration of the vertical blank period VBP1 when the display panel 110 is driven at a first frequency FRQ1 can differ from the duration of the vertical blank period VBP2 when the display panel 110 is driven at a second frequency FRQ2, which is different from the first frequency FRQ1. During the same duration, the number of times the pulses of the first scan signal S1 and the second scan signal S2 are applied to the pixel PX (e.g., the number of times the light-emitting diode (LED) is turned off) when the display panel 110 is driven at the first frequency FRQ1 can differ from the number of times the pulses of the first scan signal S1 and the second scan signal S2 are applied to the pixel PX when the display panel 110 is driven at the second frequency FRQ2. Accordingly, even if the display device according to the comparative example displays an image with the same grayscale, the brightness of the display panel 110 may change when the driving frequency DF of the display panel 110 changes, and flickering may occur.

[0073] Figure 5 is a timing diagram illustrating the brightness of a display device according to a comparative example at a first frequency FRQ1 and a second frequency FRQ2.

[0074] Referring to FIG5, in the display device according to the comparative example, the LEDs of the display panel 110 driven at a first frequency FRQ1 (e.g., approximately 240 Hz) can be turned off approximately four times during the same time period, and the LEDs of the display panel 110 driven at a second frequency FRQ2 (e.g., approximately 60 Hz) can be turned off approximately once. Accordingly, the average brightness AVGLUM2 of the display panel 110 driven at the second frequency FRQ2 (e.g., 2.1 nits) can be higher than the average brightness AVGLUM1 of the display panel 110 driven at the first frequency FRQ1 (e.g., 1.6 nits).

[0075] Figure 6 is a diagram illustrating the operation of pixel PX at the second frequency FRQ2 when using dummy cutoff drive.

[0076] Referring to Figures 2 and 6, in order to reduce or prevent the brightness increase of the display panel 110 at low frequencies, the first scan signal S1 can be provided to the pixel PX at the drive frequency DF, and the second scan signal S2 can be provided to the pixel PX at the maximum drive frequency (e.g., the first frequency FRQ1). The driving mode in which the second scan signal S2 is provided to the pixel PX at the maximum drive frequency can be referred to as dummy cutoff driving.

[0077] As illustrated in Figure 6, when the display panel 110 is driven at a second frequency FRQ2, which is lower than the first frequency FRQ1 (the maximum driving frequency), the pulses of the first scan signals S1_1, ..., S1_N and the effective pulse PS_A of the second scan signals S2_1, ..., S2_N can be provided to the pixel PX sequentially on a pixel-row basis during the effective time period AP2. The pulses of the first scan signals S1_1, ..., S1_N can not be provided to the pixel PX during the vertical blank time period VBP2, and the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be provided to the pixel PX at least once on a pixel-row basis during the vertical blank time period VBP2. For example, as illustrated in Figure 6, when the display panel 110 is driven at the second frequency FRQ2, the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N can be provided to the pixel PX three times during the vertical blank time period VBP2. Correspondingly, during the vertical blank period VBP2, when the pulses of the first scan signals S1_1, ..., S1_N are not applied to pixel PX, and the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N are applied to pixel PX, the third transistor T3 of pixel PX can apply the reference voltage VREF to the second node NS, and the voltages V_NS_1, ..., V_NS_N of the second node NS can be changed from the first power voltage ELVDD to the reference voltage VREF. Because the voltages V_NS_1, ..., V_NS_N of the second node NS with the reference voltage VREF are present, the light-emitting diode (LED) of pixel PX can remain off. Accordingly, when the pulses of the first scan signals S1_1, ..., S1_N and the effective pulse PS_A of the second scan signals S2_1, ..., S2_N are applied to pixel PX during the effective time period AP2, the light-emitting diode (LED) may not emit light. Furthermore, when only the dummy pulses PS_D1, PS_D2, and PS_D3 of the second scan signals S2_1, ..., S2_N are applied to pixel PX, the LED may not emit light.

[0078] Figure 7 is a timing diagram illustrating the brightness of the display device at the second frequency FRQ2 when using a dummy cutoff drive.

[0079] Referring to Figures 5 and 7, when using dummy cutoff driving, the number of times the LED of pixel PX is turned off when driving display panel 110 at the first frequency FRQ1 can be substantially the same as the number of times the LED of pixel PX is turned off when driving display panel 110 at the second frequency FRQ2. Accordingly, when using dummy cutoff driving, even if the driving frequency DF of display panel 110 changes, the brightness of display panel 110 can remain largely unchanged, and flickering can be avoided. As illustrated in Figures 5 and 7, when using dummy cutoff driving, the LED of display panel 110 driven at the first frequency FRQ1 can be turned off approximately 4 times during the same time period, and the LED of display panel 110 driven at the second frequency FRQ2 can also be turned off approximately 4 times. Accordingly, the average brightness AVGLUM2' (e.g., 1.6 nits) of display panel 110 driven at the second frequency FRQ2 can be substantially equal to the average brightness AVGLUM1 (e.g., 1.6 nits) of display panel 110 driven at the first frequency FRQ1.

[0080] Figure 8 is a graph illustrating the relationship between frequency and brightness of a display device when using dummy cutoff driving and when not using dummy cutoff driving. Figure 9 is a graph illustrating the number of cutoffs OFF_NUM and brightness of the light-emitting diode at the first to fifth frequencies FRQ_1, FRQ_2, FRQ_3, FRQ_4, and FRQ_5 when using dummy cutoff driving.

[0081] Referring to Figures 8 and 9, when the display device does not use dummy cutoff drive, the brightness of the display device can increase as the frequency of the display device decreases. The interval between the effective cutoff OFF_A of the light-emitting diodes (e.g., the cutoff period of the light-emitting diode in the effective time period) can increase as the frequency of the display device decreases, and correspondingly, the number of effective cutoff OFF_A of the light-emitting diodes can decrease as the frequency of the display device decreases during the same time length. For example, within the same time length, the number of effective cutoff OFF_A of the light-emitting diodes at the first frequency FRQ_1 can be 7, the number of effective cutoff OFF_A of the light-emitting diodes at the second frequency FRQ_2 can be 6, the number of effective cutoff OFF_A of the light-emitting diodes at the third frequency FRQ_3 can be 4, the number of effective cutoff OFF_A of the light-emitting diodes at the fourth frequency FRQ_4 can be 3, and / or the number of effective cutoff OFF_A of the light-emitting diodes at the fifth frequency FRQ_5 can be 3.

[0082] When a display device uses a dummy cutoff drive, the brightness of the display device can be reduced or prevented from increasing at low frequencies. Even though the interval between the effective cutoff OFF_A of the LEDs increases as the frequency of the display device decreases, the number of cutoffs OFF_NUM of the LEDs, which is the sum of the number of effective cutoffs and the number of dummy cutoffs, can also increase at low frequencies because the dummy cutoff OFF_D of the LEDs (e.g., the cutoff period of the LEDs in the vertical blank period) is periodically inserted after the effective cutoff OFF_A of the LEDs.

[0083] When a display device uses a dummy cutoff drive, the number of cutoffs (OFF_NUM) for the same time length of an LED may vary depending on the frequency of the display device, and the deviation in the number of cutoffs between frequencies may increase. For example, during the same time length, the number of cutoffs (OFF_NUM) of an LED at a first frequency (FRQ_1) may be 7, the number of cutoffs (OFF_NUM) at a second frequency (FRQ_2) may be 11, the number of cutoffs (OFF_NUM) at a third frequency (FRQ_3) may be 7, the number of cutoffs (OFF_NUM) at a fourth frequency (FRQ_4) may be 9, and / or the number of cutoffs (OFF_NUM) at a fifth frequency (FRQ_5) may be 7. Accordingly, the brightness deviation between frequencies may increase, and the image quality of the display device may deteriorate.

[0084] Figure 10 is a timing diagram illustrating a first scan signal S1, a second scan signal S2, a first power voltage ELVDD, a second power voltage ELVSS, and a brightness LUM according to some example embodiments.

[0085] Referring to Figure 10, the second scan signal S2 may include an effective pulse PS_A in the effective time period AP and multiple dummy pulses PS_D in the vertical blank time period VBP. In some example embodiments, to reduce brightness deviation between frequencies, the width of each of the dummy pulses PS_D in the second scan signal S2 may be smaller than the width of the effective pulse PS_A in the second scan signal S2. In some example embodiments, a dummy pulse driven by a dummy cutoff may be divided into multiple dummy pulses PS_D. The driving mode of dividing a dummy pulse driven by a dummy cutoff into multiple dummy pulses PS_D can be referred to as segmented dummy cutoff driving. The interval WDD between the dummy pulses PS_D in the second scan signal S2 may be smaller than the interval WAD between the effective pulse PS_A and the first dummy pulse PS_D in the second scan signal S2. The width of each of the dummy pulses PS_D in the second scan signal S2 may be smaller than the width of the effective pulse PS_A in the second scan signal S2, such that the width of the dummy cutoff OFF_D of the light-emitting diode in the vertical blank time period VBP may be smaller than the width of the effective cutoff OFF_A of the light-emitting diode in the effective time period AP.

[0086] In some example embodiments, the widths of the dummy pulses PS_D of the second scan signal S2 may be equal to each other. In some example embodiments, the intervals WDD between the dummy pulses PS_D of the second scan signal S2 may be equal to each other.

[0087] The first scan signal S1 may include a pulse in the effective time period AP and may have a deactivation level in the vertical blank time period VBP.

[0088] The first power voltage, ELVDD, can have a constant high voltage level, VLH. The second power voltage, ELVSS, can have a constant low voltage level, VLL. The low voltage level, VLL, can be lower than the high voltage level, VLH.

[0089] Figure 11 is a graph illustrating the relationship between frequency and brightness of a display device when using dummy cutoff driving and when using split dummy cutoff driving. Figure 12 is a graph illustrating the brightness of a display device at the same frequency when using dummy cutoff driving and when using split dummy cutoff driving.

[0090] Referring to Figures 11 and 12, the brightness deviation between frequencies when using segmented dummy cutoff drive can be smaller than that when using dummy cutoff drive. In dummy cutoff drive, because the width of the dummy cutoff OFF_D of the LED is relatively large, the brightness deviation between frequencies is large depending on whether the dummy cutoff OFF_D of the LED is present. However, in segmented dummy cutoff drive, because the width of the dummy cutoff OFF_D of the LED is relatively small, the brightness deviation between frequencies can be small regardless of whether the dummy cutoff OFF_D of the LED is present. In other words, in dummy cutoff drive, because the width of the dummy cutoff OFF_D of the LED is relatively large, the brightness reduction due to the addition of one dummy cutoff OFF_D of the LED is relatively large. However, in segmented dummy cutoff drive, because the width of the dummy cutoff OFF_D of the LED is relatively small, the brightness reduction can be relatively small even if one dummy cutoff OFF_D of the LED is added.

[0091] Figure 13 is a timing diagram illustrating a first scan signal S1, a second scan signal S2, a first power voltage ELVDD, a second power voltage ELVSS, and a brightness LUM according to some example embodiments.

[0092] Referring to Figure 13, the first power voltage ELVDD can have a constant high voltage level VLH during the active period AP, and can include multiple pulses PS during the vertical blank period VBP. The pulses PS of the first power voltage ELVDD can have a low voltage level VLL. The low voltage level VLL can be lower than the high voltage level VLH. During the vertical blank period VBP, the light-emitting diode of the pixel can be turned off in response to the pulses PS of the first power voltage ELVDD, and the number of times the light-emitting diode is turned off during the vertical blank period VBP can be equal to the number of pulses PS of the first power voltage ELVDD during the vertical blank period VBP.

[0093] In some example embodiments, to reduce brightness deviations between frequencies, the width of each of the pulses PS of the first power voltage ELVDD can be smaller than the width of the effective pulse PS_A of the second scan signal S2. Furthermore, the interval WSS between the pulses PS of the first power voltage ELVDD can be smaller than the interval WAS between the effective pulse PS_A of the second scan signal S2 and the first pulse PS of the first power voltage ELVDD. The fact that the width of each of the pulses PS of the first power voltage ELVDD is smaller than the width of the effective pulse PS_A of the second scan signal S2 allows the width of the dummy cutoff OFF_D of the light-emitting diode during the vertical blank period VBP to be smaller than the width of the effective cutoff OFF_A of the light-emitting diode during the active period AP.

[0094] Therefore, according to some example embodiments, the display device using segmented dummy cutoff driving according to the example embodiments can display images with improved image quality having reduced or eliminated flicker and reduced brightness deviation.

[0095] In some example embodiments, the pulse widths of the first power voltage ELVDD pulses PS can be equal to each other. In some example embodiments, the intervals WSS between the pulses PS of the first power voltage ELVDD can be equal to each other.

[0096] The first scan signal S1 may include a pulse in the effective time period AP and may have a deactivation level in the vertical blank time period VBP.

[0097] The second scan signal S2 may include the valid pulse PS_A in the valid time period AP, and may have the deactivation level in the vertical blank time period VBP.

[0098] The second power voltage ELVSS can have a constant low voltage level VLL.

[0099] Figure 14 is a timing diagram illustrating a first scan signal S1, a second scan signal S2, a first power voltage ELVDD, a second power voltage ELVSS, and a brightness LUM according to some example embodiments.

[0100] Referring to Figure 14, the second power voltage ELVSS can have a constant low voltage level VLL during the active period AP, and can include multiple pulses PS during the vertical blank period VBP. The pulses PS of the second power voltage ELVSS can have a high voltage level VLH. The high voltage level VLH can be higher than the low voltage level VLL. During the vertical blank period VBP, the light-emitting diode of the pixel can be turned off in response to the pulses PS of the second power voltage ELVSS, and the number of times the light-emitting diode is turned off during the vertical blank period VBP can be equal to the number of pulses PS of the second power voltage ELVSS during the vertical blank period VBP.

[0101] In some example embodiments, to reduce brightness deviation between frequencies, the width of each of the pulses PS of the second power voltage ELVSS can be smaller than the width of the effective pulse PS_A of the second scan signal S2. The interval WSS between the pulses PS of the second power voltage ELVSS can be smaller than the interval WAS between the effective pulse PS_A of the second scan signal S2 and the first pulse PS of the second power voltage ELVSS. The width of each of the pulses PS of the second power voltage ELVSS can be smaller than the width of the effective pulse PS_A of the second scan signal S2, such that the width of the dummy cutoff OFF_D of the light-emitting diode in the vertical blank period VBP can be smaller than the width of the effective cutoff OFF_A of the light-emitting diode in the active period AP.

[0102] In some example embodiments, the pulse widths (PS) of the second power voltage ELVSS can be equal to each other. In some example embodiments, the intervals (WSS) between the pulses (PS) of the second power voltage ELVSS can be equal to each other.

[0103] The first scan signal S1 may include a pulse in the effective time period AP and may have a deactivation level in the vertical blank time period VBP.

[0104] The second scan signal S2 may include the valid pulse PS_A in the valid time period AP, and may have the deactivation level in the vertical blank time period VBP.

[0105] The first power voltage ELVDD can have a constant high voltage level VLH.

[0106] Figure 15 is a block diagram illustrating an electronic device 1000 according to some example embodiments. Figure 16 is a diagram illustrating an example in which the electronic device 1000 of Figure 15 is implemented as a computer monitor.

[0107] Referring to Figures 15 and 16, the electronic device 1000 can output various information through the display module 1040 within the operating system. When the processor 1010 executes an application stored in the memory 1020, the display module 1040 can provide application information to the user through the display panel 1041. In some example embodiments, the processor 1010 can provide the input image data IDAT of Figure 1 and the control signal CTRL of Figure 1 to the display module 1040.

[0108] Processor 1010 can obtain external input through input module 1030 and / or sensor module 1061, and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 1041, processor 1010 can obtain user input through input sensors 1061-2 and can activate camera module 1071. Processor 1010 can transmit image data corresponding to the captured image acquired by camera module 1071 to display module 1040. Display module 1040 can display the image corresponding to the captured image through display panel 1041. Some of the components of electronic device 1000 can be integrated and provided as one component, or one component can be separately provided as two or more components.

[0109] Electronic device 1000 can communicate with external electronic device 1002 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In some example embodiments, electronic device 1000 may include processor 1010, memory 1020, input module 1030, display module 1040, power module 1050, internal module 1060, and / or external module 1070. In some example embodiments, electronic device 1000 may omit at least one of the above-mentioned components, and / or may add one or more other components. In some example embodiments, some of the above-mentioned components (e.g., sensor module 1061, antenna module 1062, and / or sound output module 1063) may be integrated into another component (e.g., display module 1040).

[0110] The processor 1010 can execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1010, and can perform various data processing and / or calculations. In some example embodiments, as at least part of the data processing and / or calculations, the processor 1010 can store commands and / or data received from another component (e.g., input module 1030, sensor module 1061, and / or communication module 1073) in volatile memory 1021, can process commands and / or data stored in volatile memory 1021, and can store result data in non-volatile memory 1022.

[0111] Processor 1010 may include main processor 1011 and / or coprocessor 1012. Main processor 1011 may include one or more of central processing unit (CPU) 1011-1 and application processor (AP). Main processor 1011 may further include one or more of graphics processing unit (GPU) 1011-2, communication processor (CP), and image signal processor (ISP). At least two of the above processing units and processors may be implemented as integrated components (e.g., a single chip), or each may be implemented as a separate component (e.g., multiple chips).

[0112] The coprocessor 1012 may include a controller 1012-1. The controller 1012-1 may include interface conversion circuitry and / or timing control circuitry. The controller 1012-1 may receive image signals from the main processor 1011, convert the data format of the image signals to suit the interface specifications of the display module 1040, and output image data. The controller 1012-1 may output various control signals required or sufficient to drive the display module 1040.

[0113] The coprocessor 1012 may further include a data conversion circuit 1012-2, a gamma correction circuit 1012-3 (or gamma compensation circuit), a rendering circuit 1012-4, etc. The data conversion circuit 1012-2 can receive image data from the controller 1012-1 and can compensate the image data to display the image at a desired brightness according to the characteristics of the electronic device 1000 and / or user settings, or can convert the image data to reduce power consumption and / or compensate for afterimages. The gamma correction circuit 1012-3 can convert the image data and / or gamma reference voltage to give the image displayed on the electronic device 1000 the desired gamma characteristics. The rendering circuit 1012-4 can receive image data from the controller 1012-1 and can render the image data by taking into account the pixel arrangement of the display panel 1041 applied to the electronic device 1000. At least one of the data conversion circuit 1012-2, gamma correction circuit 1012-3, and rendering circuit 1012-4 may be integrated into another component (e.g., the main processor 1011 and / or the controller 1012-1). At least one of the data conversion circuit 1012-2, gamma correction circuit 1012-3, and rendering circuit 1012-4 may be integrated into the data driver 1043, which will be described below.

[0114] The memory 1020 may store various data used by at least one component of the electronic device 1000 (e.g., processor 1010 and / or sensor module 1061), as well as input data and / or output data for commands associated therewith. The memory 1020 may include at least one of volatile memory 1021 and non-volatile memory 1022.

[0115] The input module 1030 can receive commands and / or data from outside the electronic device 1000 (e.g., from a user and / or an external electronic device 1002) that will be used in components of the electronic device 1000 (e.g., processor 1010, sensor module 1061, and / or sound output module 1063).

[0116] Input module 1030 may include a first input module 1031 through which commands and / or data are input from a user and / or a second input module 1032 through which commands and / or data are input from an external electronic device 1002. The first input module 1031 may include a microphone, mouse, keyboard, keys (e.g., buttons), and / or a pen (e.g., a passive pen and / or an active pen). The second input module 1032 may support specified protocols that can be connected to the external electronic device 1002 via wiring and / or wirelessly. In some example embodiments, the second input module 1032 may include a High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, and / or an audio interface. The second input module 1032 may include connectors such as an HDMI connector, a USB connector, an SD card connector, and / or an audio connector (e.g., a headphone connector) that can be physically connected to the external electronic device 1002.

[0117] Display module 1040 can provide visual information to the user. Display module 1040 may include display panel 1041, grid driver 1042 and / or data driver 1043. Display module 1040 may further include a window, base frame and / or bracket for protecting display panel 1041. Display module 1040 may correspond to display device 100 of FIG1. ​​Display panel 1041, grid driver 1042 and data driver 1043 may correspond to display panel 110, scan driver 130 and data driver 120 of FIG1, respectively.

[0118] Power module 1050 can supply power to components of electronic device 1000. Power module 1050 may include a battery charged with electrical voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, and / or a fuel cell. Power module 1050 may include power management circuitry 1051. Power management circuitry 1051 can supply optimized power to at least one of the above-described modules and the modules described below. Power management circuitry 1051 may correspond to power management circuitry 140 of FIG. 1. Power module 1050 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple coil-shaped antenna radiators.

[0119] The electronic device 1000 may further include an internal module 1060 and / or an external module 1070. The internal module 1060 may include a sensor module 1061, an antenna module 1062, and / or a sound output module 1063. The external module 1070 may include a camera module 1071, an optical module 1072, and / or a communication module 1073.

[0120] The sensor module 1061 can detect input made by the user's body and / or input made by the pen in the first input module 1031, and can generate an electrical signal and / or data value corresponding to the input. The sensor module 1061 may include at least one of a fingerprint sensor 1061-1, an input sensor 1061-2, and a digitizer 1061-3.

[0121] The processor 1010 can output commands and / or data to the display module 1040, the sound output module 1063, the camera module 1071, and / or the optical module 1072 based on input data received from the input module 1030. For example, the processor 1010 can generate image data and output the image data to the display module 1040 in response to input data applied via a mouse and / or an active pen, or it can generate command data in response to input data and output the command data to the camera module 1071 and / or the optical module 1072. When no input data is received from the input module 1030 for a specific period of time, the processor 1010 can switch the operating mode of the electronic device 1000 to a low-power mode and / or a sleep mode to reduce the power consumption of the electronic device 1000.

[0122] The processor 1010 can output commands and / or data to the display module 1040, the sound output module 1063, the camera module 1071, and / or the light module 1072 based on the sensing data received from the sensor module 1061. For example, the processor 1010 can compare the authentication data sensed by the fingerprint sensor 1061-1 with the authentication data stored in the memory 1020, and then execute an application based on the comparison result. The processor 1010 can execute commands and / or output corresponding image data to the display module 1040 based on the sensing data detected by the input sensor 1061-2 or the digitizer 1061-3. When the sensor module 1061 includes a temperature sensor, the processor 1010 can receive temperature data for the temperature measured from the sensor module 1061, and can further perform brightness correction on the image data, etc., based on the temperature data.

[0123] In some example embodiments, as illustrated in FIG16, the electronic device 1000 can be implemented as a computer monitor. However, the example embodiments are not limited thereto, and in some example embodiments, the electronic device 1000 can be implemented as a television, mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation device, laptop computer, head-mounted display device, artificial reality (AR) device, etc.

[0124] The display device according to some example embodiments can be applied to display devices included in computers (e.g., laptops), mobile phones, smartphones, smart tablets, smartwatches, PMPs, PDAs, and / or MP3 players.

[0125] One or more of the elements disclosed above may include or be implemented as one or more processing circuits, such as hardware including logic circuits, hardware / software combinations such as processors executing software, or combinations thereof. For example, more specifically, the processing circuits may include, but are not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0126] Although display devices and electronic devices according to some exemplary embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are exemplary and may be modified and altered by those skilled in the art without departing from the spirit of the technology described in the claims.

Claims

1. A display device, comprising: A display panel, including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; The system also includes a power management circuit configured to provide a first power voltage and a second power voltage to the pixel, wherein the second scan signal includes a valid pulse in an effective time period of constant length and a plurality of dummy pulses in a vertical blank time period of variable length, wherein the width of each of the plurality of dummy pulses is less than the width of the valid pulse, and wherein the interval between the plurality of dummy pulses is less than the interval between the valid pulse and the first dummy pulse among the plurality of dummy pulses.

2. The display device according to claim 1, wherein, The widths of the plurality of dummy pulses are equal to each other.

3. The display device according to claim 1, wherein, The intervals between the plurality of dummy pulses are equal to each other.

4. The display device according to claim 1, wherein, The pixel includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive the first power voltage, and a second terminal connected to a second node; a second transistor including a second gate configured to receive the first scan signal, a third terminal configured to receive a data voltage, and a fourth terminal connected to the first node; a third transistor including a third gate configured to receive the second scan signal, a fifth terminal configured to receive a reference voltage, and a sixth terminal connected to the second node; a capacitor including a seventh terminal connected to the first node and an eighth terminal connected to the second node; and a light-emitting diode including a ninth terminal connected to the second node and a tenth terminal configured to receive the second power voltage.

5. The display device according to claim 4, wherein, In response to the pulses of the first scan signal and the second scan signal during the effective time period, the capacitor is configured to store the difference between the data voltage and the reference voltage, and wherein the third transistor is configured to apply the reference voltage to the second node in response to the plurality of dummy pulses.

6. The display device according to claim 5, wherein, The reference voltage level is lower than the threshold voltage level of the light-emitting diode.

7. The display device according to claim 4, wherein, The first scan signal includes the pulse in the effective time period and the deactivation level in the vertical blank time period.

8. The display device according to claim 4, wherein, The first power voltage has a constant high voltage level, and the second power voltage has a constant low voltage level lower than the constant high voltage level.

9. A display device, comprising: A display panel, including pixels; a scan driver configured to provide a first scan signal and a second scan signal to the pixels; And a power management circuit configured to provide a power voltage to the pixel, wherein the second scan signal includes a valid pulse in an effective time period of constant duration, wherein the power voltage includes a plurality of pulses in a vertical blank time period of variable duration, wherein the width of each of the plurality of pulses of the power voltage is less than the width of the valid pulse, and wherein the interval between the plurality of pulses of the power voltage is less than the interval between the valid pulse and the first pulse of the plurality of pulses of the power voltage.

10. The display device according to claim 9, wherein, The widths of the plurality of pulses of the electrical voltage are equal to each other.

11. The display device according to claim 9, wherein, The intervals between the plurality of pulses of the electrical voltage are equal to each other.

12. The display device according to claim 9, wherein, The pixel includes: a first transistor including a first gate connected to a first node, a first terminal configured to receive a first power voltage, and a second terminal connected to a second node; a second transistor including a second gate configured to receive the first scan signal, a third terminal configured to receive a data voltage, and a fourth terminal connected to the first node; a third transistor including a third gate configured to receive the second scan signal, a fifth terminal configured to receive a reference voltage, and a sixth terminal connected to the second node; a capacitor including a seventh terminal connected to the first node and an eighth terminal connected to the second node; and a light-emitting diode including a ninth terminal connected to the second node and a tenth terminal configured to receive a second power voltage, wherein the power voltage is either the first power voltage or the second power voltage.

13. The display device according to claim 12, wherein, The power voltage is the first power voltage and has a constant high voltage level during the effective period, and the plurality of pulses of the power voltage have a low voltage level lower than the constant high voltage level.

14. The display device according to claim 12, wherein, The power voltage is the second power voltage and has a constant low voltage level during the effective period, and the plurality of pulses of the power voltage have a high voltage level higher than the constant low voltage level.

15. The display device according to claim 12, wherein, The first scan signal includes the pulse in the effective time period and the deactivation level in the vertical blank time period.

16. The display device according to claim 12, wherein, The second scan signal has a deactivation level during the vertical blank period.

17. An electronic device comprising: The display device according to any one of claims 1 to 16; And a processor, configured to control the display device.

Images