Semiconductor memory device

Abstract

The present disclosure provides a semiconductor memory device including: a die including a plurality of planes, each plane having a plurality of memory cells; a plurality of temperature sensors arranged in the die and arranged to correspond to the respective planes; and a temperature compensation circuit configured to generate a read control signal for performing a read operation on each of the plurality of planes based on the plane temperature values obtained from the respective temperature sensors.

Description

Semiconductor memory devices

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0149779, filed on October 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The techniques and embodiments disclosed herein generally relate to a semiconductor memory device for storing data. Background Technology

[0004] Semiconductor memory devices may include multiple memory cells for storing data. Furthermore, semiconductor memory devices can be classified into non-volatile memory devices and volatile memory devices. Non-volatile memory devices retain stored data even during power interruptions, while volatile memory devices do not retain data during power interruptions.

[0005] Depending on the operating environment, such as temperature and / or the number of programming / erase cycles, the memory cells included in a non-volatile memory device may have different operating characteristics. To prevent performance degradation of the non-volatile memory device due to such variations in operating characteristics, it is necessary to provide the memory cells with an operating voltage corresponding to the temperature and / or the number of programming / erase cycles. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a semiconductor memory device that performs read operations corresponding to temperature changes in memory cells.

[0007] According to embodiments of the present disclosure, a semiconductor memory device may include: a die including a plurality of planes, each plane having a plurality of memory cells; a plurality of temperature sensors disposed in the die and arranged to correspond to a respective plane; and a temperature compensation circuit configured to generate a read control signal based on plane temperature values ​​obtained from the respective temperature sensors, the read control signal being used to perform a read operation on each of the plurality of planes.

[0008] According to another embodiment of this disclosure, a semiconductor memory device may include: a plurality of planes, each plane including a plurality of memory cells; a plurality of temperature sensors corresponding to the respective planes; a temperature compensation circuit configured to generate a read reference voltage based on plane temperature values ​​obtained from the respective temperature sensors, the read reference voltage being used to perform a read operation on each of the plurality of planes; and a page buffer circuit configured to determine data by comparing the voltage level of a signal transmitted via bit lines connected to the plurality of planes with the read reference voltage.

[0009] According to another embodiment of the present disclosure, a semiconductor memory device may include: a plurality of planes, each plane including a plurality of memory cells; a plurality of temperature sensors arranged to correspond to a respective plane; a temperature compensation circuit configured to generate a voltage control signal based on plane temperature values ​​obtained from the respective temperature sensors, the voltage control signal being used to control the level of an offset control voltage required to offset the threshold voltage distribution of the memory cells; and a voltage generator configured to generate an offset control voltage based on the voltage control signal.

[0010] It should be understood that the foregoing general description and the following detailed description of this disclosure are illustrative and are intended to provide a further description of the claimed embodiments of this disclosure. Attached Figure Description

[0011] The above and other features and advantages of embodiments of the present disclosure will become apparent when considered in conjunction with the accompanying drawings and the following detailed description.

[0012] Figure 1 is a block diagram illustrating a memory system based on some embodiments of the present disclosure.

[0013] Figure 2 is a block diagram illustrating the memory device shown in Figure 1 based on some embodiments of the present disclosure.

[0014] Figure 3 is a schematic diagram showing the layout structure of the temperature sensor shown in Figure 2 based on some embodiments of the present disclosure.

[0015] Figure 4 is a flowchart illustrating a temperature compensation method for a memory device based on some embodiments of the present disclosure.

[0016] Figure 5 is a diagram illustrating the operation of operation S430 according to Figure 4 based on some embodiments of the present disclosure.

[0017] Figure 6 is a diagram illustrating the operation of operation S440 according to Figure 4 based on some embodiments of the present disclosure.

[0018] Figure 7 is a flowchart illustrating a temperature compensation method for a memory device based on some other embodiments of the present disclosure.

[0019] Figure 8 is a diagram illustrating the operation of operation S720 according to Figure 7.

[0020] Figure 9 is a schematic diagram illustrating the method used to calculate the representative temperature values ​​described in Figure 8. Detailed Implementation

[0021] This disclosure provides embodiments and examples of semiconductor memory devices for storing data, which can be used in configurations that effectively address one or more technical or engineering problems and mitigate limitations or disadvantages encountered in some other semiconductor memory devices. Some embodiments of this disclosure relate to a semiconductor memory device that performs read operations corresponding to temperature changes in the memory cells. Recognizing the above problems, embodiments of this disclosure provide a semiconductor memory device that can improve the performance of read operations by utilizing temperature information obtained from a plurality of temperature sensors arranged adjacent to each plane of the semiconductor memory device to set read conditions.

[0022] Reference will now be made in detail to embodiments of the present disclosure illustrated in the accompanying drawings. Throughout the drawings, the same reference numerals are used wherever possible to refer to the same or similar parts. While various modifications and alternatives are readily possible with respect to the embodiments of the present disclosure, specific embodiments are shown in the drawings by way of example. However, these embodiments should not be construed as limiting oneself to the embodiments set forth herein.

[0023] In the following description, various embodiments will be illustrated with reference to the accompanying drawings. However, it should be understood that the embodiments of this disclosure are not limited to the specific embodiments, but include various modifications, equivalents, and / or alternatives to the embodiments. The embodiments of this disclosure can provide various effects that can be directly or indirectly recognized.

[0024] Figure 1 is a block diagram illustrating an example of a memory system 1 based on some embodiments of the present disclosure.

[0025] Referring to FIG1, the memory system 1 may include a memory device 10 and a memory controller 20.

[0026] The memory system 1 can be implemented as internal memory embedded in an electronic system (e.g., a smartphone, tablet, computer, television, etc.). For example, the memory system 1 can be embedded universal flash memory (UFS), embedded multimedia card (eMMC), or solid-state drive (SSD). According to one embodiment, the memory system 1 can be implemented as external memory detachably connected to an electronic device, and can be, for example, a UFS memory card, compact flash memory (CF) card, secure digital card (SD) card, micro-secure digital card (micro-SD) card, mini-secure digital card (mini-SD) card, extreme digital card (xD) card, or memory stick.

[0027] The memory system 1 can store data received from the host in the memory device 10 based on an access request from the host, or it can read data requested by the host from the memory device 10 and transfer the read data to the host.

[0028] Memory device 10 may include a plurality of memory cells, each of which stores data. According to one embodiment, each of the plurality of memory cells may be a non-volatile memory cell, which retains the stored data even during a power outage. For example, when the memory cells are non-volatile memory cells, memory device 10 may be implemented as electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), resistive random access memory (RRAM), nanofloating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc. In the following description, embodiments of this disclosure will be used as examples where the plurality of memory cells are NAND flash memory cells, but the embodiments of this disclosure are not limited thereto. Memory device 10 may perform programming operations, reading operations, and / or erasing operations under the control of memory controller 20.

[0029] The memory controller 20 can provide the memory device 10 with control signals (CTRL), commands (CMD), and addresses (ADDR). The control signals (CTRL) can include information required for the memory device 10 to perform an operation corresponding to a command (CMD) received from the memory controller 20. For example, the control signals (CTRL) can include information related to sensing parameters required for the memory device 10 to read data from a memory cell. The commands (CMD) can indicate the operation to be performed by the memory device 10 during a programming operation, a read operation, or an erase operation. The addresses (ADDR) can indicate the location of data in the memory device 10 that the memory controller 20 expects to access. Data (DATA) can be transferred and / or received between the memory controller 20 and the memory device 10 based on commands (CMD) and addresses (ADDR).

[0030] The memory controller 20 can control various operations of the memory device 10 in response to access requests from the host, such as programming data (DATA) in the memory device 10, reading data (DATA) from the memory device 10, and / or erasing data (DATA) from the memory device 10. For example, the memory controller 20 can transfer data (DATA) received from the host to the memory device 10 by executing a write command, or it can transfer data (DATA) read from the memory device 10 to the host by executing a read command. Additionally, the memory controller 20 can provide clock signals, chip select signals, etc., to the memory device 10.

[0031] Figure 2 is a block diagram illustrating the memory device 10 shown in Figure 1 based on some embodiments of the present disclosure.

[0032] Referring to FIG2, the memory device 10 may include a memory cell array 11, a page buffer circuit 12, a control circuit 13, a voltage generator 14, a row decoder 15, and a temperature sensor 17.

[0033] According to one embodiment, although not shown in FIG2, the memory device 10 may further include data input / output (I / O) circuitry or input / output (I / O) interface, the data input / output (I / O) circuitry being used to communicate with an external device such as the memory controller 20, and the input / output (I / O) interface being used to communicate with the external device.

[0034] The memory cell array 11 may include multiple memory cells. The memory cell array 11 may be connected to the drain select line (DSL), word line (WL), source select line (SSL), and bit line (BL). The memory cell array 11 may be connected to the line decoder 15 via the drain select line (DSL), word line (WL), and source select line (SSL), and may be connected to the page buffer circuit 12 via the bit line (BL).

[0035] The memory cell array 11 may include multiple planes, each plane including multiple memory blocks. Each memory block may include multiple memory cells arranged in a two-dimensional (2D) or three-dimensional (3D) structure. The memory cell array 11 may include at least one of a single-level cell (SLC) block with single-level cells (SLC), a multi-level cell (MLC) block with multiple-level cells (MLC), a three-level cell (TLC) block with three-level cells (TLC), and a four-level cell (QLC) block with four-level cells (QLC). For example, some of the multiple memory blocks may be single-level cell (SLC) blocks, and other memory blocks may include multi-level cell (MLC) blocks, three-level cell (TLC) blocks, or four-level cell (QLC) blocks.

[0036] Page buffer circuit 12 can operate in response to control signals from control circuit 13. Page buffer circuit 12 can select some bit lines in the bit line (BL) in response to column address (Y-ADDR). For example, page buffer circuit 12 can operate as a write driver or a sense amplifier.

[0037] According to one embodiment, during a programming operation, the page buffer circuit 12 can operate as a write driver to apply a voltage to the bit line (BL) based on the data (DATA) to be stored in the memory cell array 11. According to another embodiment, during a read operation, the page buffer circuit 12 can operate as a sense amplifier to detect the data (DATA) stored in the memory cell array 11 received via the bit line (BL). The page buffer circuit 12 can detect the data (DATA) using a read reference voltage (RJV) received from the control circuit 13. For example, the page buffer circuit 12 can determine the data (DATA) by comparing the voltage level of the signal received via the bit line (BL) with the read reference voltage (RJV).

[0038] The control circuit 13 can output internal control signals based on commands (CMD), addresses (ADDR), and control signals (CTRL) to program (write) data (DATA) into (write) the memory cell array 11 or to read data (DATA) from the memory cell array 11. For example, the control circuit 13 can output voltage control signals (VC) to control the levels of various reference voltages generated by the voltage generator 14.

[0039] Control circuit 13 may include temperature compensation circuit 16. Temperature compensation circuit 16 may perform temperature compensation based on temperature data (TEMP) received from temperature sensor 17. In this case, temperature compensation may refer to setting read conditions corresponding to the temperature data (TEMP) to properly read data (DATA) stored in memory cell array 11. Read conditions may include conditions related to read reference voltage (RJV), through voltage applied to unselected memory cells, drain select line voltage applied to drain select line (DSL), and / or source select line voltage applied to source select line (SSL).

[0040] According to one embodiment, the temperature compensation circuit 16 can output a voltage control signal (VC) causing the voltage generator 14 to generate a reference voltage (RV) determined according to such temperature compensation. According to another embodiment, the temperature compensation circuit 16 can output a read reference voltage (RJV) determined according to temperature compensation.

[0041] In Figure 2, control circuit 13 is shown as including temperature compensation circuit 16; however, the scope or spirit of this disclosure is not limited thereto, and temperature compensation circuit 16 may be arranged externally to control circuit 13. According to another embodiment, temperature compensation circuit 16 may be included in voltage generator 14, or implemented as a configuration independent of control circuit 13. Optionally, temperature compensation circuit 16 may be located external to memory device 10 (e.g., as part of memory controller 20).

[0042] The control circuit 13 can provide the row address (X-ADDR) for selecting the word line (WL) to the row decoder 15, and can provide the column address (Y-ADDR) for selecting the bit line (BL) to the page buffer circuit 12.

[0043] Voltage generator 14 can generate various types of reference voltages (RVs) required to perform programming, reading, and erasing operations on memory cell array 11 based on voltage control signals (VC). Specifically, voltage generator 14 can generate word line voltages (e.g., programming voltage, read voltage, pass voltage, erase verification voltage, or programming verification voltage) applied to the word line (WL), and can further generate drain select line voltages applied to the drain select line (DSL) and source select line voltages applied to the source select line (SSL). That is, the reference voltage (RV) can include word line voltages, drain select line voltages, and source select line voltages.

[0044] The row decoder 15 can select one of a plurality of memory blocks in response to a row address (X-ADDR), and can select one of the word lines (WL) of the selected memory block. The row decoder 15 can use a reference voltage (RV) to supply the voltage required for programming, reading, or erasing operations on the word line (WL), drain select line (DSL), and source select line (SSL) for the memory cell connected to the selected word line (WL).

[0045] Temperature sensor 17 may be disposed inside or near memory cell array 11 to generate temperature data (TEMP) indicating the temperature of memory cell array 11, and may transmit the temperature data (TEMP) to temperature compensation circuit 16. According to one embodiment, temperature sensor 17 may be any of an integrated circuit (IC) temperature sensor and a semiconductor temperature sensor, each of which includes a resistor whose resistance value changes with temperature, and generates temperature data (TEMP) as a result of detecting the change in resistance value.

[0046] The memory device 10 may include a plurality of temperature sensors 17 to accurately measure the temperature of the memory cell array 11, and the arrangement and operation of the temperature sensors 17 will be described later.

[0047] Figure 3 is a schematic diagram showing the layout structure of the temperature sensor shown in Figure 2 based on some embodiments of the present disclosure.

[0048] Referring to FIG3, the memory device 10 may be implemented as a chip, and a chip may include at least one die 300. The die 300 may include at least some of the components of the memory device 10, and is shown in FIG3 as including a plane (P0~P3) and a temperature sensor (TS) (310-1~310-4), but the embodiments of this disclosure are not limited thereto.

[0049] Specifically, the die 300 may include planes (P0~P3) arranged in a matrix shape and temperature sensors (310-1~310-4) arranged to correspond to the planes (P0~P3) respectively.

[0050] Each of the planes (P0-P3) may include multiple memory blocks, and each memory block includes multiple memory cells. In this disclosure, for ease of description, the memory cells included in the planes (P0-P3) are single-level cells (SLC), but the technical concept of this disclosure can be substantially applied even when the memory cells included in the planes (P0-P3) are multi-level cells (MLC), three-level cells (TLC), and / or four-level cells (QLC).

[0051] The first temperature sensor 310-1 can be arranged closest to the first plane (P0) among the planes (P0~P3). The first temperature sensor 310-1 can measure the ambient temperature to generate a temperature value for the first plane. Since the first temperature sensor 310-1 is located closest to the first plane (P0), the temperature value of the first plane can represent the temperature of the first plane (P0).

[0052] The second temperature sensor 310-2 can be arranged closest to the second plane (P1) among the planes (P0~P3). The second temperature sensor 310-2 can measure the ambient temperature to generate a temperature value for the second plane. Since the second temperature sensor 310-2 is arranged closest to the second plane (P1), the temperature value of the second plane can represent the temperature of the second plane (P1).

[0053] The third temperature sensor 310-3 can be arranged closest to the third plane (P2) among the planes (P0~P3). The third temperature sensor 310-3 can measure the ambient temperature to generate a third plane temperature value. Since the third temperature sensor 310-3 is arranged closest to the third plane (P2), the third plane temperature value can represent the temperature of the third plane (P2).

[0054] The fourth temperature sensor 310-4 can be arranged closest to the fourth plane (P3) among the planes (P0~P3). The fourth temperature sensor 310-4 can measure the ambient temperature to generate a temperature value for the fourth plane. Since the fourth temperature sensor 310-4 is arranged closest to the fourth plane (P3), the temperature value of the fourth plane can represent the temperature of the fourth plane (P3).

[0055] The temperature values ​​of the first to fourth planes can be included in the temperature data (TEMP) described in Figure 2. That is, the temperature values ​​of the first to fourth planes can be transmitted to the temperature compensation circuit 16.

[0056] In Figure 3, each of the first to fourth temperature sensors (310-1 to 310-4) is shown as being located at the corresponding vertex closest to the die 300, such that the first to fourth temperature sensors (310-1 to 310-4) can be located at positions closest to the first to fourth planes (P0 to P3), respectively. However, the embodiments of this disclosure are not limited to this. The positions of the first to fourth temperature sensors (310-1 to 310-4) can vary as long as each of the first to fourth temperature sensors (310-1 to 310-4) is closest to the corresponding plane.

[0057] In another embodiment, some of the first to fourth temperature sensors (310-1 to 310-4) corresponding to the first to fourth planes (P0 to P3) can be omitted, so that some of the temperature sensors corresponding to the first to fourth planes (P0 to P3) can be omitted.

[0058] Figure 4 is a flowchart illustrating a temperature compensation method for a memory device based on some embodiments of the present disclosure. Figure 5 is a diagram illustrating operation S430 according to Figure 4 based on some embodiments of the present disclosure. Figure 6 is a diagram illustrating operation S440 according to Figure 4 based on some embodiments of the present disclosure.

[0059] Referring to FIG4, a temperature compensation method performed by the memory device 10 is shown, and the temperature compensation method of FIG4 will be described using the temperature compensation method for the die 300 shown in FIG3. The temperature compensation method of FIG4 can be a temperature compensation method for the case where read conditions are independently applied to each of the first to fourth planes (P0~P3).

[0060] The temperature compensation circuit 16 can obtain the plane temperature value (P0~P3) of the corresponding plane from the corresponding temperature sensor (310-1~310-4) (S410).

[0061] The temperature compensation circuit 16 can determine whether the plane temperature values ​​are included in the same temperature range (S420). The temperature compensation circuit 16 can manage a temperature range that is the entire temperature range of the plane temperature values ​​output from the temperature sensors (310-1 to 310-4) divided into predetermined temperature intervals. For example, the temperature range may include a first temperature range (20℃ to 30℃), a second temperature range (30℃ to 40℃), a third temperature range (40℃ to 50℃), etc.

[0062] If the planar temperature values ​​of the temperature sensors (310-1~310-4) are included in the same temperature range (e.g., the second temperature range) (i.e., yes in S420), the temperature compensation circuit 16 can control the elements in the memory device 10 to perform a read operation according to a read condition corresponding to the temperature range that includes the planar temperature values ​​(S430).

[0063] Referring to Figure 5, the distribution of memory cells changes according to temperature variations. In this disclosure, the distribution of memory cells may refer to the distribution (or discreteness) of the threshold voltages of the memory cells.

[0064] The first distribution (510a, 510b) may correspond to the distribution of memory cells included in each of the planes (P0~P3) before the temperature rise, and the first distribution 510a may represent the distribution of threshold voltages of memory cells used as ON-Cells based on the first read reference voltage (RJV1), and the first distribution 510b may represent the distribution of threshold voltages of memory cells used as OFF-Cells based on the first read reference voltage (RJV1).

[0065] The second distribution (520a, 520b) may correspond to the distribution of memory cells included in each of the planes (P0~P3) after the temperature rises, and the second distribution 520a may represent the distribution of the threshold voltage of the memory cell used as an on-cell based on the second read reference voltage (RJV2), and the second distribution 520b may represent the distribution of the threshold voltage of the memory cell used as an off-cell based on the second read reference voltage (RJV2).

[0066] In other words, the first distribution (510a, 510b) can shift to the second distribution (520a, 520b) based on the increased temperature. Even after the temperature rises, when a read operation is performed on a memory cell with the second distribution (520a, 520b) at the first read reference voltage (RJV1), a fault may occur in which the memory cell corresponding to the second distribution 520a with a threshold voltage higher than the first read reference voltage (RJV1) is detected as a shut-off cell.

[0067] To prevent this phenomenon, the temperature compensation circuit 16 can apply read conditions corresponding to temperature ranges (e.g., a second temperature range) that include planar temperature values. According to one embodiment, the temperature compensation circuit 16 can manage a table in which each temperature range and the corresponding read condition are matched to each other. For example, the temperature compensation circuit 16 can store a table of temperature ranges and read conditions that match each other, or it can access a table stored in an external component (e.g., memory cell array 11 or memory controller 20) to obtain the necessary read conditions. The temperature compensation circuit 16 can control read operations by matching predetermined temperature ranges with read conditions, and thus can reduce the resources required for the table of read conditions and simplify the types of read conditions.

[0068] According to one embodiment, the temperature compensation circuit 16 can control the execution of a read operation using a read reference voltage corresponding to a temperature range (e.g., a second temperature range) that includes plane temperature values. The read reference voltage corresponding to the temperature range including plane temperature values ​​can increase as the temperature increases and decrease as the temperature decreases.

[0069] In Figure 5, when the read reference voltage corresponding to the temperature range (e.g., the second temperature range) including the plane temperature value after temperature rise is the second read reference voltage (RJV2), the temperature compensation circuit 16 can provide the second read reference voltage (RJV2) as the read reference voltage (RJV) to the page buffer circuit 12. Therefore, by performing read operations based on the second read reference voltage (RJV2), failure of memory cells with the second distribution (520a, 520b) can be prevented.

[0070] According to one embodiment, the temperature compensation circuit 16 can use an offset control voltage corresponding to a temperature range (e.g., a second temperature range) including a plane temperature value to control the execution of a read operation. Here, the offset control voltage can refer to a voltage applied to the peripheral transistor of the selected memory cell to move (or offset) the threshold voltage distribution of the memory cell to the left (in the direction of decreasing threshold voltage) or to the right (in the direction of increasing threshold voltage). The offset control voltage can include a pass voltage, a drain select voltage, and / or a source select voltage, with the pass voltage applied to an unselected memory cell belonging to a NAND string including the selected memory cell, the drain select voltage applied to a drain select transistor belonging to the corresponding NAND string, and the source select voltage applied to a source select transistor belonging to the corresponding NAND string. That is, the offset control voltage can be a portion of a reference voltage (RV). The drain select transistor can be connected between a bit line (BL) and each of the series-connected memory cells, and the source select transistor can be connected between a source line and each of the series-connected memory cells.

[0071] When the pass voltage, drain select voltage, and / or source select voltage increase, the threshold voltage distribution of the selected memory cell may shift to the right due to the change in potential. Conversely, when the pass voltage, drain select voltage, and / or source select voltage decrease, the threshold voltage distribution of the selected memory cell may shift to the left due to the change in potential.

[0072] The offset control voltage, which corresponds to a temperature range including the plane temperature value, can decrease as the temperature increases and increase as the temperature decreases.

[0073] In Figure 5, when the offset control voltage corresponding to a temperature range (e.g., a second temperature range) including the plane temperature value after temperature rise is a specific offset control voltage, the temperature compensation circuit 16 can provide a voltage control signal (VC) to the voltage generator 14. This voltage control signal is used to generate a reference voltage (RV) corresponding to the specific offset control voltage and supply the reference voltage (RV) to the corresponding plane. The specific offset control voltage can be a voltage used to offset the second distribution (520a, 520b) to a second distribution (520a', 520b') that is substantially the same as the first distribution (510a, 510b). Therefore, even if a read operation is performed based on the first read reference voltage (RJV1), memory cell failure can be prevented as the memory cells having the second distribution (520a, 520b) are offset to the second distribution (520a', 520b').

[0074] The voltage control signals used to control the read reference voltage and offset control voltage described in Figure 5 can be collectively referred to as read control signals. These read control signals are generated by the temperature compensation circuit 16 to perform a read operation on each of the planes (P0~P3).

[0075] Referring again to Figure 4, when the planar temperature values ​​of the temperature sensors (310-1 to 310-4) are included in different temperature ranges (e.g., a second temperature range and a third temperature range) (i.e., not in S420), the temperature compensation circuit 16 can control the elements in the memory device 10 to perform a read operation according to multiple read conditions corresponding to the different temperature ranges that include the planar temperature values ​​(S440).

[0076] Referring to Figure 6, the distribution of memory cells changes according to temperature variations.

[0077] The third distribution (610a, 610b) can correspond to the distribution of memory cells included in the plane (P0~P3) before the temperature rises, and the third distribution 610a can represent the distribution of the threshold voltage of the memory cell that can be used as an ON-Cell (i.e., the conducting cell) based on the third read reference voltage (RJV3), and the third distribution 610b can represent the distribution of the threshold voltage of the memory cell that can be used as an OFF-Cell (i.e., the turning-off cell) based on the third read reference voltage (RJV3).

[0078] The fourth distribution (620a, 620b) may correspond to the distribution of memory cells included in some planes (e.g., P0~P2) after the temperature rises, and the fourth distribution 620a may represent the distribution of the threshold voltage of the memory cell that can be used as an ON-Cell (i.e., a conducting cell) based on the fourth read reference voltage (RJV4), and the fourth distribution 620b may represent the distribution of the threshold voltage of the memory cell that can be used as an OFF-Cell (i.e., a turning-off cell) based on the fourth read reference voltage (RJV4).

[0079] The fifth distribution (630a, 630b) may correspond to the distribution of memory cells included in the remaining plane (e.g., P3) after the temperature rises, and the fifth distribution 630a may represent the distribution of the threshold voltage of the memory cell that can be used as an ON-Cell (i.e., a conducting cell) based on the fifth read reference voltage (RJV5), and the fifth distribution 630b may represent the distribution of the threshold voltage of the memory cell that can be used as an OFF-Cell (i.e., a turning-off cell) based on the fifth read reference voltage (RJV5).

[0080] The temperature increment in some planes (e.g., P0~P2) may be smaller than the temperature increment in the remaining planes (e.g., P3), and the plane temperature value of some planes (e.g., P0~P2) may be smaller than the plane temperature value of the remaining planes (e.g., P3).

[0081] As the temperature increases, the third distribution (610a, 610b) can shift to the fourth distribution (620a, 620b) or the fifth distribution (630a, 630b). However, since the planes (P0~P3) are all located on the same die 300, depending on the arrangement of the planes, the distribution of memory cells included in the plane adjacent to the integrated circuit (IC) with relatively high heat generation (e.g., P3) can shift to the fifth distribution (630a, 630b), or the distribution of memory cells included in the planes far away from the integrated circuit (IC) with high heat generation (e.g., P0~P2) can shift to the fourth distribution (620a, 620b).

[0082] Even after the temperature rises, if a read operation is performed on a memory cell with a fourth distribution (620a, 620b) or a fifth distribution (630a, 630b) at a third read reference voltage (RJV3), a fault may occur in which a memory cell with a threshold voltage higher than the third read reference voltage (RJV3) is detected as a shut-off cell among the memory cells corresponding to the fourth distribution 620a or the fifth distribution 630a.

[0083] To prevent this phenomenon, the temperature compensation circuit 16 can apply read conditions corresponding to temperature ranges (e.g., a second temperature range or a third temperature range) that include plane temperature values ​​to each plane. According to one embodiment, the temperature compensation circuit 16 can manage a table in which each temperature range and the corresponding read condition are matched to each other. For example, the temperature compensation circuit 16 can store a table of temperature ranges and read conditions that match each other, or it can access a table stored in an external device (e.g., memory cell array 11 or memory controller 20) to obtain the necessary read conditions.

[0084] According to one embodiment, the temperature compensation circuit 16 can use a read reference voltage corresponding to a temperature range (e.g., a second temperature range) that includes the temperature value of each plane to control the execution of a read operation for the plane corresponding to each plane temperature value.

[0085] In Figure 6, when the read reference voltage corresponding to the temperature range (e.g., the second temperature range) of the plane temperature values ​​including some planes (e.g., P0~P2) after temperature rise is a fourth read reference voltage (RJV4), the temperature compensation circuit 16 can provide the page buffer circuit 12 with the fourth read reference voltage (RJV4) as the read reference voltage (RJV) for some planes (e.g., P0~P2).

[0086] Therefore, since read operations are performed on some planes (e.g., P0~P2) based on the fourth read reference voltage (RJV4), failures of memory cells with the fourth distribution (620a, 620b) can be prevented.

[0087] Additionally, when the read reference voltage corresponding to the temperature range (e.g., the third temperature range) of the remaining plane (e.g., P3) after temperature rise is the fifth read reference voltage (RJV5), the temperature compensation circuit 16 can provide the page buffer circuit 12 with the fifth read reference voltage (RJV5) as the read reference voltage (RJV) for the remaining plane (e.g., P3).

[0088] Therefore, since the read operation is performed on the remaining plane (e.g., P3) based on the fifth read reference voltage (RJV5), the failure of memory cells with the fifth distribution (630a, 630b) can be prevented.

[0089] Although a method for performing temperature compensation for a read operation using a read reference voltage has been described with reference to FIG6, temperature compensation for a read operation can also be performed using an offset control voltage described with reference to FIG5.

[0090] In other words, the temperature compensation circuit 16 can generate a reference voltage (RV) corresponding to the offset control voltage used to offset the fourth distribution (620a, 620b) to a distribution substantially the same as the third distribution (610a, 610b), and can provide a voltage control signal (VC) to the voltage generator 14 to supply the reference voltage (RV) to the corresponding plane (e.g., P0~P2). Additionally, the temperature compensation circuit 16 can provide a voltage control signal (VC) to the voltage generator 14 such that the temperature compensation circuit 16 can generate a reference voltage (RV) corresponding to the offset control voltage used to offset the fifth distribution (630a, 630b) to a distribution substantially the same as the third distribution (610a, 610b), and can supply this reference voltage (RV) to the corresponding plane (e.g., P3).

[0091] Therefore, even if the read operation is performed based on the third read reference voltage (RJV3), the memory cells with the fourth distribution (620a, 620b) or the fifth distribution (630a, 630b) are offset to a distribution that is substantially the same as the third distribution (610a, 610b), thereby preventing memory cell failure.

[0092] Figure 7 is a flowchart illustrating a temperature compensation method for a memory device based on some other embodiments of the present disclosure. Figure 8 is a diagram illustrating operation S720 according to Figure 7. Figure 9 is a schematic diagram illustrating a method for calculating the representative temperature value described in Figure 8.

[0093] Referring to FIG7, another embodiment of the temperature compensation method performed by the memory device 10 is shown, and the temperature compensation method for the die 300 shown in FIG3 will be described. The temperature compensation method of FIG7 may be a temperature compensation method for an example case in which a single read condition is applied to each of the first to fourth planes (P0 to P3), rather than applying read conditions independently to each of the first to fourth planes (P0 to P3).

[0094] The temperature compensation circuit 16 can obtain the plane temperature value (S710) of the corresponding plane (P0~P3) from the corresponding temperature sensor (310-1~310-4).

[0095] The temperature compensation circuit 16 can determine a reading condition based on the plane temperature value (S720).

[0096] Referring to Figure 8, the distribution of memory cells changes according to temperature variations.

[0097] The sixth distribution (810a, 810b) can correspond to the distribution of memory cells included in the plane (P0~P3) before the temperature rises, and the sixth distribution 810a can represent the distribution of the threshold voltage of the memory cell that can be used as a turn-on cell based on the sixth read reference voltage (RJV6), and the sixth distribution 810b can represent the distribution of the threshold voltage of the memory cell that can be used as a turn-off cell based on the sixth read reference voltage (RJV6).

[0098] The seventh distribution (820a, 820b) can correspond to the distribution of memory cells included in some planes (e.g., P0~P2) after the temperature rises. The seventh distribution 820a can represent the distribution of the threshold voltage of the memory cell that can be used as the conduction cell based on the seventh read reference voltage (RJV7), and the seventh distribution 820b can represent the distribution of the threshold voltage of the memory cell that can be used as the shutdown cell based on the seventh read reference voltage (RJV7).

[0099] The eighth distribution (830a, 830b) may correspond to the distribution of memory cells included in the remaining plane (e.g., P3) after the temperature rises, and the eighth distribution 830a may represent the distribution of the threshold voltage of the memory cell that can be used as a turn-on cell based on the eighth read reference voltage (RJV8), and the eighth distribution 830b may represent the distribution of the threshold voltage of the memory cell that can be used as a turn-off cell based on the eighth read reference voltage (RJV8).

[0100] In other words, depending on the increased temperature, the sixth distribution (810a, 810b) can shift to the seventh distribution (820a, 820b) or the eighth distribution (830a, 830b). If, even after the temperature rises, a read operation is performed on a memory cell with the seventh distribution (820a, 820b) or the eighth distribution (830a, 830b) using the sixth read reference voltage (RJV6), a fault may occur in which, among the memory cells corresponding to the seventh distribution (820a, 820b) or the eighth distribution (830a, 830b), the memory cell with a threshold voltage higher than the sixth read reference voltage (RJV6) is detected as a shut-down cell.

[0101] The temperature compensation circuit 16 can calculate a representative temperature value by calculating the planar temperature values ​​obtained from the temperature sensors (310-1 to 310-4). The representative temperature value may refer to a value representing the planar temperature values ​​obtained from the temperature sensors (310-1 to 310-4) included in the die 300. According to one embodiment, the temperature compensation circuit 16 can calculate the representative temperature value by calculating the average of the planar temperature values ​​obtained from the temperature sensors (310-1 to 310-4). According to another embodiment, the temperature compensation circuit 16 can calculate the representative temperature value by calculating the median value of the planar temperature values ​​obtained from the temperature sensors (310-1 to 310-4).

[0102] Another embodiment of calculating representative temperature values ​​using temperature compensation circuit 16 will be described with reference to FIG9. FIG9 shows the die 300 described with reference to FIG3 and the temperature center 910 of the first temperature sensor to the fourth temperature sensor (310-1 to 310-4).

[0103] Temperature center 910 can refer to the centroid of the polygon (e.g., the square in Figure 9) formed by the first to fourth temperature sensors (310-1 to 310-4). When calculating representative temperature values, temperature center 910 can be a reference point for determining the weights to be applied.

[0104] The temperature compensation circuit 16 can calculate a reference temperature value by calculating the plane temperature values ​​obtained from the temperature sensors (310-1~310-4). For example, the reference temperature value can be the average or median value of the plane temperature values. The temperature compensation circuit 16 can calculate the temperature weight based on the position of the temperature sensors (310-1~310-4) and the plane temperature values.

[0105] The temperature compensation circuit 16 can calculate the first to fourth vectors based on the positions of the temperature sensors (310-1~310-4) and the planar temperature values ​​of the temperature sensors (310-1~310-4), and can calculate a sum vector (S) as the sum of the first to fourth vectors, which typically starts at the temperature center 910 of the temperature sensors (310-1~310-4), and each vector has an endpoint pointing to the corresponding one of the temperature sensors (310-1~310-4). The sum vector (S) can be represented by the following Equation 1.

[0106] Equation 1

[0107]

[0108] In Equation 1, the first vector can be the product of the planar temperature value (a) of temperature sensor 310-1 and a unit vector (A) having a direction from temperature center 910 toward temperature sensor 310-1. The second vector can be the product of the planar temperature value (b) of temperature sensor 310-2 and a unit vector (B) having a direction from temperature center 910 toward temperature sensor 310-2. The third vector can be the product of the planar temperature value (c) of temperature sensor 310-3 and a unit vector (C) having a direction from temperature center 910 toward temperature sensor 310-3. The fourth vector can be the product of the planar temperature value (d) of temperature sensor 310-4 and a unit vector (D) having a direction from temperature center 910 toward temperature sensor 310-4.

[0109] Considering the positions and planar temperature values ​​of the temperature sensors (310-1~310-4), the sum vector (S) can represent the direction and magnitude (i.e., distance) of the movement of the temperature center 910. In Figure 9, the planar temperature values ​​of the temperature sensors (310-1~310-3) are equal to each other, and the planar temperature value of temperature sensor 310-4 is higher than that of temperature sensors (310-1~310-3). Therefore, the sum vector (S) can have a direction toward temperature sensor 310-4 and a magnitude of a predetermined scalar value. That is, the temperature center 910 can be moved to a temperature center 920 changed by the sum vector (S).

[0110] When the planar temperature value of a particular temperature sensor (e.g., 310-4) is significantly different from the planar temperature values ​​of other planes, the magnitude of the vector (S) can represent the difference between the planar temperature value of the particular temperature sensor (e.g., 310-4) and the other planar temperature values.

[0111] The temperature compensation circuit 16 can calculate the temperature weight by utilizing the magnitude of the sum vector (S) calculated based on the position and plane temperature values ​​of the temperature sensors (310-1~310-4). According to one embodiment, the temperature compensation circuit 16 can calculate the temperature weight by scaling down the magnitude of the sum vector (S). For example, scaling down can refer to converting the magnitude of the sum vector (S) into a temperature weight ranging from 1.0 to 1.5. Here, the range of the temperature weight can be determined experimentally based on the performance of the error correction code (ECC) circuit (not shown). Furthermore, the magnitude of the sum vector (S) and the temperature weight can be proportional to each other.

[0112] The temperature compensation circuit 16 can calculate a representative temperature value by calculating a reference temperature value and a temperature weight (e.g., multiplying them). That is, unlike the embodiments described above that use an average or median value as the representative temperature value, this embodiment reflects the temperature weight in the representative temperature value when the plane temperature value of a particular temperature sensor is significantly higher or lower than the plane temperature values ​​of most other planes. This can reduce the likelihood of uncorrectable error correction code (UECC) errors, in which the number of errors detected in the plane corresponding to the particular temperature sensor exceeds the error correction capability, making such errors uncorrectable based on the ECC error correction operation of the ECC circuit (not shown).

[0113] Referring again to Figure 8, the temperature compensation circuit 16 can determine the read conditions corresponding to representative temperature values. According to one embodiment, the temperature compensation circuit 16 can manage a table in which representative temperature values ​​and corresponding read conditions are matched. For example, the temperature compensation circuit 16 can store a table of matched representative temperature values ​​and read conditions, or it can access a table stored in an external device (e.g., memory cell array 11 or memory controller 20) to obtain the necessary read conditions.

[0114] In Figure 8, the temperature compensation circuit 16 can calculate (e.g., average) the plane temperature values ​​of some planes (e.g., P0~P2) and the plane temperature values ​​of the remaining plane (e.g., P3), and thus can calculate a representative temperature value. The representative temperature value can be greater than the plane temperature values ​​of some planes (e.g., P0~P2) and can be less than the plane temperature value of the remaining plane (e.g., P3). Therefore, the ninth read reference voltage (RJV9) corresponding to the representative temperature value can be greater than the seventh read reference voltage (RJV7) corresponding to the plane temperature values ​​of some planes (e.g., P0~P2) and can be less than the eighth read reference voltage (RJV8) corresponding to the plane temperature value of the remaining plane (e.g., P3).

[0115] If a read operation is performed on a memory cell with a seventh distribution (820a, 820b) or an eighth distribution (830a, 830b) at a seventh read reference voltage (RJV7), a fault may occur in which, among the memory cells corresponding to the eighth distribution 830a, the memory cell with a threshold voltage higher than the seventh read reference voltage (RJV7) is detected as a shut-off cell. Alternatively, if a read operation is performed on a memory cell with a seventh distribution (820a, 820b) or an eighth distribution (830a, 830b) at an eighth read reference voltage (RJV8), a fault may occur in which, among the memory cells corresponding to the seventh distribution 820b, the memory cell with a threshold voltage lower than the eighth read reference voltage (RJV8) is detected as a turned-on cell. In this case, the ratio of faulty memory cells in each distribution may be relatively high, which may lead to a UECC error.

[0116] In this disclosure, the temperature compensation circuit 16 can determine a ninth read reference voltage (RJV9) corresponding to a representative temperature value as a read condition. The ninth read reference voltage (RJV9) can be greater than the seventh read reference voltage (RJV7) and less than the eighth read reference voltage (RJV8).

[0117] When a read operation is performed on a memory cell with a seventh distribution (820a, 820b) or an eighth distribution (830a, 830b) at the ninth read reference voltage (RJV9), a fault may occur. In this fault, among the memory cells corresponding to the eighth distribution 830a, memory cells 840 with a threshold voltage higher than the ninth read reference voltage (RJV9) are detected as off cells. A fault may also occur where, among the memory cells corresponding to the seventh distribution 820b, memory cells 850 with a threshold voltage lower than the ninth read reference voltage (RJV9) are detected as on cells. In these cases, the ratio of faulty memory cells in each distribution can be relatively low, so the detected errors will not exceed the error correction capability, thereby significantly reducing the likelihood of UECC errors.

[0118] Although a method for performing temperature compensation for a read operation using a read reference voltage has been described with reference to FIG8, temperature compensation for a read operation can also be performed using an offset control voltage as described with reference to FIG5.

[0119] Referring again to Figure 7, the temperature compensation circuit 16 can control the elements within the memory device 10 to perform a read operation according to the determined read conditions (S730).

[0120] According to embodiments of this disclosure, the performance of the readout operation can be improved by using temperature information obtained from multiple temperature sensors arranged adjacent to each plane (P0~P3) included in the die 300 to set the readout conditions.

[0121] As is evident from the above description, the semiconductor memory device according to embodiments of the present disclosure can improve the performance of read operations by using temperature information obtained from a plurality of temperature sensors arranged adjacent to each plane of the semiconductor memory device to set read conditions.

[0122] The embodiments disclosed herein can provide various advantageous effects that can be directly or indirectly recognized through the above embodiments.

[0123] Those skilled in the art will understand that the concepts of this disclosure can be implemented in other specific ways besides those set forth herein. Furthermore, claims not expressly set forth in the appended claims may be offered as a combination of embodiments or incorporated as new claims by subsequent amendments after filing.

[0124] Although several illustrative embodiments have been described, it should be understood that modifications and enhancements to the disclosed embodiments and other embodiments can be designed based on what is described and / or shown in this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor memory device, comprising: The die comprises multiple planes, each plane having multiple memory cells; Multiple temperature sensors are arranged in the die and are positioned to correspond to corresponding planes; And a temperature compensation circuit, which generates a read control signal for performing a read operation on each of the plurality of planes based on the plane temperature values ​​obtained from the respective temperature sensors.

2. The semiconductor memory device according to claim 1, wherein: Each of the plurality of temperature sensors is arranged to be closest to the corresponding one of the plurality of planes.

3. The semiconductor memory device according to claim 1, wherein: The plurality of planes are arranged in a matrix shape, and each of the plurality of temperature sensors is arranged as the corresponding vertex closest to the die.

4. The semiconductor memory device according to claim 1, wherein: The read control signal includes a read reference voltage, which is used to determine the data.

5. The semiconductor memory device according to claim 4, further comprising: The page buffer circuit determines the data by comparing the voltage level of the signal transmitted via the bit line with the read reference voltage.

6. The semiconductor memory device according to claim 1, wherein: The read control signal includes a voltage control signal, which is used to control the level of the offset control voltage required to offset the threshold voltage distribution of the memory cell.

7. The semiconductor memory device according to claim 6, further comprising: A voltage generator generates the offset control voltage based on the voltage control signal.

8. The semiconductor memory device according to claim 6, wherein, The offset control voltage includes: a word line voltage to be applied to the word line, a drain select line voltage to be applied to the drain select line, and a source select line voltage to be applied to the source select line.

9. The semiconductor memory device according to claim 1, wherein: When the plane temperature value is included in a single temperature range, the temperature compensation circuit generates a read control signal corresponding to the single temperature range.

10. The semiconductor memory device according to claim 1, wherein: When the plane temperature value is included in different temperature ranges, the temperature compensation circuit generates multiple read control signals corresponding to the corresponding temperature range.

11. The semiconductor memory device of claim 10, wherein: The read reference voltage used to perform a read operation on a plane corresponding to a plane temperature value included in the first temperature range is lower than the read reference voltage used to perform a read operation on a plane corresponding to a plane temperature value included in the second temperature range, where the second temperature range is higher than the first temperature range.

12. The semiconductor memory device of claim 10, wherein: The offset control voltage used to offset the threshold voltage distribution of memory cells in a plane corresponding to the plane temperature values ​​included in the first temperature range is higher than the offset control voltage used to offset the threshold voltage distribution of memory cells in a plane corresponding to the plane temperature values ​​included in the second temperature range, wherein the second temperature range is higher than the first temperature range.

13. The semiconductor memory device according to claim 1, wherein, The temperature compensation circuit calculates a representative temperature value by calculating the plane temperature value, and generates a read control signal corresponding to the representative temperature value.

14. The semiconductor memory device according to claim 13, wherein: The representative temperature value is the average value of the plane temperature values.

15. The semiconductor memory device according to claim 13, wherein: The representative temperature value is the median value of the plane temperature values.

16. The semiconductor memory device of claim 13, wherein: The representative temperature value is the product of a reference temperature value and a temperature weight, whereby the reference temperature value is the average or median value of the plane temperature values.

17. The semiconductor memory device of claim 16, wherein: The temperature weights are calculated based on the magnitude of a sum vector, which is obtained by summing multiple vectors, typically starting from the centroid of a polygon formed by the multiple temperature sensors, and the endpoint of each vector points to a corresponding temperature sensor among the multiple temperature sensors.

18. The semiconductor memory device of claim 17, wherein: Each of the plurality of vectors has the magnitude of a planar temperature value obtained from the corresponding temperature sensor.

19. A semiconductor memory device, comprising: Multiple planes, each plane including multiple memory units; Multiple temperature sensors are arranged to correspond to the respective planes; A temperature compensation circuit generates a read reference voltage for each of the plurality of planes based on the plane temperature values ​​obtained from the respective temperature sensors. And a page buffer circuit that determines data by comparing the voltage level of a signal transmitted via a bit line connected to the plurality of planes with the read reference voltage.

20. A semiconductor memory device, comprising: Multiple planes, each plane including multiple memory units; Multiple temperature sensors are arranged to correspond to the respective planes; A temperature compensation circuit generates a voltage control signal based on the plane temperature value obtained from the corresponding temperature sensor. The voltage control signal is used to control the level of the offset control voltage required to offset the threshold voltage distribution of the memory cell. And a voltage generator that generates the offset control voltage based on the voltage control signal.

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