Relay circuit, relay method, and storage system
By using a relay circuit connected in parallel within the FPGA to amplify and precharge the bit lines, the problem of bit line signal attenuation is solved, resulting in faster read/write speeds and improved topology integrity.
Patent Information
- Application Number
- CN202610091633.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-22
- Publication Date
- 2026-05-01
AI Technical Summary
In FPGAs and other chips, bit line signals attenuate over long paths, resulting in slow read/write speeds and high error rates. Existing relay circuits increase signal delays and disrupt topology.
A parallel relay circuit is used, including a first amplifier circuit, a second amplifier circuit, and a pre-charge circuit, which are connected in parallel with the bit line. The signal is amplified and pre-charged by controlling the enable line and the power line, thus maintaining the original topology.
It reduces signal latency, improves read and write speeds, maintains the integrity of the bitline topology, and does not increase node latency or static power consumption.
Smart Images
Figure CN121963813A_ABST
Abstract
Description
Relay circuits, relay methods and storage systems Technical Field
[0001] This disclosure relates to the field of FPGA SRAM read / write technology, and more specifically, to a relay circuit, relay method, and storage system. Background Technology
[0002] In FPGAs (Field Programmable Gate Arrays) and other chips, a large-capacity SRAM (Static Random Access Memory) array is often required to meet system configuration or large data storage requirements. However, accessing this large-capacity SRAM array presents a problem: the bit line signals (containing a pair of complementary signals, data and datan) attenuate over such a long path, affecting read / write speed and even causing errors.
[0003] To ensure successful read / write operations and improve access speed, the entire bit line is often divided into several segments, with a relay circuit connected in series between each pair of segments. This relay circuit amplifies the bit line signal from the previous segment before transmitting it to the next. Figure 1 shows a traditional bit line relay solution. In this solution, when writing to SRAM, a buffer is needed to amplify the received digital signal before transmitting it to the next segment; when reading from SRAM, a sense amplifier is needed to read the SRAM output before transmitting it to the next segment, and finally, the signal is transmitted to the read / write control circuit. This relay circuit requires disconnecting the original bit line, connecting read / write nodes in series on the signal transmission path, increasing signal delay, severely impacting read / write speed, and disrupting the original topology, affecting the regularity of SRAM bit line routing. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.
[0005] This disclosure provides a relay circuit, a relay method, and a storage system. The relay circuit, relay method, and storage system can reduce signal latency, improve read / write speed, and maintain the original topology.
[0006] This disclosure provides a relay circuit applied to a memory, comprising: the relay circuit being connected in parallel with a first bit line and a second bit line of the memory; the signal levels on the first bit line and the signal levels on the second bit line being opposite; the relay circuit comprising: a first amplifier circuit being connected to a first drive enable line, a second drive enable line, a first power line, the first bit line, and the second bit line, respectively, configured to provide a signal from the first power line to the first bit line or the second bit line under the control of the signals from the first drive enable line, the second drive enable line, the first bit line, and the second bit line, so as to amplify the low-level signal on the parallel bit line, wherein the signal from the first power line... The first bit line is a low-level signal; the second amplifier circuit is connected to the first drive enable line, the second power line, the first bit line, and the second bit line respectively, and is configured to provide the second power line signal to the first bit line or the second bit line under the control of the signals of the first drive enable line, the second power line, the first bit line, and the second bit line, so as to amplify the high-level signal on the parallel bit line, wherein the signal of the second power line is a high-level signal; the pre-charge circuit is connected to the pre-charge control line, the second power line, the first bit line, and the second bit line respectively, and is configured to provide the second power line signal to the first bit line or the second bit line under the control of the signals of the pre-charge control line and the second power line.
[0007] In one exemplary embodiment, the first amplification circuit includes a positive feedback circuit and an output circuit; the positive feedback circuit is connected to a first drive enable line, a second drive enable line, a first power line, a first bit line, a second bit line, a third node, and a fourth node, respectively, and is configured to provide a signal on the first power line or a signal from the first drive enable line to the third node and the fourth node, respectively, under the control of the signals from the second drive enable line, the first bit line, and the second bit line; the output circuit is connected to the first power line, the first bit line, the second bit line, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power line to the first bit line or the second bit line, under the control of the signals from the third node and the fourth node.
[0008] In one exemplary embodiment, the positive feedback circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, and a tenth transistor; the control electrode of the first transistor is connected to a first node, the first terminal of the first transistor is connected to the first drive enable line, and the second terminal of the first transistor is connected to the first terminal of the third transistor; the first node is connected to the first bit line; the control electrode of the second transistor is connected to a second node, the first terminal of the second transistor is connected to the first terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the fourth transistor; the second node is connected to the second bit line; the control electrode of the third transistor is connected to the second terminal of the fourth transistor, the first terminal of the third transistor is connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to... The second terminal of the third transistor is connected; the first terminal of the fourth transistor is connected to the second terminal of the second transistor; the second terminal of the fourth transistor is connected to the fourth node; the control terminal of the fifth transistor is connected to the fourth node; the first terminal of the fifth transistor is connected to the third node; the second terminal of the fifth transistor is connected to the first power line; the control terminal of the sixth transistor is connected to the third node; the first terminal of the sixth transistor is connected to the fourth node; the second terminal of the sixth transistor is connected to the first power line; the control terminal of the ninth transistor is connected to the second drive enable line; the first terminal of the ninth transistor is connected to the third node; the second terminal of the ninth transistor is connected to the first power line; the control terminal of the tenth transistor is connected to the second drive enable line; the first terminal of the tenth transistor is connected to the fourth node; the second terminal of the tenth transistor is connected to the first power line.
[0009] In one exemplary embodiment, the output circuit includes a seventh transistor and an eighth transistor; the control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the first node, and the second electrode of the seventh transistor is connected to the first power line; the control electrode of the eighth transistor is connected to the fourth node, the first electrode of the eighth transistor is connected to the second node, and the second electrode of the eighth transistor is connected to the first power line.
[0010] In one exemplary embodiment, the second amplifier circuit includes an eleventh transistor and a twelfth transistor; the control electrode of the eleventh transistor is connected to the second node; the first electrode of the eleventh transistor is connected to the second power supply line, and the second electrode of the eleventh transistor is connected to the first node; the control electrode of the twelfth transistor is connected to the first node; the first electrode of the twelfth transistor is connected to the second power supply line, and the second electrode of the twelfth transistor is connected to the second node.
[0011] In one exemplary embodiment, the pre-charge circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; the control electrode of the thirteenth transistor is connected to a fifth node; the first electrode of the thirteenth transistor is connected to a first node, and the second electrode of the thirteenth transistor is connected to a second node; the fifth node is connected to the pre-charge control line; the control electrode of the fourteenth transistor is connected to the fifth node; the first electrode of the fourteenth transistor is connected to a second power line, and the second electrode of the fourteenth transistor is connected to the first electrode of the thirteenth transistor; the control electrode of the fifteenth transistor is connected to the fifth node; the first electrode of the fifteenth transistor is connected to a second power line, and the second electrode of the fifteenth transistor is connected to the second electrode of the thirteenth transistor.
[0012] In one exemplary embodiment, the relay circuit includes a plurality of relay circuits; the plurality of relay circuits are arranged at a preset interval.
[0013] This disclosure also provides a relay method applied to the relay circuit described in any of the above embodiments, comprising: providing signals to a first drive enable line, a second drive enable line, a first bit line, and a second bit line, such that a signal of a first power line is provided to the first bit line or the second bit line to amplify a low-level signal on the parallel bit line, wherein the signal of the first power line is a low-level signal; providing signals to the first drive enable line, the second power line, the first bit line, and the second bit line, such that a signal of a second power line is provided to the first bit line or the second bit line to amplify a high-level signal on the parallel bit line, wherein the signal of the second power line is a high-level signal; and providing signals to the precharge control line and the second power line, such that a signal of a second power line is provided to the first bit line or the second bit line.
[0014] This disclosure also provides a storage system, including: a memory and a relay circuit as described in any of the above embodiments.
[0015] In one exemplary embodiment, the memory includes static random access memory.
[0016] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description and the drawings. Attached Figure Description
[0017] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.
[0018] Figure 1 is a schematic diagram of a relay circuit in the prior art; Figure 2 is a schematic diagram of a relay circuit according to an embodiment of the present disclosure; Figure 3 is a schematic diagram of the arrangement of multiple relay circuits according to an embodiment of the present disclosure; Figure 4 is a schematic diagram of a relay circuit according to an embodiment of the present disclosure; Figure 5 is a timing diagram of the relay circuit shown in Figure 4; Figure 6 is a timing diagram of the relay circuit shown in Figure 4. Detailed Implementation
[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.
[0020] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.
[0021] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.
[0022] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.
[0023] Figure 2 is a schematic diagram of a relay circuit according to an embodiment of the present disclosure. The relay circuit is applied to a memory and is connected in parallel with the first bit line and the second bit line of the memory. The signal levels on the first bit line and the signal levels on the second bit line are opposite. As shown in Figure 2, the relay circuit includes a first amplifier circuit, a second amplifier circuit, and a pre-charge circuit.
[0024] The first amplifier circuit is connected to the first drive enable line en-drv, the second drive enable line enn-drv, the first power line VSS, the first bit line datan, and the second bit line data, respectively. It is configured to provide the first power line VSS signal to either the first bit line datan or the second bit line data, under the control of the signals from the first drive enable line en-drv, the second drive enable line enn-drv, the first bit line datan, and the second bit line data, to amplify the low-level signal on the parallel bit line. The signal from the first power line VSS is a low-level signal. The second amplifier circuit is connected to the first drive enable line en-drv, the second power line VCC, and the first bit line data, respectively. The first bit line (n) and the second bit line (data) are connected. Under the control of the signals of the first drive enable line (en-drv), the second power supply line (VCC), the first bit line (datan), and the second bit line (data), the second power supply line (VCC) provides the signal of the second power supply line (VCC) to the first bit line (datan) or the second bit line (data) to amplify the high-level signal on the parallel bit line. The signal of the second power supply line (VCC) is a high-level signal. The pre-charge circuit is connected to the pre-charge control line, the second power supply line, the first bit line (datan), and the second bit line (data), respectively. Under the control of the signals of the pre-charge control line and the second power supply line (VCC), the pre-charge circuit provides the signal of the second power supply line (VCC) to the first bit line or the second bit line (data).
[0025] The relay circuit disclosed herein is connected in parallel with the first and second bit lines of the memory, and can precharge the first and second bit lines. It can also amplify the high-level and low-level signals on the first and second bit lines, which not only reduces signal delay and improves read and write speed, but also maintains the original topology.
[0026] For example, the signal of the first power line VSS can always be logic 0, and the signal of the second power line VCC can always be logic 1.
[0027] In one exemplary embodiment, the first amplification circuit may include a positive feedback circuit and an output circuit; the positive feedback circuit is connected to a first drive enable line, a second drive enable line, a first power line, a first bit line, a second bit line, a third node, and a fourth node, respectively, and is configured to provide a signal on the first power line or a signal from the first drive enable line to the third node and the fourth node, respectively, under the control of the signals from the second drive enable line, the first bit line, and the second bit line; the output circuit is connected to the first power line, the first bit line, the second bit line, the third node, and the fourth node, respectively, and is configured to provide a signal from the first power line to the first bit line or the second bit line, under the control of the signals from the third node and the fourth node.
[0028] In one exemplary embodiment, the positive feedback circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, and a tenth transistor; the control electrode of the first transistor is connected to a first node, the first terminal of the first transistor is connected to the first drive enable line, and the second terminal of the first transistor is connected to the first terminal of the third transistor; the first node is connected to the first bit line; the control electrode of the second transistor is connected to a second node, the first terminal of the second transistor is connected to the first terminal of the first transistor, and the second terminal of the second transistor is connected to the first terminal of the fourth transistor; the second node is connected to the second bit line; the control electrode of the third transistor is connected to the second terminal of the fourth transistor, the first terminal of the third transistor is connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to... The second terminal of the third transistor is connected; the first terminal of the fourth transistor is connected to the second terminal of the second transistor; the second terminal of the fourth transistor is connected to the fourth node; the control terminal of the fifth transistor is connected to the fourth node; the first terminal of the fifth transistor is connected to the third node; the second terminal of the fifth transistor is connected to the first power line; the control terminal of the sixth transistor is connected to the third node; the first terminal of the sixth transistor is connected to the fourth node; the second terminal of the sixth transistor is connected to the first power line; the control terminal of the ninth transistor is connected to the second drive enable line; the first terminal of the ninth transistor is connected to the third node; the second terminal of the ninth transistor is connected to the first power line; the control terminal of the tenth transistor is connected to the second drive enable line; the first terminal of the tenth transistor is connected to the fourth node; the second terminal of the tenth transistor is connected to the first power line.
[0029] In one exemplary embodiment, the output circuit includes a seventh transistor and an eighth transistor; the control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the first node, and the second electrode of the seventh transistor is connected to the first power line; the control electrode of the eighth transistor is connected to the fourth node, the first electrode of the eighth transistor is connected to the second node, and the second electrode of the eighth transistor is connected to the first power line.
[0030] In one exemplary embodiment, the second amplifier circuit includes an eleventh transistor and a twelfth transistor; the control electrode of the eleventh transistor is connected to the second node; the first electrode of the eleventh transistor is connected to the second power supply line, and the second electrode of the eleventh transistor is connected to the first node; the control electrode of the twelfth transistor is connected to the first node; the first electrode of the twelfth transistor is connected to the second power supply line, and the second electrode of the twelfth transistor is connected to the second node.
[0031] In one exemplary embodiment, the pre-charge circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; the control electrode of the thirteenth transistor is connected to a fifth node; the first electrode of the thirteenth transistor is connected to a first node, and the second electrode of the thirteenth transistor is connected to a second node; the fifth node is connected to the pre-charge control line; the control electrode of the fourteenth transistor is connected to the fifth node; the first electrode of the fourteenth transistor is connected to a second power line, and the second electrode of the fourteenth transistor is connected to the first electrode of the thirteenth transistor; the control electrode of the fifteenth transistor is connected to the fifth node; the first electrode of the fifteenth transistor is connected to a second power line, and the second electrode of the fifteenth transistor is connected to the second electrode of the thirteenth transistor.
[0032] For example, relay circuits can also be applied to the read / write circuits or read / write relays of memory.
[0033] Figure 3 is a schematic diagram of the arrangement of multiple relay circuits according to an embodiment of the present disclosure. As shown in Figure 3, the multiple relay circuits are arranged at a preset interval. Each relay circuit is connected across the first bit line datan and the second bit line data, and is connected in parallel with the first bit line datan and the second bit line data, respectively.
[0034] For example, the preset interval can be equal. In some other embodiments, the preset interval can also be unequal.
[0035] Figure 4 is a second schematic diagram of a relay circuit according to an embodiment of this disclosure. As shown in Figure 4, the relay circuit includes a first amplifier circuit 10, a second amplifier circuit 20, and a pre-charge circuit 30.
[0036] The first amplifier circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
[0037] The control electrode of the first transistor M1 is connected to the first node N1, the first terminal of the first transistor M1 is connected to the first drive enable line en_drv, and the second terminal of the first transistor M1 is connected to the first terminal of the third transistor M3; the first node N1 is connected to the first bit line datan. The control electrode of the second transistor M2 is connected to the second node N2, the first terminal of the second transistor M2 is connected to the first terminal of the first transistor M1, and the second terminal of the second transistor M2 is connected to the first terminal of the fourth transistor M4; the second node N2 is connected to the second bit line data. The control electrode of the third transistor M3 is connected to the second terminal of the fourth transistor M4, the first terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, and the second terminal of the third transistor M3 is connected to the third node N3. The control electrode of the fourth transistor M4 is connected to the second terminal of the third transistor M3, the first terminal of the fourth transistor M4 is connected to the second terminal of the second transistor M2, and the second terminal of the fourth transistor M4 is connected to the fourth node N4. The control electrode of the fifth transistor M5 is connected to the fourth node N4, the first terminal of the fifth transistor M5 is connected to the third node N3, and the second terminal of the fifth transistor M5 is connected to the first bit line datan. The first power line VSS is connected; the control electrode of the sixth transistor M6 is connected to the third node N3, the first electrode of the sixth transistor M6 is connected to the fourth node N4, and the second electrode of the sixth transistor M6 is connected to the first power line VSS; the control electrode of the seventh transistor M7 is connected to the third node N3, the first electrode of the seventh transistor M7 is connected to the first node N1, and the second electrode of the seventh transistor M7 is connected to the first power line VSS; the control electrode of the eighth transistor M8 is connected to the fourth node N4, the first electrode of the eighth transistor M8 is connected to the second node N2, and the second electrode of the eighth transistor M8 is connected to the first power line VSS; the control electrode of the ninth transistor M9 is connected to the second drive enable line enn_drv, the first electrode of the ninth transistor M9 is connected to the third node N3, and the second electrode of the ninth transistor M9 is connected to the first power line VSS; the control electrode of the tenth transistor M10 is connected to the second drive enable line enn_drv, the first electrode of the tenth transistor M10 is connected to the fourth node N4, and the second electrode of the tenth transistor M10 is connected to the first power line VSS; the second amplifier circuit 20 includes an eleventh transistor M11 and a twelfth transistor M12.
[0038] The control electrode of the eleventh transistor M11 is connected to the second node N2; the first electrode of the eleventh transistor M11 is connected to the second power supply line VCC, and the second electrode of the eleventh transistor M11 is connected to the first node N1; the control electrode of the twelfth transistor M12 is connected to the first node N1; the first electrode of the twelfth transistor M12 is connected to the second power supply line VCC, and the second electrode of the twelfth transistor M12 is connected to the second node N2; the pre-charge circuit 30 includes the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15.
[0039] The control electrode of the thirteenth transistor M13 is connected to the fifth node N5; the first electrode of the thirteenth transistor M13 is connected to the first node N1, and the second electrode of the thirteenth transistor M13 is connected to the second node N2; the fifth node N5 is connected to the precharge control line prechg_n; the control electrode of the fourteenth transistor M14 is connected to the fifth node N5; the first electrode of the fourteenth transistor M14 is connected to the second power line VCC, and the second electrode of the fourteenth transistor M14 is connected to the first electrode of the thirteenth transistor M13; the control electrode of the fifteenth transistor M15 is connected to the fifth node N5; the first electrode of the fifteenth transistor M15 is connected to the second power line VCC, and the second electrode of the fifteenth transistor M15 is connected to the second electrode of the thirteenth transistor M13.
[0040] The first power supply line VSS is always at a low level, and the second power supply line VCC is always at a high level.
[0041] The first to fifth transistors constitute a positive feedback circuit.
[0042] When the first to fifteenth transistors are MOS transistors, the control electrode of the first to fifteenth transistors is the gate, the first electrode of the first to fifteenth transistors is the drain (or source), and the second electrode of the first to fifteenth transistors is the source (or drain).
[0043] Taking transistors 1 to 4, 11 to 15 in Figure 4 as PMOS transistors and transistors 5 to 10 as NMOS transistors as an example, Figure 5 is the timing diagram for reading data from the circuit in Figure 4. Figure 6 is the timing diagram for writing data from the circuit in Figure 4.
[0044] The circuit operates as follows during data reading: In the P1 stage (pre-charge stage), the second drive enable line enn_drv is high, while the pre-charge control line prechg_n and the first drive enable line en_drv are low. The thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on, while the first transistor M1, the second transistor M2, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned off.
[0045] Because the fifteenth transistor M15 is turned on, the second power supply corresponding to the second power line VCC charges the second node N2 through the turned-on fifteenth transistor M15; because the fourteenth transistor M14 is turned on, the second power supply corresponding to the second power line VCC charges the first node N1 through the turned-on fourteenth transistor M14. That is, both the first bit line datan and the second bit line data are charged to V. CC , where V CC This indicates the voltage of the second power source.
[0046] In phase P2 (read data phase), when reading data begins (read is the read enable signal, WL is the word line timing), assuming the stored data has the first bit line datan high and the second bit line data low, then the first drive enable line en_drv and the second bit line data are low, while datan remains high. The precharge control line prechg_n and the second drive enable line enn_drv are also high. Because the second drive enable line enn_drv is high, the ninth transistor M9 and the tenth transistor M10 are turned on, while the seventh transistor M7 and the eighth transistor M8 are turned off.
[0047] Afterwards, the second driver enable line enn_drv first goes down, releasing M7 and M8. Then, the first driver enable line en_drv goes high. Since the second bit line data is low, the second transistor M2 and the fourth transistor M4 are turned on, and the fourth node is high. Because the fourth node is high, the eighth transistor and the fifth transistor are turned on, and the level of the second node N2 is V. SS V SS The voltage level on the first power line VSS is typically logic "0". This amplifies the low-level signal on the second bit line data, effectively pulling the signal on the second bit line data to ground.
[0048] After the signal on the second bit line data is pulled to ground, the eleventh transistor M11 turns on, pulling the signal on the first bit line datan high to Vcc. At the same time, the twelfth transistor turns off, keeping the signal on the second bit line data pulled to ground.
[0049] The circuit operates similarly to the data reading circuit when writing data: In the P1 stage (pre-charge stage), the second drive enable line enn_drv is high, while the pre-charge control line prechg_n and the first drive enable line en_drv are low. The thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on, while the first transistor M1, the second transistor M2, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, and the twelfth transistor M12 are turned off.
[0050] Because the fifteenth transistor M15 is turned on, the second power supply corresponding to the second power line VCC charges the second node N2 through the turned-on fifteenth transistor M15; because the fourteenth transistor M14 is turned on, the second power supply corresponding to the second power line VCC charges the first node N1 through the turned-on fourteenth transistor M14. That is, both the first bit line datan and the second bit line data are charged to V. CC , where V CCThis indicates the voltage of the second power source.
[0051] In phase P2 (the data writing phase), when writing data begins (write is the write enable signal, WL is the word line timing), the precharge control line prechg_n jumps up. Since the second drive enable line enn_drv is high, transistors M9 and M10 are turned on, while transistors M7 and M8 are turned off to release transistors M1 and M2. The read / write control circuit sets data=0 and datan=1.
[0052] Subsequently, the second driver enable line `enn_drv` is down-jumped, the first driver enable line `en_drv` is high, the first bit line `datan` is high, and the second bit line `data` is low. Therefore, the second transistor M2 and the fourth transistor M4 are turned on, and the fourth node is high. Since the fourth node is high, the eighth transistor and the fifth transistor are turned on, and the level of the second node N2 is V. SS V SS The voltage level on the first power line VSS is typically logic "0". This amplifies the low-level signal on the second bit line data, effectively pulling the signal on the second bit line data to ground.
[0053] After the signal on the second bit line `data` is pulled to ground, the eleventh transistor `M11` turns on, pulling the signal on the first bit line `data` high to `Vcc`. Simultaneously, the twelfth transistor turns off, keeping the signal on the second bit line `data` pulled to ground. At this point, the signals `data=0` and `datan=1` are sent to the memory's data input / output port, and the data "1" is written to the memory.
[0054] The relay circuit in this embodiment does not change the bit line structure and can be directly connected in parallel to the bit line to play the role of relay and acceleration. It has a small area cost, reliable operation, does not increase node delay, and has no static power consumption, which has a huge advantage over traditional solutions.
[0055] This disclosure also provides a relay method applied to the relay circuit described in any of the above embodiments, comprising: providing signals to a first drive enable line, a second drive enable line, a first bit line, and a second bit line, such that a signal of a first power line is provided to the first bit line or the second bit line to amplify a low-level signal on the parallel bit line, wherein the signal of the first power line is a low-level signal; providing signals to the first drive enable line, the second power line, the first bit line, and the second bit line, such that a signal of a second power line is provided to the first bit line or the second bit line to amplify a high-level signal on the parallel bit line, wherein the signal of the second power line is a high-level signal; and providing signals to the precharge control line and the second power line, such that a signal of a second power line is provided to the first bit line or the second bit line.
[0056] This disclosure also provides a storage system, including: a memory and a relay circuit as described in any of the above embodiments.
[0057] For example, the memory includes, but is not limited to, SRAM memory.
[0058] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.
[0059] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.
[0060] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.
[0061] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of those features.
[0062] In the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0063] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," "fixing," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0064] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.
[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.
[0066] Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.
Claims
1. A relay circuit applied to a memory, characterized in that, include: The relay circuit is connected in parallel with the first bit line and the second bit line of the memory, respectively; The signal levels on the first bit line and the second bit line are opposite. The relay circuit includes: a first amplifier circuit connected to a first drive enable line, a second drive enable line, a first power line, a first bit line, and a second bit line, respectively, configured to provide a first power line signal to the first bit line or the second bit line under the control of the signals of the first drive enable line, the second drive enable line, the first bit line, and the second bit line, so as to amplify the low-level signal on the parallel bit line, wherein the signal of the first power line is a low-level signal; a second amplifier circuit connected to the first drive enable line, the second power line, the first bit line, and the second bit line, respectively, configured to provide a second power line signal to the first bit line or the second bit line under the control of the signals of the first drive enable line, the second power line, the first bit line, and the second bit line, so as to amplify the high-level signal on the parallel bit line, wherein the signal of the second power line is a high-level signal; and a pre-charge circuit connected to a pre-charge control line, a second power line, the first bit line, and the second bit line, respectively, configured to provide a second power line signal to the first bit line or the second bit line under the control of the signals of the pre-charge control line and the second power line.
2. The relay circuit as described in claim 1, characterized in that, The first amplification circuit includes a positive feedback circuit and an output circuit. The positive feedback circuit is connected to a first drive enable line, a second drive enable line, a first power line, a first bit line, a second bit line, a third node, and a fourth node, respectively. It is configured to provide the first power line signal or the first drive enable line signal to the third node and the fourth node, respectively, under the control of the signals of the second drive enable line, the first bit line, and the second bit line. The output circuit is connected to the first power line, the first bit line, the second bit line, the third node, and the fourth node, respectively. It is configured to provide the first power line signal to the first bit line or the second bit line, respectively, under the control of the signals of the third node and the fourth node.
3. The relay circuit as described in claim 2, characterized in that, The positive feedback circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, and a tenth transistor; the control electrode of the first transistor is connected to the first node, the first electrode of the first transistor is connected to the first drive enable line, and the second electrode of the first transistor is connected to the first electrode of the third transistor. The first node is connected to the first bit line; the control electrode of the second transistor is connected to the second node, the first electrode of the second transistor is connected to the first electrode of the first transistor, and the second electrode of the second transistor is connected to the first electrode of the fourth transistor; the second node is connected to the second bit line; the control electrode of the third transistor is connected to the second electrode of the fourth transistor, the first electrode of the third transistor is connected to the second electrode of the first transistor, and the second electrode of the third transistor is connected to the third node; the control electrode of the fourth transistor is connected to the second electrode of the third transistor, the first electrode of the fourth transistor is connected to the second electrode of the second transistor, and the second electrode of the fourth transistor is connected to the fourth node; the fifth transistor... The control electrode of the fifth transistor is connected to the fourth node; the first electrode of the fifth transistor is connected to the third node; and the second electrode of the fifth transistor is connected to the first power line. The control electrode of the sixth transistor is connected to the third node; the first electrode of the sixth transistor is connected to the fourth node; and the second electrode of the sixth transistor is connected to the first power line. The control electrode of the ninth transistor is connected to the second drive enable line; the first electrode of the ninth transistor is connected to the third node; and the second electrode of the ninth transistor is connected to the first power line. The control electrode of the tenth transistor is connected to the second drive enable line; the first electrode of the tenth transistor is connected to the fourth node; and the second electrode of the tenth transistor is connected to the first power line.
4. The relay circuit as described in claim 3, characterized in that, The output circuit includes a seventh transistor and an eighth transistor; the control electrode of the seventh transistor is connected to the third node, the first electrode of the seventh transistor is connected to the first node, and the second electrode of the seventh transistor is connected to the first power line; the control electrode of the eighth transistor is connected to the fourth node, the first electrode of the eighth transistor is connected to the second node, and the second electrode of the eighth transistor is connected to the first power line.
5. The relay circuit as described in claim 4, characterized in that, The second amplifier circuit includes an eleventh transistor and a twelfth transistor; the control electrode of the eleventh transistor is connected to the second node; the first electrode of the eleventh transistor is connected to the second power supply line, and the second electrode of the eleventh transistor is connected to the first node; the control electrode of the twelfth transistor is connected to the first node; the first electrode of the twelfth transistor is connected to the second power supply line, and the second electrode of the twelfth transistor is connected to the second node.
6. The relay circuit as described in claim 5, characterized in that, The pre-charge circuit includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; the control electrode of the thirteenth transistor is connected to a fifth node; the first electrode of the thirteenth transistor is connected to a first node, and the second electrode of the thirteenth transistor is connected to a second node; the fifth node is connected to the pre-charge control line; the control electrode of the fourteenth transistor is connected to the fifth node; the first electrode of the fourteenth transistor is connected to a second power line, and the second electrode of the fourteenth transistor is connected to the first electrode of the thirteenth transistor; the control electrode of the fifteenth transistor is connected to the fifth node; the first electrode of the fifteenth transistor is connected to a second power line, and the second electrode of the fifteenth transistor is connected to the second electrode of the thirteenth transistor.
7. The relay circuit as described in claim 1, characterized in that, The relay circuit includes multiple relay circuits; the multiple relay circuits are arranged at preset intervals.
8. A relay method, applied to the relay circuit according to any one of claims 1 to 7, characterized in that, include: Signals are provided to the first drive enable line, the second drive enable line, the first bit line, and the second bit line to provide a first power line signal to the first bit line or the second bit line, thereby amplifying the low-level signal on the parallel bit line, wherein the signal on the first power line is a low-level signal; signals are also provided to the first drive enable line, the second power line, the first bit line, and the second bit line to provide a second power line signal to the first bit line or the second bit line, thereby amplifying the high-level signal on the parallel bit line, wherein the signal on the second power line is a high-level signal; signals are also provided to the precharge control line and the second power line to provide a second power line signal to the first bit line or the second bit line.
9. A storage system, characterized in that, include: The memory and the relay circuit according to any one of claims 1 to 7.
10. The storage system as claimed in claim 9, characterized in that, The memory includes static random access memory.