Battery protection chip, cascade battery protection circuit and electronic equipment

Abstract

The invention discloses a battery protection chip, a cascade battery protection circuit and an electronic device, the battery protection chip comprises a cell connection pin, a first charge and discharge control pin, a second charge and discharge control pin, a load signal feedback pin and a voltage detection pin; the cascade level detection circuit and the charging and discharging control circuit are integrated in the battery protection chip, and the cascade level detection circuit is integrated in a single chip, so that the cascade level detection circuit can automatically identify a high-level side working mode or a low-level side working mode according to the level of a first charging and discharging control pin; and a signal processing path of an internal charging and discharging control circuit is correspondingly configured in the mode, so that when a cascade system is constructed, reliable protection can be realized only by a few external resistors, the number of peripheral devices is greatly reduced, the hardware cost and the circuit design complexity are reduced, and the reliability of the cascade system is improved. And chips of the same model can be universally used in cascade and non-cascade scenes, so that the material preparation and application design of customers can be obviously simplified.

Description

Battery protection chips, cascaded battery protection circuits and electronic devices Technical Field

[0001] This invention relates to the field of battery management technology, and in particular to a battery protection chip, a cascaded battery protection circuit, and an electronic device. Background Technology

[0002] Lithium-ion battery packs typically consist of multiple cells connected in series to provide high voltage. To protect the battery pack, a battery protection chip is required. However, single-chip protection has limited voltage withstand capability; when the battery pack voltage is very high, directly designing a single high-voltage protection chip is extremely difficult and costly.

[0003] One existing solution is to use a cascaded approach, which combines multiple low-voltage protection chips to protect high-voltage battery packs. For example, a communication path is established using two protection integrated circuit chips and a series of peripheral discrete components, such as resistors, capacitors, and transistors, enabling the two protection integrated circuit chips to work together to achieve overall protection.

[0004] However, this existing cascading solution relies on complex peripheral circuits to achieve signal transmission and level conversion, resulting in high hardware costs, complex circuit board design, and challenges to system reliability. Summary of the Invention

[0005] This invention provides a battery protection chip, a cascaded battery protection circuit, and an electronic device to address the problems of high hardware cost, complex circuit board design, and challenges to system reliability in existing cascaded solutions.

[0006] A battery protection chip includes a cell connection pin, a first charge / discharge control pin, a second charge / discharge control pin, a load signal feedback pin, and a voltage detection pin; and a cascaded level detection circuit and a charge / discharge control circuit integrated within the battery protection chip. The cell connection pin is used to connect at least one cell. The cascaded level detection circuit is connected to the first charge / discharge control pin and is used to determine whether the current operation is in a high-side mode or a low-side mode based on the input level on the first charge / discharge control pin. The charge / discharge control circuit is connected to the cascaded level detection circuit, the cell connection pin, the first charge / discharge control pin, the second charge / discharge control pin, and the load signal feedback pin. The feedback pin is connected to the voltage detection pin; the charge / discharge control circuit is configured to generate a first control signal and output it through the second charge / discharge control pin based on the cell status detected by the cell connection pin and / or the first input signal of the voltage detection pin in the high-level side mode; the charge / discharge control circuit is also configured to generate a second control signal and output it through the second charge / discharge control pin based on the cell status detected by the cell connection pin and / or the second input signal of the first charge / discharge control pin in the low-level side mode, and generate a load feedback signal and output it through the load signal feedback pin based on the third input signal of the voltage detection pin.

[0007] Further, the charge / discharge control circuit includes a cell detection circuit, a voltage source circuit, a charge / discharge drive circuit, a voltage detection circuit, a load signal feedback circuit, and a logic processing circuit; the cell detection circuit is connected to the cell connection pin and the logic processing circuit, and is used to detect the cell state; the voltage source circuit is used to provide a voltage signal; the charge / discharge drive circuit is connected to the voltage source circuit, the first charge / discharge control pin, and the logic processing circuit, and is used to output a charge / discharge drive signal according to the voltage signal and the second input signal of the first charge / discharge control pin in the low-level side mode; the voltage detection circuit is connected to the voltage detection pin and the logic processing circuit, and is used to output a voltage detection signal according to the first input signal or the third input signal; the load signal feedback circuit is connected to the voltage source circuit, the first charge / discharge control pin, the second input signal of the first charge / discharge control pin, and the logic processing circuit. The first feedback pin is connected to the logic processing circuit and is used to output the load feedback signal according to the voltage signal under the control of the logic processing circuit. The logic processing circuit is connected to the second charge / discharge control pin and is used to shield the charge / discharge drive signal in the high-level side mode, generate a first control signal based on the cell state detected by the cell detection circuit and / or the voltage detection signal output by the voltage detection circuit, and output it through the second charge / discharge control pin. In the low-level side mode, based on the cell state detected by the cell detection circuit and / or the charge / discharge drive signal output by the charge / discharge drive circuit, generate a second control signal and output it through the second charge / discharge control pin, and control the load signal feedback circuit to output the load feedback signal based on the voltage detection signal output by the voltage detection circuit.

[0008] Furthermore, the first charge / discharge control pin includes a first charge control pin and a first discharge control pin; the charge / discharge driving circuit includes two driving circuits; one driving circuit is connected to the voltage source circuit, the first charge control pin, and the logic processing circuit; the other driving circuit is connected to the voltage source circuit, the first discharge control pin, and the logic processing circuit.

[0009] Further, the driving circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a Schmitt trigger; the drain of the first PMOS transistor is connected to the first charging control pin or the first discharging control pin, the gate of the first PMOS transistor is connected to the first output terminal of the voltage source circuit, the source of the first PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor is connected to the second output terminal of the voltage source circuit, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second NMOS transistor is connected to the third output terminal of the voltage source circuit. The second NMOS transistor is connected to the ground terminal; the drain of the second PMOS transistor is connected to the second output terminal of the voltage source circuit; the gate of the second PMOS transistor is connected to the fourth output terminal of the voltage source circuit; the source of the second PMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the connection node between the first NMOS transistor and the second NMOS transistor; and the source of the third NMOS transistor is connected to the ground terminal. The input terminal of the Schmitt trigger is connected to the connection node between the second PMOS transistor and the third NMOS transistor, and the output terminal of the Schmitt trigger is connected to the logic processing circuit.

[0010] Furthermore, the load signal feedback circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor; the drain of the fourth NMOS transistor is connected to the load signal feedback pin, the gate of the fourth NMOS transistor is connected to the second output terminal of the voltage source circuit, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the logic processing circuit, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the third output terminal of the voltage source circuit, and the drain of the sixth NMOS transistor is connected to the ground terminal.

[0011] A cascaded battery protection circuit includes a battery assembly, a charge / discharge switch circuit, and at least two of the aforementioned battery protection chips. The charge / discharge switch circuit is connected in series between the battery assembly and a charge / discharge interface. At least two of the battery protection chips are connected in series. The cell connection pin of each of the battery protection chips is used to connect to the battery assembly. The battery assembly includes multiple cells. The control terminal of the charge / discharge switch circuit is connected to the lower-level chip among the at least two battery protection chips.

[0012] Furthermore, the two battery protection chips include a high-level side chip and a low-level side chip; the first charge / discharge control pin of the high-level side chip is used to connect to the ground terminal, the voltage detection pin of the high-level side chip is connected to the load signal feedback pin of the low-level side chip, the second charge / discharge control pin of the high-level side chip is connected to the first charge / discharge control pin of the low-level side chip, the voltage detection pin of the low-level side chip is connected to the charge / discharge connection interface, and the second charge / discharge control pin of the low-level side chip is connected to the charge / discharge switch circuit.

[0013] Furthermore, the cascaded battery protection circuit also includes a first resistor circuit and a second resistor circuit; the first end of the first resistor circuit is connected to the second charge / discharge control pin of the advanced-side chip, and the second end of the first resistor circuit is connected to the first charge / discharge control pin of the low-level chip; the first end of the second resistor circuit is connected to the voltage detection pin of the advanced-side chip, and the second end of the second resistor circuit is connected to the load signal feedback pin of the low-level chip.

[0014] Furthermore, the cascaded battery protection circuit also includes a third resistor circuit; the first end of the third resistor circuit is connected to the first charge / discharge control pin of the advanced side chip, and the second end of the third resistor circuit is connected to the ground terminal.

[0015] An electronic device comprising the aforementioned cascaded battery protection circuit.

[0016] This invention provides a battery protection chip, a cascaded battery protection circuit, and an electronic device. By integrating the cascade level detection circuit into a single chip, it can automatically identify the high-level or low-level operating mode based on the level of the first charge / discharge control pin, and configure the signal processing path of the internal charge / discharge control circuit accordingly in that mode. Thus, when building a cascaded system, only a very small number of external resistors are needed to achieve reliable protection. This not only significantly reduces the number of peripheral components, lowers hardware costs and circuit design complexity, but also allows the same model of chip to be used in both cascaded and non-cascaded scenarios, significantly simplifying customers' material preparation and application design. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 is a schematic diagram of a battery protection chip in one embodiment of the present invention; Figure 2 is a schematic diagram of a cascaded battery protection circuit in one embodiment of the present invention; Figure 3 is a schematic diagram of a charge / discharge drive circuit in one embodiment of the present invention; Figure 4 is another schematic diagram of a charge / discharge drive circuit in one embodiment of the present invention; Figure 5 is a schematic diagram of a load signal feedback circuit in one embodiment of the present invention.

[0019] In the diagram: 1. Battery protection chip; 11. Cascaded level detection circuit; 12. Charge / discharge control circuit; 121. Cell detection circuit; 122. Voltage source circuit; 123. Charge / discharge drive circuit; 124. Voltage detection circuit; 125. Load signal feedback circuit; 126. Logic processing circuit; 2. High-level side chip; 3. Low-level side chip; 4. Charge / discharge switch circuit; 5. Battery assembly. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0022] To fully understand this invention, detailed structures and steps will be presented in the following description to illustrate the technical solution proposed by this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0023] In the description of this invention, the terms "advanced side" and "lower side" are defined based on the relative position of the battery protection chip 1 in the cascaded system. Generally, the battery protection chip 1 that directly monitors the higher voltage cells in the battery pack 5 is called the advanced side chip 2; the chip that directly controls the charge / discharge switch circuit 4 and monitors the lower voltage cells in the battery pack 5 is called the lower side chip 3.

[0024] This embodiment provides a cascaded battery protection circuit. As shown in FIG2, the circuit includes a battery assembly 5, a charge / discharge switch circuit 4, and at least two battery protection chips 1. Exemplarily, the at least two battery protection chips 1 include a first battery protection chip 1 and a second battery protection chip 1. The first battery protection chip 1 is a high-level chip 2, and the second battery protection chip 1 is a low-level chip 3. The first battery protection chip 1 and the second battery protection chip 1 are the same type of protection chip that integrates cascading functionality.

[0025] A charge / discharge switch circuit 4 is connected in series between the battery assembly 5 and the charge / discharge interface. The charge / discharge interface includes a positive terminal P+ / CH+ and a negative terminal P- / CH-. At least two battery protection chips 1 are connected in series; the cell connection pins of each battery protection chip 1 are used to connect to the corresponding cells in the battery assembly 5. The control terminal of the charge / discharge switch circuit 4 is connected to the chip in the low-level mode of the battery protection chip 1, that is, connected to the second battery protection chip 1.

[0026] The battery assembly 5 consists of multiple cells connected in series. The charge / discharge switch circuit 4 includes a charging switch and a discharging switch (not shown in the figure). Both the charging switch and the discharging switch are MOSFETs.

[0027] As shown in Figure 1, each battery protection chip 1 includes a cell connection pin, a first charge / discharge control pin (DOIN, COIN), a second charge / discharge control pin (DO, CO), a load signal feedback pin (CHS), and a voltage detection pin (VM). The number of cell connection pins includes at least one, for example, VC1 to VCn. The first charge / discharge control pin (DOIN, COIN) includes a first charge control pin (COIN) and a first discharge control pin (DOIN), and the second charge / discharge control pin (DO, CO) includes a second charge control pin (CO) and a second discharge control pin (DO).

[0028] Specifically, the two battery protection chips 1 include a high-level side chip 2 and a low-level side chip 3.

[0029] The cell connection pins of the advanced-side chip 2 are used to connect to the first portion of the cells in the battery assembly 5. The first charge / discharge control pins (DOIN, COIN) of the advanced-side chip 2 are connected to the ground terminal via a third resistor circuit. Exemplarily, as shown in FIG2, the third resistor circuit includes a resistor RDOIN2, with the first charge control pin COIN and the first discharge control pin DOIN connected to the first end of the resistor RDOIN2, and the second end of the resistor RDOIN2 connected to the ground terminal. The voltage detection pin VM of the advanced-side chip 2 is connected to the load signal feedback pin CHS of the low-level chip 3 via a second resistor circuit. The second charge / discharge control pins (DO, CO) of the advanced-side chip 2 are connected to the first charge / discharge control pins (DOIN, COIN) of the low-level chip 3 via a first resistor circuit. Exemplarily, the first resistor circuit includes resistors RCOIN and RDOIN, with the second charge control pin CO of the advanced-side chip 2 connected to the first charge control pin COIN of the low-level chip 3 via resistor RCOIN, and the second discharge control pin DO of the advanced-side chip 2 connected to the first discharge control pin DOIN of the low-level chip 3 via resistor RDOIN.

[0030] The cell connection pin of the low-level chip 3 is used to connect to the second part of the cells in the battery assembly 5. The voltage detection pin VM of the low-level chip 3 is connected to the charge / discharge connection interface and is used to detect the presence of a charger or load. The second charge / discharge control pins (DO, CO) of the low-level chip 3 are connected to the control terminals of the charge / discharge switch circuit 4. For example, the second charge control pin CO of the low-level chip 3 is connected to the charge switch transistor, and the second discharge control pin DO of the low-level chip 3 is connected to the discharge switch transistor.

[0031] In one embodiment, the battery protection chip 1 integrates a cascade level detection circuit 11 and a charge / discharge control circuit 12. The cascade level detection circuit 11 is connected to a first charge / discharge control pin (DOIN, COIN) and is used to determine whether the current operation is in high-side mode or low-side mode based on the input level on the first charge / discharge control pin (DOIN, COIN). The charge / discharge control circuit 12 is connected to the cascade level detection circuit 11, the cell connection pin, the first charge / discharge control pin (DOIN, COIN), the second charge / discharge control pin (DO, CO), the load signal feedback pin CHS, and the voltage detection pin VM. The charge / discharge control circuit 12 is configured to, in high-side mode, based on the cell connection pin... The first input signal of the cell status and / or voltage detection pin VM detected by the cell connection pin generates a first control signal and outputs it through the second charge / discharge control pin (DO, CO); the charge / discharge control circuit 12 is also configured to generate a second control signal and output it through the second charge / discharge control pin (DO, CO) based on the cell status detected by the cell connection pin and / or the second input signal of the first charge / discharge control pin (DOIN, COIN) in low-level side mode, and generate a load feedback signal and output it through the load signal feedback pin CHS based on the third input signal of the voltage detection pin VM.

[0032] As an example, the cascade level detection circuit 11 is directly connected to the first charge / discharge control pin (DOIN, COIN). By detecting the static DC level or configuration status on the first charge / discharge control pin (DOIN, COIN), the position of the battery protection chip 1 in the cascade system is determined.

[0033] In practical implementation, when the resistor RDOIN2 in the third resistor circuit of the first charge / discharge control pin (DOIN, COIN) of battery protection chip 1 is forcibly pulled down to ground, the cascaded level detection circuit 11 will detect this low level, for example, close to 0V, and determine that battery protection chip 1 should operate in advanced side mode. At this time, battery protection chip 1 identifies itself as the signal initiator and upstream of logic control.

[0034] Conversely, for the low-level chip 3, its first charge / discharge control pin (DOIN, COIN) is connected to the second charge / discharge control pin (DO, CO) of the high-level chip through a first resistor circuit. The level state of the first charge / discharge control pin (DOIN, COIN) of the low-level chip 3 is dynamically controlled by the high-level chip 2 and is not fixedly pulled low. When the cascade level detection circuit 11 detects that its first charge / discharge control pin (DOIN, COIN) is not forcibly pulled low to ground externally, i.e., it is in a floating state or can be driven by the high-level chip 2, it determines that the battery protection chip 1 should work in low-level mode. At this time, the battery protection chip 1 identifies itself as the signal receiver and the controller of the charge / discharge switch circuit 4.

[0035] The output signal of the cascaded level detection circuit 11 is provided to the charge and discharge control circuit 12 inside the battery protection chip 1 to configure the path of its internal data flow and control logic.

[0036] In one embodiment, the charge / discharge control circuit 12 includes a cell detection circuit 121, a voltage source circuit 122, a charge / discharge drive circuit 123, a voltage detection circuit 124, a load signal feedback circuit 125, and a logic processing circuit 126.

[0037] Specifically, the cell detection circuit 121 is connected to the cell connection pin and the logic processing circuit 126 to detect the cell status. For example, the cell status includes the cell's voltage, temperature, etc., to determine the overcharge or over-discharge state of a single cell.

[0038] As an example, voltage source circuit 122 is used to provide a stable internal voltage signal. This voltage signal can be used as a bias signal. Voltage source circuit 122 includes a first output terminal VCCL, a second output terminal V4V, a third output terminal VBN, and a fourth output terminal VBP, which are used to output different voltage signals, such as VCCL, V4V, VBN, and VBP in Figures 2 to 5.

[0039] As an example, the charge / discharge drive circuit 123 is connected to the voltage source circuit 122, the first charge / discharge control pins (DOIN, COIN), and the logic processing circuit 126. In low-level mode, it outputs a charge / discharge drive signal based on the voltage signal and the second input signal of the first charge / discharge control pins (DOIN, COIN). As shown in Figures 2 and 3, the charge / discharge drive circuit 123 includes two drive circuits, which process the charging control signal and the discharging control signal, respectively. One drive circuit is connected to the voltage source circuit 122, the first charging control pin, and the logic processing circuit 126; the other drive circuit is connected to the voltage source circuit 122, the first discharging control pin, and the logic processing circuit 126. The specific structure of each drive circuit includes a first PMOS transistor Q1, a second PMOS transistor Q5, a first NMOS transistor Q2, a second NMOS transistor Q3, a third NMOS transistor Q4, and a Schmitt trigger. Taking the charging control path on the left side of Figure 3 as an example, the drain of the first PMOS transistor Q1 is connected to the first charging control pin COIN, and the gate is connected to the first output terminal VCCL of the voltage source circuit 122. The source of the first PMOS transistor Q1 is connected to the drain of the first NMOS transistor Q2. The gate of the first NMOS transistor Q2 is connected to the second output terminal V4V of the voltage source circuit 122. The source of the first NMOS transistor Q2 is connected to the drain of the second NMOS transistor Q3. The gate of the second NMOS transistor Q3 is connected to the third output terminal VBN of the voltage source circuit 122, and the source is connected to the ground terminal. The drain of the second PMOS transistor Q5 is connected to the second output terminal V4V of the voltage source circuit 122, the gate of the second PMOS transistor Q5 is connected to the fourth output terminal VBP of the voltage source circuit 122, and the source of the second PMOS transistor Q5 is connected to the drain of the third NMOS transistor Q4. The gate of the third NMOS transistor Q4 is connected to the connection node (point A) between the first NMOS transistor Q2 and the second NMOS transistor Q3, and the source of the third NMOS transistor Q4 is connected to ground. The input terminal of the Schmitt trigger is connected to the connection node (point B) between the second PMOS transistor Q5 and the third NMOS transistor Q4, and the output terminal is connected to the logic processing circuit 126, outputting a charge / discharge drive signal. In this example, in low-level side mode, the charge / discharge drive circuit 123 performs level conversion and shaping based on the level change of the second input signal from the high-level side chip 2, namely the first charge / discharge control pin (DOIN, COIN), and outputs the charge / discharge drive signal to the logic processing circuit 126.

[0040] As an example, voltage detection circuit 124 is connected to voltage detection pin VM and logic processing circuit 126 to output a voltage detection signal based on a first input signal or a third input signal. For example, voltage detection circuit 124 outputs a voltage detection signal to logic processing circuit 126 based on the first input signal of voltage detection pin VM in high-side mode, which comes from load feedback of low-side chip 3, or based on the third input signal of voltage detection pin VM in low-side mode, which is used to detect load or charger.

[0041] As an example, the load signal feedback circuit 125 is connected to the voltage source circuit 122, the load signal feedback pin CHS, and the logic processing circuit 126. Under the control of the logic processing circuit 126, it outputs a load feedback signal based on the voltage signal. As shown in Figure 3, the load signal feedback circuit 125 includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fourth NMOS transistor is connected to the load signal feedback pin CHS, its gate is connected to the second output terminal of the voltage source circuit 122, and its source is connected to the drain of the fifth NMOS transistor. The gate of the fifth NMOS transistor is connected to the logic processing circuit 126, and its source is connected to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the third output terminal of the voltage source circuit 122, and its source is connected to ground. In this embodiment, under the control of the logic processing circuit 126, the load signal feedback circuit 125 pulls the load signal feedback pin CHS low based on the voltage signal, outputting a load feedback signal to the voltage detection pin VM of the advanced-side chip 2.

[0042] As an example, the logic processing circuit 126 is connected to the second charge / discharge control pins (DO, CO) for overall protection logic judgment and timing control. Its operating mode is controlled by the mode signal output by the cascaded level detection circuit 11. The logic processing circuit 126 is configured to, in high-level side mode, shield the charge / discharge drive signal, generate a first control signal based on the cell status detected by the cell detection circuit 121 and / or the voltage detection signal output by the voltage detection circuit 124, and output it through the second charge / discharge control pins (DO, CO); in low-level side mode, based on the cell status detected by the cell detection circuit 121 and / or the charge / discharge drive signal output by the charge / discharge drive circuit 123, generate a second control signal based on the cell status detected by the cell detection circuit 121 and / or the charge / discharge drive signal output by the charge / discharge drive circuit 123, and output it through the second charge / discharge control pins (DO, CO), and control the load signal feedback circuit 125 to output a load feedback signal based on the voltage detection signal output by the voltage detection circuit 124. For example, as shown in Figures 3 to 5, the logic processing circuit 126 is connected to two driving circuits via CO_H2L and DO_H2L respectively, and is connected to the load signal feedback circuit 125 via Det_load.

[0043] Specifically, in high-side mode, the logic processing circuit 126 receives a high-side identifier from the cascaded level detection circuit 11 and accordingly masks the signal input from the internal charge / discharge drive circuit 123 of the chip. The logic processing circuit 126 mainly generates a first control signal based on the state of the battery cell it is responsible for, detected by the cell detection circuit 121, and the voltage detection signal output by the voltage detection circuit 124, and outputs it through its second charge / discharge control pin (DO, CO). This first control signal is used to drive the downstream low-side chip 3.

[0044] In low-level side mode, the logic processing circuit 126 receives the low-level side identifier. At this time, it makes a judgment based on two main inputs: first, the state of the cell it is responsible for, detected by the cell detection circuit 121; and second, the charge / discharge drive signal output by the charge / discharge drive circuit 123. After combining this information, the logic processing circuit 126 generates a second control signal and outputs it through its second charge / discharge control pins (DO, CO). This signal directly controls the gate of the external charge / discharge switch MOSFET, achieving the final shutdown of the charge / discharge path. Simultaneously, in low-level side mode, the logic processing circuit 126 also controls the load signal feedback circuit 125 to operate based on the voltage detection signal output by the voltage detection circuit 124, outputting a load feedback signal to the high-level side chip 2.

[0045] In one embodiment, the working principle is illustrated using over-discharge protection as an example: When the system is powered on, after a preset time, the high-side chip 2, through its cascade level detection circuit 11, detects that its first charge / discharge control pin (DOIN, COIN) is pulled low by the pull-down resistor circuit, thus establishing high-side mode. The low-side chip 3, through its cascade level detection circuit 11, detects that its first charge / discharge control pin (DOIN, COIN) is not forcibly pulled low, thus establishing low-side mode.

[0046] The cell detection circuit 121 of the advanced-side chip 2 detects that the voltage of a certain cell it monitors is lower than the over-discharge threshold. Based on this, the logic processing circuit 126 of the advanced-side chip 2 generates a first control signal to control its second charge / discharge control pin (DO, CO) to change from high level to low level.

[0047] The low-level first control signal serves as the second input signal, transmitted to the first discharge control pin of the low-level chip 3 via the first resistor circuit. The charge / discharge drive circuit 123 of the low-level chip 3 detects the change in the level of this pin, processes it, and outputs a high-level drive signal to the logic processing circuit 126 of the low-level chip 3.

[0048] Upon receiving the drive signal, the logic processing circuit 126 of the low-level chip 3 generates a second control signal, causing its second charge / discharge control pins (DO, CO) to output a low level, thus turning off the discharge switch. Simultaneously, if a load is present, the voltage detection circuit 124 of the low-level chip 3 detects the third input signal through its voltage detection pin VM. The logic processing circuit 126 then outputs a control signal, causing the load signal feedback circuit 125 to pull the load signal feedback pin CHS low.

[0049] The low level of the load signal feedback pin CHS serves as the first input signal, which is transmitted to the voltage detection pin VM of the advanced-side chip 2 via the second resistor circuit. Based on this, the voltage detection circuit 124 and logic processing circuit 126 of the advanced-side chip 2 determine the presence of the load, enter the load lockout state, and maintain the output of the second charge / discharge control pin (DO, CO) at a low level until the cell voltage recovers and the load is removed.

[0050] In this embodiment, by integrating the cascade level detection circuit 11 into a single chip, it can automatically identify the high-level or low-level operating mode based on the level of the first charge / discharge control pin (DOIN, COIN), and configure the signal processing path of the internal charge / discharge control circuit 12 accordingly in this mode. Thus, when building a cascaded system, only a very small number of external resistors are needed to achieve reliable protection. This not only significantly reduces the number of peripheral devices, lowers hardware costs and circuit design complexity, but also allows the same model of chip to be used in both cascaded and non-cascaded scenarios, significantly simplifying the customer's material preparation and application design.

[0051] Furthermore, by integrating key signal interface modules such as the charge / discharge drive circuit 123 and the load signal feedback circuit 125 into the chip and cooperating with the corresponding pins, reliable protection can be achieved with only three external resistors when building a cascaded system. This not only significantly reduces the number of peripheral devices, lowers hardware costs and circuit design complexity, but also significantly simplifies the customer's material preparation process.

[0052] In other embodiments, more than two identical battery protection chips 1 can be cascaded to form a multi-level cascaded system to protect a larger number of battery cells. In this case, the intermediate level chip receives signals from the previous level through its first charge / discharge control pin (DOIN, COIN) and outputs signals to the next level through its second charge / discharge control pin (DO, CO). Its operating mode logic needs to be expanded accordingly.

[0053] In an alternative, the cascaded level detection circuit 11 can also have its operating mode set via a dedicated mode selection pin.

[0054] The first resistor circuit, the second resistor circuit, and the third resistor circuit may each contain one or more resistors, the resistance values ​​of which can be selected according to specific application requirements.

[0055] The present invention also provides an electronic device, such as an electric bicycle, power tool, energy storage power supply, uninterruptible power supply, etc., which includes the above-mentioned cascaded battery protection circuit, thereby obtaining a highly integrated, low-cost, and highly reliable battery protection function.

[0056] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A battery protection chip, characterized in that, The battery protection chip includes a cell connection pin, a first charge / discharge control pin, a second charge / discharge control pin, a load signal feedback pin, and a voltage detection pin; as well as a cascaded level detection circuit and a charge / discharge control circuit integrated within the chip. The cell connection pin is used to connect at least one cell. The cascaded level detection circuit is connected to the first charge / discharge control pin and is used to determine whether the current operating mode is high-side or low-side based on the input level on the first charge / discharge control pin. The charge / discharge control circuit is connected to the cascaded level detection circuit, the cell connection pin, the first charge / discharge control pin, the second charge / discharge control pin, and the load signal feedback pin. The circuit is connected to the voltage detection pin. The charge / discharge control circuit is configured in the high-side mode to generate a first control signal based on the cell state detected by the cell connection pin and / or the first input signal of the voltage detection pin, and output it through the second charge / discharge control pin. The charge / discharge control circuit is also configured in the low-side mode to generate a second control signal based on the cell state detected by the cell connection pin and / or the second input signal of the first charge / discharge control pin, and output it through the second charge / discharge control pin, and generate a load feedback signal based on the third input signal of the voltage detection pin, and output it through the load signal feedback pin.

2. The battery protection chip according to claim 1, characterized in that, The charge / discharge control circuit includes a cell detection circuit, a voltage source circuit, a charge / discharge drive circuit, a voltage detection circuit, a load signal feedback circuit, and a logic processing circuit. The cell detection circuit is connected to the cell connection pin and the logic processing circuit to detect the cell status. The voltage source circuit provides a voltage signal. The charge / discharge drive circuit is connected to the voltage source circuit, the first charge / discharge control pin, and the logic processing circuit, and outputs a charge / discharge drive signal based on the voltage signal and a second input signal from the first charge / discharge control pin in the low-level side mode. The voltage detection circuit is connected to the voltage detection pin and the logic processing circuit, and outputs a voltage detection signal based on the first input signal or the third input signal. The load signal feedback circuit is connected to the voltage source circuit and the load signal feedback circuit. The pin is connected to the logic processing circuit and is used to output the load feedback signal according to the voltage signal under the control of the logic processing circuit; the logic processing circuit is connected to the second charge / discharge control pin and is used to shield the charge / discharge drive signal in the high-level side mode, generate a first control signal based on the cell state detected by the cell detection circuit and / or the voltage detection signal output by the voltage detection circuit, and output it through the second charge / discharge control pin; in the low-level side mode, generate a second control signal based on the cell state detected by the cell detection circuit and / or the charge / discharge drive signal output by the charge / discharge drive circuit, output it through the second charge / discharge control pin, and control the load signal feedback circuit to output the load feedback signal based on the voltage detection signal output by the voltage detection circuit.

3. The battery protection chip according to claim 2, characterized in that, The first charge / discharge control pin includes a first charge control pin and a first discharge control pin; the charge / discharge drive circuit includes two drive circuits; one drive circuit is connected to the voltage source circuit, the first charge control pin and the logic processing circuit; the other drive circuit is connected to the voltage source circuit, the first discharge control pin and the logic processing circuit.

4. The battery protection chip according to claim 3, characterized in that, The driving circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a Schmitt trigger. The drain of the first PMOS transistor is connected to the first charging control pin or the first discharging control pin. The gate of the first PMOS transistor is connected to the first output terminal of the voltage source circuit. The source of the first PMOS transistor is connected to the drain of the first NMOS transistor. The gate of the first NMOS transistor is connected to the second output terminal of the voltage source circuit. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the third output terminal of the voltage source circuit. The source of the second NMOS transistor is connected to ground; the drain of the second PMOS transistor is connected to the second output terminal of the voltage source circuit; the gate of the second PMOS transistor is connected to the fourth output terminal of the voltage source circuit; the source of the second PMOS transistor is connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor is connected to the connection node between the first NMOS transistor and the second NMOS transistor; and the source of the third NMOS transistor is connected to ground. The input of the Schmitt trigger is connected to the connection node between the second PMOS transistor and the third NMOS transistor, and the output of the Schmitt trigger is connected to the logic processing circuit.

5. The battery protection chip according to claim 2, characterized in that, The load signal feedback circuit includes a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The drain of the fourth NMOS transistor is connected to the load signal feedback pin, the gate of the fourth NMOS transistor is connected to the second output terminal of the voltage source circuit, the source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the logic processing circuit, the source of the fifth NMOS transistor is connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is connected to the third output terminal of the voltage source circuit, and the drain of the sixth NMOS transistor is connected to the ground terminal.

6. A cascaded battery protection circuit, characterized in that, The battery assembly includes a battery module, a charge / discharge switch circuit, and at least two battery protection chips as described in any one of claims 1 to 5; the charge / discharge switch circuit is connected in series between the battery module and the charge / discharge interface; at least two of the battery protection chips are connected in series; the cell connection pin of each of the battery protection chips is used to connect to the battery module; the battery module includes multiple cells; the control terminal of the charge / discharge switch circuit is connected to the lower-level chip of at least two of the battery protection chips.

7. The cascaded battery protection circuit according to claim 6, characterized in that, The two battery protection chips include a high-level side chip and a low-level side chip; the first charge / discharge control pin of the high-level side chip is used to connect to the ground terminal, the voltage detection pin of the high-level side chip is connected to the load signal feedback pin of the low-level side chip, the second charge / discharge control pin of the high-level side chip is connected to the first charge / discharge control pin of the low-level side chip, the voltage detection pin of the low-level side chip is connected to the charge / discharge connection interface, and the second charge / discharge control pin of the low-level side chip is connected to the charge / discharge switch circuit.

8. The cascaded battery protection circuit according to claim 7, characterized in that, The cascaded battery protection circuit further includes a first resistor circuit and a second resistor circuit; the first end of the first resistor circuit is connected to the second charge / discharge control pin of the advanced-side chip, and the second end of the first resistor circuit is connected to the first charge / discharge control pin of the low-side chip; the first end of the second resistor circuit is connected to the voltage detection pin of the advanced-side chip, and the second end of the second resistor circuit is connected to the load signal feedback pin of the low-side chip.

9. The cascaded battery protection circuit according to claim 7, characterized in that, The cascaded battery protection circuit also includes a third resistor circuit; the first end of the third resistor circuit is connected to the first charge / discharge control pin of the advanced side chip, and the second end of the third resistor circuit is connected to the ground terminal.

10. An electronic device, characterized in that, Includes the cascaded battery protection circuit as described in any one of claims 6 to 9.

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