System-level electrostatic discharge protection circuit, integrated circuit chip and electronic equipment

Abstract

The invention discloses a system-level electrostatic discharge protection circuit, an integrated circuit chip and electronic equipment. The circuit includes a protected circuit unit connected between first and second power supply terminals. In a system-level static test mode, the unit receives a fixed level enable signal to turn on the internal transistor. The circuit also includes at least one current limiting resistive element connected in series in a source or drain path of the transistor. When electrostatic discharge occurs, the current-limiting resistor increases the impedance of a discharge path flowing through the conduction transistor to limit the current and promote the current to preferentially flow to the ESD clamping circuit connected in parallel. According to the invention, internal small-size devices are prevented from being burnt out, and the antistatic capability is improved; the integrated circuit chip and the electronic equipment both comprise the protection circuit.

Description

A system-level electrostatic discharge protection circuit, integrated circuit chip, and electronic device Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a system-level electrostatic discharge protection circuit, an integrated circuit chip, and an electronic device. Background Technology

[0002] As semiconductor processes continue to shrink, the gate oxide layer of internal devices on integrated circuit chips is becoming thinner and the channel length is becoming shorter, leading to a significant decrease in their electrostatic discharge (ESD) immunity. To prevent ESD damage, existing chip designs typically incorporate ESD clamping circuits (ESDClamp) between power rails, utilizing their low impedance characteristics under high current to discharge ESD energy and protect the core circuitry. However, during system-level ESD testing (e.g., IEC 61000-4-2 standard testing), the chip is often in a specific operating mode or standby state. For certain internally protected circuit units (such as inverters, buffers, or logic gates), their inputs (e.g., the enable pin EN) are typically configured to receive a fixed level signal (logic "0" or logic "1") in such tests.

[0003] In existing technologies, this fixed-level input results in a specific electrical connection state within the control circuit, directly exposing fragile, small-sized internal components to the ESD impact path.

[0004] The first scenario: As shown in Figure 1, when the EN terminal is fixed with a "0" (low level) input, the internal P-type transistor (Mp1) is turned on, and the N-type transistor (Mn1) is turned off. Its equivalent circuit is shown in Figure 2. At this time, although Mn1 is in the off state, because Mp1 is turned on, the drain of Mn1 is actually connected to the first power supply terminal (Power) with low impedance through Mp1. When an ESD pulse enters from the power supply terminal or I / O terminal, because Mn1 is typically an internal logic device, extremely small in size, and not designed according to ESD layout rules (no ballast resistor), it is more prone to breakdown and conduction than a parallel ESD clamping circuit. As a result, the ESD current preferentially flows through the turned-on Mp1 to Mn1, causing it to break down and burn out.

[0005] The second scenario: As shown in Figure 3, when the EN terminal is fixed with a "1" (high level), the internal P-type transistor (Mp1) is cut off, and the N-type transistor (Mn1) is turned on. Its equivalent circuit is shown in Figure 4. At this time, although Mp1 is in the off state, because Mn1 is turned on, the drain of Mp1 is connected to ground (or the second power supply terminal). Similarly, Mp1 directly bears the high-voltage ESD stress from the power supply terminal. Since Mp1 is also a small internal device and has no ESD layout rules, it often fails before the ESD clamping circuit, causing current to preferentially flow through Mp1 and burn it out.

[0006] Therefore, there is an urgent need in the existing technology for a solution that can effectively address the problem of small-sized internal logic devices (whether due to conduction or breakdown) burning out due to system-level ESD impacts under fixed input test conditions. Summary of the Invention

[0007] In view of this, one of the objectives of the present invention is to provide a system-level electrostatic discharge protection circuit to solve the problems mentioned in the background art.

[0008] The second objective of this invention is to provide an integrated circuit chip;

[0009] The third objective of this invention is to provide an electronic device.

[0010] To achieve the aforementioned primary objective, the present invention provides the following technical solution:

[0011] A system-level electrostatic discharge (ESD) protection circuit includes: a protected circuit unit connected between a first power supply terminal and a second power supply terminal; the protected circuit unit includes at least one first conductivity type transistor and at least one second conductivity type transistor connected in a logic gate structure; wherein the protected circuit unit is configured to receive a fixed-level enable signal in a system-level ESD test mode, causing at least one of the first conductivity type transistor or the second conductivity type transistor to be in a conducting state, thereby constituting a transistor in a conducting state; the protection circuit further includes at least one current-limiting resistor element, the current-limiting resistor element being connected in series at at least one of the following locations:

[0012] (a) Between the source of the first conductivity type transistor and the first power supply terminal; (b) Between the drain of the first conductivity type transistor and the signal output terminal of the protected circuit unit; (c) Between the drain of the second conductivity type transistor and the signal output terminal of the protected circuit unit; (d) Between the source of the second conductivity type transistor and the second power supply terminal.

[0013] The current-limiting resistor element is configured to increase the discharge path impedance through the transistor in the on state when a system-level electrostatic discharge event occurs, thereby limiting the discharge current.

[0014] Based on the above technical solution, it can be seen that this invention effectively solves the problem of easily burning out internal transistors due to the fixed input level causing them to be in a conducting state during system-level electrostatic discharge (ESD) testing by connecting a current-limiting resistor element in series in the transistor path (such as the source or drain) of the protected circuit unit. Its beneficial effect is that the current-limiting resistor element significantly increases the discharge path impedance flowing through the conducting transistor, thereby limiting the peak current flowing through the fragile logic device. According to the current shunting principle, this forces most of the ESD energy to be discharged through the parallel ESD clamping circuit (ESDClamp), preventing thermal failure of small internal devices due to current overload, and significantly improving the chip's anti-static reliability in specific operating modes.

[0015] As a further embodiment of the present invention: when the enable signal is low, the first conductivity type transistor is in the on state, and the current limiting resistor element is connected in series between the source of the first conductivity type transistor and the first power supply terminal, and / or connected in series between the drain of the first conductivity type transistor and the signal output terminal.

[0016] As a further embodiment of the present invention: when the enable signal is high, the second conductivity type transistor is in the on state, and the current limiting resistor element is connected in series between the source of the second conductivity type transistor and the second power supply terminal, and / or connected in series between the drain of the second conductivity type transistor and the signal output terminal.

[0017] As a further aspect of the present invention: the first conductivity type transistor and the second conductivity type transistor are internal logic circuit transistors. The internal logic circuit transistors do not adopt electrostatic discharge layout rules in their layout design, that is, they do not use layout techniques such as silicide blocking or drain ballast stretching to increase the device area, and their channel size is smaller than the size of the input / output drive transistors.

[0018] As a further aspect of the present invention: the current-limiting resistor element is selected from at least one of polysilicon resistors, diffusion resistors, metal thin film resistors, metal wire parasitic resistance, or metal oxide semiconductor devices operating in the linear region.

[0019] As a further embodiment of the present invention: the protection circuit further includes an ESD clamping circuit connected in parallel between the first power supply terminal and the second power supply terminal, wherein the resistance value of the current limiting resistor element is configured such that, in an electrostatic discharge event, the voltage drop on the current path flowing through the transistor in the on state reaches the trigger voltage of the ESD clamping circuit, thereby causing the ESD clamping circuit to turn on before the transistor in the on state experiences thermal failure.

[0020] To achieve the second objective mentioned above, the present invention provides an integrated circuit chip including the aforementioned system-level electrostatic discharge protection circuit.

[0021] To achieve the third objective mentioned above, the present invention provides an electronic device including the aforementioned integrated circuit chip, wherein the electronic device is selected from a battery management system, a photovoltaic inverter controller, a new energy vehicle electronic control unit, or an industrial control terminal. Attached Figure Description

[0022] Figure 1 is a schematic diagram of the circuit structure of a typical control circuit unit in the prior art;

[0023] Figure 2 is a schematic diagram of the equivalent circuit and current discharge path of the circuit shown in Figure 1 under the system-level electrostatic discharge test mode when receiving a fixed low-level enable signal (showing the risk of Mn1 failure).

[0024] Figure 3 is a schematic diagram of the circuit structure of another typical control circuit unit in the prior art;

[0025] Figure 4 shows the equivalent circuit and current discharge path of the circuit shown in Figure 3 under the system-level electrostatic discharge test mode when receiving a fixed high-level enable signal (showing the risk of Mp1 failure).

[0026] Figure 5 is a schematic diagram of the system-level electrostatic discharge protection circuit provided in Embodiment 1 of the present invention (for low-level input mode).

[0027] Figure 6 is a schematic diagram of the system-level electrostatic discharge protection circuit provided in Embodiment 2 of the present invention (for high-level input mode).

[0028] The correspondence between the labels and component names in the attached figures is as follows:

[0029] 11. First conductivity type transistor; 12. Second conductivity type transistor; 21. Pull-up control transistor; 22. Pull-down control transistor; 31. First ESD discharge element; 32. Second ESD discharge element; 4. ESD clamping circuit; 5. Internal functional circuit. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] As shown in Figures 1 and 3, a traditional electrostatic discharge protection circuit includes a protected circuit unit, which comprises a first conductivity type transistor 11 (e.g., a P-type field-effect transistor Mp1) and a second conductivity type transistor 12 (e.g., an N-type field-effect transistor Mn1) that are complementaryly connected. These transistors are connected between a first power supply terminal (e.g., VDD / Power) and a second power supply terminal (e.g., VSS / Ground) to form logic gate structures such as inverters or buffers.

[0032] Referring to Figure 1, the protected circuit unit also includes a pull-up control transistor 21 (e.g., a P-type transistor Mp2) connected between the first power supply terminal and the common gate terminal of Mp1 / Mn1 (node ​​X), whose gate is controlled by a first control signal (ENB).

[0033] Referring to Figure 3, another form of the protected circuit unit also includes a pull-down control transistor 22 (e.g., an N-type transistor Mn2) connected between the second power supply terminal and the common gate terminal of Mp1 / Mn1 (node ​​X), whose gate is controlled by a second control signal (ENB).

[0034] In addition, as a basic protection for the chip's input / output ports, the protection circuit also includes primary electrostatic discharge elements (first ESD discharge element 31 and second ESD discharge element 32) connected to the signal input / output pads (PADs). Specifically, the first ESD discharge element 31 (illustrated as ESD1) is connected between the pad and the first power terminal (Power) to discharge positive ESD pulses; the second ESD discharge element 32 (illustrated as ESD2) is connected between the pad and the second power terminal (Ground) to discharge negative ESD pulses. ESD1 and ESD2 are typically composed of diodes, diode-connected MOSFETs, or silicon controlled rectifiers (SCRs).

[0035] It should be noted that the aforementioned protection circuit is connected to the chip's internal functional circuit 5 (represented by the "control circuit" block in the diagram). This internal functional circuit 5 is connected to the signal input / output terminal via an input resistor and is used to process core logic signals. It does not fall within the scope of the electrostatic discharge path that is the main improvement of this invention.

[0036] This invention addresses the specific problem of device failure during system-level ESD testing. In such tests, the signal input (EN) typically receives a fixed voltage level. Failure mechanism analysis:

[0037] Referring to Figure 2, the first failure scenario is illustrated. When the EN terminal is fixed with a "0" (low level) input, Mp1 is in the ON state, and Mn1 is in the OFF state. At this time, Mp1 forms a low-impedance path from the power supply terminal to node X / output terminal in the equivalent circuit, directly conducting the power supply voltage to the drain of Mn1. Since Mn1 is a small internal device, it lacks ESD protection capabilities. Under high-voltage ESD pulses, Mn1 is highly susceptible to drain-substrate breakdown or parasitic bipolar junction transistor (BJT) conduction. Once Mn1 breaks down, the ESD current will form a discharge path of "power supply → Mp1 → Mn1 → ground", causing Mn1 to overheat and burn out instantly (as shown by the explosion symbol in Figure 2).

[0038] Referring to Figure 4, the second failure scenario is illustrated. When the EN terminal is fixed with a "1" (high level), Mp1 is in the OFF state, and Mn1 is in the ON state. At this time, Mn1 pulls the drain of Mp1 low to ground potential in the equivalent circuit. When an ESD pulse is applied to the power supply, a huge voltage drop is directly applied across the source and drain of Mp1. Similarly, since Mp1 is a fragile internal logic device, it is more prone to breakdown or failure than the external main ESD clamping circuit 4. In this case, the ESD current will preferentially flow through the path "power supply → Mp1 → Mn1 → ground," causing Mp1 to burn out (as shown by the explosion symbol in Figure 4).

[0039] To address the above problems, the present invention proposes the following embodiments.

[0040] Example 1

[0041] As shown in Figure 5, this embodiment illustrates a protection structure for a low-level input mode (corresponding to the failure scenario in Figure 2). In the circuit structure of this embodiment, the control circuit includes an auxiliary pull-up transistor (Mp2), whose source is connected to the first power supply terminal, and its drain is connected to node X (i.e., the gates of Mp1 and Mn1), with the gate connected to the signal ENB. In test mode, in conjunction with a low-level input to the EN terminal, Mp2 is in the off state (or in a specific state according to logic), causing node X to remain at a low level, thereby turning on Mp1 and turning off Mn1.

[0042] In the circuit structure of this embodiment, in order to prevent ESD current from breaking down and flowing through the vulnerable Mn1 (and the current-carrying Mp1), the present invention configures current-limiting resistor elements at the critical path nodes A, B, C, and D of the protected circuit unit.

[0043] The specific connection relationship is as follows: Node A (source side): A current-limiting resistor is connected in series between the source of Mp1 and the first power supply terminal. Here, the series resistor not only limits the peak current but also acts as a source degradation mechanism, raising the source potential and reducing the gate-source voltage when a large ESD current flows. ), to prevent gate oxide breakdown.

[0044] Node B (Drain Side): A current-limiting resistor is connected in series between the drain of Mp1 and the signal output terminal. The resistor at this location is mainly used to increase the discharge path impedance through the drain of Mp1, thereby limiting the ESD current flowing through the Mp1 channel, and using the voltage drop across the resistor to force the ESD energy to be discharged mainly through the parallel ESD clamping circuit 4.

[0045] Node C (Drain side): A current-limiting resistor is connected in series between the drain of Mn1 and the signal output terminal. The resistor at this location directly increases the impedance of the discharge path, forcing the current to be diverted to the parallel ESD clamping circuit 4 path.

[0046] Node D (Source side): In the topology shown in Figure 5, node D can correspond to the area between the source of Mn1 and the second power supply terminal (Ground), serving as an auxiliary protection.

[0047] Based on the actual circuit performance (PPA) requirements, the designer can flexibly choose the above resistor combination method: (1) Single point configuration: connect the resistor in series at any one of nodes A, B, C or D.

[0048] (2) Multiple-point combination: Connect resistors in series at nodes A and B, or A and C, or combinations of A, B, and C. For example, if the output drive capability is required to be high, a resistor can be connected in series only at node A (source); if timing delay is not sensitive, resistors can be connected in series at nodes A and C to obtain the maximum protection effect.

[0049] In system-level ESD testing, when an electrostatic discharge event occurs, the resistor connected in series at the aforementioned locations significantly increases the overall impedance flowing through the "Mp1-Mn1" branch. According to the current shunt principle, the increased path impedance forces the majority of the ESD current to flow to the parallel-designed ESD clamping circuit 4 (ESDClamp). Furthermore, the voltage drop across the resistor reduces the voltage stress applied to vulnerable devices (such as Mn1) and facilitates faster turn-on and conduction of the ESD clamping circuit 4. In this way, the problems of Mn1 breaking down due to overvoltage or Mp1 burning out due to overcurrent are effectively avoided.

[0050] Example 2

[0051] As shown in Figure 6, this embodiment demonstrates a protection structure for the high-level input mode (corresponding to the failure scenario in Figure 4). In this mode, although Mn1 is in the conducting state, as mentioned earlier, the weakest link is often Mp1, which bears the high-voltage stress. To protect Mp1 from being burned out, this invention configures current-limiting resistor elements at critical nodes E, F, G, and H.

[0052] The specific connection is as follows: Node H (source side): A current-limiting resistor is connected in series between the source of Mn1 and the second power supply terminal (Ground / VSS). Similarly, the source degradation effect is used to protect Mn1.

[0053] Node F (drain side): A current-limiting resistor is connected in series between the drain of Mp1 and the signal output terminal. The resistor at this location is mainly used to prevent excessive current from flowing through Mp1 due to breakdown when it is subjected to high voltage stress.

[0054] Node G (drain side): A current-limiting resistor is connected in series between the drain of Mn1 and the signal output terminal. The resistance at this position significantly increases the discharge path impedance, limits the current flowing through the on-state Mn1, and forces the ESD energy to be discharged through the parallel ESD clamping circuit.

[0055] Node E (Source side): A current-limiting resistor is connected in series between the source of Mp1 and the first power supply terminal.

[0056] Similarly, the resistors at nodes E, F, G, and H can exist individually or in any combination (e.g., simultaneously at E and F, E and G, or E, F, G, and H connected in series) to block ESD current from flowing to Mn1.

[0057] When the circuit is in the high-level input state shown in Figure 4, Mp1 is easily burned out without protection. Introducing the current-limiting resistor of this invention also increases the impedance flowing through the "Mp1-Mn1" path. This not only limits the current through Mn1, but more importantly, it shares the voltage applied across Mp1, preventing destructive breakdown. By forcing the current to discharge through the main ESD clamping circuit 4, the tiny internal Mp1 transistor is protected.

[0058] The current-limiting resistor element of this invention can be selected from polysilicon resistors, diffusion resistors, metal thin-film resistors, metal wire parasitic resistance, or MOS devices operating in the linear region. Its resistance value is typically configured such that the voltage drop across the path of the on / downgraded transistor is sufficient to cause the ESD clamping circuit 4 to turn on before the internal transistor undergoes thermal burn-out.

[0059] The working mechanism of this invention is as follows:

[0060] In system-level ESD testing (e.g., according to the IEC 61000-4-2 standard), when an ESD pulse enters from the InputPAD or OutputPAD, the current is first conducted to the power rail or ground rail through the primary electrostatic discharge element. Taking a positive pulse as an example, the ESD current flows to the first power terminal via ESD1. At this time, if the current-limiting resistor of this invention is lacking, since Mp1 (when EN=0) or Mn1 (when EN=1) is in the on state and has extremely low impedance, the current introduced into the first power terminal from ESD1 will be shunted: part flows to the main ESD clamping circuit 4 (ESDClamp), and the other part will preferentially flow through these small-sized devices (Mp1 / Mn1) in the on state to reach the output terminal or ground terminal, causing them to burn out.

[0061] With the introduction of the current-limiting resistor of this invention, the impedance of the conducting branch (i.e., the path flowing through Mp1 or Mn1) increases significantly. According to the current shunting principle, the main ESD current will be forced to flow to the parallel-designed ESD clamping circuit 4 (ESDClamp). In addition, the voltage drop across the resistor can accelerate the opening of the ESD clamping circuit 4, thereby successfully dissipating ESD energy before the small-size transistor reaches the thermal failure threshold.

[0062] The system-level ESD protection circuit provided by this invention is particularly suitable for the new energy industry, where reliability requirements are extremely high.

[0063] (1) Battery Management System (BMS): This circuit can be applied to the analog front-end (AFE) control chip in the BMS. BMS often faces complex electromagnetic interference. By adding the resistor protection structure of this invention to the control logic, the failure of the BMS due to the burn-out of the control tube can be prevented during system-level electrostatic testing or actual operation, thus ensuring the safety of battery pack monitoring.

[0064] (2) Photovoltaic inverter: In the power control board of a photovoltaic inverter, the logic control unit (such as the front end of the PWM generator) is usually in a fixed-level standby state. This invention can effectively protect these internal logics from damage under outdoor lightning surges or electrostatic induction.

[0065] (3) New energy vehicle electronics: Electronic control units (ECUs) for electric vehicles (EVs) that meet the requirements of automotive-grade electronic components for high reliability ESD protection.

[0066] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A system-level electrostatic discharge protection circuit, comprising: The protected circuit unit is connected between a first power supply terminal and a second power supply terminal. The protected circuit unit includes at least one first conductivity type transistor (11) and at least one second conductivity type transistor (12) connected in a logic gate structure. The protected circuit unit is configured to receive a fixed-level enable signal in a system-level electrostatic discharge test mode, causing at least one of the first conductivity type transistor (11) or the second conductivity type transistor (12) to be in a conducting state, thereby constituting a transistor in a conducting state. The protection circuit further includes at least one current-limiting resistor element. The current-limiting resistor element is connected in series at at least one of the following locations: (a) between the source of the first conductivity type transistor (11) and the first power supply terminal; (b) between the drain of the first conductivity type transistor (11) and the signal output terminal of the protected circuit unit; (c) between the drain of the second conductivity type transistor (12) and the signal output terminal of the protected circuit unit; (d) between the source of the second conductivity type transistor (12) and the second power supply terminal; the current-limiting resistor element is configured to increase the discharge path impedance through the transistor in the on state to limit the discharge current when a system-level electrostatic discharge event occurs.

2. The system-level electrostatic discharge protection circuit as described in claim 1, characterized in that, When the enable signal is low, the first conductivity type transistor (11) is in the on state, and the current limiting resistor element is connected in series between the source of the first conductivity type transistor (11) and the first power supply terminal, and / or connected in series between the drain of the first conductivity type transistor (11) and the signal output terminal.

3. The system-level electrostatic discharge protection circuit as described in claim 1, characterized in that, When the enable signal is high, the second conductivity type transistor (12) is in the on state, and the current limiting resistor element is connected in series between the source of the second conductivity type transistor (12) and the second power supply terminal, and / or connected in series between the drain of the second conductivity type transistor (12) and the signal output terminal.

4. The system-level electrostatic discharge protection circuit as described in claim 1, characterized in that, The first conductivity type transistor (11) and the second conductivity type transistor (12) are internal logic circuit transistors. The internal logic circuit transistors do not adopt electrostatic discharge layout rules in layout design, and their channel size is smaller than that of the input / output drive transistors.

5. The system-level electrostatic discharge protection circuit as described in claim 1, characterized in that, The current-limiting resistor element is selected from at least one of polysilicon resistors, diffusion resistors, metal thin film resistors, metal wire parasitic resistance, or metal oxide semiconductor devices operating in the linear region.

6. The system-level electrostatic discharge protection circuit as described in claim 1, characterized in that, It also includes an ESD clamping circuit (4) connected in parallel between the first power supply terminal and the second power supply terminal, wherein the resistance value of the current limiting resistor element is configured such that, in an electrostatic discharge event, the voltage drop on the current path flowing through the transistor in the on state reaches the trigger voltage of the ESD clamping circuit (4), causing the ESD clamping circuit (4) to turn on before the transistor in the on state experiences thermal failure.

7. An integrated circuit chip, characterized in that, Includes a system-level electrostatic discharge protection circuit as described in any one of claims 1 to 6.

8. An electronic device, characterized in that, The electronic device includes the integrated circuit chip as described in claim 7, and is selected from a battery management system, a photovoltaic inverter controller, a new energy vehicle electronic control unit, or an industrial control terminal.

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