Center frequency reconfigurable amplitude limiting filter based on series-parallel topology

Abstract

The invention discloses a center frequency reconfigurable amplitude limiting filter based on series-parallel topology. The center frequency reconfigurable amplitude limiting filter comprises a main transmission line, a first-stage amplitude limiting circuit, a transmission line TL1, a second-stage amplitude limiting circuit, a frequency reconfigurable unit and a lumped parallel resonator, the frequency reconfigurable unit realizes working center frequency adjustability by adjusting bias voltage VDC; and the second-stage amplitude limiting circuit widens the out-of-band rejection width by introducing a transmission zero point. Compared with an existing amplitude limiting filter, the band-pass filter has the advantages that the out-of-band rejection width is remarkably improved while the frequency reconfigurable function is achieved, and the band-pass filter can be applied to a multifunctional and high-performance radio frequency front-end system.

Description

A center frequency reconfigurable limiting filter based on series-parallel topology Technical Field

[0001] This invention relates to the field of microwave passive device technology, specifically to a center frequency reconfigurable limiting filter based on a series-parallel topology. Background Technology

[0002] In recent years, with the rapid evolution of civilian wireless communication technology, a large amount of spectrum resources in free space have been occupied, and the phenomenon of spectrum congestion has become increasingly severe. Therefore, spread spectrum, frequency hopping, and dynamic frequency allocation technologies have been widely used in the design of radio frequency front-end devices to achieve efficient utilization of the electromagnetic spectrum.

[0003] As a crucial component in the RF front-end receiving link, the clipping filter not only reflects high-power microwave signals within the band to protect power-sensitive devices such as low-noise amplifiers in subsequent stages, but also effectively suppresses out-of-band interference signals, ensuring good received signal quality. Due to the miniaturization and integration trends in modern RF devices, most existing clipping filters have fixed performance characteristics, including fixed center frequency, bandwidth, and out-of-band rejection. For example, Chinese invention patent application CN114826179A, "A Millimeter-Wave Clipping Filter Chip Based on Collaborative Fusion," describes a clipping filter based on collaborative fusion that reduces insertion loss and circuit area in the RF front-end while maintaining high power capacity, but it cannot achieve center frequency reconfigurability. The traditional method for implementing a center frequency-adjustable clipping filter is to cascade an adjustable filter with a broadband clipper. This simple cascading method leads to impedance mismatch between devices, severely degrading filtering performance, such as poor out-of-band rejection and high insertion loss. Furthermore, device cascading increases circuit size and the design complexity of the RF front-end.

[0004] Therefore, in advanced RF front-ends that require dynamic adjustment of operating frequency, how to realize the reconfigurable operating frequency of integrated limiting filters and how to effectively widen the external suppression bandwidth are urgent problems to be solved. Summary of the Invention

[0005] The technical problem to be solved by this invention is: how to design an integrated amplitude limiting filter with reconfigurable center frequency and effectively improve stopband suppression performance.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a center frequency reconfigurable limiting filter based on a series-parallel topology, comprising: a main transmission line and a first-stage limiting circuit 10, a transmission line TL1, a second-stage limiting circuit 20, a frequency reconfigurable unit 30, and a lumped parallel resonator 40 connected thereon in sequence; the frequency reconfigurable unit 30 achieves adjustable operating center frequency by adjusting the bias voltage VDC; the second-stage limiting circuit 20 widens the external suppression width by introducing a transmission zero.

[0007] In this embodiment, the circuit topology of the first-stage limiting circuit 10 is symmetrical from top to bottom; two diodes D1 are stacked in series to form a limiting unit; the upper limiting circuit mainly consists of two anti-parallel limiting units connected in parallel with the spiral inductor L2, and then coupled to the transmission line TL1 through the capacitor C2; the lower limiting circuit mainly consists of two anti-parallel limiting units connected in parallel with the spiral inductor L3, and then coupled to the transmission line TL1 through the capacitor C3.

[0008] In this embodiment, the first-stage limiting circuit 10 integrates the limiting and filtering functions. In the filtering state, diode D1 is equivalent to a capacitor, and the limiting unit is also equivalent to a capacitor. The equivalent capacitance of the limiting unit and the spiral inductor form a parallel resonant circuit, generating a filter passband. The equivalent capacitance of the limiting unit, the spiral inductor, and the coupling capacitor form a series resonant circuit, introducing a transmission zero on the left side of the filter passband. The coupling capacitors C2 and C3 have different capacitance values, allowing the first-stage limiting circuit to generate two zeros. In the limiting state, diode D1 is equivalent to a resistor, and the limiting unit is also equivalent to a resistor. The impedance of the RF input port matches the detuned reflected high-power microwave input, achieving the limiting purpose.

[0009] In this embodiment, the second-stage limiting circuit 20 based on the series-parallel topology includes inductor L4, inductor L5, capacitor C4 and diode D2; inductor L5, capacitor C4 and diode D2 are connected in parallel and in series with inductor L4.

[0010] In this embodiment, in the filtering state, the inductor L4 and the equivalent capacitance of the diode D2 form a grounded series resonant circuit in the second-stage limiting circuit 20. A transmission zero is introduced on the right side of the passband to widen the stopband suppression width. The capacitor C4 is used to deepen the stopband suppression depth, and the inductor L5 is used to reduce the passband insertion loss. In the limiting state, the diode D2 is equivalent to a resistor, and the incident high-power microwave is reflected due to impedance mismatch, thus realizing the limiting function.

[0011] In this embodiment, the frequency reconfigurable unit 30 based on the equivalent series-parallel topology includes a capacitor C5, a transmission line TL2, and a diode D3 connected in series; it also includes a bias voltage source VDC, a bias resistor R1, and a bypass capacitor C6; the positive terminal of the adjustable bias voltage source VDC is connected to the anode of the diode D3 via the bias resistor R1, and the negative terminal is grounded; one end of the bypass capacitor C6 is connected to the positive terminal of the adjustable bias voltage source VDC, and the other end is grounded.

[0012] In this embodiment, the odd-numbered multiple short-circuit quarter-wavelength transmission line TL2 is equivalent to a parallel resonant circuit, which is connected in series with capacitor C5 and diode D3 (equivalent capacitance), introducing three transmission zeros. The electrical lengths of transmission line TL2 at the frequencies of the three transmission zeros are, respectively, one-quarter wavelength, three-quarter wavelength, and five-quarter wavelength. The transmission zeros from left to right are the first zero, the second zero, and the third zero. The first and second zeros are located on both sides of the passband, and the third zero is located in the high-frequency stopband. The first and second zeros control the operating center frequency, and the third zero widens the stopband suppression width.

[0013] In this embodiment, the voltage adjustment range of the bias voltage source VDC is 0.6~1.0 V, with a step of U0V; as the adjustable bias voltage VDC gradually increases from 0.6V to 1.0V, the equivalent capacitance of diode D3 gradually increases, and the three transmission zero frequencies gradually decrease; conversely, the operating center frequency can be reconfigured.

[0014] In this embodiment, capacitor C5 is connected in series with diode D3 to increase the range of variation of the equivalent capacitance value in the frequency reconfigurable unit 30 with the bias voltage VDC.

[0015] In this embodiment, the lumped parallel resonator 40 includes an inductor L6 and a capacitor C7 connected in parallel, and introduces a transmission zero at its resonant frequency, located on the right side of the filter passband, to improve stopband suppression at high frequencies.

[0016] Compared with the prior art, the beneficial effects of the present invention are: the present invention solves the problems of the non-adjustable operating frequency and narrow out-of-band suppression width when performing integrated amplitude limiting and filtering design in the prior art.

[0017] The first-stage limiting circuit of the center frequency reconfigurable limiting filter of this invention generates a passband and a transmission zero in small-signal filtering mode, realizing an integrated limiting and filtering design. The second-stage limiting circuit generates a transmission zero on the right side of the passband, widening the out-of-band rejection width. The frequency reconfigurable unit adopts an equivalent series-parallel topology, that is, the short-circuited quarter-wavelength transmission line is equivalent to a parallel resonator and is connected in series with a variable capacitance unit with a loaded diode, realizing reconfigurable operating frequency. In addition, the transmission zero generated on the right side of the passband by the frequency reconfigurable unit further optimizes the out-of-band rejection width at high frequencies.

[0018] Compared to existing clipping filters, this invention, based on a series-parallel topology design, achieves frequency reconfiguration while significantly improving out-of-band rejection, and can be applied to multifunctional, high-performance RF front-end systems. Attached Figure Description

[0019] Figure 1 is a schematic diagram of the circuit topology of a center frequency reconfigurable limiting filter based on a series-parallel topology in an embodiment of the present invention.

[0020] Figure 2 is an equivalent schematic diagram of the second-stage limiting circuit of the reconfigurable limiting filter in the filtering state in an embodiment of the present invention.

[0021] Figure 3 is a schematic diagram of the equivalent series-parallel topology of the frequency reconfigurable unit of the reconfigurable limiting filter in an embodiment of the present invention.

[0022] Figure 4 is a schematic diagram of the simulation results of the adjustable capacitor Ci1 in the frequency reconfigurable unit of the reconfigurable limiting filter in the embodiment of the present invention under different bias voltages VDC.

[0023] Figure 5 is a schematic diagram of the simulation results of the three transmission zeros introduced by the frequency reconfigurable unit of the reconfigurable limiting filter in the embodiment of the present invention under different bias voltages VDC.

[0024] Figure 6 is a schematic diagram of the simulation results of the reconfigurable limiting filter S21 parameters under different bias voltages VDC in the embodiment of the present invention.

[0025] Figure 7 is a schematic diagram of the simulation results of the S21 parameter of the reconfigurable limiting filter in the embodiment of the present invention when loading a second-stage limiting circuit with different topologies.

[0026] Figure 8 is a schematic diagram of the simulation results of the limiting characteristics of the reconfigurable limiting filter at the center frequency under different bias voltages VDC in the embodiment of the present invention. Detailed Implementation

[0027] To facilitate understanding of the technical solution of the present invention by those skilled in the art, the technical solution of the present invention will now be further described in conjunction with the accompanying drawings.

[0028] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0029] Referring to Figure 1, this invention provides a center frequency reconfigurable limiting filter based on a series-parallel topology, comprising: a main transmission line and a first-stage limiting circuit 10, a transmission line TL1, a second-stage limiting circuit 20, a frequency reconfigurable unit 30, and a lumped parallel resonator 40 connected thereon in sequence. The frequency reconfigurable unit 30 achieves adjustable operating center frequency by adjusting the bias voltage VDC, and the second-stage limiting circuit 20 widens the external suppression width by introducing a transmission zero.

[0030] In one embodiment of the present invention, the center frequency reconfigurable limiting filter further includes an input impedance matching unit and an output impedance matching unit.

[0031] In this embodiment, the input impedance matching unit is mainly composed of a grounding inductor L1 and a DC blocking capacitor C1 connected in sequence, located at the RF input terminal. in Between the first-stage limiting circuit 10 and the output impedance matching unit, which mainly includes a DC blocking capacitor C8, located between the lumped parallel resonator 40 and the RF output terminal RF. out between.

[0032] In one embodiment of the present invention, the circuit topology of the first-stage limiting circuit 10 is symmetrical, with two diodes D1 stacked in series to form a limiting unit. The upper limiting circuit mainly consists of two anti-parallel limiting units connected in parallel with a spiral inductor L2, and then coupled to the transmission line TL1 through a capacitor C2. The lower limiting circuit mainly consists of two anti-parallel limiting units connected in parallel with a spiral inductor L3, and then coupled to the transmission line TL1 through a capacitor C3.

[0033] In this embodiment, the first-stage limiting circuit 10 integrates limiting and filtering functions. In the filtering state, diode D1 is equivalent to a capacitor, and the limiting unit is also equivalent to a capacitor. The equivalent capacitance of the limiting unit and the spiral inductor form a parallel resonant circuit, generating a filter passband. The equivalent capacitance of the limiting unit, the spiral inductor, and the coupling capacitor form a series resonant circuit, introducing a transmission zero on the left side of the filter passband. The coupling capacitors C2 and C3 have different capacitance values, allowing the first-stage limiting circuit to generate two zeros. In the limiting state, diode D1 is equivalent to a resistor, and the limiting unit is also equivalent to a resistor. The impedance of the RF input port matches the detuned reflected high-power microwave input, achieving the limiting purpose.

[0034] In one embodiment of the invention, the quarter-wavelength transmission line TL1 is used as an inter-stage open / short-circuit impedance converter to improve limiting isolation.

[0035] In one embodiment of the present invention, the second-stage limiting circuit 20 based on a series-parallel topology includes an inductor L4, an inductor L5, a capacitor C4, and a diode D2. As shown in FIG2, the inductor L5, the capacitor C4, and the diode D2 are connected in parallel and in series with the inductor L4.

[0036] In this embodiment, in the filtering state, the second-stage limiting circuit 20 forms a grounded series resonant circuit with the equivalent capacitance of inductor L4 and diode D2, introducing a transmission zero on the right side of the passband to widen the stopband suppression width. Capacitor C4 is used to deepen the stopband suppression depth, and inductor L5 is used to reduce the passband insertion loss. In the limiting state, diode D2 is equivalent to a resistor, and the incident high-power microwave is reflected due to impedance mismatch, thus achieving the limiting function.

[0037] In one embodiment of the present invention, the frequency reconfigurable unit 30 based on an equivalent series-parallel topology includes a capacitor C5, a transmission line TL2, and a diode D3 connected in series, and also includes a bias voltage source VDC, a bias resistor R1, and a bypass capacitor C6; the positive terminal of the adjustable bias voltage source VDC is connected to the anode of the diode D3 via the bias resistor R1, and the negative terminal is grounded. One end of the bypass capacitor C6 is connected to the positive terminal of the adjustable bias voltage source VDC, and the other end is grounded.

[0038] In this embodiment, the odd-multiple short-circuited quarter-wavelength transmission line TL2 is equivalent to a parallel resonant circuit, which is connected in series with capacitor C5 and diode D3 (equivalent capacitance), introducing three transmission zeros. The electrical lengths of transmission line TL2 at the frequencies of the three transmission zeros are, respectively, one-quarter wavelength, three-quarter wavelength, and five-quarter wavelength. The transmission zeros, from left to right, are the first zero, the second zero, and the third zero. The first and second zeros are located on opposite sides of the passband, while the third zero is located in the high-frequency stopband. The first and second zeros control the operating center frequency, and the third zero widens the stopband suppression width.

[0039] In this embodiment, capacitor C5 is connected in series with diode D3 to increase the range of variation of the effective capacitance value of the frequency reconfigurable unit with the bias voltage VDC.

[0040] In this embodiment, the bypass capacitor C6 is used for filtering the power supply voltage, and the bias resistor R1 uses its high impedance characteristics to isolate the radio frequency signal from the DC bias, thereby reducing signal loss.

[0041] In one embodiment of the present invention, the lumped parallel resonator 40 includes an inductor L6 and a capacitor C7 connected in parallel, and introduces a transmission zero at its resonant frequency, located on the right side of the filter passband, to improve stopband suppression at high frequencies.

[0042] Please refer to Figure 3. In one embodiment of the present invention, the principle for achieving center frequency reconfigurability is as follows: the frequency reconfigurable unit 30 of the equivalent series-parallel topology includes a capacitor C5, a transmission line TL2, and a diode D3 connected in series. The odd-numbered multiple short-circuited quarter-wavelength transmission line TL2 is equivalent to a unit consisting of capacitor C5, a transmission line TL2, and a diode D3 connected in series. TL2 With inductor L TL2The parallel resonant circuit formed has an equivalent capacitance C of capacitor C5 and diode D3. D3 In series connection, the input impedance Z of the frequency reconfigurable unit 30 is... in It can be represented as: In the formula, The imaginary unit, ω is the angular frequency. When Z in When f = 0, the frequency reconfigurable unit generates a zero; the zero frequency f TZi It can be represented as: Where Z1 and θ1 are the characteristic impedance and electrical length of transmission line TL2, respectively. Pi It is the tangent function.

[0043] From the above formula, we can see that the zero-point frequency f TZi With equivalent capacitance C i1 Value related. Equivalent capacitance C i1 With diode D3 and equivalent capacitance C D3 It is related and varies with the bias voltage VDC. Therefore, the zero-point frequency f TZi It can be controlled by the bias voltage VDC.

[0044] Zero frequency f TZi It is also related to the electrical length θ1 of transmission line TL2. In this embodiment, the frequency reconfigurable unit 30 introduces three transmission zeros. The electrical lengths of transmission line TL2 at the frequencies of the three transmission zeros are, respectively, one-quarter wavelength, three-quarter wavelength, and five-quarter wavelength. The transmission zeros, from left to right, are the first zero, the second zero, and the third zero. The first and second zeros are located on both sides of the passband, and the third zero is located in the high-frequency stopband. The first and second zeros control the operating center frequency, and the third zero widens the stopband suppression width. The voltage adjustment range of the bias voltage source VDC is 0.6~1.0 V, with a step of U0V, specifically set to 0.2 V for example. As the adjustable bias voltage VDC gradually increases from 0.6V to 1.0V, the equivalent capacitance C of diode D3 increases. D3 As the frequency of the three transmission zeros gradually increases, the frequency of the three transmission zeros gradually decreases. Conversely, the frequency of the working center can be reconfigured.

[0045] As shown in Figure 4, the adjustable capacitor C in the frequency reconfigurable unit 30 i1 Simulation results under different bias voltages VDC. The figure shows the adjustable capacitor C. i1 The adjustable capacitor C in this embodiment varies with the bias voltage VDC. i1 It can be controlled by the bias voltage VDC.

[0046] Figure 5 shows the simulation results of the three transmission zeros introduced by the frequency reconfigurable unit 30 under different bias voltages VDC. The figure displays the three transmission zeros introduced by the frequency reconfigurable unit 30, and the zero-point frequencies change with the bias voltage VDC, indicating that the zero-point frequency f in this embodiment... TZ It can be controlled by the bias voltage VDC.

[0047] Figure 6 shows the simulation results of the S21 parameters of the center frequency reconfigurable limiting filter based on a series-parallel topology under different bias voltages VDC. The figure shows that the adjustable transmission zeros on both sides of the passband change with the bias voltage VDC, realizing the reconfigurable center frequency function. The rightmost adjustable transmission zero significantly widens the stopband rejection width.

[0048] Figure 7 shows the simulation results of the S21 parameters of the center frequency reconfigurable limiting filter based on a series-parallel topology when a second-stage limiting circuit with different topologies is applied. The figure shows that the second-stage limiting circuit introduces a transmission zero on the right side of the passband, effectively widening the stopband rejection width. The parallel capacitor C4 deepens the stopband rejection depth, and the parallel inductor L5 reduces the passband insertion loss.

[0049] Figure 8 shows the simulation results of the limiting characteristics of the center frequency reconfigurable limiting filter based on series-parallel topology at different bias voltages VDC. The figure shows that it has good limiting performance at the adjustable center frequencies of 9 GHz, 9.5 GHz, and 10 GHz.

[0050] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0051] The above embodiments are merely examples of implementation methods of the invention. The scope of protection of the present invention is not limited to the above embodiments. For those skilled in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A center frequency reconfigurable limiting filter based on a series-parallel topology, characterized in that, Includes: a main transmission line and a first-stage limiting circuit (10), a transmission line TL1, a second-stage limiting circuit (20), a frequency reconfigurable unit (30), and a lumped parallel resonator (40) connected thereon; the frequency reconfigurable unit (30) achieves adjustable operating center frequency by adjusting the bias voltage VDC; the second-stage limiting circuit (20) widens the external suppression width by introducing a transmission zero.

2. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 1, characterized in that, The circuit topology of the first-stage limiting circuit (10) is symmetrical from top to bottom; two diodes D1 are stacked in series to form a limiting unit; the upper limiting circuit is mainly composed of two anti-parallel limiting units connected in parallel with the spiral inductor L2, and then coupled to the transmission line TL1 through the capacitor C2; the lower limiting circuit is mainly composed of two anti-parallel limiting units connected in parallel with the spiral inductor L3, and then coupled to the transmission line TL1 through the capacitor C3.

3. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 2, characterized in that, The first-stage limiting circuit (10) realizes the integrated design of limiting and filtering functions; in the filtering state, diode D1 is equivalent to a capacitor, and the limiting unit is equivalent to a capacitor. The equivalent capacitance of the limiting unit and the spiral inductor form a parallel resonant circuit to generate a filter passband; the equivalent capacitance of the limiting unit, the spiral inductor and the coupling capacitor form a series resonant circuit to introduce a transmission zero on the left side of the filter passband; the coupling capacitors C2 and C3 have different capacitance values, and the first-stage limiting circuit can generate two zeros; in the limiting state, diode D1 is equivalent to a resistor, and the limiting unit is equivalent to a resistor. The impedance of the RF input port is matched with the detuned reflected high-power microwave input to achieve the limiting purpose.

4. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 1, characterized in that, The second-stage limiting circuit (20) based on the series-parallel topology includes inductor L4, inductor L5, capacitor C4 and diode D2; inductor L5, capacitor C4 and diode D2 are connected in parallel and in series with inductor L4.

5. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 4, characterized in that, In the filtering state, the second-stage limiting circuit (20) forms a grounded series resonant circuit with the equivalent capacitance of inductor L4 and diode D2. A transmission zero is introduced on the right side of the passband to widen the stopband suppression width. Capacitor C4 is used to deepen the stopband suppression depth, and inductor L5 is used to reduce the passband insertion loss. In the limiting state, diode D2 is equivalent to a resistor. The incident high-power microwave is reflected due to impedance mismatch, thus realizing the limiting function.

6. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 1, characterized in that, The frequency reconfigurable unit (30) based on the equivalent series-parallel topology includes a capacitor C5, a transmission line TL2, and a diode D3 connected in series; it also includes a bias voltage source VDC, a bias resistor R1, and a bypass capacitor C6; the positive terminal of the adjustable bias voltage source VDC is connected to the anode of the diode D3 via the bias resistor R1, and the negative terminal is grounded; one end of the bypass capacitor C6 is connected to the positive terminal of the adjustable bias voltage source VDC, and the other end is grounded.

7. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 6, characterized in that, An odd-multiple short-circuited quarter-wavelength transmission line TL2 is equivalent to a parallel resonant circuit, which is connected in series with capacitor C5 and diode D3 (equivalent capacitance), introducing three transmission zeros. The electrical lengths of transmission line TL2 at the frequencies of the three transmission zeros are, respectively, one-quarter wavelength, three-quarter wavelength, and five-quarter wavelength. The transmission zeros, from left to right, are the first zero, the second zero, and the third zero. The first and second zeros are located on both sides of the passband, and the third zero is located in the high-frequency stopband. The first and second zeros control the operating center frequency, and the third zero widens the stopband suppression width.

8. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 7, characterized in that, The voltage adjustment range of the bias voltage source VDC is 0.6~1.0 V, with a step of U0V. As the adjustable bias voltage VDC gradually increases from 0.6V to 1.0V, the equivalent capacitance of diode D3 gradually increases, and the frequencies of the three transmission zeros gradually decrease; conversely, the frequency of the bias voltage source VDC decreases, thus realizing the reconfigurability of the operating center frequency.

9. The center frequency reconfigurable limiting filter based on series-parallel topology according to claim 8, characterized in that, Capacitor C5 is connected in series with diode D3 to increase the range of variation of the effective capacitance value in the frequency reconfigurable unit (30) with the bias voltage VDC.

10. The center frequency reconfigurable limiting filter based on a series-parallel topology according to claim 1, characterized in that, The lumped parallel resonator (40) includes an inductor L6 and a capacitor C7 connected in parallel, and introduces a transmission zero at its resonant frequency, located on the right side of the filter passband, to improve stopband suppression at high frequencies.

Images