Rising edge flip-flop and low noise amplifier
By designing a rising-edge trigger and using the conduction and cutoff of P-type and N-type transistors to control the RC circuit, the problem of large capacitor area occupied by the rising-edge trigger is solved, realizing fast power-on and switching in a small area, which is suitable for RF low-noise amplifiers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- LANSUS TECH INC
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-09
AI Technical Summary
In existing RF low-noise amplifiers, the charging capacitor of the RC circuit in the edge trigger occupies a large area, resulting in a large area occupied by the edge trigger, which is not suitable for small-area RF low-noise amplifiers.
Design a rising-edge trigger, including a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate, and a third inverter. By controlling the conduction and cutoff of the P-type and N-type transistors, the resistance is equivalent to that of an RC circuit, thus reducing the area of the capacitor.
By reducing the size of P-type and N-type transistors, lowering the area of the equivalent resistance, and reducing the space occupied by the charging capacitor, rapid power-on and switching within a small area is achieved, meeting the specifications of RF low-noise amplifiers.
Smart Images
Figure CN121966516B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication technology, and in particular to a rising edge trigger and a low noise amplifier used in radio frequency front-end modules. Background Technology
[0002] The low-noise amplifier (LNA) uses a source-degenerate inductor common-source architecture, such as... Figure 1 As shown, the related RF low-noise amplifier includes field-effect transistors (M1, M2, M3, M4, M5, M6, M7), inductors (LS, LD), resistors (R1, R2), and a current source (Iref). Field-effect transistors M1 and M4 form a common-gate transistor (CG), with the gates of M1 and M4 respectively connected to a first bias voltage VGcg. Field-effect transistors M2 and M5 form a common-source transistor (CRT). Source (CS), the gates of field-effect transistors M2 and M5 are used to connect to the second bias voltage VGcs, one end of inductor LD is used to connect to the operating voltage Vdd, one end of inductor LS is grounded to Gnd, one end of current source Iref is used to connect to the operating voltage Vdd, the gates of the third field-effect transistor M3 and the seventh field-effect transistor M7 are used to connect to the enable signal En, the source of the third field-effect transistor M3 is grounded to Gnd, and the gate of the sixth field-effect transistor M6 is used to connect to the delay control signal (Burst Stop, Bstp).
[0003] The specifications of the aforementioned RF low-noise amplifiers generally require power-on and switching to be completed in about 1µs. The enable switch of the RF low-noise amplifier is used to control the power-on of the low-noise amplifier enable signal (LNAEN). However, the gate voltage power-on of the common-gate transistor and common-source transistor is relatively slow, requiring a delay module. At the same time as the low-noise amplifier enable signal is powered on, the delay module simultaneously provides a fast power-on and fast switching signal of about 1µs, enabling the common-gate transistor and common-source transistor of the RF low-noise amplifier to be powered on quickly at the same time, so as to ensure that the power-on time is within the specification range. After the fast power-on is completed, the delay signal output of the delay module is 0, and the RF low-noise amplifier enters the normal operating state. A large resistor R2 is connected between the field-effect transistor M2 in the mirror branch and the switch for protection. The circuit that generates the delay signal is called a rising edge trigger or edge-triggered trigger.
[0004] Edge triggers in related technologies are used to generate delayed signals. The pulse width is determined by the charging of the RC circuit composed of resistors and capacitors and the high and low threshold voltages of the Schmitt trigger. The area of the Schmitt trigger changes very little, while the area of the charging capacitor in the RC circuit is large. That is, the charging capacitor occupies a large area, which leads to the edge trigger occupying a large area, making it unsuitable for small-area RF low-noise amplifiers.
[0005] Therefore, a new rising-edge trigger and a low-noise amplifier are needed to solve the above problems. Summary of the Invention
[0006] To address the shortcomings of the aforementioned related technologies, this invention proposes a rising edge trigger and a low-noise amplifier to solve the problem that the charging capacitor of the RC circuit in the rising edge trigger occupies a large area, resulting in a large area occupied by the rising edge trigger.
[0007] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a rising edge trigger for generating a delayed signal to control a low-noise amplifier, which includes a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate, and a third inverter.
[0008] The input terminal of the first inverter serves as the input terminal of the rising edge trigger, and is used to connect the enable signal that controls the operation of the low-noise amplifier;
[0009] The input terminal of the second inverter is connected to the output terminal of the first inverter, and the power supply terminal of the second inverter is used to connect to the current output terminal of the current source that provides reference current for the low-noise amplifier;
[0010] The first terminal of the capacitor is connected to the output terminal of the second inverter, and the second terminal of the capacitor is grounded.
[0011] The input of the Schmitt trigger is connected to the output of the second inverter;
[0012] The input terminal of the inverting circuit is connected to the output terminal of the Schmitt trigger; the inverting circuit is used to shape the received enable signal.
[0013] The first input terminal of the NAND gate is connected to the output terminal of the inverter circuit, and the second input terminal of the NAND gate is connected to the output terminal of the first inverter.
[0014] The input terminal of the third inverter is connected to the output terminal of the NAND gate, and the output terminal of the third inverter serves as the output terminal of the rising edge trigger, used to output a delay control signal.
[0015] Preferably, the Schmitt trigger includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, and a sixth field-effect transistor;
[0016] The gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are connected and together serve as the input terminal of the Schmitt trigger.
[0017] The source of the first field-effect transistor is used to connect to the first operating voltage;
[0018] The source of the second field-effect transistor is connected to the drain of the first field-effect transistor;
[0019] The drain of the third field-effect transistor is connected to the drain of the second field-effect transistor and together they serve as the output terminal of the Schmitt trigger.
[0020] The drain of the fourth field-effect transistor is connected to the source of the third field-effect transistor, and the source of the fourth field-effect transistor is grounded.
[0021] The source of the fifth field-effect transistor is connected to the drain of the first field-effect transistor, and the drain of the fifth field-effect transistor is grounded.
[0022] The source of the sixth field-effect transistor is connected to the source of the third field-effect transistor, the drain of the sixth field-effect transistor is used to connect to the second operating voltage, and the gate of the sixth field-effect transistor and the gate of the fifth field-effect transistor are respectively connected to the drain of the second field-effect transistor.
[0023] Preferably, the inverter circuit includes a fourth inverter and a fifth inverter;
[0024] The input terminal of the fourth inverter serves as the input terminal of the inverting circuit;
[0025] The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter serves as the output terminal of the inverting circuit.
[0026] Preferably, the second inverter includes a seventh field-effect transistor and an eighth field-effect transistor;
[0027] The gate of the seventh field-effect transistor and the gate of the eighth field-effect transistor are connected and together serve as the input terminal of the second inverter, and the source of the seventh field-effect transistor serves as the power supply terminal of the second inverter.
[0028] The drain of the eighth field-effect transistor is connected to the drain of the seventh field-effect transistor and together they serve as the output terminal of the second inverter; the source of the eighth field-effect transistor is grounded.
[0029] In a second aspect, the present invention provides a low-noise amplifier, which includes a first current source, a second current source, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, a first inductor, a twelfth field-effect transistor, a thirteenth field-effect transistor, a second inductor, a fourteenth field-effect transistor, a fifteenth field-effect transistor, a first resistor, a second resistor, and a rising edge trigger as described above.
[0030] The current inflow terminals of the first current source and the second current source are respectively used to connect to the third operating voltage;
[0031] The gate of the ninth field-effect transistor is used to connect to the first bias voltage, and the drain of the ninth field-effect transistor is connected to the current outflow terminal of the first current source.
[0032] The drain of the tenth field-effect transistor is connected to the source of the ninth field-effect transistor;
[0033] The gate of the eleventh field-effect transistor is used to receive the enable signal that controls the operation of the low-noise amplifier. The drain of the eleventh field-effect transistor is connected to the source of the tenth field-effect transistor, and the source of the eleventh field-effect transistor is grounded.
[0034] The first terminal of the first inductor is used to connect to the fourth operating voltage;
[0035] The gate of the twelfth field-effect transistor is used to connect to the first bias voltage, and the drain of the twelfth field-effect transistor is connected to the second terminal of the first inductor.
[0036] The drain of the thirteenth field-effect transistor is connected to the source of the twelfth field-effect transistor;
[0037] The first terminal of the second inductor is connected to the source of the thirteenth field-effect transistor, and the second terminal of the second inductor is grounded.
[0038] The gate of the fourteenth field-effect transistor is used to receive the delay control signal output by the rising edge trigger.
[0039] The gate of the fifteenth field-effect transistor is used to receive an enable signal. The source of the fifteenth field-effect transistor is connected to the source of the fourteenth field-effect transistor and is connected to the gate of the thirteenth field-effect transistor.
[0040] The first terminal of the first resistor is connected to the drain of the fifteenth field-effect transistor;
[0041] The first end of the second resistor is connected to the drain of the fourteenth field-effect transistor and the second end of the first resistor, respectively, and the second end of the second resistor is connected to the gate of the tenth field-effect transistor.
[0042] The power supply terminal of the second inverter is connected to the current output terminal of the second current source.
[0043] Compared with related technologies, the rising edge trigger in this invention is designed with a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate, and a third inverter. The input of the first inverter is used to receive the enable signal controlling the operation of the low-noise amplifier, and the power supply of the second inverter is connected to the current output of the current source providing the reference current to the low-noise amplifier. Thus, the received enable signal can be converted to a low level by the first inverter, and the current source providing the reference current to the low-noise amplifier controls the conduction of the P-transistor (PMOS transistor) of the second inverter, making it equivalent to the resistor in the RC circuit of related technologies. It also controls the cutoff of the N-transistor (NMOS transistor) of the second inverter, so that its equivalent resistance and the load capacitance form an RC circuit structure. Furthermore, the P-transistor and N-transistor in this structure are smaller in size, and the area of the equivalent resistance is smaller than that of passive devices. Therefore, the area of the capacitor is reduced by controlling the current magnitude of the current source providing the reference current to the low-noise amplifier, ultimately reducing the area occupied by the rising edge trigger. Attached Figure Description
[0044] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:
[0045] Figure 1 Circuit diagram of a radio frequency low-noise amplifier provided for related technologies;
[0046] Figure 2 A circuit diagram of a rising-edge trigger provided for an embodiment of the present invention;
[0047] Figure 3 The circuit diagram of the Schmitt trigger in the rising edge trigger provided in the embodiment of the present invention;
[0048] Figure 4 The circuit diagram of the second inverter in the rising edge flip-flop provided in the embodiment of the present invention;
[0049] Figure 5 Timing diagram of a rising edge trigger provided in an embodiment of the present invention;
[0050] Figure 6 The circuit diagram of a low-noise amplifier provided for an embodiment of the present invention. Detailed Implementation
[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.
[0052] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0054] Example 1
[0055] This invention provides a rising edge trigger 100, such as... Figure 2 As shown, it includes a first inverter INV1, a second inverter INV2, a capacitor C, a Schmitt trigger SMT, an inverter circuit 1, a NAND gate NAND, and a third inverter INV3.
[0056] The rising edge trigger 100 is used to generate a delay signal to control the low noise amplifier.
[0057] The input terminal of the first inverter INV1 serves as the input terminal VIN of the rising edge trigger 100 and is used to connect to the enable signal that controls the operation of the low noise amplifier. This enable signal can be the enable signal connected to the low noise amplifier or the same enable signal connected to the low noise amplifier. This means that the low noise amplifier needs to be connected to the enable signal that controls its operation.
[0058] The input terminal of the second inverter INV2 is connected to the output terminal of the first inverter INV1. The power supply terminal of the second inverter INV2 is used to connect to the current output terminal of the current source that provides the reference current for the low noise amplifier, which is equivalent to the low noise amplifier being connected to a current source that provides the reference current for it.
[0059] The first terminal of capacitor C is connected to the output terminal of the second inverter INV2, and the second terminal of capacitor C is grounded.
[0060] The input of the Schmitt trigger SMT is connected to the output of the second inverter INV2.
[0061] The input of the inverting circuit 1 is connected to the output of the Schmitt trigger (SMT); the inverting circuit 1 is used to shape the received enable signal.
[0062] The first input terminal of the NAND gate is connected to the output terminal of the inverter circuit 1, and the second input terminal of the NAND gate is connected to the output terminal of the first inverter INV1.
[0063] The input of the third inverter INV3 is connected to the output of the NAND gate. The output of the third inverter INV3 serves as the output VOUT of the rising edge trigger 100 and is used to output the delay control signal.
[0064] In this embodiment, as Figure 3 As shown, the Schmitt trigger (SMT) includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, and a sixth field-effect transistor M6.
[0065] The gates of the first field-effect transistor M1, the second field-effect transistor M2, the third field-effect transistor M3, and the fourth field-effect transistor M4 are connected and together serve as the input Vin of the Schmitt trigger SMT.
[0066] The source of the first field-effect transistor M1 is connected to the first operating voltage VDD1.
[0067] The source of the second field-effect transistor M2 is connected to the drain of the first field-effect transistor M1.
[0068] The drain of the third field-effect transistor M3 is connected to the drain of the second field-effect transistor M2, and together they serve as the output terminal Vout of the Schmitt trigger SMT.
[0069] The drain of the fourth field-effect transistor M4 is connected to the source of the third field-effect transistor M3, and the source of the fourth field-effect transistor M4 is grounded.
[0070] The source of the fifth field-effect transistor M5 is connected to the drain of the first field-effect transistor M1, and the drain of the fifth field-effect transistor M5 is grounded.
[0071] The source of the sixth field-effect transistor M6 is connected to the source of the third field-effect transistor M3. The drain of the sixth field-effect transistor M6 is used to connect to the second operating voltage VDD2. The gate of the sixth field-effect transistor M6 and the gate of the fifth field-effect transistor M5 are respectively connected to the drain of the second field-effect transistor M2.
[0072] The inverter circuit 1 includes a fourth inverter INV4 and a fifth inverter INV5.
[0073] The input terminal of the fourth inverter INV4 serves as the input terminal of the inverter circuit 1.
[0074] The input terminal of the fifth inverter INV5 is connected to the output terminal of the fourth inverter INV4, and the output terminal of the fifth inverter INV5 serves as the output terminal of the inverter circuit 1.
[0075] like Figure 4 As shown, the second inverter INV2 includes a seventh field-effect transistor M7 and an eighth field-effect transistor M8; the seventh field-effect transistor M7 is a P-type transistor, and the eighth field-effect transistor M8 is an N-type transistor.
[0076] The gate of the seventh field-effect transistor M7 and the gate of the eighth field-effect transistor M8 are connected and together serve as the input terminal VIn of the second inverter INV2. The source of the seventh field-effect transistor M7 serves as the power supply terminal of the second inverter INV2.
[0077] The drain of the eighth field-effect transistor M8 is connected to the drain of the seventh field-effect transistor M7 and together they serve as the output terminal VOut of the second inverter INV2; the source of the eighth field-effect transistor M8 is grounded.
[0078] In this embodiment, the circuits of the first inverter INV1, the third inverter INV3, the fourth inverter INV4, and the fifth inverter INV5 are basically the same as those of the second inverter INV2. The difference is that the power supply terminals of the first inverter INV1, the third inverter INV3, the fourth inverter INV4, and the fifth inverter INV5 are not used to connect to the current source of the low-noise amplifier, but are used to connect to the operating voltage.
[0079] like Figure 5 As shown, arranged from top to bottom, the first line is the timing line of the input terminal VIN of the rising edge flip-flop 100, the second line is the timing line of node A of the rising edge flip-flop 100, the third line is the timing line of node A of the rising edge flip-flop 100, and the fourth line is the timing line of the output terminal VOUT of the rising edge flip-flop 100.
[0080] In the rising edge trigger 100 of this embodiment, after the enable signal controlling the operation of the low-noise amplifier is connected to the input terminal of the rising edge trigger 100, the enable signal is converted to a low level by the first inverter INV1; the input terminal of the second inverter INV2 is connected to this low level, and after the power supply terminal of the second inverter INV2 is connected to the current output of the current source that provides the reference current for the low-noise amplifier, the P-transistor of the second inverter INV2 is turned on, which is equivalent to the resistor of the RC circuit in the related art, and the N-transistor is turned off. Its equivalent resistance and the capacitance C of the load form an RC circuit structure, and the P-transistor and N-transistor in this structure are relatively small in size. The effective resistor area is smaller than the resistance of the passive device, and node A generates a smooth ramp-up voltage. After this voltage reaches the threshold voltage of the Schmitt trigger SMT, the output node of the Schmitt trigger SMT flips. After being shaped by the inverter circuit 1, the output becomes the voltage of node B. Finally, after passing through the NAND gate logic, a delay control signal of about 1µs is generated, i.e., a delayed high-level signal, which is output through the third inverter INV3, thereby controlling the first bias voltage and the second bias voltage connected to the low-noise amplifier, so that the field-effect transistor of the low-noise amplifier can be quickly powered on, thereby starting the low-noise amplifier. Equivalently, the rising edge trigger 100 in this embodiment can control the charging speed and adjust the length of the delay time by adjusting the current source that provides the reference current to the low-noise amplifier, so as to reduce the size of the current source and reduce the area of the charging capacitor C. The control is simple, has a large control range, and high control accuracy.
[0081] Compared with related technologies, the rising edge trigger 100 in this embodiment is designed with a first inverter INV1, a second inverter INV2, a capacitor C, a Schmitt trigger SMT, an inverter circuit 1, a NAND gate NAND, and a third inverter INV3. The input terminal of the first inverter INV1 is used to receive the enable signal controlling the operation of the low-noise amplifier, and the power supply terminal of the second inverter INV2 is connected to the current output terminal of the current source providing the reference current for the low-noise amplifier. Thus, the received enable signal can be converted by the first inverter INV1 into a... The low level controls the P-transistor of the second inverter INV2 to turn on through the current source that provides the reference current for the low noise amplifier, making it equivalent to the resistor of the RC circuit in the related technology. It also controls the N-transistor of the second inverter INV2 to turn off, so that its equivalent resistance and the load capacitor C form an RC circuit structure. In this structure, the P-transistor and N-transistor are small in size, and the area of the equivalent resistance is smaller than that of the passive device. Thus, the area of capacitor C is reduced by the current magnitude of the current source that provides the reference current for the low noise amplifier, and finally the area occupied by the rising edge trigger 100 is reduced.
[0082] Example 2
[0083] This embodiment provides a low-noise amplifier 200, combined with... Figure 6As shown, it includes a first current source Iref1, a second current source Iref2, a ninth field-effect transistor M9, a tenth field-effect transistor M10, an eleventh field-effect transistor M11, a first inductor L1, a twelfth field-effect transistor M12, a thirteenth field-effect transistor M13, a second inductor L2, a fourteenth field-effect transistor M14, a fifteenth field-effect transistor M15, a first resistor R1, a second resistor R2, and a rising-edge trigger 100 as described in Embodiment 1.
[0084] The current inflow terminals of the first current source Iref1 and the second current source Iref2 are respectively used to connect to the third working voltage VDD3.
[0085] The gate of the ninth field-effect transistor M9 is used to connect to the first bias voltage VGCG, and the drain of the ninth field-effect transistor M9 is connected to the current outflow terminal of the first current source Iref1.
[0086] The drain of the tenth field-effect transistor M10 is connected to the source of the ninth field-effect transistor M9.
[0087] The gate of the eleventh field-effect transistor M11 is used to connect to the enable signal EN that controls the operation of the low-noise amplifier 200. The drain of the eleventh field-effect transistor M11 is connected to the source of the tenth field-effect transistor M10, and the source of the eleventh field-effect transistor M11 is grounded.
[0088] The first terminal of the first inductor L1 is used to connect to the fourth operating voltage VDD4.
[0089] The gate of the twelfth field-effect transistor M12 is used to connect to the first bias voltage VGCG, and the drain of the twelfth field-effect transistor M12 is connected to the second terminal of the first inductor L1.
[0090] The drain of the thirteenth field-effect transistor M13 is connected to the source of the twelfth field-effect transistor M12.
[0091] The first terminal of the second inductor L2 is connected to the source of the thirteenth field-effect transistor M13, and the second terminal of the second inductor L2 is grounded.
[0092] The gate of the fourteenth field-effect transistor M14 is used to receive the delay control signal output by the rising edge trigger 100.
[0093] The gate of the fifteenth field-effect transistor M15 is used to receive the enable signal EN. The source of the fifteenth field-effect transistor M15 and the source of the fourteenth field-effect transistor M14 are connected together and connected to the gate of the thirteenth field-effect transistor M13 to provide the second bias voltage VGCS for the thirteenth field-effect transistor M13.
[0094] The first terminal of the first resistor R1 is connected to the drain of the fifteenth field-effect transistor M15.
[0095] The first end of the second resistor R2 is connected to the drain of the fourteenth field-effect transistor M14 and the second end of the first resistor R1, respectively. The second end of the second resistor R2 is connected to the gate of the tenth field-effect transistor M10, and is used to provide the second bias voltage VGCS for the tenth field-effect transistor M10.
[0096] The power supply terminal of the second inverter INV2 is connected to the current output terminal of the second current source Iref2.
[0097] Since the low-noise amplifier 200 in this embodiment uses the rising edge trigger 100 in embodiment one, it can also achieve the technical effect achieved by the rising edge trigger 100 in embodiment one, which will not be described in detail here.
[0098] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.
Claims
1. A rising-edge trigger for generating a delayed signal to control a low-noise amplifier, characterized in that, The rising edge trigger includes a first inverter, a second inverter, a capacitor, a Schmitt trigger, an inverting circuit, a NAND gate, and a third inverter; The input terminal of the first inverter serves as the input terminal of the rising edge trigger, and is used to connect the enable signal that controls the operation of the low-noise amplifier; The input terminal of the second inverter is connected to the output terminal of the first inverter, and the power supply terminal of the second inverter is used to connect to the current output terminal of the current source that provides reference current for the low-noise amplifier; The first terminal of the capacitor is connected to the output terminal of the second inverter, and the second terminal of the capacitor is grounded. The input of the Schmitt trigger is connected to the output of the second inverter; The input terminal of the inverting circuit is connected to the output terminal of the Schmitt trigger; The inverting circuit is used to shape the received enable signal; The first input terminal of the NAND gate is connected to the output terminal of the inverter circuit, and the second input terminal of the NAND gate is connected to the output terminal of the first inverter. The input terminal of the third inverter is connected to the output terminal of the NAND gate, and the output terminal of the third inverter serves as the output terminal of the rising edge trigger, used to output a delay control signal.
2. The rising-edge trigger as described in claim 1, characterized in that, The Schmitt trigger includes a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, and a sixth field-effect transistor; The gates of the first field-effect transistor, the second field-effect transistor, the third field-effect transistor, and the fourth field-effect transistor are connected and together serve as the input terminal of the Schmitt trigger. The source of the first field-effect transistor is used to connect to the first operating voltage; The source of the second field-effect transistor is connected to the drain of the first field-effect transistor; The drain of the third field-effect transistor is connected to the drain of the second field-effect transistor and together they serve as the output terminal of the Schmitt trigger. The drain of the fourth field-effect transistor is connected to the source of the third field-effect transistor, and the source of the fourth field-effect transistor is grounded. The source of the fifth field-effect transistor is connected to the drain of the first field-effect transistor, and the drain of the fifth field-effect transistor is grounded. The source of the sixth field-effect transistor is connected to the source of the third field-effect transistor, the drain of the sixth field-effect transistor is used to connect to the second operating voltage, and the gate of the sixth field-effect transistor and the gate of the fifth field-effect transistor are respectively connected to the drain of the second field-effect transistor.
3. The rising-edge trigger as described in claim 1, characterized in that, The inverter circuit includes a fourth inverter and a fifth inverter; The input terminal of the fourth inverter serves as the input terminal of the inverting circuit; The input terminal of the fifth inverter is connected to the output terminal of the fourth inverter, and the output terminal of the fifth inverter serves as the output terminal of the inverting circuit.
4. The rising-edge trigger as described in claim 1, characterized in that, The second inverter includes a seventh field-effect transistor and an eighth field-effect transistor; The gate of the seventh field-effect transistor and the gate of the eighth field-effect transistor are connected and together serve as the input terminal of the second inverter, and the source of the seventh field-effect transistor serves as the power supply terminal of the second inverter. The drain of the eighth field-effect transistor is connected to the drain of the seventh field-effect transistor and together they serve as the output terminal of the second inverter; the source of the eighth field-effect transistor is grounded.
5. A low-noise amplifier, characterized in that, The low-noise amplifier includes a first current source, a second current source, a ninth field-effect transistor, a tenth field-effect transistor, an eleventh field-effect transistor, a first inductor, a twelfth field-effect transistor, a thirteenth field-effect transistor, a second inductor, a fourteenth field-effect transistor, a fifteenth field-effect transistor, a first resistor, a second resistor, and a rising-edge trigger as described in any one of claims 1 to 4; The current inflow terminals of the first current source and the second current source are respectively used to connect to the third operating voltage; The gate of the ninth field-effect transistor is used to connect to the first bias voltage, and the drain of the ninth field-effect transistor is connected to the current outflow terminal of the first current source. The drain of the tenth field-effect transistor is connected to the source of the ninth field-effect transistor; The gate of the eleventh field-effect transistor is used to receive the enable signal that controls the operation of the low-noise amplifier. The drain of the eleventh field-effect transistor is connected to the source of the tenth field-effect transistor, and the source of the eleventh field-effect transistor is grounded. The first terminal of the first inductor is used to connect to the fourth operating voltage; The gate of the twelfth field-effect transistor is used to connect to the first bias voltage, and the drain of the twelfth field-effect transistor is connected to the second terminal of the first inductor. The drain of the thirteenth field-effect transistor is connected to the source of the twelfth field-effect transistor; The first terminal of the second inductor is connected to the source of the thirteenth field-effect transistor, and the second terminal of the second inductor is grounded. The gate of the fourteenth field-effect transistor is used to receive the delay control signal output by the rising edge trigger. The gate of the fifteenth field-effect transistor is used to receive an enable signal. The source of the fifteenth field-effect transistor is connected to the source of the fourteenth field-effect transistor and is connected to the gate of the thirteenth field-effect transistor. The first terminal of the first resistor is connected to the drain of the fifteenth field-effect transistor; The first end of the second resistor is connected to the drain of the fourteenth field-effect transistor and the second end of the first resistor, respectively, and the second end of the second resistor is connected to the gate of the tenth field-effect transistor. The power supply terminal of the second inverter is connected to the current output terminal of the second current source.