Bidirectional level conversion circuit with IO port mode identification and output mode switching

Abstract

The invention discloses a bidirectional level conversion circuit with IO port mode recognition and output mode switching. The bidirectional level conversion circuit comprises a first voltage domain circuit and a second voltage domain circuit which are of the same structure. During conversion, the two voltage domain input detection modules identify IO port modes of input signals A1 and B1, configure a driving mode of the side, convert the signals into driving signals and output the driving signals to the opposite side, and transmit detection signals to the arbitration and control module. And after receiving the signal, the module outputs a direction control signal to the IO switching module to control the switching direction and output corresponding in-phase signals A2 and B2. The IO port mode is matched with the driving mode, push-pull output and open-drain output are compatible, level conflicts are avoided, and the stability and compatibility of the circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a bidirectional level conversion circuit with I / O port mode recognition and output mode switching. Background Technology

[0002] In modern integrated circuit design, many different functions are often integrated on the same chip, forming a complex System-on-a-Chip (SoC). In order to achieve a good trade-off between circuit performance and power consumption, multi-voltage technology is usually adopted, which allows different functional modules to operate at different voltages to obtain optimal performance and power consumption. However, this multi-voltage design also brings new challenges, namely how to achieve efficient and reliable information transfer between two systems with different voltages.

[0003] To transmit information between systems with different voltages, appropriate level conversion circuits must be used to achieve data conversion between circuits with different power supply voltages. The function of level conversion circuits is to convert the signal level of one voltage domain to the signal level of another voltage domain. Traditional level conversion circuits are mainly divided into two types: unidirectional level conversion and bidirectional level conversion.

[0004] Unidirectional level shifting circuits can only achieve signal transmission in one direction and are typically used in scenarios where the data transmission direction is fixed. In practical applications, bidirectional data transmission between two voltage domains is often required, necessitating the use of bidirectional level shifting circuits. However, current bidirectional level shifting circuit solutions have the following problems: 1. Inaccurate transmission direction detection: Due to potential delays or jitter on the signal line, inaccurate direction detection leads to data transmission errors; 2. Weak driving capability: Traditional bidirectional level shifting circuits typically employ simple transmission gate structures with limited driving capability, making it difficult to meet the data transmission requirements of I / O ports with high driving capability; 3. Limited application scope: Existing bidirectional level shifting chips are divided into those for push-pull output circuits and those for open-drain output circuits, which are not compatible and can only be used in circuits where both sides are push-pull or open-drain, making it impossible to adjust the output mode by identifying the I / O port structure; 4. Insufficient versatility: Existing bidirectional level shifting circuits require differentiation between high and low level regions, and users cannot specify the direction of high and low level regions according to design requirements.

[0005] Therefore, a new type of bidirectional level shifting circuit is needed that can achieve high driving capability and adapt to multiple input / output modes to meet the needs of modern integrated circuit design. Summary of the Invention

[0006] The problem to be solved by this invention is to provide a bidirectional level conversion circuit with I / O port mode recognition and output mode switching, which can automatically detect the input / output mode and signal direction of the corresponding I / O port, without the need for additional control signals, and realize adaptive switching between open-drain output and push-pull output.

[0007] This invention adopts the following technical solution: a bidirectional level conversion circuit with IO port mode recognition and output mode switching, comprising: a first voltage domain circuit and a second voltage domain circuit, both the first and second voltage domain circuits including an IO switching module, an input detection module, and an output driving module, wherein the first voltage domain circuit further includes an arbitration and control module; the IO switching module realizes the switching of the input and output directions of the level conversion signal under the configuration of the IO direction control signal; the input detection module can automatically identify the IO port mode corresponding to the input signal and output the IO status signal of the voltage domain and the output driving signal of the relative voltage domain; the output driving module adjusts the open-drain output and push-pull output modes according to the IO status signal of the voltage domain and the output driving signal of the relative voltage domain; after receiving the IO status signals of the two voltage domains and the external control signal, the arbitration and control module configures the input and output directions of the IO switching modules of the two voltage domains respectively, and through the interaction of the above modules, the signal direction switching of the bidirectional level conversion circuit is realized.

[0008] Before level conversion, the IO switching module first transmits input signal A1 to the first input detection module and input signal B1 to the second input detection module by default. The input detection module identifies the IO port mode (push-pull output, open-drain output, or high-impedance input) corresponding to input signal A1 and input signal B1 through a voltage divider network and comparator circuit, and generates a first IO status signal L1 (hereinafter referred to as signal L1) and a second IO status signal L2 (hereinafter referred to as signal L2). The arbitration and control module combines signal L1 and signal L2 to output a first direction control signal D1 (hereinafter referred to as signal D1) and a second direction control signal D2 (hereinafter referred to as signal D2) to the second IO switching module and the first IO switching module, respectively.

[0009] When the first signal port PORT_A (hereinafter referred to as PORT_A) is used as an input port and the second signal port PORT_B (hereinafter referred to as PORT_B) is used as an output port, the arbitration and control module, in conjunction with signals L1 and L2, outputs signals D1 and D2 to the second IO switching module and the first IO switching module respectively, adjusting the transmission direction of PORT_A as input and PORT_B as output. Simultaneously, the first input detection module converts input signal A1 into the second output drive signal C1 (hereinafter referred to as signal C1) and transmits it to the second output drive module. Signal L2 adjusts its own drive mode to adapt its output mode to the second voltage domain IO port mode, and outputs an output signal A2 in phase with A1 to PORT_B, completing the level conversion from the first voltage domain to the second voltage domain. When PORT_B is used as an input port... When PORT_A is used as an output port, the arbitration and control module similarly controls the second IO switching module and the first IO switching module to adjust the transmission direction of PORT_B as input and PORT_A as output. At the same time, the second input detection module converts the input signal B1 into the first output drive signal C2 (hereinafter referred to as signal C2) and transmits it to the first output drive module. The first output drive module adjusts its own drive mode according to signal L1 to adapt its output mode to the mode of the first voltage domain IO port, and outputs the output signal B2, which is in phase with the input signal B1, to PORT_A, thus completing the level conversion from the second voltage domain to the first voltage domain.

[0010] When both the first and second signal terminals are detected as push-pull output modes, the arbitration and control module identifies the risk of level conflict through the logical judgment of signals L1 and L2. Both the first direction control signal D1 and the second direction control signal D2 output low levels, causing the first IO switching module and the second IO switching module to disconnect their respective input channels to prevent short circuits caused by both sides being output. Normal transmission is restored after the conflict is resolved or an external control signal intervenes. This design solves the short circuit problem when both PORT_A and PORT_B are push-pull outputs in the bidirectional level conversion circuit, enabling the push-pull output mode to be applied to bidirectional level conversion and expanding the application range of the circuit.

[0011] Preferably, the first input detection module includes a comparator composed of three voltage divider networks (R1-R2, R3-R4, R5-R6), two operational amplifiers (OP1, OP2), and an AND gate (AND1). The input signal A1 is divided by R1-R2 and then input to the non-inverting input of OP1 and the inverting input of OP2, respectively. The voltage divider network composed of R3-R4 provides a high-level reference voltage for OP1; the voltage divider network composed of R5-R6 provides a low-level reference voltage for OP2. OP1 compares the divided input signal A1 with the high-level voltage and outputs a mode recognition signal to AND1. OP2 compares the divided input signal A1 with the low-level reference voltage and outputs signal C1, which is simultaneously transmitted to AND1 and the second output driver module. AND1 performs logical processing on the two comparison signals to generate signal L1, realizing the identification of the IO port mode and transmission direction, thus solving the problem of inaccurate transmission direction detection.

[0012] Preferably, the second input detection module has the same structure as the first input detection module, including a three-group voltage divider network (R10-R11, R8-R9, R12-R13), a comparator composed of two operational amplifiers (OP3, OP4), and an AND gate (AND4). The input signal B1 is divided by R10-R11 and then input to the non-inverting input of OP3 and the inverting input of OP4, respectively. R8-R9 provides a high-level reference voltage, and R12-R13 provides a low-level reference voltage. OP3 outputs a mode recognition signal to AND4, and OP4 outputs signal C2 to AND4 and the first output driver module. AND4 outputs signal L2. This structure ensures the symmetry of the two voltage domain mode detections, solves the problem of distinguishing between high and low voltage domains in traditional bidirectional level conversion circuits, and enhances the versatility of the circuit.

[0013] Preferably, the first output driving module consists of PMOS transistors (MP1, MP2, MP3), NMOS transistors (MN1, MN2, MN3), and pull-up resistors R7; MP1 is a dual-gate field-effect transistor, with its G1 terminal connected to the output signal L1 of the first input detection module and its G2 terminal connected to the output signal C2 of the second input detection module; the source of MP1 and the drain of MN2 are connected to the first voltage domain power supply Vdd1, and the source of MN3 and the drain of MP3 are connected to ground Gnd1; the source of MP3 and the source of MP2 are connected to the drain of MP1; the source of MN2 and the source of MN1 are connected to the drain of MN3; the gate of MP3, the gate of MN2, the source of MP2, and the source of MN1 serve as a common connection point and are connected to the first IO switching module as output terminals; when signal L1 is low, MP1, MP2, MP3 and MN1, MN2, MN3 are turned on in tandem to achieve a push-pull output mode and improve driving capability; when signal L1 is low, MP1, MP2, MP3 and MN1, MN2, MN3 are turned on in tandem to achieve a push-pull output mode and improve driving capability; when signal L1 is low, MP1, MP2, MP3 and MN1, MN2, MN3 are turned on in tandem to achieve a push-pull output mode and improve driving capability; when signal L1 is low, MP1, MP2, MP3 and MN1, MN2, MN3 are turned on in tandem to achieve a push-pull output mode and improve driving capability. When the signal is high, MP1 is cut off, the high-level driving capability is turned off, and only MN1 and MN3 are turned on. In conjunction with R7, an open-drain output mode is achieved. This design enhances the output driving capability of the circuit and adapts to different I / O port requirements.

[0014] Preferably, the second output driving module has the same structure as the first output driving module, consisting of PMOS transistors (MP4, MP5, MP6), NMOS transistors (MN4, MN5, MN6), and pull-up resistors R14; MP4 is a dual-gate field-effect transistor, with its G1 terminal connected to the L2 signal of the second input detection module and its G2 terminal connected to the output signal C1 of the first input detection module; its push-pull / open-drain mode switching logic is consistent with that of the first output driving module, ensuring the symmetry of the driving characteristics of the two voltage domains and the stability of signal conversion.

[0015] Preferably, the arbitration and control module includes logic circuits (AND2, AND3, OR1, OR2, OR3) and external control signal ports ([Safe_Set_A], [Safe_Set_B]); signal L1 is input to the input terminals of AND2 and OR2, and signal L2 is input to the input terminals of AND3 and OR2; external control signal [Safe_Set_A] is connected to OR1, and [Safe_Set_B] is connected to OR3; the output signals of AND2 and OR1 are combined to form a first voltage domain direction control signal D1, and the output signals of AND3 and OR3 are combined to form a second voltage domain direction control signal D2; when both signals L1 and L2 indicate the output mode, OR2 outputs a low level, triggering AND2 and AND3 latches, causing the IO switching module devices SW1 and SW2 to disconnect the signal inputs on both sides, putting the circuit into a protection state; external control signals [Safe_Set_A] and [Safe_Set_B]... When the signal is high, the corresponding transmission direction is forcibly locked, and its priority is higher than the internal detection signal. When the signal is low by default, the external control signal is automatically controlled by signals L1 and L2. This circuit allows for manual intervention in the transmission direction, improving the flexibility and reliability of the circuit. Attached Figure Description

[0016] Figure 1 This is a block diagram of a bidirectional level converter with I / O port mode recognition and output mode switching according to the present invention; Figure 2 This is a circuit diagram of a bidirectional level conversion circuit with I / O port mode recognition and output mode switching according to the present invention; Detailed Implementation

[0017] To make the technical solution and advantages clearer, the technical solution of the present invention will be further described in detail below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, not all embodiments. Non-creative modifications made by those skilled in the art based on the embodiments are all within the protection scope of the present invention.

[0018] In one embodiment of the present invention, a bidirectional level conversion circuit with I / O port mode recognition and output mode switching is shown in the figure (see attached circuit diagram in the reference document), including a first voltage domain circuit (Vdd1-Gnd1) and a second voltage domain circuit (Vdd2-Gnd2); the first voltage domain circuit includes a first I / O switching module. 100 First input detection module 300 First output driver module 200 Arbitration and Control Module 400 The second voltage domain circuit includes a second I / O switching module. 110Second input detection module 310 Second output driver module 210 The common terminal of the bidirectional MUX device SW1 in the first IO switching module is connected to the first signal terminal PORT_A, and the common terminal of the bidirectional MUX device SW2 in the second IO switching module is connected to the second signal terminal PORT_B. Both PORT_A and PORT_B are bidirectional ports. The arbitration and control module connects the detection module and the switching module of the two voltage domains through logic circuits to realize integrated control of pattern recognition, direction control and conflict protection.

[0019] Specifically, the IO switching module devices SW1 and SW2 both adopt bidirectional multiplexed MUX devices. The direction control terminals are respectively connected to the direction control signals D2 and D1 output by the arbitration and control modules. When signal D2 is high, SW1 conducts the input channel, and the input signal A1 of PORT_A is transmitted to the first input detection module. When signal D2 is low, SW1 conducts the output channel, and the output signal A2 of the first output drive module is transmitted to PORT_A. The working logic of SW2 is the same as that of SW1. When signal D1 is high, the input channel is conducted, and when it is low, the output channel is conducted, ensuring the channel switching of the signal transmission direction.

[0020] Specifically, the resistor parameters of the first input detection module are selected as follows: R1=10kΩ, R2=10kΩ, R3=9kΩ, R4=1kΩ, R5=1kΩ, R6=9kΩ. Operational amplifiers OP1 and OP2 are high-speed comparators. A1, after being divided by R1-R2, is input to the non-inverting input of OP1 and the inverting input of OP2. The low-level reference voltage Vdd1 / 10 is obtained by dividing by R3-R4 and input to the inverting input of OP1. The high-level reference voltage Vdd9 / 10 is obtained by dividing by R5-R6 and input to the non-inverting input of OP2. When the input signal A1 is a push-pull output high level, OP1 outputs a high level and OP2 outputs a low level. After AND1 logic processing, the first IO status signal L1 = low level is output. When the input signal A1 is an open-drain output high level or a high-impedance input, OP1 outputs a high level and OP2 outputs a high level. AND1 outputs the first IO status signal L1 = low level. The high level design enables the distinction between push-pull, open-drain, and high-impedance I / O states.

[0021] Specifically, the MOSFETs selected for the first output drive module are as follows: MP1, MP2, and MP3 are P-channel MOSFETs, and MN1, MN2, and MN3 are N-channel MOSFETs. The pull-up resistor R7 = 10kΩ. The G1 terminal of MP1 is connected to signal L1, and the G2 terminal is connected to signal C2 output from the second input detection module. When signal L1 is low (push-pull mode), MP1 is enabled, and signal C2 controls MP2, MP1, MN1, and MN3 to conduct in tandem, forming the push-pull output core and outputting a high level Vdd1 or a low level Gnd1 to meet the transmission requirements of high-drive capability IO. When the first IO status signal L1 is high (open-drain mode), MP1 is cut off under the control of signal L1. Signal C2 can only control MN1 and MN3 to conduct and output a low level, or pull up to output a high level through R7, adapting to the level conversion requirements of open-drain signals, and the output impedance can be flexibly adjusted through R7.

[0022] Specifically, the logic circuit of the arbitration and control module is composed of high-speed CMOS logic gates. AND2, AND3, OR1, OR2, and OR3 are two-input logic gates. The external control signals [Safe_Set_A] and [Safe_Set_B] are low by default. When manual locking of the direction is required, a high level can be input to force the channel direction to be set. When PORT_A is a push-pull output (signal L1 = low) and PORT_B is a high-impedance input (signal L2 = high), OR2 outputs a high level, AND2 outputs a low level, and OR1 outputs a low level, synthesizing the first IO direction control signal D1 = low level. AND3 outputs a high level, and OR3 outputs a high level, synthesizing the second IO direction control signal D2 = high level. Under the control of signals D1 and D2, SW1 conducts input and SW2 conducts output. The input signal A1 generates signal C1 through the first input detection module and transmits it to the second output drive module. The second drive module is adapted to open-drain mode and outputs an output signal A2 that is in phase with the input signal A1. The circuit converts the level from Vdd1 to Vdd2 via PORT_B. Similarly, when PORT_A is a high-impedance input (signal L1 = high) and PORT_B is a push-pull output (signal L2 = low), the circuit can convert the level from Vdd2 to Vdd1.

[0023] Specifically, when PORT_A and PORT_B are both in push-pull output mode, the first IO status signal L1 is low, the second IO status signal L2 is low, OR2 outputs low, triggering AND2 and AND3 latches, signals D1 and D2 both output low, SW1 and SW2 both disconnect the input channels on both sides, at this time the circuit enters protection state until the system is reset and one of the signal ports is recognized as input mode, OR2 outputs low, the latch is released, and the circuit resumes normal transmission.

[0024] Specifically, when PORT_A is in push-pull output mode and PORT_B is a high-drive input, the first IO status signal L1 is low and the second IO status signal L2 is low. Under the control of signal L2, the high-drive output of the second output driver module is activated, and signals D1 and D2 remain low. SW2 conducts the output channel. By inputting a high level through the external control signal [Safe_Set_B], SW1 is switched to input mode, realizing high-drive output from PORT_A to PORT_B. Similarly, when PORT_B is in push-pull output mode and PORT_A is an input requiring high drive capability, the high-drive output of the first output driver module is activated under the control of signal L1. By inputting a high level through the external control signal [Safe_Set_A], SW2 is switched to input mode, realizing high-drive output from PORT_B to PORT_A.

[0025] In summary, this invention integrates automatic I / O port mode identification, adaptive drive mode switching, arbitration control, and conflict protection into a single design, compatible with push-pull and open-drain output modes, thus avoiding the problems of single mode and easy conflict in traditional circuits. At the same time, the symmetrical circuit structure improves the versatility of the bidirectional level conversion circuit. This circuit expands the application range of the bidirectional level conversion circuit, making it applicable to various I / O port mode application scenarios.

[0026] The above description is only a preferred embodiment of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the circuit parameters and device selection, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A bidirectional level conversion circuit with I / O port mode recognition and output mode switching, characterized in that... include: A first voltage domain circuit and a second voltage domain circuit, both including an I / O switching module, an input detection module, and an output driving module, wherein the first voltage domain circuit further includes an arbitration and control module; a first signal port PORT_A is connected to the common terminal of the first I / O switching module, and a second signal port PORT_B is connected to the common terminal of the second I / O switching module, both being bidirectional ports; the input signal A1 of the first signal port PORT_A is input to the first input detection module through the first I / O switching module, and after generating a first I / O status signal L1 at the output terminal of the first input detection module, it is input to the first output driving module and the arbitration and control module, whereby the first input detection module converts the input signal A1 into a second output driving signal C1 and inputs it to the second output driving module; simultaneously, the input signal B1 of the second signal port PORT_B is input to the second input detection module through the second I / O switching module, and after generating a second I / O status signal L2 at the output terminal of the second input detection module, it is input to the second output driving module and the arbitration and control module, whereby the second input detection module converts the input signal B1 into a first output driving signal C2 and inputs it to the first output driving module; the first I / O status signal L1... The second IO status signal L2 is input to the arbitration and control module to generate a first IO direction control signal D1 and a second IO direction control signal D2. The first IO direction control signal D1 and the second IO direction signal D2 control the input and output directions of the IO switching module, thereby enabling the transmission of the input signal A1 of the first signal port PORT_A to the first input detection module, and then the second output driving module to transmit the level-converted output signal A2 to the second signal port PORT_B, or the transmission of the input signal B1 of the second signal port PORT_B to the second input detection module, and then the first output driving module to transmit the level-converted output signal B2 to the first signal port PORT_A, thus realizing the bidirectional level conversion function.

2. The bidirectional level conversion circuit with I / O port mode recognition and output mode switching according to claim 1, characterized in that, The IO switching module uses a bidirectional multiplexed MUX device. Its common terminal is connected to the corresponding bidirectional signal port. A high level connects the multiplexed terminal to the input detection module, and a low level connects the multiplexed terminal to the output drive module. The selection terminal is connected to the direction control signal output by the arbitration and control module. By switching the high and low levels of the direction control signal, the conduction switching between the signal input channel and the output channel is realized.

3. The bidirectional level conversion circuit with I / O port mode recognition and output mode switching as described in claim 1, characterized in that, The input detection module includes a voltage divider network, a comparator circuit, and an AND gate circuit. After the input signal is divided and processed by the voltage divider network, it is compared with the reference voltage by the comparator to complete the identification of the IO port mode. The IO status signal is output to the arbitration and control module and the output driver module of this voltage domain, and the input signal is sent to the output driver module of the opposite voltage domain.

4. The bidirectional level conversion circuit with I / O port mode recognition and output mode switching according to claim 1, characterized in that, The output drive module includes a PMOS transistor, an NMOS transistor, and a pull-up resistor. The core PMOS transistor is a dual-gate field-effect transistor. By receiving the input signal from the opposing voltage domain and the level conversion signal of the current voltage domain, the MOS transistor is controlled to turn on and off, realizing adaptive switching between push-pull output and open-drain output modes, and outputting the level-converted signal to the IO switching module.

5. A bidirectional level conversion circuit with I / O port mode recognition and output mode switching as described in claim 1, characterized in that, The arbitration and control module includes logic gate circuits and external control signal ports. The logic gate circuits receive IO status signals from two voltage domains, perform logical judgments, and output direction control signals to the IO switching modules. The external control signals can manually lock the signal transmission direction and have a higher priority than the internal IO status signal control. When the first signal port PORT_A and the second signal port PORT_B are simultaneously detected as output modes, the arbitration and control module identifies the risk of level conflict and disconnects the input directions of the two IO switching modules to avoid short circuits.

Images