Digital-analog conversion device

Abstract

A digital-to-analog conversion device at least comprises a controller, at least one first front-end circuit, at least one second front-end circuit and an addition amplification circuit, the first front-end circuit is used for adjusting an attenuation gain value, the controller sets an attenuation ratio according to the attenuation gain value, and the second front-end circuit is used for adjusting the attenuation ratio according to the attenuation gain value. The first front-end circuit is used for receiving the attenuation ratio and outputting a first analog voltage signal and a second analog voltage signal according to the attenuation ratio, and the first front-end circuit and the second front-end circuit are used for receiving the first analog voltage signal and the second analog voltage signal respectively and outputting a fine-tuning output voltage and a coarse-tuning output voltage; and the addition amplification circuit outputs an analog output signal according to the fine adjustment output voltage and the coarse adjustment output voltage.

Description

Technical Field

[0001] This invention relates to a digital-to-analog converter, and more particularly to a digital-to-analog converter capable of improving resolution by setting voltage divider and magnification. Background Technology

[0002] A digital-to-analog converter (DAC) is an electronic device that converts digital signals into continuous analog signals. DACs have wide applications in modern electronic systems, including audio playback, video processing, communication systems, and control systems.

[0003] Among them, digital-to-analog converters can convert precise digital signals generated by digital systems into analog signals, enabling precise control of analog devices. At the same time, because digital-to-analog converters are easy to integrate with digital systems (such as microcontrollers and digital signal processors), they facilitate the design of complex digital-to-analog hybrid circuits, and therefore can be widely used in embedded systems, consumer electronics products, etc.

[0004] However, digital-to-analog converters still have the following drawbacks: (1) The resolution (i.e. bit depth) of a DAC directly affects the fineness of the output analog signal. A DAC with lower resolution may not meet the requirements of high-precision applications.

[0005] (2) High-resolution, high-speed and high-precision DACs are usually more complex and have higher manufacturing costs.

[0006] High resolution is a current industry requirement; however, applying digital-to-analog converters (DACs) to high-resolution applications inevitably increases circuit complexity. For every bit of resolution increase, the number of quantization stages in the DAC doubles. For example, increasing from 16 bits to 18 bits increases the number of quantization stages from 65,536 to 262,144. This necessitates more circuit components and more complex circuit designs to process significantly more digital information.

[0007] Using more circuit components and more complex circuit designs inevitably increases design and production costs significantly. Therefore, to solve this problem, this invention uses a microcontroller unit (MCU) for control, combined with circuit design, to achieve higher resolution and increased speed, thus making its application more widespread and flexible. Therefore, this invention should be considered the best solution. Summary of the Invention

[0008] The present invention provides a digital-to-analog conversion device, comprising at least: a controller for outputting a first analog voltage signal and a second analog voltage signal; at least one first front-end circuit electrically connected to the controller, the first front-end circuit comprising at least a voltage divider and a first buffer, the voltage divider being electrically connected to the first buffer, the voltage divider being set to a fine-tuning voltage division ratio, and the voltage divider also being used to receive the first analog voltage signal, and, according to the fine-tuning voltage division ratio, the first front-end circuit being able to output a fine-tuning output voltage; and at least one second front-end circuit electrically connected to the controller, the second front-end circuit comprising at least a second buffer, the second buffer being used to receive the first analog voltage signal and the second analog voltage signal. The system outputs two analog voltage signals and a coarse-adjustment output voltage; an adder amplifier circuit is electrically connected to the first front-end circuit and the second front-end circuit to receive the fine-adjustment output voltage and the coarse-adjustment output voltage, and outputs an analog output signal based on the fine-adjustment output voltage and the coarse-adjustment output voltage; wherein the controller sets an attenuation gain value, and sets a first attenuation ratio and a second attenuation ratio based on the attenuation gain value, the first attenuation ratio being the reciprocal of the attenuation gain value, and the second attenuation ratio being 1 minus the first attenuation ratio, and the second analog voltage signal being the first analog voltage signal multiplied by the second attenuation ratio, and the first attenuation ratio being equal to the fine-adjustment voltage division ratio.

[0009] More specifically, the voltage divider has at least two resistive elements, and the voltage divider sets the fine-tuning voltage division ratio through the at least two resistive elements.

[0010] More specifically, the voltage divider has at least one resistive element and a resolution controller. The voltage divider sets the fine-tuning voltage division ratio through the at least one resistive element and the resolution controller. The resolution controller is electrically connected to the controller and can synchronously adjust the fine-tuning voltage division ratio according to the first attenuation ratio set by the controller.

[0011] More specifically, the resolution controller is a digitally adjustable resistor element, wherein if the controller changes the first attenuation ratio, the digitally adjustable resistor element can synchronously adjust its resistance value so that the fine-tuning voltage division ratio of the resistor element and the digitally adjustable resistor element can be equal to the first attenuation ratio.

[0012] More specifically, the first buffer has a first buffer gain value of 1.

[0013] More specifically, the second buffer has a second buffer gain value of 1.

[0014] More specifically, the first front-end circuit also has a first filter, which is connected between the voltage divider and the first buffer.

[0015] More specifically, the first front-end circuit also has a second filter, which is electrically connected to the second buffer.

[0016] More specifically, the fine-tuned output voltage is the first analog voltage signal multiplied by the fine-tuning voltage division ratio, while the coarse-tuned output voltage is equal to the second analog voltage signal.

[0017] More specifically, the controller can convert a digital signal into an analog signal and output the converted first analog voltage signal and the second analog voltage signal to the first front-end circuit and the second front-end circuit, respectively.

[0018] The beneficial effects of this invention are as follows: 1. This invention can change the attenuation gain value through adjustable voltage divider elements, and with the help of circuit design, achieve higher resolution and increased speed, thus making its application more widespread and flexible.

[0019] 2. The resolution of the circuit architecture of this invention after final integration is significantly higher than that of a single DAC. In addition, it can be synchronously adjusted through digitally adjustable resistors, which will help users meet their needs in different situations.

[0020] 3. The circuit architecture of this invention can reduce overall cost and achieve higher energy efficiency, which is impossible to achieve by using multiple conventional DACs. Attached Figure Description

[0021] Figure 1A : A schematic diagram of the architecture of the digital-to-analog conversion device of the present invention; Figure 1B : A schematic diagram of the architecture of the first front-end circuit of the digital-to-analog conversion device of the present invention; Figure 1C : A schematic diagram of the architecture of the second front-end circuit of the digital-to-analog conversion device of the present invention; Figure 2 : A circuit connection diagram of the digital-to-analog conversion device of the present invention; Figure 3 : A schematic diagram of signal synthesis simulation for the digital-to-analog conversion device of the present invention.

[0022] Explanation of reference numerals in the attached figures 1. Controller; 2. First front-end circuit; 21. Voltage divider; 211. Resolution controller; 22. First filter; 23. First buffer; 3. Second front-end circuit; 31. Second filter; 32. Second buffer; 4. Adding amplifier circuit; 5. Communication interface signal. Detailed Implementation

[0023] Other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings.

[0024] Please see section [number] Figures 1A to 1C Figure 1 shows a schematic diagram of the first implementation architecture, the first front-end circuit architecture, and the second front-end circuit architecture of the digital-to-analog conversion device of the present invention. As shown in the figure, the digital-to-analog conversion device includes at least a controller 1, at least one first front-end circuit 2, at least one second front-end circuit 3, and an adder amplifier circuit 4.

[0025] The controller 1 has the function of converting a digital signal into an analog signal, and thus can output the converted first analog voltage signal and second analog voltage signal to the first front-end circuit 2 and the second front-end circuit 3.

[0026] The controller 1 is set with an attenuation gain value (e.g., A), and sets a first attenuation ratio (e.g., 1 / A) and a second attenuation ratio (e.g., 1-1 / A) based on the attenuation gain value. The first attenuation ratio is the reciprocal of the attenuation gain value, and the second attenuation ratio is 1 minus the first attenuation ratio. The second analog voltage signal is the first analog voltage signal multiplied by the second attenuation ratio.

[0027] The controller 1 can be implemented by a microprocessor (MCU).

[0028] The first front-end circuit 2 is electrically connected to the controller 1. The first front-end circuit 2 includes at least a voltage divider 21, a first filter 22, and a first buffer 23.

[0029] The voltage divider 21 is electrically connected to the first buffer 23. The voltage divider 21 can be set with a fine-tuning voltage division ratio (e.g., 1 / A). The voltage divider 21 is also used to receive the first analog voltage signal and, according to the fine-tuning voltage division ratio, enable the first front-end circuit 2 to output a fine-tuning output voltage (the first analog voltage signal multiplied by the fine-tuning voltage division ratio), wherein the fine-tuning voltage division ratio is equal to the first attenuation ratio.

[0030] The voltage divider 21 can use a combination of at least two resistive elements to set the fine-tuning voltage division ratio to achieve the purpose of voltage division.

[0031] However, if a combination of resistors is used to set the fine-tuning voltage division ratio, since the resistors referred to here are general resistors, they do not have an adjustable characteristic.

[0032] Therefore, in order to achieve an adjustable effect and to enable the fine-tuning voltage division ratio to be adjusted synchronously with the first attenuation ratio, the present invention provides another embodiment in which the voltage divider 21 sets the fine-tuning voltage division ratio through at least one resistive element and a resolution controller 211.

[0033] The resolution controller 211 of the present invention is a digitally adjustable resistor element. Therefore, when the digitally adjustable resistor element is used in conjunction with a general resistor element, if the controller 1 changes the first attenuation ratio, the digitally adjustable resistor element can synchronously adjust its resistance value so that the fine-tuning voltage division ratio of the resistor element and the digitally adjustable resistor element can be equal to the first attenuation ratio.

[0034] In addition, if a resolution controller 211 is used, the controller 1 is also provided with a control interface to enable the controller 1 to be electrically connected to the resolution controller 211.

[0035] The first buffer 23 has a first buffer gain value of 1.

[0036] The second front-end circuit 3 is electrically connected to the controller 1, and the second front-end circuit 3 includes at least a second filter 31 and a second buffer 32.

[0037] The second buffer 32 is used to receive the second analog voltage signal and can output a coarse-tuned output voltage.

[0038] The second buffer 32 has a second buffer gain value of 1.

[0039] The adder amplifier circuit 4 is electrically connected to the first front-end circuit 2 and the second front-end circuit 3 to receive the fine-tuning output voltage and the coarse-tuning output voltage, and output an analog output signal based on the fine-tuning output voltage and the coarse-tuning output voltage.

[0040] like Figure 2 The diagram shown is a circuit connection diagram. The circuit in this embodiment is exemplified by its adjustable characteristics. If it is to be implemented as non-adjustable, the resolution controller 211 can be directly replaced with a general resistor element. (The non-adjustable nature referred to in this invention means that it can only be adjusted at the factory or after disassembly, while the adjustable nature referred to in this invention means that it can be adjusted synchronously and in real time.)

[0041] The controller 1 is used to output a first analog voltage signal (DACout1) and a second analog voltage signal (DACout2).

[0042] The first front-end circuit 2 has a voltage divider 21 (composed of R132 and VRA, wherein the VRA inside the resolution controller 211 is a digitally adjustable resistor element), a first filter 22 (C55), and a first buffer 23 (U8C).

[0043] If the controller 1 sets a new attenuation gain value, it will also change the first attenuation ratio and the second attenuation ratio. The controller 1 can output a communication interface signal 5 (I 2 The resolution controller 211 is connected via C, SPI, etc., and the digitally adjustable resistor element (VRA) of the resolution controller 211 can synchronously adjust its resistance value according to the content of the communication interface signal 5, thereby synchronously changing the fine-tuning voltage division ratio of the voltage divider 21 (R132 and VRA).

[0044] For example, when controller 1 sets a new attenuation gain value (e.g., 10), it will also set a first attenuation ratio (1 / 10) and a second attenuation ratio (9 / 10). At the same time, it will adjust the fine-tuning voltage division ratio through a digital adjustable resistor element (VRA) so that the fine-tuning voltage division ratio is equal to the first attenuation ratio (1 / 10).

[0045] The controller 1 outputs a first analog voltage signal (e.g., 3.3V), and the controller 1 outputs a second analog voltage signal, which is the first analog voltage signal multiplied by the attenuation ratio (1-1 / 10). For example, 3.3V multiplied by 9 / 10 results in a second analog voltage signal of 2.97V.

[0046] The first front-end circuit 2 receives the first analog voltage signal (3.3V) and, after fine-tuning the voltage division ratio (1 / 10), can input 0.33V to the first buffer 23 (U8C), and the first buffer 23 (U8C) will output a fine-tuned output voltage (Vout1=0.33V).

[0047] The second front-end circuit 3 has a second filter 31 (C59) and a second buffer 32 (U8D), and a resistor (R138) is connected to the front end of the second filter 31 (C59).

[0048] The second front-end circuit 3 receives the second analog voltage signal (2.97V) and directly inputs 2.97V to the second buffer 32 (U8D), and the second buffer 32 (U8D) will output a coarse adjustment output voltage (Vout2=2.97V).

[0049] The adder amplifier circuit 4 has an operational amplifier (U6C) that combines the fine-tuning output voltage (0.33V) and the coarse-tuning output voltage (2.97V) and outputs an analog output signal.

[0050] The following examples illustrate different bits, where the input voltage is an example of full-scale voltage (e.g., 3.3V). However, the implementation of this invention is not limited to full-scale voltage.

[0051] In the first example, if the controller output voltage is 3.3V, the attenuation gain is 10, the first attenuation ratio is 1 / 10, the second attenuation ratio is 9 / 10, the fine-tuning voltage divider ratio is 1 / 10, and the controller output resolution in bits is 2. 12 =4096, different numerical analyses are as follows: (1) The first analog voltage signal is 3.3V (the full scale mentioned in this invention represents the highest voltage value. In the implementation of this invention, the full scale refers to 3.3V), and the input voltage is divided to 0.33V (3.3*1 / 10).

[0052] (2) The second analog voltage signal is 2.97V (3.3*(9 / 10)).

[0053] (3) Resolution voltage (a) First analog voltage signal, resolution voltage is 80.566uV (0.33V / 4096).

[0054] (b) Second analog voltage signal, resolution voltage is 0.7251mV (2.97V / 4096).

[0055] (4) Finally, since the digital signal output by the controller is 12 bits, the present invention uses the concept of multiplier to improve the resolution and speed by using the addition amplifier circuit. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit number is 40963 (3.3V / 80.566uV), of which 40963 exceeds 15 bits (32768).

[0056] (5) It can be seen that by setting the attenuation gain value, the first attenuation ratio, the second attenuation ratio and the fine-tuning voltage division ratio, the resolution can be increased from 12 bits to more than 15 bits. Therefore, the present invention can indeed improve the resolution by setting the voltage division and the multiplier.

[0057] In the second example, if the controller output voltage is 3.3V, the attenuation gain is 15, the first attenuation ratio is 1 / 15, the second attenuation ratio is 14 / 15, the fine-tuning voltage divider ratio is 1 / 15, and the controller output resolution bits are 2. 12 =4096, different numerical analyses are as follows: (1) The first analog voltage signal is 3.3V (the full scale mentioned in this invention represents the highest voltage value. In the implementation of this invention, the full scale refers to 3.3V), and the input voltage is divided to 0.22V (3.3*1 / 15).

[0058] (2) The second analog voltage signal is 3.08V (3.3*(14 / 15)).

[0059] (3) Resolution voltage (c) First analog voltage signal, resolution voltage is 53.71uV (0.22V / 4096).

[0060] (d) Second analog voltage signal, resolution voltage is 0.7519mV (3.08V / 4096).

[0061] (4) Finally, since the digital signal output by the controller is 12 bits, the present invention uses the concept of multiplier to improve the resolution and speed by using the addition amplifier circuit. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit number is 61441 (3.3V / 53.71uV), of which 61441 exceeds 15 bits (32768).

[0062] (5) It can be seen that by setting the attenuation gain value, the first attenuation ratio, the second attenuation ratio and the fine-tuning voltage division ratio, the resolution can be increased from 12 bits to more than 15 bits. Therefore, the present invention can indeed improve the resolution by setting the voltage division and the multiplier.

[0063] The third example: Suppose the controller output voltage is 3.3V, the attenuation gain is 16, the first attenuation ratio is 1 / 16, the second attenuation ratio is 15 / 16, the fine-tuning voltage divider ratio is 1 / 16, and the controller output resolution bits are 2. 12 =4096, different numerical analyses are as follows: (1) The first analog voltage signal is 3.3V (the full scale mentioned in this invention represents the highest voltage value. In the implementation of this invention, the full scale refers to 3.3V), and the input voltage is divided to 0.20625V (3.3*1 / 16).

[0064] (2) The second analog voltage signal is 3.09375V (3.3*(15 / 16)).

[0065] (3) Resolution voltage (e) First analog voltage signal, resolution voltage is 50.354uV (0.20625V / 4096).

[0066] (f) Second analog voltage signal, resolution voltage is 0.75531mV (3.09375V / 4096).

[0067] (4) Finally, since the digital signal output by the controller is 12 bits, the present invention uses the concept of multiplier to improve the resolution and speed by using the addition amplifier circuit. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit number is 65536 (3.3V / 50.354uV), where 65536 is equal to 16 bits (65536).

[0068] (5) It can be seen that by setting the attenuation gain value, the first attenuation ratio, the second attenuation ratio and the fine-tuning voltage division ratio, the resolution can be increased from 12 bits to 16 bits. Therefore, the present invention can indeed improve the resolution by setting the voltage division and the multiplier.

[0069] The fourth example: Suppose the controller output voltage is 3.3V, the attenuation gain is 20, the first attenuation ratio is 1 / 20, the second attenuation ratio is 19 / 20, the fine-tuning voltage divider ratio is 1 / 20, and the controller output resolution bits are 2. 12 =4096, different numerical analyses are as follows: (1) The first analog voltage signal is 3.3V (the full scale mentioned in this invention represents the highest voltage value. In the implementation of this invention, the full scale refers to 3.3V), and the input voltage is divided to 0.165V (3.3*1 / 20).

[0070] (2) The second analog voltage signal is 3.135V (3.3*(19 / 20)).

[0071] (3) Resolution voltage (g) First analog voltage signal, resolution voltage is 40.2832uV (0.165V / 4096).

[0072] (h) Second analog voltage signal, resolution voltage is 0.76538mV (3.135V / 4096).

[0073] (4) Finally, since the digital signal output by the controller is 12 bits, the present invention uses the concept of multiplier to improve the resolution and speed by using the addition amplifier circuit. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit number is 81920 (3.3V / 40.2832uV), of which 81920 is greater than 16 bits (65536).

[0074] (5) It can be seen that by setting the attenuation gain value, the first attenuation ratio, the second attenuation ratio and the fine-tuning voltage division ratio, the resolution can be increased from 12 bits to more than 16 bits. Therefore, the present invention can indeed improve the resolution by setting the voltage division and the multiplier.

[0075] The fifth example: Suppose the adder amplifier circuit 4 is to output 1V, the controller's input voltage is 3.3V, the attenuation gain is 10, the first attenuation ratio is 1 / 10, the second attenuation ratio is 9 / 10, the fine-tuning voltage divider ratio is 1 / 10, and the controller's output resolution is 2 bits. 10 =1024, explained as follows: (1) The controller output mechanism is as follows: (a) Fine-tuning the output voltage to 0.1V (1*(1 / 10)), which is 0.33V (3.3*(1 / 10)). Adjusting the output to 0.1V, but because the fine-tuning voltage division ratio is 1 / 10, the output will be attenuated by 10 times. Therefore, the fine-tuning output voltage must be multiplied by 10, which is 1V. The fine-tuning is synthesized by 310 COUNTs (1 / 3.3*1024).

[0076] (b) The coarse adjustment output voltage is 0.9V (1*(9 / 10)), which is 2.97V (3.3*(9 / 10)). The output is adjusted to 0.9V, where the coarse adjustment is synthesized by 279 COUNTs (0.9 / 3.3*1024).

[0077] (2) The first analog voltage signal is 1V, and the input voltage is divided into 0.1V (1*1 / 10).

[0078] (3) The second analog voltage signal is 0.9V.

[0079] (4) Resolution voltage (i) First analog voltage signal with a resolution voltage of 97.656uV (0.1V / 1024).

[0080] (j) The second analog voltage signal has a resolution voltage of 0.8789mV (0.9V / 1024).

[0081] (5) Finally, since the digital signal output by the controller is 10 bits, the present invention uses the concept of multiplier to improve the resolution and speed by using the addition amplifier circuit. Therefore, after coarse adjustment and fine adjustment, the actual resolution bit number is 10240 (1V / 97.656uV), of which 10240 exceeds 13 bits (9192) and is close to 14 bits (16384).

[0082] (6) It can be seen that by setting the attenuation gain value, the first attenuation ratio, the second attenuation ratio and the fine-tuning voltage division ratio, the resolution can be increased from 10 bits to more than 13 bits. Therefore, the present invention can indeed improve the resolution by setting the voltage division and the multiplier.

[0083] This invention uses 10 bits as an example to simulate a voltage signal over 10 seconds to illustrate the resolution change. 10 bits is equivalent to 1024; however, to present this graphically, 1024 levels would need to be drawn. Therefore, this invention... Figure 3 As shown, the scale is represented by 10 levels, where the first nine levels represent nine-tenths and the last level represents one-tenth. Nine-tenths is used to represent coarse adjustments, and one-tenth represents fine adjustments.

[0084] As shown in the figure, nine-tenths of the signal represents the first analog voltage signal (DACout1) and the second analog voltage signal (DACout2) output by controller 1, while the last ten sub-orders represent the analog output signal of the adder amplifier circuit 4. If we assume the values ​​are as before, after calculation, we can finally obtain 10248, which is close to 14 bits (16384).

[0085] and Figure 3 The last segment in the diagram is presented in tenth order to make its changes clearer. However, in actual implementation, after filtering, the jagged edges of the tenth order will be filtered out, resulting in a linear structure.

[0086] Depend on Figure 3 As we can see, fine-tuning is used to add to coarse-tuning to increase resolution. Here, simulation can be used to express the full-scale state or the state before reaching the full scale. For example, if the output is 3.3V (full scale), 9 / 10 of 3.3V is coarse-tuning and 1 / 10 of 3.3V is fine-tuning; but if the output is 1.5V (50% of full scale), 9 / 10 of 1.5V is coarse-tuning and 1 / 10 of 1.5V is fine-tuning.

[0087] The present invention can also be applied to multiple sets of analog voltage signal outputs (first analog voltage signal, second analog voltage signal, third analog voltage signal... Nth analog voltage signal) to perform multi-stage and different proportion fine-tuning using multiple sets.

[0088] The digital-to-analog conversion device provided by this invention has the following advantages compared with other existing technologies: 1. This invention can change the attenuation gain value through adjustable voltage divider elements, and with the help of circuit design, achieve higher resolution and increased speed, thus making its application more widespread and flexible.

[0089] 2. The resolution of the circuit architecture of this invention after final integration is significantly higher than that of a single DAC. In addition, it can be synchronously adjusted through digitally adjustable resistors, which will help users meet their needs in different situations.

[0090] 3. The circuit architecture of this invention can reduce overall cost and achieve higher energy efficiency, which is impossible to achieve by using multiple conventional DACs.

[0091] The present invention has been disclosed above through the above embodiments, but it is not intended to limit the present invention. Any person skilled in the art, after understanding the foregoing technical features and embodiments of the present invention, may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of patent protection of the present invention shall be determined by the claims.

Claims

1. A digital-to-analog conversion device, characterized in that, At least including: A controller for outputting a first analog voltage signal and a second analog voltage signal; At least one first front-end circuit is electrically connected to the controller. The first front-end circuit includes at least a voltage divider and a first buffer. The voltage divider is electrically connected to the first buffer. The voltage divider is set with a fine-tuning voltage division ratio. The voltage divider is also used to receive the first analog voltage signal and output a fine-tuning output voltage according to the fine-tuning voltage division ratio. At least one second front-end circuit is electrically connected to the controller. The second front-end circuit includes at least one second buffer for receiving the second analog voltage signal and outputting a coarse-adjustment output voltage. An adder amplifier circuit is electrically connected to the first front-end circuit and the second front-end circuit to receive the fine-tuning output voltage and the coarse-tuning output voltage, and output an analog output signal based on the fine-tuning output voltage and the coarse-tuning output voltage. The controller is set with an attenuation gain value, and sets a first attenuation ratio and a second attenuation ratio based on the attenuation gain value. The first attenuation ratio is the reciprocal of the attenuation gain value, and the second attenuation ratio is 1 minus the first attenuation ratio. The second analog voltage signal is the first analog voltage signal multiplied by the second attenuation ratio, and the first attenuation ratio is equal to the fine-tuning voltage divider ratio.

2. The digital-to-analog conversion device as described in claim 1, characterized in that, The voltage divider has at least two resistive elements, and the voltage divider is set by the fine-tuning voltage division ratio through the at least two resistive elements.

3. The digital-to-analog conversion device as described in claim 1, characterized in that, The voltage divider has at least one resistive element and a resolution controller. The voltage divider sets the fine-tuning voltage division ratio through the at least one resistive element and the resolution controller. The resolution controller is electrically connected to the controller and adjusts the fine-tuning voltage division ratio synchronously according to the first attenuation ratio set by the controller.

4. The digital-to-analog conversion device as described in claim 3, characterized in that, The resolution controller is a digitally adjustable resistor element. When the controller changes the first attenuation ratio, the digitally adjustable resistor element adjusts its resistance value synchronously so that the fine-tuned voltage division ratio of the resistor element and the digitally adjustable resistor element is equal to the first attenuation ratio.

5. The digital-to-analog conversion device as described in claim 1, characterized in that, The first buffer has a first buffer gain value of 1.

6. The digital-to-analog conversion device as described in claim 1, characterized in that, The second buffer has a second buffer gain value of 1.

7. The digital-to-analog conversion device as described in claim 1, characterized in that, The first front-end circuit also includes a first filter connected between the voltage divider and the first buffer.

8. The digital-to-analog conversion device as described in claim 1, characterized in that, The first front-end circuit also has a second filter, which is electrically connected to the second buffer.

9. The digital-to-analog conversion device as described in claim 1, characterized in that, The fine-tuning output voltage is the first analog voltage signal multiplied by the fine-tuning voltage division ratio, while the coarse-tuning output voltage is equal to the second analog voltage signal.

10. The digital-to-analog conversion device as described in claim 1, characterized in that, The controller converts a digital signal into an analog signal and outputs the converted first analog voltage signal and the second analog voltage signal to the first front-end circuit and the second front-end circuit, respectively.

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