Self-interference elimination circuit

Abstract

The invention discloses a self-interference elimination circuit. The self-interference elimination circuit comprises an input attenuation module, a variable gain delay array and an output attenuation module. The input attenuation module is used for regulating and controlling the power of a self-interference signal generated by a transmitter; the variable gain time delay array is used for performing high-precision time delay frequency characteristic and amplitude frequency characteristic regulation and control on the self-interference signal; the output attenuation module is used for regulating and controlling the output power of the variable gain delay array; the self-interference elimination circuit establishes a self-interference elimination signal by simulating group delay, phase and amplitude response of a self-interference signal in a propagation process, and realizes self-interference elimination at a radio frequency front end. The self-interference elimination circuit can be used for self-interference elimination of the radio frequency front end and has the advantages of being large in delay range and high in adjustment precision.

Description

A self-interference cancellation circuit Technical Field

[0001] This invention belongs to the fields of wireless communication and electronic science and technology, and relates to a self-interference cancellation circuit. Background Technology

[0002] With the rapid development of wireless communication technology, spectrum resources are becoming increasingly scarce. To further improve spectrum utilization efficiency, full-duplex communication (FDC) has been proposed and has become an important development direction for future wireless communication systems. This technology allows the transmitter and receiver to operate simultaneously on the same frequency band and at the same time, theoretically doubling spectrum efficiency. However, in full-duplex systems, strong signals output by the transmitter can enter the receiver through antenna coupling, line leakage, and other paths, forming strong self-interference signals that can lead to decreased receiver sensitivity or even failure. Therefore, effectively eliminating self-interference at the radio frequency front end is one of the key technologies for realizing full-duplex communication.

[0003] In existing technologies, self-interference suppression methods are broadly classified into three categories: antenna isolation, radio frequency (RF) domain cancellation, and digital domain cancellation. Existing RF domain self-interference cancellation circuits still have several shortcomings. For example, some schemes are complex in structure and consume high power, making them difficult to implement in integrated systems; some schemes have limited delay and phase adjustment ranges, failing to effectively adapt to interference signals from different coupling paths; and some designs present a trade-off between bandwidth, adjustable accuracy, and circuit linearity, resulting in limited cancellation performance in broadband full-duplex systems.

[0004] The Gm-C N-Path filter proposed in the paper "Zhou J, Chuang TH, Dinc T, et al. 19.1 Receiver with > 20MHz bandwidth self-interference cancellation suitable for FDD, co-existence and full-duplex applications[C] / / 2015 IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers. IEEE, 2015: 1-3" achieves adjustable center frequency by introducing Gm-C units, thus enabling its application in broadband self-interference cancellation scenarios. However, the reliance on transconductance amplifiers in this scheme inevitably leads to higher power consumption and chip area overhead while achieving frequency tunability. In contrast, this invention, through a modular variable gain delay array structure, allows for flexible selection of different types of delay units and their combinations according to actual application requirements, effectively improving structural flexibility and implementation freedom while ensuring adjustment accuracy.

[0005] The literature “Kolodziej KE, Mcmichael JG, Perry BT. Multitap RF Canceller for In-Band Full-Duplex Wireless Communications[J].IEEE Transactions on Wireless Communications, 2016, 15(6):1-1” proposes a multi-tap design to cope with complex multipath self-interference environments. However, the injection noise of the receiver's low-noise amplifier gradually deteriorates with the increase of the number of taps. Furthermore, since each tap has independent weight adjustment capabilities, an excessive number of taps will cause great difficulties in the design of input matching. In contrast, this invention uses a variable gain delay array structure to flexibly adjust different tap structures and the number of taps, achieving flexible coverage of different delay ranges and amplitude characteristics, thereby achieving a better overall balance between delay accuracy, noise performance, and input matching.

[0006] The invention patent "A Wideband Full-Duplex Receiver with Shared Interference Cancellation Circuit" (CN116470924A, 2023.04.18) describes a dual-injection self-interference cancellation circuit, including an input matching network and an input downmixer, a quadrature selection phase shifter, and a baseband variable gain low-pass filter. This scheme transfers the delay and gain adjustment functions from the RF domain to the baseband, which is beneficial for obtaining a larger delay adjustment range and reducing implementation difficulty, but its delay adjustment accuracy is relatively limited. In contrast, this invention uses a variable gain delay array structure, which, through multi-stage delay units, achieves a wide range of delay adjustment while providing more precise delay step control, thereby significantly improving the matching accuracy of self-interference signals and the self-interference cancellation effect.

[0007] To address the limitations of existing self-interference cancellation circuits, such as limited adjustment range and poor adaptability, this invention provides a self-interference cancellation circuit. This circuit achieves joint compensation for the amplitude, phase, and delay of self-interference signals by introducing an input attenuation module, a variable gain delay array, and an output attenuation module. The circuit structure is modular and reconfigurable, allowing parameter configuration according to different communication frequency bands and coupling environments. This enables wide-bandwidth, high-precision, and adaptive self-interference cancellation at the RF front end, resulting in greater system flexibility. Summary of the Invention

[0008] Purpose of the invention: The purpose of this invention is to provide a self-interference cancellation circuit to solve the problem of the serious impact of self-interference signals on receiver performance in simultaneous full-duplex communication systems. This circuit establishes a high-precision self-interference cancellation signal by accurately simulating the group delay, phase, and amplitude response of the self-interference signal during propagation, thereby achieving efficient and wide-bandwidth interference cancellation at the radio frequency front end, thus improving spectrum utilization efficiency, system reliability, and communication quality.

[0009] To achieve self-interference cancellation in the radio frequency front-end circuit, the present invention adopts the following solution:

[0010] A self-interference cancellation circuit includes an input attenuation module, a variable gain delay array, and an output attenuation module. The input attenuation module regulates the power of the self-interference signal generated by the transmitter; the variable gain delay array precisely regulates the time delay and amplitude frequency characteristics of the self-interference signal; and the output attenuation module regulates the output power of the variable gain delay array. The self-interference cancellation circuit establishes a self-interference cancellation signal by simulating the group delay, phase, and amplitude response of the self-interference signal during propagation, thus achieving self-interference cancellation at the radio frequency front end. This invention can be used for self-interference cancellation in radio frequency front ends and has the advantages of a large delay range and high adjustment accuracy.

[0011] Preferably, the variable gain delay array includes n (n≥1) variable gain delay modules and a synthesis unit, and each variable gain delay module includes one or m (m≥1) delay units and gain adjustment units.

[0012] Furthermore, the variable gain delay module is composed of a delay unit and a gain adjustment unit connected in series.

[0013] Preferably, the variable gain delay array is composed of n (n≥1) variable gain delay modules connected in parallel. The input terminals of each variable gain delay module are connected together as the input terminal of the array, and the output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit. The output terminal of the synthesis unit serves as the output terminal of the variable gain delay array.

[0014] Preferably, the variable gain delay array is composed of n (n≥1) variable gain delay modules connected in a stepped manner. The input of variable gain delay module 1 serves as the input terminal of the array. The input terminal of variable gain delay module k is connected to the internal node of variable gain delay module k-1. This internal node is located after the delay unit in variable gain delay module k-1. The output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit. The output terminal of the synthesis unit serves as the output terminal of the variable gain delay array.

[0015] Preferably, the delay unit in the variable gain delay module consists of an RC-CR filter and a G m It can be composed of one or more of the following: -C active filter, N-Path filter, and TI N-Path filter.

[0016] Preferably, the RC-CR filter in the delay unit of the variable gain delay module is composed of a resistor (R) and a capacitor (C). When the capacitor and the resistor are connected in different series and parallel configurations, low-pass, high-pass, or band-pass filtering can be achieved.

[0017] Preferably, the delay unit G in the variable gain delay module m -C active filters consist of a transconductance amplifier and a capacitor (C). The signal is converted from input voltage to current through the transconductance unit, and then integrated by the capacitor to achieve low-pass, high-pass, or band-pass filtering.

[0018] Preferably, the N-Path filter in the delay unit of the variable gain delay module consists of N (N≥2) periodic switching channels and capacitors. The switches are periodically turned on at a clock frequency, so that the signal is sampled onto the capacitors in a time-division manner and then synthesized into an output.

[0019] Preferably, the TI N-Path filter in the delay unit of the variable gain delay module is based on the N-Path filter and introduces a time-interleaving extension structure to achieve sampling and synthesis with higher time resolution.

[0020] Preferably, the gain adjustment unit in the variable gain delay module is composed of one or more of a resistive attenuator, a capacitive attenuator, and a signal selection switch current attenuator;

[0021] Preferably, the resistive attenuator in the gain adjustment unit of the variable gain delay module uses a resistor as the core component and achieves signal attenuation through resistor voltage division or current division.

[0022] Furthermore, the resistive attenuator is composed of one or more of the following: a T-type resistive attenuator, a bridge T-type resistive attenuator, a Π-type resistive attenuator, and a Π-type attenuator based on an NMOS switching resistor;

[0023] Preferably, the T-type resistive attenuator consists of two transistors, two series resistors, and one parallel resistor.

[0024] Preferably, the bridge T-type attenuator consists of two transistors, two series resistors, one parallel resistor, and one bridging resistor.

[0025] Preferably, the Π-type attenuator consists of two transistors, two parallel resistors, and one series resistor.

[0026] Preferably, the Π-type attenuator based on NMOS switching resistors utilizes the variable on-resistance of MOSFETs under different gate control voltages to achieve continuous or graded adjustable attenuation control by switching multiple NMOS switching units or adjusting their gate bias.

[0027] Preferably, the capacitive attenuator in the gain adjustment unit of the variable gain delay module uses a capacitor as the core component and achieves attenuation through capacitive voltage division, which is effective for AC signals.

[0028] Preferably, the signal selection switch current attenuator in the gain adjustment unit of the variable gain delay module adjusts the attenuation amount by switching different attenuation networks.

[0029] Preferably, the self-interference cancellation circuit is integrated into a single chip, and the input attenuation module, the variable gain delay array (including the delay unit and gain adjustment unit in the variable gain delay module), and the output attenuation module are configured through a digital control unit.

[0030] Compared to existing technologies, this solution has the following advantages:

[0031] This invention addresses the problem of significant variations in the amplitude, phase, and delay of self-interference signals under complex coupling environments due to channel variations. It employs a variable gain delay array and an attenuation module to achieve high-precision joint compensation of the amplitude, phase, and delay of the self-interference signal, thereby achieving excellent self-interference cancellation capabilities over a wide frequency range. This scheme adjusts the input signal through the input attenuation module, ensuring the delay and gain adjustment units operate within a suitable linear region, avoiding large signal compression and improving system linearity and stability. The variable gain delay array jointly adjusts the delay and amplitude of the self-interference cancellation signal, matching the amplitude, phase, and group delay responses of the self-interference cancellation signal with the response of the self-interference coupling channel, thus improving the self-interference cancellation amount under broadband conditions. Compared to traditional schemes that only perform phase / amplitude adjustment or use baseband-side delay compensation, this invention offers advantages such as a large delay range, high step accuracy, high linearity, and wide frequency coverage, improving RF-end delay matching accuracy and enhancing broadband cancellation performance. This circuit can be widely used in scenarios with strong self-interference or strong coupling echoes, such as full-duplex communication, co-frequency transceiver, radar transceiver integration, and electronic countermeasures, to solve the problem of difficult self-interference suppression of RF front-end under spectrum congestion, coexistence, and complex multipath coupling conditions. Attached Figure Description

[0032] Figure 1 is a schematic diagram of the structure of a self-interference cancellation circuit according to the present invention.

[0033] Figure 2 shows the parallel structure of the variable gain delay array of the present invention.

[0034] Figure 3 shows the stepped structure of the variable gain delay array of the present invention.

[0035] Figure 4 shows the T-type resistor attenuator used in this invention.

[0036] Figure 5 shows the bridge T-type resistor attenuator used in this invention.

[0037] Figure 6 is a schematic diagram of an embodiment of the input attenuation module of the present invention.

[0038] Figure 7 shows the RC-CR filter used in this invention.

[0039] Figure 8 shows the G used in this invention. m -C filter,

[0040] Figure 9 is a schematic diagram of an embodiment of the delay unit of the variable gain delay module of the present invention.

[0041] Figure 10 is a schematic diagram of a second embodiment of the delay unit of the variable gain delay module of the present invention. Detailed Implementation

[0042] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0043] Figure 1 is a block diagram of a self-interference cancellation circuit according to the present invention. The self-interference cancellation circuit includes an input attenuation module, a variable gain delay array, and an output attenuation module. The input attenuation module regulates the power of the self-interference signal generated by the transmitter; the variable gain delay array performs high-precision regulation of the time delay frequency characteristics and amplitude frequency characteristics of the self-interference signal; the output attenuation module regulates the output power of the variable gain delay array; the self-interference cancellation circuit establishes a self-interference cancellation signal by simulating the group delay, phase, and amplitude response of the self-interference signal during propagation, thereby achieving self-interference cancellation at the radio frequency front end.

[0044] The variable gain delay array comprises n (n≥1) variable gain delay modules and a synthesis unit. Each variable gain delay module comprises one or m (m≥1) delay units and a gain adjustment unit.

[0045] A specific connection method of a variable delay array is shown in Figure 2. The variable gain delay array is composed of n (n≥1) variable gain delay modules connected in parallel. The input terminals of each variable gain delay module are connected together as the input terminal of the array. The output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit, and the output terminal of the synthesis unit serves as the output terminal of the variable gain delay array.

[0046] A specific connection method of a variable delay array is shown in Figure 3. The variable gain delay array is composed of n (n≥1) variable gain delay modules connected in a stepped manner. The input of variable gain delay module 1 serves as the input terminal of the array. The input terminal of variable gain delay module k is connected to the internal node of variable gain delay module k-1. This internal node is located after the delay unit in variable gain delay module k-1. The output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit. The output terminal of the synthesis unit serves as the output terminal of the variable gain delay array.

[0047] The delay unit of the variable gain delay module is composed of one or more of the following: RC-CR filter, Gm-C active filter, N-Path filter, and TI N-Path filter.

[0048] The gain adjustment unit of the variable gain delay module is composed of one or more of a resistive attenuator, a capacitive attenuator, and a signal selection switch current attenuator.

[0049] The variable gain delay module can be composed of any number of delay units and gain adjustment units connected in series.

[0050] Referring to the schematic diagram of an embodiment of the input attenuation module shown in Figure 6, the circuit consists of a series resistor. It consists of two symmetrical parallel branches, each with a fixed resistor. It is constructed by connecting an NMOS transistor in series. The input signal comes from... Duan Jing Transmit to Part of the signal is discharged to ground through parallel branches on both sides, thus achieving amplitude attenuation. This is achieved by adjusting the control voltage. It can change the on-resistance of the NMOS transistor, thereby changing the equivalent impedance of the parallel branch and achieving adjustable attenuation function.

[0051] Referring to the schematic diagram of the delay unit of the variable gain delay module shown in Figure 9, the principle of applying the N-Path filter to the delay is the switching of the sample-and-hold state of the switched capacitor. The group delay introduced in the circuit is caused by the two switching local oscillator signals φ. 𝑋 and φ 𝑋d The time delay between them is determined by the two sets of local oscillator clocks φ1~φ2 that control the switches of each branch of the N-Path filter. N and φ 1d ~φ Nd All are N-phase non-overlapping clocks with a duty cycle of 1 / N.

[0052] Referring to the schematic diagram of the second embodiment of the delay unit of the variable gain delay module shown in Figure 10, it is equivalent to a two-stage cascaded N-Path filter, which can significantly improve the delay range.

[0053] The above embodiments are merely illustrative of the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solutions based on the technical concept proposed in this invention shall fall within the scope of protection of this invention.

Claims

1. A self-interference cancellation circuit, characterized in that, It includes an input attenuation module, a variable gain delay array, and an output attenuation module; the input attenuation module regulates the power of the self-interference signal generated by the transmitter; the variable gain delay array performs high-precision regulation of the time delay frequency characteristics and amplitude frequency characteristics of the self-interference signal; and the output attenuation module regulates the output power of the variable gain delay array.

2. The self-interference cancellation circuit according to claim 1, characterized in that, The variable gain delay array comprises n (n≥1) variable gain delay modules and one synthesis unit. Each variable gain delay module contains one or m (m≥1) delay units and a gain adjustment unit. The variable gain delay array is composed of n (n≥1) variable gain delay modules connected in parallel. The input terminals of each variable gain delay module are connected together as the input terminal of the array. The output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit, and the output terminal of the synthesis unit serves as the output terminal of the variable gain delay array. The variable gain delay array is composed of n (n≥1) variable gain delay modules connected in a stepped manner. The input of variable gain delay module 1 serves as the input terminal of the array. The input terminal of variable gain delay module k is connected to an internal node of variable gain delay module k-1, which is located after the delay unit in variable gain delay module k-1. The output terminals of the n variable gain delay modules are connected to the input terminal of the synthesis unit, and the output terminal of the synthesis unit serves as the output terminal of the variable gain delay array.

3. The self-interference cancellation circuit according to claim 2, characterized in that, The variable gain delay module consists of a delay unit and a gain adjustment unit connected in series.

4. The self-interference cancellation circuit according to claim 3, characterized in that, The delay unit consists of an RC-CR filter and a G m The filter is composed of one or more of the following: an RC-CR active filter, an N-Path filter, and a TI N-Path (Time-Interleaved N-Path) filter. The RC-CR filter consists of a resistor (R) and a capacitor (C) to achieve low-pass, high-pass, or band-pass filtering. m The -C active filter consists of a transconductance amplifier and a capacitor (C). The signal is converted from input voltage to current through the transconductance unit, and then integrated by the capacitor to achieve low-pass, high-pass, or band-pass filtering. The N-Path filter consists of N (N≥2) periodic switching channels and capacitors. The switches are periodically turned on at a clock frequency, so that the signal is sampled onto the capacitors in a time-division manner and then synthesized into an output. The TI N-Path filter introduces a time-interleaving extension structure on the basis of the N-Path filter to achieve sampling and synthesis with higher time resolution.

5. The self-interference cancellation circuit according to claim 3, characterized in that, The gain adjustment unit is composed of one or more of a resistive attenuator, a capacitive attenuator, and a signal selection switch current attenuator; the resistive attenuator uses a resistor as the core element and achieves signal attenuation through resistive voltage division or current division; the capacitive attenuator uses a capacitor as the core element and achieves attenuation through capacitive voltage division, which is effective for AC signals; the signal selection switch current attenuator adjusts the attenuation amount by switching different attenuation networks.

6. The self-interference cancellation circuit according to claim 5, characterized in that, The resistive attenuator consists of a T-type resistive attenuator, a bridge T-type resistive attenuator, and... The attenuator is composed of one or more of the following: a T-type resistor attenuator and a Π-type attenuator based on NMOS switching resistors; the T-type resistor attenuator consists of two transistors, two series resistors, and one parallel resistor; the bridge T-type attenuator consists of two transistors, two series resistors, one parallel resistor, and one bridging resistor. The Π-type resistor attenuator consists of two transistors, two parallel resistors, and one series resistor. The Π-type attenuator based on NMOS switching resistors utilizes the variable on-resistance of MOSFETs under different gate control voltages to achieve continuous or graded adjustable attenuation control by switching multiple NMOS switching units or adjusting their gate bias.

7. The self-interference cancellation circuit according to claim 1, characterized in that, The input attenuation module and the output attenuation module are composed of one or more of the following: resistive attenuator, capacitive attenuator, and signal selection switch current attenuator.

8. The self-interference cancellation circuit according to claim 1, characterized in that, The self-interference cancellation circuit is integrated into a single chip, and the input attenuation module, variable gain delay array, and output attenuation module are configured through a digital control unit; the variable gain delay array includes a delay unit and a gain adjustment unit in the variable gain delay module.

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