Integrated circuit and method for controller area network communication

Abstract

The invention relates to an integrated circuit and a method for controller area network communication. According to one aspect, an integrated circuit includes a digital processing unit (MCU), a transceiver circuit (TRC) configured to transmit data between the MCU and a controller area network (CAN) data bus, the transceiver circuit being configured to transmit differential signals CANH and CANL according to a dominant mode and a recessive mode, and an adjustment circuit (ADPC) configured to adjust the differential signals CANH and CANL according to the dominant mode and the recessive mode. Each transition of the differential signals CANH and CANL between the dominant mode and the recessive mode is synchronized using an adaptation bit received by the transceiver circuit; an adjustment circuit (ADPC) is used to adjust at least one adaptation bit as a function of at least one comparison between a common mode of the differential signals CANH and CANL and at least one threshold voltage.

Description

Integrated circuits and methods for controller area network communication Cross-references to related applications

[0001] This application claims the benefit of French patent application No. 2411927, filed on October 31, 2024, which is hereby cited and incorporated herein by reference. Technical Field

[0002] The embodiments and implementations relate to communication via a Controller Area Network (CAN) bus. Background Technology

[0003] The CAN protocol is commonly used in automotive vehicles to manage communication between various electronic devices such as sensors, actuators, and control units. Therefore, a CAN network is defined among these various electronic devices connected together via a CAN bus. Each electronic device thus forms a node in the CAN network.

[0004] The CAN bus consists of two lines configured to transmit two signals, CANH (CAN high) and CANL (CAN low), between nodes in a CAN network. The CANH and CANL signals are generated by the transceiver circuitry of various electronic devices within the CAN network.

[0005] The CAN bus can operate in either dominant or recessive mode.

[0006] In dominant mode, the potential difference between signals CANH and CANL is high. Specifically, signal CANH reaches a high level of 3.5 volts, and signal CANL reaches a low level of 1.5 volts.

[0007] In recessive mode, the levels of signals CANH and CANL converge to around 2.5 volts, thereby reducing the potential difference.

[0008] However, when the operating mode changes, a time shift may occur between the CANH and CANL signals.

[0009] This time shift may cause brief pulses (or glitches) on the common mode of signals CANH and CANL. Relative to a common reference point, such as ground, the common mode of signals “CANH” and “CANL” corresponds to the common voltage component of the two signal lines. Therefore, the common mode can correspond to the average voltage of signals CANH and CANL.

[0010] These brief pulses can interfere with the operation of the CAN bus. For example, such interference can increase unwanted electromagnetic radiation or interference (EMI) on the CAN bus. This EMI can affect nearby electronic circuitry. Furthermore, the interference can be amplified depending on temperature.

[0011] Therefore, a solution is needed to improve communication in CAN networks by reducing interference that can lead to particularly undesirable electromagnetic radiation. Summary of the Invention

[0012] According to one aspect, an integrated circuit is proposed, comprising: a digital processing unit, particularly a microcontroller; transceiver circuitry configured to transmit data between the digital processing unit and a controller area network (CAN) data bus, the transceiver circuitry being configured to transmit differential signals referred to as CANH and CANL according to a dominant mode and a recessive mode, each transition of the differential signals CANH and CANL between the mode and the recessive mode being synchronized using an adapter bit received by the transceiver circuitry; and circuitry for adjusting at least one adapter bit based on at least one comparison between the common mode of the differential signals CANH and CANL and at least one threshold voltage.

[0013] This adjustment circuit reduces common-mode interference to signals CANH and CANL by adjusting the adapter bits, thereby optimizing the synchronization of signals CANH and CANL. Therefore, this adjustment circuit can limit unwanted electromagnetic radiation (EMI) from the CAN bus caused by common-mode interference signals to CANH and CANL.

[0014] Furthermore, this adjustment circuit has the advantage of being unaffected by temperature changes. This is because the adjustment circuit automatically adjusts itself when temperature drift occurs due to the common mode of the monitoring signals CANL and CANH.

[0015] In an advantageous embodiment, the adjustment circuit includes: a detection circuit configured to detect common-mode interference to the differential signals CANH and CANL; and a processing circuit configured to adjust at least one adapter bit when the detection circuit detects common-mode interference.

[0016] Advantageously, the digital processing unit is configured to transmit control signals indicating the modes of the CANL and CANH signals. The processing circuit is then configured to receive the control signals so as to adapt at least one adaptation bit associated with the mode transition of the CANL and CANH signals, corresponding to the mode indicated by the control signals, when the detection circuit detects interference.

[0017] Preferably, the detection circuit is configured to receive signals CANH and CANL, and includes: a first resistive element and a second resistive element, connected in series and configured to receive signals CANL and CANL to obtain the common mode of these signals CANL and CANL at a common node between the first and second resistive elements; a third resistive element and a fourth resistive element; a current source connected in series between the common node of the first and second resistive elements and a reference node, particularly to ground; a low-pass filter whose input is connected to the common node between the third and fourth resistive elements to generate a threshold voltage as an output for monitoring the common mode of signals CANL and CANL; a first comparator having a first input connected to the common node between the first and second resistive elements and a second input connected to the output of the low-pass filter; a second comparator having a first input connected to the common node between the fourth resistive element and the current source and a second input connected to the output of the low-pass filter; and an adder circuit having two inputs respectively connected to the outputs of the first and second comparators, and an output connected to the processing circuit.

[0018] This detection circuit is simple and occupies very little space in the integrated circuit.

[0019] Advantageously, the processing circuitry includes: a first counter configured to increment whenever the detection circuitry detects common-mode interference during a transition to a dominant mode, the value of the first counter defining at least one adapter bit for the transition to a dominant mode; and a second counter configured to increment whenever the detection circuitry detects common-mode interference during a transition to a recessive mode, the value of the second counter defining at least one adapter bit for the transition to a recessive mode.

[0020] In an advantageous embodiment, the processing circuitry includes an event monitoring circuitry connected to the output of the detection circuitry and configured to increment a first counter or a second counter according to the pattern of signals CANH and CANL indicated by a control signal transmitted by the digital processing unit whenever an interference is detected.

[0021] In another aspect, an electronic device is proposed, comprising the integrated circuit described above. Such an electronic device can be integrated into a CAN network. Attached Figure Description

[0022] Other advantages and features of the invention will become apparent from reading the detailed description of the non-limiting embodiments and from the accompanying drawings, wherein:

[0023] Figure 1 shows an electronic device configured to operate in a CAN network;

[0024] Figure 2 shows the signals CANH and CANL according to the dominant and recessive modes;

[0025] Figure 3 shows the adjustment circuit, which includes interference detection circuit and processing circuit;

[0026] Figure 4 shows a first embodiment of the interference detection circuit;

[0027] Figure 5 illustrates a second embodiment of the interference detection circuit; and

[0028] Figure 6 illustrates an embodiment of the processing circuit. Detailed Implementation

[0029] Figure 1 illustrates an electronic device (DIS) configured to operate within a Controller Area Network (CAN) network. The electronic device (DIS) can thus form nodes within the CAN network. Examples of electronic devices (DIS) include components of a motor vehicle: ECU, ABS box, dashboard, etc.

[0030] Electronic device DIS includes integrated circuits (ICs). The ICs include digital processing units (MCUs), such as microcontrollers (MCUs), and transceiver circuits (TRCs) for implementing CAN communication. Specifically, the TRCs are configured to be connected to the CAN bus that connects the various nodes of the CAN network.

[0031] Specifically, the transceiver circuit TRC can operate during transmission. In this case, the transceiver circuit is configured to receive data DAT provided by the digital processing unit (MCU) for transmission to the CAN bus.

[0032] The transceiver circuit TRC can operate during reception. In this case, the transceiver circuit is configured to receive data from the CAN bus in order to transmit the data to the digital processing unit microcontroller.

[0033] The transceiver circuit TRC is configured to control signals CANH and CANL based on either the dominant or recessive mode. The dominant and recessive modes are defined by the digital processing unit (MCU), specifically via the control signal TX.

[0034] Figure 2 illustrates the signals CANH and CANL according to the dominant mode D_MOD and the recessive mode R_MOD. The offset of signals CANH and CANL can cause common-mode interference to both signals. This offset can occur during the T_D, T_R transitions between the dominant mode D_MOD and the recessive mode R_MOD. This interference can potentially generate unwanted electromagnetic radiation on the CAN bus.

[0035] With respect to a common reference point, such as ground, the common mode of signals “CANH” and “CANL” corresponds to the common voltage component of the two signal lines. Therefore, the common mode can correspond to the average voltage of signals CANH and CANL.

[0036] To limit the timing of the transitions between dominant and recessive modes for signals CANH and CANL, the transceiver circuit TRC is configured to receive at least one digital adapter signal, TRM_R, TRM_D, for adjusting the transitions of signals CANH and CANL. Specifically, digital signal TRM_R can be used for the transition from CANH and CANL to recessive mode, and digital signal TRM_D can be used for the transition from CANH and CANL to dominant mode. Each digital adapter signal, TRM_R, TRM_D, can be transmitted by the digital processing unit (MCU). Each digital adapter signal, TRM_R, TRM_D, includes several adapter bits. These adapter bits can also be specified using the term "fine-tuning bits." These adapter bits are used to adjust the edges of signals CANH and CANL for the transitions between dominant and recessive modes.

[0037] The transceiver circuitry takes into account each digital adapter signal to adjust signals CANH and CANL, thereby synchronizing the voltage level transitions of signals CANH and CANL. For example, this adjustment can be performed via a timing circuit of the transceiver circuitry TLC, which can be configured by the adapter bits.

[0038] Specifically, the integrated circuit also includes the ADPC circuit for adjusting the adapter bit.

[0039] The ADPC circuit for adjusting the adapter bits is configured to adjust at least one adapter bit, specifically multiple adapter bits, such that the common mode of signals CANH and CANL is kept within a single envelope. For example, the ADPC circuit is configured to adjust the adapter bit BTS_R of the digital adjustment signal TRM_R and the adapter bit BTS_D of the digital adjustment signal TRM_D. The adapter bit BTS_R can correspond to the N least significant bits of the digital adjustment signal TRM_R. The adapter bit BTS_D can correspond to the N least significant bits of the digital adjustment signal TRM_D. To modify the digital adapter signals TRM_R and TRM_D, as shown in the figure, the adapter bits BTS_R and BTS_D can be transmitted to the digital processing unit. In a variant, the adapter bits can be directly transmitted to the transceiver circuit TRC. In this configuration, the digital processing unit (MCU) can simply transmit the K most significant bits of signals TRM_D and TRM_R to the transceiver circuit TRC, where K equals MN, and M is the total number of adaptive bits in the adaptive signals TRM_R or TRM_D. These K adaptation bits can be stored in non-volatile memory NVM, accessible to the MCU in read-only mode. In this configuration, the MCU can only transmit these K most significant bits to the transceiver circuit TRC, which then combines them with the N least significant bits to form the digital adaptation signals TRM_R or TRM_D.

[0040] As shown in Figure 3, in order to adjust the adapter position, the adjustment circuit ADPC includes the interference detection circuit DETC and the processing circuit PRC.

[0041] The interference detection circuit DETC is configured to receive the signals CANH and CANL transmitted by the transceiver circuit TRC as inputs, and determine whether synchronization adjustment is needed by monitoring the common mode of the signals CANH and CANL. Specifically, the interference detection circuit ADPC is configured to detect interference, particularly glitches, in the common mode of the signals CANH and CANL.

[0042] The processing circuit PRC is configured to adjust the value of at least one adapter bit when synchronization correction of signals CANL and CANH is required. More specifically, the processing circuit PRC is configured to adjust the adapter bit when common-mode interference to signals CANL and CANH is detected.

[0043] The processing circuit PRC is configured to determine whether it is necessary to correct the dominant mode of the recessive mode. To this end, the processing circuit PRC is configured to receive a control signal TX. As previously described, this control signal TX indicates whether the electronic device DIS is in a dominant or recessive mode. This control signal TX is generated by the digital processing unit. For example, when TX equals "0", the electronic device DIS is in a dominant mode, and when TX equals "1", the electronic device DIS is in a recessive mode.

[0044] Therefore, when the processing circuit PRC detects that synchronization correction is required when the control signal TX indicates that the electronic device DIS is in dominant mode, it means that the dominant mode requires synchronization correction of signals CANL and CANH.

[0045] Similarly, when the processing circuit PRC detects that synchronization correction is required when the information signal TX indicates that the electronic device DIS is in recessive mode, it means that the synchronization of signals CANL and CANH needs to be corrected in recessive mode.

[0046] This adjustment circuit, ADPC, reduces common-mode interference to CANH and CANL signals by adjusting the adapter bits to achieve optimal synchronization. Therefore, ADPC can limit unwanted electromagnetic radiation from the CAN bus caused by common-mode interference to CANH and CANL signals.

[0047] Furthermore, the ADPC adjustment circuit has the advantage of being unaffected by temperature changes. This is because the ADPC adjustment circuit automatically adjusts itself when temperature drift occurs due to common-mode interference between the monitoring signals CANL and CANH.

[0048] Figure 4 shows a first embodiment of the interference detection circuit DETC.

[0049] The interference detection circuit DETC includes a first resistive element R1, which has a first terminal configured to receive the signal CANL.

[0050] The interference detection circuit DETC also includes a second resistor element R2, which has a first terminal configured to receive the signal CANH.

[0051] The first resistive element R1 and the second resistive element R2 each have a second end that is connected to a common node of the adjustment circuit.

[0052] Advantageously, the first resistive element R1 and the second resistive element R2 have the same ohmic value. This allows a voltage corresponding to the common-mode voltage to be obtained at the common node between the first resistive element R1 and the second resistive element R2. Preferably, the values ​​of the first resistive element R1 and the second resistive element R2 are chosen to avoid interfering with CAN communication. Specifically, the value is chosen to be an order of magnitude larger than the differential resistance of the CAN bus in recessive mode.

[0053] The interference detection circuit DETC also includes a third resistor element R3, having a first end that is connected to a common node between the first resistor element R1 and the second resistor element R2.

[0054] The interference detection circuit DETC also includes a fourth resistive element R4. This fourth resistive element R4 has a first terminal that is connected to the second terminal of the third resistive element R3.

[0055] The interference detection circuit DETC also includes a current source CS, which has a first end connected to the second terminal of the fourth resistive element R4 and a second end connected to a reference node. This reference node can specifically be connected to ground. Preferably, the current limited by the current source is relatively low to avoid excessive current consumption on the CANL and CANH signals, which could affect CAN communication.

[0056] Therefore, the third resistor element R3, the fourth resistor element R4, and the current source CS are connected in series between the common node between the first resistor element R1 and the second resistor element R2 and the reference node to which the second end of the current source CS is connected.

[0057] The values ​​of the third resistor R3 and the fourth resistor R4 are determined based on the envelope required to detect common-mode interference to signals CANL and CANH. These values ​​may be the same or different.

[0058] Specifically, the third resistor R3 and the fourth resistor R4 can define a voltage VMID at the first terminal of the third resistor R3 and a voltage VB at the second terminal of the fourth resistor R4.

[0059] The voltage VMID corresponds to the common-mode voltage.

[0060] The voltage VB corresponding to the common-mode voltage minus the threshold voltage, for example, 200 millivolts.

[0061] The interference detection circuit includes a low-pass filter LPF. The input of the low-pass filter LPF is connected to the second terminal of the third resistor R3 and the first terminal of the fourth resistor R4.

[0062] The low-pass filter LPF has an output configured to deliver a voltage VA. The voltage VA corresponds to the common-mode voltage minus a threshold voltage, such as 100 millivolts.

[0063] The output of the low-pass filter LPF is connected to two comparators CMP1 and CMP2 to generate the inverse envelope of the common mode for monitoring signals CANL and CANH.

[0064] Specifically, the interference detection circuit DETC includes a first voltage comparator CMP1. The first comparator CMP1 has a first input, specifically an inverting input, which is connected to the first terminal of the third resistor element R3 to receive the voltage VMID.

[0065] The first comparator CMP1 also has a second input, specifically a non-inverting input, which is connected to the output of the low-pass filter LPF, and more specifically, to the output of the low-pass filter LPF in order to receive the voltage VA.

[0066] The first comparator CMP1 has an output configured to transmit a voltage corresponding to the difference between voltage VA and voltage VMID.

[0067] The interference detection circuit DETC also includes a second voltage comparator CMP2. This second comparator CMP2 has a first input, specifically an inverting input, which is connected to the output of a low-pass filter LPF, and more specifically, to receive the voltage VA.

[0068] The second comparator CMP2 also has a second input, specifically a non-inverting input, which is connected to the second terminal of the fourth resistor R4 and the first terminal of the current source CS to receive the voltage VB.

[0069] The second comparator CMP2 has an output configured to transmit a voltage corresponding to the difference between voltage VA and voltage VMID.

[0070] The first comparator CMP1 and the second comparator CMP2 are capable of comparing the common mode of signals CANH and CANL with the defined inverse envelope. Advantageously, comparators CMP1 and CMP2 are implemented in an integrated circuit IC to detect the transition between dominant and recessive modes sufficiently quickly.

[0071] The interference detection circuit DETC also includes an adder circuit ADD, which is configured to add the signal output from the first comparator CMP1 to the signal output from the second comparator CMP2. Specifically, the adder circuit ADD has a first input connected to the output of the first comparator CMP1 and a second input connected to the output of the second comparator CMP2.

[0072] The adder circuit ADD can detect glitches, which are short pulses (positive or negative) that leave the defined envelope on the common mode. Therefore, the adder circuit ADD can detect whether synchronization correction for signals CANL and CANH is required. Figure 2 shows an example of the signal that can be obtained at the output of the adder circuit ADD.

[0073] Figure 5 shows a second embodiment of the interference detection circuit DETC.

[0074] The second embodiment differs from the first embodiment in that it defines an envelope rather than an inverse envelope. This is because two low-pass filters, LPF1 and LPF2, are used to define the common-mode envelope of the monitoring signals CANH and CANL, instead of using a single low-pass filter, LPF, to define the inverse envelope.

[0075] Therefore, the first low-pass filter LPF1 has an input connected to the first terminal of the third resistor element R3, and an output connected to the input of the first comparator CMP1. This first low-pass filter LPF1 is capable of defining a first voltage threshold for the envelope.

[0076] The second low-pass filter LPF2 has an input connected to the second terminal of the fourth resistor element R4, and an output connected to the input of the second comparator CMP2. This second low-pass filter LPF2 is capable of defining a second voltage threshold for the envelope.

[0077] The first comparator CMP1 and the second comparator CMP2 are then configured to receive the common mode of signals CANH and CANL when connected to the second terminal of the third resistor element R3 and the first terminal of the fourth resistor element R4.

[0078] Compared to the second embodiment, the first embodiment of the interference detection circuit DETC shown in FIG4 has the advantage of occupying less space in the integrated circuit because a single low-pass filter LPF is used instead of two low-pass filters LPF1 and LPF2.

[0079] Figure 6 illustrates an embodiment of the processing circuit PRC. The processing circuit PRC includes an event monitoring circuit EVTD and two counters, CNT_R and CNT_D.

[0080] The event monitoring circuit EVTD is connected to the output of the adder circuit ADD to detect whether the value of the adjustment bit is adjusted according to the value output from the adder circuit.

[0081] The event monitoring circuit EVTD may include, for example, a trigger configured to be reinitialized each time the control signal TX changes to a dominant mode and each time it changes to a recessive mode.

[0082] Based on the modes of the signals CANH and CANL indicated by the control signal TX, when synchronization correction is required, the value of the adjustment bit can be adjusted by the event monitoring circuit EVTD incrementing the counter CNT_R or counter CNT_D.

[0083] Specifically, the counter CNT_D is used to adjust the adapter bit of the dominant mode, and the counter CNT_R is used to adjust the adapter bit of the recessive mode.

[0084] The value of each counter can limit the adaptation bit to be adjusted.

[0085] For example, each digital adapter signal TMR_R or TMR_D includes M adapter bits. Each counter can be an N-bit counter capable of adapting the N least significant bits of the digital adapter signal TMR_R or TMR_D, where N is less than M. Each adapter signal TMR_R or TMR_D may also include K most significant bits stored in non-volatile memory, where K equals MN.

[0086] When interference on the common mode of signals CANH and CANL is detected, specifically during the transition to the dominant mode, the value of the counter CNT_D associated with the dominant mode can be incremented.

[0087] When common-mode interference to signals CANH and CANL is detected, specifically during the transition to recessive mode, the value of the counter CNT_R associated with the recessive mode can be incremented.

[0088] This processing circuit, PRC, can easily adjust the adapter bit.

Claims

1. An integrated circuit comprising: a digital processing unit; transceiver circuitry configured to transmit data between the digital processing unit and a controller area network (CAN) data bus, the transceiver circuitry configured to transmit differential signals CAN high CANH and CAN low CANL according to a dominant mode and a recessive mode, the differential signals CANH and CANL being synchronized using an adapter bit received by the transceiver circuitry for each transition between the dominant mode and the recessive mode; and an adjustment circuitry configured to adjust at least one adapter bit according to at least one comparison between the common mode of the differential signals CANH and CANL and at least one threshold voltage.

2. The integrated circuit of claim 1, wherein the adjustment circuit is configured to be automatically adjusted in response to temperature drift.

3. The integrated circuit of claim 1, wherein the adjustment circuit comprises: a detection circuit configured to detect common-mode interference to the differential signals CANH and CANL; and a processing circuit configured to adjust the at least one adapter bit in response to the detection circuit detecting the common-mode interference.

4. The integrated circuit of claim 3, wherein the digital processing unit is configured to transmit a control signal indicating the mode of the differential signals CANL and CANH, and wherein the processing circuit is configured to receive the control signal in order to adapt the at least one adaptation bit associated with the transition to the mode of the differential signals CANL and CANH corresponding to the mode indicated by the control signal in response to the detection circuit detecting the interference.

5. The integrated circuit of claim 4, wherein the detection circuit is configured to receive the differential signals CANH and CANL, and comprises: a first resistive element and a second resistive element, connected in series and configured to receive the differential signals CANL and CANL to obtain the common mode of the differential signals CANL and CANL at a common node between the first resistive element and the second resistive element; A third resistive element, a fourth resistive element, and a current source, wherein the current source is connected in series between the common node of the first resistive element and the second resistive element and the reference node; A low-pass filter having an input connected to a common node between the third and fourth resistive elements to generate a threshold voltage at the output for monitoring the common mode of the differential signals CANH and CANL; The first comparator has a first input connected to the common node between the first resistive element and the second resistive element, and a second input connected to the output of the low-pass filter; The second comparator has a first input connected to a common node between the fourth resistive element and the current source, and a second input connected to the output of the low-pass filter; And an adder circuit having two inputs that are respectively connected to the outputs of the first comparator and the second comparator, and an output that is connected to the processing circuit.

6. The integrated circuit of claim 4, wherein the processing circuitry comprises: a first counter configured to increment in response to the detection circuitry detecting a first interference to the common mode during a transition to a dominant mode, a first value of the first counter defining at least one first adapter bit for the transition to the dominant mode; and a second counter configured to increment in response to the detection circuitry detecting a second interference to the common mode during a transition to the recessive mode, a second value of the second counter defining at least one second adapter bit for the transition to the recessive mode.

7. The integrated circuit of claim 6, wherein the processing circuit includes an event monitoring circuit connected to the output of the detection circuit and configured to increment the first counter or the second counter in response to the detection of the interference, according to the pattern of the differential signals CANH and CANL indicated by the control signal transmitted by the digital processing unit.

8. An electronic system comprising: a controller area network (CAN) data bus; a first electronic device coupled to the CAN data bus; a second electronic device coupled to the CAN data bus, wherein each electronic device includes an integrated circuit, the integrated circuit including: a digital processing unit; transceiver circuitry configured to transmit data between the digital processing unit and the CAN data bus, the transceiver circuitry being configured to transmit differential signals CAN high CANH and CAN low CANL according to a dominant mode and a recessive mode, each transition of the differential signals CANH and CANL between the dominant mode and the recessive mode being synchronized using an adapter bit received by the transceiver circuitry; and an adjustment circuitry configured to adjust at least one adapter bit according to at least one comparison between the common mode of the differential signals CANH and CANL and at least one threshold voltage.

9. The integrated circuit of claim 8, wherein the adjustment circuit is configured to automatically adjust temperature drift.

10. The electronic system of claim 8, wherein the adjustment circuit comprises: a detection circuit configured to detect common-mode interference to the differential signals CANH and CANL; and a processing circuit configured to adjust the at least one adapter bit in response to the detection circuit detecting the common-mode interference.

11. The electronic system of claim 10, wherein the digital processing unit is configured to transmit a control signal indicating the mode of the differential signals CANL and CANH in response to the detection circuit detecting the interference, and wherein the processing circuit is configured to receive the control signal to adapt the at least one adaptation bit associated with the transition to the mode of the differential signals CANL and CANH corresponding to the mode indicated by the control signal.

12. The electronic system of claim 11, wherein the detection circuit is configured to receive the differential signals CANH and CANL, and comprises: a first resistive element and a second resistive element, connected in series and configured to receive the differential signals CANL and CANL to obtain the common mode of the differential signals CANL and CANL at a common node between the first resistive element and the second resistive element; A third resistive element, a fourth resistive element, and a current source, wherein the current source is connected in series between the common node of the first resistive element and the second resistive element and the reference node; A low-pass filter having an input connected to a common node between the third and fourth resistive elements to generate a threshold voltage at the output for monitoring the common mode of the differential signals CANH and CANL; A first comparator has a first input connected to the common node between the first resistive element and the second resistive element, and a second input connected to the output of the low-pass filter; The second comparator has a first input connected to a common node between the fourth resistive element and the current source, and a second input connected to the output of the low-pass filter; And an adder circuit having two inputs that are respectively connected to the outputs of the first comparator and the second comparator, and an output that is connected to the processing circuit.

13. The electronic system of claim 11, wherein the processing circuitry comprises: a first counter configured to increment in response to the detection circuitry detecting a first interference to the common mode during a transition to a dominant mode, a first value of the first counter defining at least one first adapter bit for the transition to the dominant mode; and a second counter configured to increment in response to the detection circuitry detecting a second interference to the common mode during a transition to the recessive mode, a second value of the second counter defining at least one second adapter bit for the transition to the recessive mode.

14. The electronic system of claim 13, wherein the processing circuitry includes an event monitoring circuitry connected to the output of the detection circuitry and configured to increment the first counter or the second counter in response to the detection of the interference, according to the pattern of the differential signals CANH and CANL indicated by the control signal transmitted by the digital processing unit.

15. A method of operating an integrated circuit, the method comprising: transmitting data between a digital processing unit and a controller area network (CAN) data bus via transceiver circuitry, the transmission comprising: transmitting differential signals CAN high CANH and CAN low CANL according to a dominant mode and a recessive mode; receiving an adapter bit; and synchronizing the differential signals CANH and CANL with the adapter bit for each transition between the dominant mode and the recessive mode; comparing the common mode of the differential signals CANH and CANL with at least one threshold voltage by an adjustment circuit; and adjusting at least one adapter bit by the adjustment circuit based on the comparison.

16. The method of claim 15, further comprising automatically adjusting the adjustment circuit for temperature drift.

17. The method of claim 15, further comprising: detecting common-mode interference to the differential signals CANH and CANL by a detection circuit of the adjustment circuit; and adjusting the at least one adapter bit by a processing circuit of the adjustment circuit in response to the detection.

18. The method of claim 17, further comprising: transmitting a control signal indicating the mode of the differential signals CANL and CANH by the digital processing unit; and receiving the control signal by the processing circuitry to adapt the at least one adaptation bit associated with the transition to the mode corresponding to the mode of the differential signals CANL and CANH indicated by the control signal in response to the detection.

19. The method of claim 18, further comprising: incrementing a first counter of the processing circuit in response to the detection circuit detecting a first interference to the common mode during a transition to the dominant mode, a first value of the first counter defining at least one first adapter bit for the transition to the dominant mode; and incrementing a second counter of the processing circuit in response to the detection circuit detecting a second interference to the common mode during a transition to the recessive mode, a second value of the second counter defining at least one second adapter bit for the transition to the recessive mode.

20. The method of claim 19, further comprising, in response to the detection of the interference, the event monitoring circuit of the processing circuit incrementing the first counter or the second counter according to the pattern of the differential signals CANH and CANL indicated by the control signal transmitted by the digital processing unit.

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