Image encryption and decryption method and device based on RISC-V, equipment, storage medium and computer program product

Abstract

The invention relates to the technical field of digital images, in particular to an image encryption and decryption method and device based on RISC-V, equipment, a storage medium and a computer program product. According to the method, an initial key is written into a coprocessor based on a preset extension instruction, and the internal state of the chaotic system is configured based on the initial key; based on the internal state of the chaotic system, sponge iteration is carried out, a random sequence is generated, and an image abstract is output; writing the storage position information of the plaintext image into a coprocessor, and enabling the coprocessor to read the plaintext image pixel by pixel in a direct storage access mode to obtain a pixel stream; in the coprocessor, performing reversible confusion operation and reversible diffusion operation on the sequence of the pixel flow to obtain a processed pixel flow; and in a decryption stage, an internal state which is the same as that of the chaotic system is constructed based on the image abstract, and the processed pixel stream is subjected to reverse operation according to the same hardware logic which is multiplexed in a reverse order, so that the original pixel stream is obtained, and the efficiency of image encryption and decryption is improved.

Description

Technical Field

[0001] This application relates to the field of digital image technology, and in particular to an image encryption and decryption method, apparatus, device, storage medium, and computer program product based on RISC-V. Background Technology

[0002] With the widespread adoption of the internet, multimedia terminals, and edge computing devices, the security requirements for image data during acquisition, storage, transmission, and sharing are becoming increasingly prominent. To prevent unauthorized access or tampering of image content, existing technologies typically employ image encryption by obfuscating (scrambling) and spreading (changing pixel values) image pixels, followed by inverse operations during decryption to recover the original image. To enhance security and randomness, some solutions also introduce mechanisms such as chaotic systems, pseudo-random sequence generation, and digest / hash verification to generate random sequences and verify data integrity. However, existing image encryption and decryption implementations mainly fall into two categories: pure software implementations and dedicated hardware implementations. Pure software implementations typically rely on general-purpose processors to perform chaotic iteration, random sequence generation, pixel-level obfuscation and diffusion, and their inverse operations. When dealing with high-resolution images or real-time scenarios, they are susceptible to high computational loads and memory access overhead, resulting in high end-to-end processing latency and making it difficult to meet the business requirements with high real-time demands. While dedicated hardware implementations can improve throughput through parallel computing, common designs often rely on fixed algorithms and rigid computation paths, lacking flexibility. Furthermore, since encryption and decryption are inverse processes, using different computational logic or configuring separate decryption paths can lead to the need for separate encryption and decryption modules, resulting in poor image encryption and decryption efficiency. Therefore, improving the efficiency of image encryption and decryption has become a pressing technical problem. Summary of the Invention

[0003] The main objective of this application is to provide a RISC-V-based image encryption and decryption method, apparatus, device, storage medium, and computer program product, aiming to solve the technical problem of how to improve the efficiency of image encryption and decryption.

[0004] To achieve the above objectives, this application provides a RISC-V-based image encryption and decryption method. The method is applied to a RISC-V-based image encryption and decryption device, which integrates a RISC-V main core and a scalable coprocessor. The method includes the following steps: The initial key is written to the coprocessor based on a preset extended instruction, and the internal state of the chaotic system is configured based on the initial key; Based on the internal state of the chaotic system, sponge iteration is performed within the coprocessor to generate a random sequence associated with the plaintext image and output an image summary. The storage location information of the plaintext image is written to the coprocessor, which then reads the plaintext image pixel by pixel using direct memory access to obtain a pixel stream. In the coprocessor, a reversible obfuscation operation and a reversible diffusion operation are performed on the order of the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic of the reversible obfuscation operation and the reversible diffusion operation is reused in reverse order during the decryption stage. During the decryption phase, the same internal state as the chaotic system is constructed based on the image digest, and the same hardware logic is reused in reverse order to perform reverse operations on the processed pixel stream to obtain the original pixel stream.

[0005] In one embodiment, the step of writing an initial key to the coprocessor based on preset extension instructions and configuring the internal state of the chaotic system based on the initial key includes: Based on the RISC-V main core, an extended custom instruction UKey is generated, and the initial key address is written as a source operand into a general-purpose register so that the RISC-V main core sends the extended custom instruction UKey to the coprocessor. The coprocessor decodes the received extended custom instruction UKey, extracts the key address from the source operand, and reads the key address into the coprocessor. Based on the read key address, the coprocessor assigns or updates the state register associated with the chaotic system to complete the configuration of the internal state of the chaotic system.

[0006] In one embodiment, the step of performing sponge iteration within the coprocessor based on the internal state of the chaotic system to generate a random sequence associated with the plaintext image and output an image summary includes: The pixel data of the plaintext image is divided into multiple input data blocks according to a preset grouping rule. The coprocessor performs a sponge structure absorption phase processing on each input data block based on the internal state of the chaotic system, so as to iteratively update the state register corresponding to the sponge structure. After completing the absorption phase processing, the coprocessor performs the squeezing phase processing of the sponge structure based on the iteratively updated state register, and derives pseudo-random output data from the state register according to a preset output rule to obtain a random sequence associated with the plaintext image. The coprocessor generates an image summary based on the output data of a preset length obtained during the squeezing stage, and outputs the image summary and the random sequence as the output result of the sponge iteration.

[0007] In one embodiment, the step of writing the storage location information of the plaintext image into the coprocessor, enabling the coprocessor to read the plaintext image pixel by pixel using direct memory access to obtain a pixel stream, includes: Based on the RISC-V main core, an extended custom instruction CTRL is generated to specify the starting position and size of image data. The starting address of the plaintext image is written to register RS1 and the data size of the plaintext image is written to register RS2, so that the RISC-V main core sends the extended custom instruction CTRL to the coprocessor through the NICE request channel. The coprocessor decodes the received extended custom instruction CTRL, extracts the starting address and the data size from RS1 and RS2, and writes the starting address and the data size into the address register and length register of the coprocessor. The coprocessor initiates a direct memory access (DMA) process based on the address register and the length register, determines the storage address of subsequent pixels based on the starting address according to the pixel processing order, and sequentially reads pixel data through the memory request / response channel, so that the coprocessor reads the plaintext image pixel by pixel in direct memory access mode to obtain a pixel stream.

[0008] In one embodiment, the step of performing reversible obfuscation and reversible diffusion operations on the pixel stream based on the random sequence in the coprocessor to obtain a processed pixel stream, wherein the hardware logic of the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption phase, includes: The coprocessor receives a preset encryption extension instruction and determines the set of operations and execution order of the reversible obfuscation operation and reversible diffusion operation to be executed based on the preset encryption extension instruction, so as to generate corresponding operation scheduling parameters. During the pixel-by-pixel processing of the pixel stream, the coprocessor generates corresponding obfuscation control parameters and diffusion control parameters for the current pixel based on the random sequence, and performs reversible obfuscation and reversible diffusion operations on the pixel stream based on the operation scheduling parameters to obtain the processed pixel stream. During the decryption phase, the coprocessor reverses the execution order of the reversible obfuscation operation and the reversible diffusion operation based on the operation scheduling parameters, and performs reverse traversal of the pixel processing order. In order to control the order reversal, the coprocessor reuses the same hardware operation modules as in the encryption phase and performs reverse operation on the processed pixel stream. This enables the hardware logic of the reversible obfuscation operation and the reversible diffusion operation to be reused in reverse order during the decryption phase.

[0009] In one embodiment, the step of constructing the same internal state as the chaotic system based on the image digest during the decryption stage, and performing reverse operations on the processed pixel stream in reverse order using the same hardware logic to obtain the original pixel stream, includes: Before entering the decryption process, the image digest is written into the digest register of the coprocessor, and the state register of the chaotic system is initialized or calibrated based on the image digest to generate initial state parameters consistent with the encryption phase. The coprocessor runs the same sponge structure squeezing process or equivalent state update process as the encryption phase under the initial state parameters, and restores the pseudo-random sequence generation state consistent with the encryption phase, so as to construct the same internal state as the chaotic system. The coprocessor reverses the scheduling order of the reversible obfuscation operation and the reversible diffusion operation based on the decryption control information, generates the control parameters required for decryption based on the internal state, and reuses the hardware computing module of the encryption stage to perform reverse reversible obfuscation operation and reverse reversible diffusion operation on the processed pixel stream to obtain the original pixel stream.

[0010] Furthermore, to achieve the above objectives, this application also proposes a RISC-V-based image encryption and decryption device, which is applied to a RISC-V-based image encryption and decryption equipment. The equipment integrates a RISC-V main core and a scalable coprocessor. The RISC-V-based image encryption and decryption device includes: The data acquisition module is used to acquire RISC-V-based image encryption and decryption instructions, and determine the storage location and size information of the image data to be processed based on the RISC-V-based image encryption and decryption instructions; A state configuration module is used to write an initial key into the coprocessor based on a preset extended instruction, and to configure the internal state of the chaotic system based on the initial key. The sponge iteration module is used to perform sponge iteration within the coprocessor based on the internal state of the chaotic system, generate a random sequence associated with the plaintext image, and output an image summary. The direct read module is used to write the storage location information of the plaintext image into the coprocessor, so that the coprocessor can read the plaintext image pixel by pixel in the direct storage access mode to obtain a pixel stream; A reversible processing module is used in the coprocessor to perform reversible obfuscation and reversible diffusion operations on the order of the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic of the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption stage. The decryption reverse module is used to construct the same internal state as the chaotic system based on the image digest during the decryption stage, and to perform reverse operation on the processed pixel stream in reverse order using the same hardware logic to obtain the original pixel stream.

[0011] Furthermore, to achieve the above objectives, this application also proposes a RISC-V-based image encryption and decryption device, the device comprising: a memory, a processor, and a RISC-V-based image encryption and decryption program stored in the memory and executable on the processor, the RISC-V-based image encryption and decryption program being configured to implement the steps of the RISC-V-based image encryption and decryption method described above.

[0012] In addition, to achieve the above objectives, this application also proposes a storage medium storing a RISC-V-based image encryption and decryption program, which, when executed by a processor, implements the steps of the RISC-V-based image encryption and decryption method described above.

[0013] In addition, to achieve the above objectives, this application also proposes a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the RISC-V-based image encryption and decryption method described above.

[0014] This application writes an initial key into a coprocessor based on a preset extension instruction and configures the internal state of a chaotic system based on the initial key. Based on the internal state of the chaotic system, sponge iteration is performed within the coprocessor to generate a random sequence associated with the plaintext image and output an image digest. The storage location information of the plaintext image is written into the coprocessor, enabling the coprocessor to read the plaintext image pixel by pixel using direct memory access to obtain a pixel stream. In the coprocessor, reversible obfuscation and reversible diffusion operations are performed on the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic for the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption stage. During the decryption stage, the same internal state as the chaotic system is constructed based on the image digest, and the same hardware logic is reused in reverse order to perform reverse operations on the processed pixel stream to obtain the original pixel stream. This application directly writes the initial key and image storage location information into the coprocessor through preset extended instructions, enabling the chaotic system state configuration, sponge iteration, random sequence generation, and pixel-level obfuscation and diffusion operations to be completed within the coprocessor. This reduces the instruction overhead caused by the main core's involvement in pixel-by-pixel calculations and data scheduling. Simultaneously, the internal state of the chaotic system is used for both generating random sequences and outputting image digests during the same sponge iteration process, avoiding redundant execution of random sequence generation and digest calculations. Furthermore, the coprocessor reads the plaintext image pixel by pixel using direct memory access, reducing the memory access overhead of transferring pixel data between processors. Reversible obfuscation and diffusion operations reuse the same hardware logic in reverse order during the decryption stage, achieving reverse computation only by reversing the order, reducing hardware switching and repetitive implementation costs during encryption and decryption. Finally, the decryption stage rapidly reconstructs the chaotic system's internal state, consistent with the encryption stage, based on the image digest, avoiding re-initialization calculations and improving the efficiency of image encryption and decryption. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the first embodiment of the RISC-V-based image encryption and decryption method of this application; Figure 2 This is a schematic diagram of a sub-process in the second embodiment of the RISC-V-based image encryption and decryption method of this application; Figure 3 This is a schematic diagram of a sub-process in the third embodiment of the RISC-V-based image encryption and decryption method of this application; Figure 4 This is a schematic diagram of the RISC-V architecture extended instruction format in one embodiment of the RISC-V-based image encryption and decryption method of this application; Figure 5 This is a schematic diagram of an extended custom instruction structure in one embodiment of the RISC-V-based image encryption and decryption method of this application; Figure 6This is a schematic diagram of the module structure of the RISC-V-based image encryption and decryption device according to an embodiment of this application; Figure 7 This is a schematic diagram of the device structure of the hardware operating environment involved in the RISC-V-based image encryption and decryption method in the embodiments of this application.

[0016] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0017] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0018] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0019] It should be noted that with the widespread adoption of the internet, multimedia terminals, and edge computing devices, the security requirements for image data during acquisition, storage, transmission, and sharing are becoming increasingly prominent. To prevent unauthorized access or tampering of image content, existing technologies typically employ image encryption by obfuscating (scrambling) and spreading (changing pixel values) image pixels, and then performing corresponding reverse operations during the decryption phase to recover the original image. To improve security and randomness, some solutions also introduce mechanisms such as chaotic systems, pseudo-random sequence generation, and digest / hash verification to achieve random sequence generation and data integrity verification. However, existing image encryption and decryption implementations mainly fall into two categories: pure software implementations and dedicated hardware implementations. Pure software implementations typically rely on general-purpose processors to perform chaotic iteration, random sequence generation, pixel-level obfuscation and diffusion, and their inverse operations. When dealing with high-resolution images or real-time scenarios, they are easily affected by factors such as high computational load and high memory access overhead, resulting in high end-to-end processing latency, making it difficult to meet the business requirements with high real-time demands. While dedicated hardware implementations can improve throughput through parallel computing, common designs often rely on fixed algorithms and rigid computation paths, lacking flexibility. Furthermore, since encryption and decryption are inverse processes, using different computational logic or configuring separate decryption paths can lead to the need for separate encryption and decryption modules, resulting in poor image encryption and decryption efficiency. Therefore, improving the efficiency of image encryption and decryption has become a pressing technical problem.

[0020] The main solution of this application is as follows: An initial key is written into the coprocessor based on preset extension instructions, and the internal state of the chaotic system is configured based on the initial key; based on the internal state of the chaotic system, sponge iteration is performed within the coprocessor to generate a random sequence associated with the plaintext image and output an image digest; the storage location information of the plaintext image is written into the coprocessor, enabling the coprocessor to read the plaintext image pixel by pixel using direct memory access to obtain a pixel stream; in the coprocessor, reversible obfuscation and reversible diffusion operations are performed on the pixel stream based on the random sequence to obtain a processed pixel stream, and the hardware logic for the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption stage; during the decryption stage, the same internal state as the chaotic system is constructed based on the image digest, and the same hardware logic is reused in reverse order to perform reverse operations on the processed pixel stream to obtain the original pixel stream.

[0021] This application directly writes the initial key and image storage location information into the coprocessor through preset extended instructions, enabling the chaotic system state configuration, sponge iteration, random sequence generation, and pixel-level obfuscation and diffusion operations to be completed within the coprocessor. This reduces the instruction overhead caused by the main core's involvement in pixel-by-pixel calculations and data scheduling. Simultaneously, the internal state of the chaotic system is used for both generating random sequences and outputting image digests during the same sponge iteration process, avoiding redundant execution of random sequence generation and digest calculations. Furthermore, the coprocessor reads the plaintext image pixel by pixel using direct memory access, reducing the memory access overhead of transferring pixel data between processors. Reversible obfuscation and diffusion operations reuse the same hardware logic in reverse order during the decryption stage, achieving reverse computation only by reversing the order, reducing hardware switching and repetitive implementation costs during encryption and decryption. Finally, the decryption stage rapidly reconstructs the chaotic system's internal state, consistent with the encryption stage, based on the image digest, avoiding re-initialization calculations and improving the efficiency of image encryption and decryption.

[0022] It should be noted that the execution subject of the method in this embodiment can be a computing service device with data processing, network communication, and program execution functions, or it can be the aforementioned RISC-V-based image encryption and decryption device with the same or similar functions. This embodiment and the following embodiments will be described using a RISC-V-based image encryption and decryption device as an example.

[0023] Based on this, a first embodiment of the RISC-V-based image encryption and decryption method of this application is proposed. Please refer to [link / reference]. Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the RISC-V-based image encryption and decryption method of this application.

[0024] In this embodiment, the method is applied to a RISC-V-based image encryption / decryption device, which integrates a RISC-V main core and a scalable coprocessor. The method includes the following steps: S1: Write the initial key into the coprocessor based on the preset extended instructions, and configure the internal state of the chaotic system based on the initial key; S2: Based on the internal state of the chaotic system, perform sponge iteration within the coprocessor to generate a random sequence associated with the plaintext image and output an image summary; It should be noted that: Preset extended instructions refer to instructions derived from the RISC-V basic instruction set through custom opcodes or function fields. A coprocessor refers to a dedicated hardware module that works in conjunction with the RISC-V main core. An initial key refers to encryption parameters input externally or preset by the system. The internal state of a chaotic system refers to a set of state variables or register values ​​within the coprocessor that characterize the current operating state of the chaotic system. Sponge iteration refers to an iterative processing procedure based on a sponge structure. A random sequence refers to a pseudo-random data sequence generated by combining a chaotic system with sponge iteration. Image summarization refers to fixed-length data derived from the chaotic system state during sponge iteration.

[0025] Specifically, at the beginning of the encryption process, the RISC-V main core writes the initial key to the coprocessor through preset extended instructions. Upon receiving the initial key, the coprocessor loads it into the state register unit corresponding to the chaotic system, configuring the initial operating state of the chaotic system. This configuration process ensures that the chaotic system starts operating from defined initial conditions, thereby guaranteeing the reproducibility of the chaotic system's state evolution under the same key conditions, providing a consistent state basis for subsequent random sequence generation.

[0026] Furthermore, after configuring the internal state of the chaotic system, the coprocessor executes a sponge iteration process within that internal state. During this process, the coprocessor gradually absorbs plaintext image-related data as input into the state update process of the chaotic system, causing the internal state of the chaotic system to continuously evolve with the input data. After completing the absorption process, the coprocessor performs a squeezing process based on the updated internal state, sequentially deriving output data from the chaotic system state. A portion of the output data is used as the random sequence required for subsequent pixel obfuscation and diffusion operations, while another portion of the output data is aggregated to form an image summary, thus simultaneously completing random sequence generation and image summary output within the same sponge iteration process.

[0027] By first completing the initial key writing and chaotic system internal state configuration within the coprocessor based on extended instructions, and then performing sponge iteration on the same chaotic state to simultaneously generate random sequences and image digests, the repetitive state initialization and multiple calculation processes caused by independently executing random sequence generation and image digest calculation are avoided. At the same time, the chaotic iteration and sponge processing are implemented at the hardware level using the coprocessor, allowing the relevant calculations to be executed off the main core, reducing instruction scheduling and data interaction overhead. Thus, while ensuring the strong correlation between the random sequence and the plaintext image, the overall computational complexity is reduced, and the execution efficiency of the random control parameter generation stage in the image encryption and decryption process is improved.

[0028] S3: Write the storage location information of the plaintext image into the coprocessor, so that the coprocessor reads the plaintext image pixel by pixel in direct memory access mode to obtain a pixel stream; S4: In the coprocessor, a reversible obfuscation operation and a reversible diffusion operation are performed on the order of the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic of the reversible obfuscation operation and the reversible diffusion operation is reused in reverse order during the decryption stage. Specifically, before encryption, the RISC-V master core sends image-related control information to the coprocessor via extended instructions: the starting address and data size of the plaintext image are sent to the coprocessor as source operands (e.g., provided via RS1 and RS2 respectively) along with the extended instructions; the coprocessor receives and decodes the extended instructions via the NICE request channel to obtain the starting position and size of the image data. Subsequently, the coprocessor initiates a DMA access process, directly reading image pixels sequentially from memory through the memory request / response channel; utilizing the spatial locality of image data, the addresses of subsequent pixels can be calculated sequentially from the starting address, and the coprocessor continuously retrieves data accordingly, so that the pixel data read pixel by pixel enters the coprocessor's internal processing link in the form of a "pixel stream".

[0029] Furthermore, after the pixel stream enters the coprocessor, the coprocessor obtains the control quantities required for the current pixel processing from the previously generated random sequence. Simultaneously, it determines the required types and execution order of reversible obfuscation and reversible diffusion operations based on extended instructions. For operations that can be executed serially pixel by pixel, the coprocessor can use the Combine instruction to continuously complete SRshift, DNAC, RCA, CXOR, etc., in the configured order within the coprocessor, thereby completing as many processing steps as possible after a single pixel read, and then writing the processing results back to form the processed pixel stream. For whole-image scrambling operations like Fisher-Yates, the FYS instruction can be used to achieve reversible permutation of pixel positions. During the decryption phase, the coprocessor schedules and reuses the same hardware operation modules according to the "execution order opposite to encryption." Furthermore, for diffusion operations with chain-like characteristics (such as CXOR), processing can start from the end of the image data and proceed in reverse order, so that the hardware logic for reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption phase.

[0030] It should be noted that storage location information is used to locate the position and range of the plaintext image in memory. Direct Memory Access (DMA) refers to the coprocessor directly accessing memory to read and write image pixels through the memory request / response channel without transferring data through the main core. A pixel stream is a sequence of pixel data read continuously from memory by the coprocessor in pixel processing order. Reversible obfuscation is an operation that reversibly scrambles the pixel order / position. Reversible diffusion is an operation that reversibly transforms pixel values, associating pixel value changes with control sequences / adjacent pixels. The Combine instruction is used to configurably chain four pixel-by-pixel operations—SRshift, DNAC, RCA, and CXOR—according to the "operation set and order" specified by RS1; it also requires decryption to be in reverse order, and due to the chained nature of CXOR, decryption needs to start from the end. The CTRL instruction is used to specify the starting position and size of the image data so that the coprocessor can perform DMA sequential pixel read and write.

[0031] This step uses extended instructions such as CTRL to directly delegate the starting position and size of the plaintext image to the coprocessor. This allows the coprocessor to sequentially read pixels via DMA through the memory request / response channel and continuously calculate subsequent pixel addresses using spatial locality, thereby reducing the data handling and memory access scheduling overhead of the main core. Simultaneously, the coprocessor internally performs reversible obfuscation and reversible diffusion on the pixel stream based on a random sequence, and uses the Combine instruction to chain multiple pixel-by-pixel operations in the configured order, reducing computation and memory access overhead by "reducing the number of pixel shifts in and out and reducing the number of pixel reads and writes". Furthermore, the decryption stage reuses the same obfuscation / diffusion hardware logic in reverse order (and processes it in reverse according to the chain characteristics when necessary), avoiding the need to configure different computation paths separately for decryption, thereby improving the overall processing efficiency of image encryption and decryption with fewer reads and writes and simpler scheduling.

[0032] S5: During the decryption phase, the same internal state as the chaotic system is constructed based on the image digest, and the same hardware logic is reused in reverse order to perform reverse operation on the processed pixel stream to obtain the original pixel stream; It should be noted that the decryption stage refers to the reverse processing stage performed to recover the original image after encryption is completed and the "processed pixel stream" is obtained. The image digest (hash value) refers to the fixed-length output data obtained by the sponge structure from the plaintext image during the initial compression stage. Reverse multiplexing means that during decryption, instead of replacing the other set of computing hardware, the computing modules used in the encryption stage are scheduled in the reverse execution order, thereby completing the reverse operation. Reverse operation refers to the process of performing the reversible operation corresponding to encryption on the processed pixel stream in reverse order.

[0033] Specifically, at the start of decryption, the coprocessor obtains an image digest (hash value) corresponding to the processed pixel stream. According to the disclosure, the hash value is a fixed-length output obtained from the plaintext image during the initial squeezing phase of the sponge structure in the encryption phase, and is used to "initialize the state of the hash function and verify the integrity of the image during decryption." Therefore, the image digest can be used as initialization input in the decryption phase, allowing the coprocessor to restore the internal state corresponding to the hash / sponge structure to the same starting conditions as the encryption side, thereby constructing the same chaotic system internal state as the encryption phase (i.e., providing a consistent state basis for subsequent inverse operations).

[0034] Furthermore, after the internal state is constructed, the coprocessor performs reverse operations on the processed pixel stream. The disclosure document provides a clear reverse scheduling principle: for a set of operations that are pixel-based and can be executed sequentially (the disclosure document uses SRshift, DNAC, RCA, and CXOR as examples, and these can be configured to be executed via the Combine instruction), decryption must be performed in the reverse order of encryption; and because CXOR has a chained nature, decryption needs to start processing from the end of the image data to match its reversibility. Therefore, the coprocessor does not need to introduce new computation modules during the decryption stage. Instead, it reuses the same hardware logic from the encryption stage by "reversing the execution order (and, if necessary, overlaying the processing direction reversal)" to perform reverse operations on the processed pixel stream, ultimately obtaining the original pixel stream.

[0035] Image digests (hash values) are used to "initialize the state of the hash function during decryption." Therefore, the decryption phase can directly reconstruct the internal state consistent with the encryption phase on the coprocessor side based on the image digest, reducing the additional state derivation and repeated initialization steps required to restore the random control basis. Decryption is performed in the reverse order of encryption, and reverse processing starting from the end of the data is used when needed (such as chained CXOR). This allows decryption to reuse the same hardware operation logic as encryption by reversing the scheduling order, without the need to configure a separate dedicated decryption operation path. This reduces hardware duplication and process switching overhead while ensuring reversible recovery, thereby improving the execution efficiency of decryption processing.

[0036] This embodiment directly writes the initial key and image storage location information into the coprocessor through preset extended instructions. This allows the chaotic system state configuration, sponge iteration, random sequence generation, and pixel-level obfuscation and diffusion operations to all be completed within the coprocessor, reducing the instruction overhead caused by the main core's involvement in pixel-by-pixel calculations and data scheduling. Simultaneously, the internal state of the chaotic system is used for both generating random sequences and outputting image digests during the same sponge iteration process, avoiding redundant execution of random sequence generation and digest calculations. Furthermore, the coprocessor reads the plaintext image pixel by pixel using direct memory access, reducing the memory access overhead of transferring pixel data between processors. Reversible obfuscation and diffusion operations reuse the same hardware logic in reverse order during the decryption stage, achieving reverse computation only by reversing the order, reducing hardware switching and repetitive implementation costs during encryption and decryption. Finally, the decryption stage rapidly reconstructs the chaotic system's internal state, consistent with the encryption stage, based on the image digest, avoiding re-initialization calculations and improving the efficiency of RISC-V-based image encryption and decryption.

[0037] Based on the first embodiment described above, a second embodiment of the RISC-V-based image encryption / decryption method of this application is proposed. Please refer to... Figure 2 , Figure 2This is a schematic diagram of a sub-process in the second embodiment of the RISC-V-based image encryption and decryption method of this application.

[0038] like Figure 2 As shown, in this embodiment, step S1 includes: S11: Generate an extended custom instruction UKey based on the RISC-V main core, and write the initial key address as a source operand into a general-purpose register, so that the RISC-V main core sends the extended custom instruction UKey to the coprocessor; S12: The coprocessor decodes the received extended custom instruction UKey, extracts the key address from the source operand, and reads the key address into the coprocessor; S13: Based on the read key address, the coprocessor assigns or updates the state register associated with the chaotic system to complete the configuration of the internal state of the chaotic system.

[0039] It should be noted that the extended custom instruction UKey is an extended custom instruction used to specify the key for the encryption algorithm. The source operand / general-purpose registers (RS1, RS2) are the source of input data carried by the extended instruction; the main core places the source operand in general-purpose registers RS1 and RS2 and sends it along with the NICE request channel. The NICE interface / NICE request channel is the interface and channel through which the main core transmits the extended instruction to the coprocessor. Field decoding (Fun7 / Fun3) is the method by which the coprocessor decodes the extended instruction to generate control signals.

[0040] During the initialization phase, the RISC-V master core generates an extended custom instruction UKey and writes the initial key as the source operand of the extended instruction into a general-purpose register (e.g., RS1 / RS2). When the master core executes the extended instruction, it decodes it and marks it as a NICE instruction. Then, it sends the instruction and its source operand to the coprocessor via the NICE request channel. During this interaction, the master core pipeline may pause until a valid response is received from the response channel to ensure that the coprocessor has completed processing the instruction.

[0041] Furthermore, after receiving the UKey instruction via the NICE request channel, the coprocessor uses the Fun7 and Fun3 fields to decode the instruction and generate control signals. Fun3 is used in conjunction with RS1 / RS2 to determine the location of the source operand, and then extracts the key data from the source operand. The extracted key data is written to the coprocessor's internal storage location for key carrying / caching, and further used to assign or update the state registers related to the chaotic system / sponge hash; for example, during the absorption phase, the 256-bit state of DSLHash is initialized as the encryption key, thereby completing the configuration of the chaotic system's internal state.

[0042] Since the UKey is designed to initialize custom instructions and specify keys, and the main core can send the key as a source operand directly to the coprocessor via the NICE request channel, the coprocessor can extract the key after decoding the instructions using the Fun7 / Fun3 fields and complete the assignment / update of the status register on the hardware side (e.g., initializing the 256-bit status of DSLHash to the encryption key). Therefore, this step forms a hardware closed-loop path of "key distribution → key storage → internal status initialization", reducing the instruction overhead and number of interactions of the main core in configuring the status step by step through software routines, and ensuring that subsequent chaotic / sponge processing starts in a determined initial state, thereby providing a more efficient and repeatable state configuration foundation for subsequent random sequence generation and pixel-level processing.

[0043] Based on the first embodiment described above, in this embodiment, step S2 includes: S21: The pixel data of the plaintext image is divided into multiple input data blocks according to a preset grouping rule, and the coprocessor performs a sponge structure absorption phase processing on each input data block based on the internal state of the chaotic system, so as to iteratively update the state register corresponding to the sponge structure. S22: After completing the absorption stage processing, the coprocessor performs the squeezing stage processing of the sponge structure based on the iteratively updated state register, and derives pseudo-random output data from the state register according to a preset output rule to obtain a random sequence associated with the plaintext image; S23: The coprocessor generates an image summary based on the output data of a preset length obtained during the squeezing stage processing, and outputs the image summary and the random sequence as the output result of the sponge iteration.

[0044] It should be noted that the absorption phase refers to the stage where the sponge structure "fills and absorbs" the input data. The squeezing phase refers to the stage where the sponge structure derives the output data from its internal state. The pseudo-random output data is the output data derived from the sponge state during the squeezing phase, generated on request and used for subsequent encryption control.

[0045] Specifically, based on the pre-configured chaotic / sponge internal state, the coprocessor organizes the pixel data of the plaintext image into multiple input data blocks according to a preset grouping rule, and performs necessary padding to meet the input requirements of the sponge structure. Subsequently, the coprocessor sequentially sends each input data block to the absorption stage of the sponge structure, performing "padding and absorption" on the image data, and continuously updating the corresponding state register (sponge state) during the absorption process. In the image encryption process, HSLHash has only one absorption stage, which is used to initialize and absorb image data, thereby realizing the iterative evolution of the state.

[0046] Furthermore, after completing the absorption phase, the coprocessor enters the squeezing phase to extract output data from the updated sponge state: First, in the "initial squeezing phase," a fixed-length image digest (hash value) is obtained from the plaintext image. This digest is used to initialize the hash function state in the subsequent decryption phase and for integrity verification. After outputting the digest, the coprocessor can continue to execute multiple squeezing phases to generate pseudo-random output data. That is, during the image encryption process, the acquisition of random sequences is converted into the squeezing phase of the sponge function, and the output is squeezed from the sponge state in a "request" manner. The sponge function can generate 32 output values ​​for each request, thereby forming a random sequence associated with the plaintext image. Finally, the coprocessor outputs the image digest and the random sequence as the output result of the sponge iteration.

[0047] By mapping "plaintext image input" to an absorption phase of a sponge structure and "random sequence acquisition" to a squeezing phase, and employing a "one absorption phase + multiple squeezing phases" approach during image encryption, the coprocessor can output a fixed-length image digest (used for decryption initialization and integrity verification) in the initial squeezing phase after one absorption. Then, through subsequent squeezing phases, pseudo-random outputs are continuously generated on request (each request can generate a batch of output values) to form a random sequence. Therefore, this step simultaneously completes "digest generation + random sequence generation" within the same sponge / chaotic state evolution framework, reducing the repetitive state processing and additional module / process overhead caused by separating hashing and PRNG implementation. Furthermore, the generation mechanism of "associating random sequence with plaintext" improves the consistency of control sequence and data, thereby supporting subsequent image encryption and decryption processing on the coprocessor side with a more centralized and less repetitive computational process.

[0048] This embodiment directly writes the initial key and image storage location information into the coprocessor through preset extended instructions. This allows the chaotic system state configuration, sponge iteration, random sequence generation, and pixel-level obfuscation and diffusion operations to all be completed within the coprocessor, reducing the instruction overhead caused by the main core's involvement in pixel-by-pixel calculations and data scheduling. Simultaneously, the internal state of the chaotic system is used for both generating random sequences and outputting image digests during the same sponge iteration process, avoiding redundant execution of random sequence generation and digest calculations. Furthermore, the coprocessor reads the plaintext image pixel by pixel using direct memory access, reducing the memory access overhead of transferring pixel data between processors. Reversible obfuscation and diffusion operations reuse the same hardware logic in reverse order during the decryption stage, achieving reverse computation only by reversing the order, reducing hardware switching and repetitive implementation costs during encryption and decryption. Finally, the decryption stage rapidly reconstructs the chaotic system's internal state, consistent with the encryption stage, based on the image digest, avoiding re-initialization calculations and improving the efficiency of base image encryption and decryption.

[0049] Based on the second embodiment described above, a third embodiment of the RISC-V-based image encryption and decryption method of this application is proposed. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of a sub-process in the third embodiment of the RISC-V-based image encryption and decryption method of this application.

[0050] In this embodiment, step S3 includes: S31: Based on the RISC-V main core, generate an extended custom instruction CTRL to specify the starting position and size of image data, and write the starting address of the plaintext image into register RS1 and the data size of the plaintext image into register RS2, so that the RISC-V main core sends the extended custom instruction CTRL to the coprocessor through the NICE request channel; S32: The coprocessor decodes the received extended custom instruction CTRL, extracts the starting address and the data size from RS1 and RS2, and writes the starting address and the data size into the address register unit and length register unit of the coprocessor. S33: The coprocessor initiates a direct memory access (DMA) process based on the address register unit and the length register unit, determines the storage address of subsequent pixels based on the starting address according to the pixel processing order, and sequentially reads pixel data through the memory request / response channel, so that the coprocessor reads the plaintext image pixel by pixel in the direct memory access mode to obtain a pixel stream.

[0051] It should be noted that the extended custom instruction CTRL is an extended custom instruction used to specify the starting position and size of image data. The address register / length register is a register / buffer unit inside the coprocessor used to store the starting address and size of the image data. Spatial locality refers to the spatial locality of image data; the address of subsequent pixels can be "easily calculated" from the starting address, thus allowing for sequential pixel reading and writing.

[0052] Specifically, before initiating image data transfer / processing, the RISC-V main core generates an extended custom instruction CTRL to specify the starting position and size of the image data, and writes the starting address and data size of the plaintext image into general-purpose registers RS1 and RS2 as source operands. When the main core executes this extended instruction, it decodes it and marks it as a NICE instruction. The CTRL instruction, along with the source operands in RS1 and RS2, is sent to the coprocessor through the NICE request channel, thus handing over the storage location information of "where the image starts and how large its range is" to the coprocessor.

[0053] Furthermore, after receiving the CTRL instruction via the NICE request channel, the coprocessor uses the Fun7 / Fun3 fields to decode the instruction and determine the source operands corresponding to RS1 and RS2. It then extracts the starting address and data size and writes them into the internal address and length registers. Subsequently, the coprocessor initiates a DMA process based on the address / length information, directly accessing memory through the memory request / response channel to sequentially read pixel data. Based on the spatial locality of image data, the storage addresses of subsequent pixels can be calculated sequentially from the starting address. Therefore, the controller can process the reading and writing of pixel data sequentially, allowing pixels to be read one by one and enter the coprocessor's internal processing link in a continuous data format, thus obtaining a pixel stream.

[0054] All encryption operations require sequentially reading pixels into the coprocessor and writing them back to memory. Therefore, the coprocessor must have DMA and introduce the CTRL instruction to specify the starting position and size of the image. At the same time, image data has spatial locality, and subsequent pixel addresses can be calculated sequentially from the starting address. The controller can process pixel read and write sequentially accordingly. Therefore, this step hardware-encapsulates and pipelines the image pixel transport and data retrieval path by using the method of "the main core sends the position information once using CTRL / RS1 / RS2 → the coprocessor decodes the parameters → the coprocessor retrieves data sequentially via the memory request / response channel using DMA". This reduces the additional overhead caused by the main core's involvement in transport and scheduling, and reduces the complexity of random memory access and addressing by using sequential access, thereby obtaining the pixel stream for subsequent encryption and decryption processing more efficiently.

[0055] Based on the second embodiment described above, in this embodiment, step S4 includes: S41: The coprocessor receives a preset encryption extension instruction and determines the set of operations and execution order of the reversible obfuscation operation and reversible diffusion operation to be executed based on the preset encryption extension instruction, so as to generate corresponding operation scheduling parameters; S42: During the pixel-by-pixel processing of the pixel stream, the coprocessor generates corresponding obfuscation control parameters and diffusion control parameters for the current pixel based on the random sequence, and performs reversible obfuscation and reversible diffusion operations on the pixel stream based on the operation scheduling parameters to obtain the processed pixel stream; S43: During the decryption phase, the coprocessor reverses the execution order of the reversible obfuscation operation and the reversible diffusion operation based on the operation scheduling parameters, and performs reverse traversal of the pixel processing order. In order to control the order reversal, the same hardware operation module as in the encryption phase is reused to perform reverse operation on the processed pixel stream, so as to realize the hardware logic of the reversible obfuscation operation and the reversible diffusion operation is reused in reverse order during the decryption phase.

[0056] It should be noted that the preset encryption extension instructions are extended custom instructions used to execute encryption / decryption, such as the Combine instruction (which executes SRshift / DNAC / RCA / CXOR serially in a configurable manner) and the FYS instruction (which implements Fisher-Yates scrambling / reverse scrambling). The operation set and execution order refer to which pixel-level operations are to be performed and their order. The operation scheduling parameters are scheduling information such as "operation type + order + direction" obtained by the coprocessor based on the parsing of the extension instructions. The obfuscation control parameters / diffusion control parameters are control values ​​generated for the current pixel by a random sequence. Reverse traversal refers to reversing the pixel processing direction during the decryption stage (e.g., processing from the last pixel forward) to meet the reverse recovery requirements of chain diffusion (such as CXOR).

[0057] Specifically, the coprocessor receives extended instructions from the RISC-V main core via the NICE request channel and decodes the instructions using fields such as Fun7 / Fun3 to generate control signals. The controller then determines whether the current instruction belongs to a "pixel-level serially combinable execution" (e.g., Combine) or a "whole-image pixel permutation" (e.g., FYS) type, and further extracts parameters for specifying the encryption strategy (e.g., the operation set and execution order corresponding to the RS1 specified value of Combine), thereby generating operation scheduling parameters. Subsequently, the controller initiates the corresponding process according to the scheduling parameters, including loading image pixels, obtaining a pseudo-random sequence from a chaotic hash function, executing the selected encryption algorithm, and storing the processed pixels.

[0058] Furthermore, during pixel-by-pixel processing of the pixel stream, the coprocessor generates obfuscation and diffusion control parameters for the current pixel based on a random sequence, and calls internal hardware operation modules according to the operation scheduling parameters. For pixel-level operations such as SRshift, DNAC, RCA, and CXOR, the coprocessor can execute them sequentially in a predetermined order to complete multiple processing steps and output the processed pixel as quickly as possible after the pixel is read in. For whole-pixel permutations such as Fisher-Yates scrambling, the corresponding reversible obfuscation process is triggered by the FYS instruction. Upon entering the decryption stage, the coprocessor reverses the operation scheduling parameters, causing decryption to call the same operation modules in the reverse order of encryption. When chain diffusion such as CXOR is involved, the pixel processing order is reversed (starting from the end) to complete the reverse operation and restore the original pixel stream by controlling the order reversal, thereby realizing the reverse reuse of hardware logic in the decryption stage.

[0059] SRshift, DNAC, RCA, and CXOR are pixel-by-pixel operations that can be executed sequentially to reduce pixel read / write operations and computational overhead. The Combine instruction can specify the "required operations and order" via RS1. Therefore, the coprocessor can form scheduling parameters based on extended instructions during the encryption phase and chain multiple diffusion-type operations in a single pixel processing link, thereby reducing the extra cycles caused by pixel shifting in and out. At the same time, decryption must be executed in reverse order, and CXOR must start from the end. This allows the coprocessor to reuse the same hardware operation modules as the encryption phase in the decryption phase by simply "reversing the order + necessary reverse traversal", avoiding the need to implement a separate set of logic for decryption. Thus, the overall image encryption and decryption efficiency is improved by reducing pixel read / write operations and hardware duplication overhead.

[0060] In this embodiment, step S5 includes: S51: Before entering the decryption process, the image digest is written into the digest register of the coprocessor, and the state register of the chaotic system is initialized or calibrated based on the image digest to generate initial state parameters consistent with the encryption stage. S52: The coprocessor runs the same sponge structure squeezing process or equivalent state update process as the encryption phase under the initial state parameters, and restores the pseudo-random sequence generation state consistent with the encryption phase, so as to construct the same internal state as the chaotic system. S53: The coprocessor reverses the scheduling order of the reversible obfuscation operation and the reversible diffusion operation based on the decryption control information, generates the control parameters required for decryption based on the internal state, and reuses the hardware operation module of the encryption stage to perform reverse reversible obfuscation operation and reverse reversible diffusion operation on the processed pixel stream to obtain the original pixel stream.

[0061] It should be noted that the initial state parameters are the state initialization results formed to ensure consistency between the decryption and encryption sides (e.g., the register contents after state initialization / calibration triggered by the hash value). Decryption control information is used to determine which pixel-level operations should be performed during decryption and their order.

[0062] Specifically, before entering the decryption process, the coprocessor first receives the image digest (hash value) corresponding to the processed pixel stream and writes it into the coprocessor's internal register / storage unit for storing the digest, so that it can be read later. The hash value originates from the initial squeezing phase of the HSLHash on the encryption side, and one of its uses is to "initialize the state of the hash function and verify the integrity of the image during the decryption process." Therefore, when decryption starts, the coprocessor uses this image digest as a basis to perform initialization or calibration operations on the state registers corresponding to the chaotic system / sponge structure, so that these state registers enter the same starting conditions as the encryption phase, thereby generating initial state parameters consistent with the encryption phase.

[0063] Furthermore, after obtaining consistent initial state parameters, the coprocessor performs the same sponge-structure squeezing process (or equivalent state update process) as the encryption phase in this state to restore the pseudo-random sequence generation state consistent with the encryption phase: after absorption, multiple squeezing phases can be entered, and "each request can squeeze 32 output values ​​from the sponge state." Therefore, the decryption side executes the same squeezing request sequence in the same state to reproduce the pseudo-random output consistent with the encryption side, which is used as the source of decryption control parameters. Subsequently, the coprocessor reads the decryption control information (e.g., the set of operations and their order determined by the Combine policy field / RS1), reverses the scheduling order of reversible obfuscation and reversible diffusion operations, and reverses the processing from the end of the image data when chained XOR (CXOR) is involved to match their reciprocal characteristics. In this way, the coprocessor can reuse the same hardware operation module as the encryption phase to perform reverse reversible obfuscation and reverse reversible diffusion operations on the processed pixel stream without changing the operation path, and finally obtain the original pixel stream.

[0064] The hash value is used to initialize the hash function state and verify integrity during decryption. After absorption, HSLHash can be exported from the sponge state on request during the squeezing phase. Therefore, the state register is initialized / calibrated based on the image digest during the decryption phase, which allows the coprocessor to quickly align to the initial state parameters consistent with encryption. Under this consistent state, the pseudo-random sequence generation state can be reproduced through the same squeezing request, thus providing a consistent source of control parameters for reverse operation. At the same time, the pixel-level operations corresponding to the Combine instruction can be executed sequentially to reduce the number of pixel reads and writes, and decryption is required to be executed in reverse order. CXOR decryption starts from the end. Therefore, the coprocessor can reuse the same hardware operation module as the encryption phase to complete the recovery during decryption by "reversing the scheduling order + necessary reverse traversal", avoiding the need for a separate decryption path and duplicate hardware, achieving lower switching / repetition overhead and improving decryption processing efficiency.

[0065] This embodiment directly writes the initial key and image storage location information into the coprocessor through preset extended instructions. This allows the chaotic system state configuration, sponge iteration, random sequence generation, and pixel-level obfuscation and diffusion operations to all be completed within the coprocessor, reducing the instruction overhead caused by the main core's involvement in pixel-by-pixel calculations and data scheduling. Simultaneously, the internal state of the chaotic system is used for both generating random sequences and outputting image digests during the same sponge iteration process, avoiding redundant execution of random sequence generation and digest calculations. Furthermore, the coprocessor reads the plaintext image pixel by pixel using direct memory access, reducing the memory access overhead of transferring pixel data between processors. Reversible obfuscation and diffusion operations reuse the same hardware logic in reverse order during the decryption stage, achieving reverse computation only by reversing the order, reducing hardware switching and repetitive implementation costs during encryption and decryption. Finally, the decryption stage rapidly reconstructs the chaotic system's internal state, consistent with the encryption stage, based on the image digest, avoiding re-initialization calculations and improving the efficiency of image encryption and decryption.

[0066] Please see Figure 4 , Figure 4 This is a schematic diagram of the RISC-V architecture extended instruction format in one embodiment of the RISC-V-based image encryption and decryption method of this application. The overall architecture of the coprocessor in this embodiment is as follows: Figure 4As shown, the coprocessor connects to the main core (Nuclei Core) via the NICE interface, which contains four channels. It receives extended instructions from the main core via the NICE request channel and accesses memory via the memory request and response channels. When an extended instruction is executed, the main core decodes it and marks it as a NICE instruction, then sends it to the coprocessor via the NICE request channel. The source operands come from general-purpose registers (i.e., registers RS1 and RS2) and a 32-bit instruction. The pipeline stalls until a valid response is received from the response channel. The coprocessor uses the Fun7 and Fun3 fields to decode the instruction to generate control signals. Fun3 determines the source operands of the current instruction from RS1 and RS2 in the NICE request. Based on Fun7, the coprocessor's controller initiates operations based on control signals from the decoder, such as loading image pixels, obtaining pseudo-random sequences from chaotic hash functions, executing selected encryption algorithms, and storing the processed pixels. From a performance perspective, moving pixels into and out of the coprocessor requires additional cycles. Furthermore, due to the spatial locality of image data, the storage address of subsequent pixels can be determined based on the starting address of the image data. Therefore, the starting position and size of the image data are provided in the RS1 and RS2 registers respectively, and the controller processes the reading and writing of pixel data sequentially.

[0067] Please see Figure 5 , Figure 5This is a schematic diagram of the extended custom instruction structure in one embodiment of the RISC-V-based image encryption and decryption method of this application. In one embodiment, five extended custom instructions are proposed. These instructions have the same opcode, distinguished by Funct7, and are encoded using one-hot encoding. Based on their operation objects and implementation stages, these instructions are divided into two categories. The first three instructions are used to initialize the image encryption algorithm. Specifically, the UKey instruction specifies the key for the encryption algorithm, while the Hash instruction calculates the hash value of the original image and uses this value to initialize the initial state of the chaotic mapping. Since all encryption operations require sequentially reading image pixels into the coprocessor for processing and then writing the processed pixels back to memory, the coprocessor must be capable of direct memory access (DMA). Therefore, a dedicated instruction CTRL is introduced to specify the starting position and size of the image data. The last two instructions are used to perform encryption and decryption operations. The four operations—Self-Reversible Shift (SRshift), DNA Encoding (DNAC), Reversible Cellular Automata (RCA), and Chained XOR (CXOR)—operate on a pixel-by-pixel basis, thus allowing sequential execution and reducing the number of pixel read / write operations, thereby reducing the computational overhead of the encryption algorithm. Additionally, the Combine instruction is introduced to perform the above operations in a configurable manner. The encryption strategy (i.e., the required operations and their order) is determined by the value specified in the RS1 register of the Combine instruction. It is important to note that the decryption process must be performed in reverse order. Furthermore, due to the chained nature of the CXOR operation, decryption must begin from the end of the image data. Since the Fisher-Yates scrambling algorithm requires permuting pixels across the entire image, a dedicated instruction, FYS, is used. In its implementation, the Combine instruction encodes the four combined instructions—Reversible Shift (SRshift), DNA Coding (DNAC), Reversible Cellular Automata (RCA), and Chained XOR (CXOR)—as 2'b00, 2'b01, 2'b10, and 2'b11, respectively. The order of encryption and decryption in the Combine instruction is specified in the RS1 register. For example, when implementing the series of operations SRshift->DNAC->RCA->CXOR, the value in RS1 is 8'b11100100.

[0068] This application also provides an image encryption / decryption device based on RISC-V. Please refer to... Figure 6 , Figure 6 This is a schematic diagram of the module structure of a RISC-V-based image encryption and decryption device according to an embodiment of this application. The device is applied to a RISC-V-based image encryption and decryption apparatus. The apparatus integrates a RISC-V main core and a scalable coprocessor. The RISC-V-based image encryption and decryption apparatus includes: The state configuration module 601 is used to write an initial key into the coprocessor based on a preset extended instruction, and to configure the internal state of the chaotic system based on the initial key. The sponge iteration module 602 is used to perform sponge iteration within the coprocessor based on the internal state of the chaotic system, generate a random sequence associated with the plaintext image, and output an image summary. The direct read module 603 is used to write the storage location information of the plaintext image into the coprocessor, so that the coprocessor reads the plaintext image pixel by pixel in the direct storage access mode to obtain a pixel stream; The reversible processing module 604 is used in the coprocessor to perform reversible obfuscation and reversible diffusion operations on the order of the pixel stream based on the random sequence to obtain the processed pixel stream. The hardware logic of the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption stage. The decryption reverse module 605 is used to construct the same internal state as the chaotic system based on the image digest during the decryption stage, and to perform reverse operation on the processed pixel stream in reverse order using the same hardware logic to obtain the original pixel stream.

[0069] The RISC-V-based image encryption and decryption apparatus provided in this application, employing the RISC-V-based image encryption and decryption method described in the above embodiments, can solve the technical problem of how to improve the efficiency of image encryption and decryption. Compared with the prior art, the beneficial effects of the RISC-V-based image encryption and decryption apparatus provided in this application are the same as those of the RISC-V-based image encryption and decryption method described in the above embodiments, and other technical features in the RISC-V-based image encryption and decryption apparatus are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0070] This application provides a RISC-V-based image encryption and decryption device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the RISC-V-based image encryption and decryption method in the above embodiments.

[0071] The following is for reference. Figure 7 , Figure 7 This is a schematic diagram of the hardware operating environment involved in the RISC-V-based image encryption and decryption method in the embodiments of this application. It shows a schematic diagram of the structure of the RISC-V-based image encryption and decryption device suitable for implementing the embodiments of this application. Figure 7The RISC-V-based image encryption and decryption device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0072] like Figure 7 As shown, a RISC-V-based image encryption / decryption device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. RAM 1004 also stores various programs and data required for the operation of the RISC-V-based image encryption / decryption device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the RISC-V-based image encryption / decryption device to communicate wirelessly or wiredly with other devices to exchange data. Although the figure shows a RISC-V-based image encryption / decryption device with various systems, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0073] In particular, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. When the computer program is executed by the processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0074] The RISC-V-based image encryption and decryption device provided in this application, employing the RISC-V-based image encryption and decryption method described in the above embodiments, can solve the technical problem of how to improve the efficiency of image encryption and decryption. Compared with the prior art, the beneficial effects of the RISC-V-based image encryption and decryption device provided in this application are the same as those of the RISC-V-based image encryption and decryption method provided in the above embodiments, and other technical features in this RISC-V-based image encryption and decryption device are the same as those disclosed in the method of the previous embodiment, and will not be repeated here.

[0075] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0076] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0077] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, which are used to execute the RISC-V-based image encryption and decryption method in the above embodiments.

[0078] The aforementioned computer-readable storage medium carries one or more programs. When these programs are executed by a RISC-V-based image encryption / decryption device, the RISC-V-based image encryption / decryption device: writes an initial key to a coprocessor based on preset extended instructions and configures the internal state of a chaotic system based on the initial key; performs sponge iteration within the coprocessor based on the internal state of the chaotic system to generate a random sequence associated with the plaintext image and outputs an image digest; writes the storage location information of the plaintext image to the coprocessor, enabling the coprocessor to read the plaintext image pixel by pixel using direct memory access to obtain a pixel stream; in the coprocessor, performs reversible obfuscation and reversible diffusion operations on the pixel stream based on the random sequence to obtain a processed pixel stream, with the hardware logic for the reversible obfuscation and reversible diffusion operations reused in reverse order during the decryption phase; during the decryption phase, constructs the same internal state as the chaotic system based on the image digest and performs reverse operations on the processed pixel stream using the same hardware logic reused in reverse order to obtain the original pixel stream. Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0079] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0080] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0081] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described RISC-V-based image encryption and decryption method, thereby solving the technical problem of how to improve the efficiency of image encryption and decryption. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the RISC-V-based image encryption and decryption method provided in the above embodiments, and will not be repeated here.

[0082] This application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the RISC-V-based image encryption and decryption method described above.

[0083] The computer program product provided in this application solves the technical problem of how to improve the efficiency of image encryption and decryption. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the RISC-V-based image encryption and decryption method provided in the above embodiments, and will not be repeated here.

[0084] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent scope of this application.

Claims

1. A RISC-V-based image encryption and decryption method, characterized in that, The method is applied to a RISC-V-based image encryption / decryption device, which integrates a RISC-V main core and a scalable coprocessor. The method includes: The initial key is written to the coprocessor based on a preset extended instruction, and the internal state of the chaotic system is configured based on the initial key; Based on the internal state of the chaotic system, sponge iteration is performed within the coprocessor to generate a random sequence associated with the plaintext image and output an image summary. The storage location information of the plaintext image is written to the coprocessor, which then reads the plaintext image pixel by pixel using direct memory access to obtain a pixel stream. In the coprocessor, a reversible obfuscation operation and a reversible diffusion operation are performed on the order of the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic of the reversible obfuscation operation and the reversible diffusion operation is reused in reverse order during the decryption stage. During the decryption phase, the same internal state as the chaotic system is constructed based on the image digest, and the same hardware logic is reused in reverse order to perform reverse operations on the processed pixel stream to obtain the original pixel stream.

2. The method as described in claim 1, characterized in that, The step of writing the initial key to the coprocessor based on preset extended instructions and configuring the internal state of the chaotic system based on the initial key includes: Based on the RISC-V main core, an extended custom instruction UKey is generated, and the initial key address is written as a source operand into a general-purpose register so that the RISC-V main core sends the extended custom instruction UKey to the coprocessor. The coprocessor decodes the received extended custom instruction UKey, extracts the key address from the source operand, and reads the key address into the coprocessor. Based on the read key address, the coprocessor assigns or updates the state register associated with the chaotic system to complete the configuration of the internal state of the chaotic system.

3. The method as described in claim 1, characterized in that, The step of performing sponge iteration within the coprocessor based on the internal state of the chaotic system to generate a random sequence associated with the plaintext image and output an image summary includes: The pixel data of the plaintext image is divided into multiple input data blocks according to a preset grouping rule. The coprocessor performs a sponge structure absorption phase processing on each input data block based on the internal state of the chaotic system, so as to iteratively update the state register corresponding to the sponge structure. After completing the absorption phase processing, the coprocessor performs the squeezing phase processing of the sponge structure based on the iteratively updated state register, and derives pseudo-random output data from the state register according to a preset output rule to obtain a random sequence associated with the plaintext image. The coprocessor generates an image summary based on the output data of a preset length obtained during the squeezing stage, and outputs the image summary and the random sequence as the output result of the sponge iteration.

4. The method as described in claim 1, characterized in that, The step of writing the storage location information of the plaintext image into the coprocessor, enabling the coprocessor to read the plaintext image pixel by pixel in direct memory access mode to obtain a pixel stream, includes: Based on the RISC-V main core, an extended custom instruction CTRL is generated to specify the starting position and size of image data. The starting address of the plaintext image is written to register RS1 and the data size of the plaintext image is written to register RS2, so that the RISC-V main core sends the extended custom instruction CTRL to the coprocessor through the NICE request channel. The coprocessor decodes the received extended custom instruction CTRL, extracts the starting address and the data size from RS1 and RS2, and writes the starting address and the data size into the address register and length register of the coprocessor. The coprocessor initiates a direct memory access (DMA) process based on the address register and the length register, determines the storage address of subsequent pixels based on the starting address according to the pixel processing order, and sequentially reads pixel data through the memory request / response channel, so that the coprocessor reads the plaintext image pixel by pixel in direct memory access mode to obtain a pixel stream.

5. The method as described in claim 1, characterized in that, In the coprocessor, the process of performing reversible obfuscation and reversible diffusion operations on the pixel stream based on the random sequence to obtain a processed pixel stream, wherein the hardware logic of the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption phase, includes: The coprocessor receives a preset encryption extension instruction and determines the set of operations and execution order of the reversible obfuscation operation and reversible diffusion operation to be executed based on the preset encryption extension instruction, so as to generate corresponding operation scheduling parameters. During the pixel-by-pixel processing of the pixel stream, the coprocessor generates corresponding obfuscation control parameters and diffusion control parameters for the current pixel based on the random sequence, and performs reversible obfuscation and reversible diffusion operations on the pixel stream based on the operation scheduling parameters to obtain the processed pixel stream. During the decryption phase, the coprocessor reverses the execution order of the reversible obfuscation operation and the reversible diffusion operation based on the operation scheduling parameters, and performs reverse traversal of the pixel processing order. In order to control the order reversal, the coprocessor reuses the same hardware operation modules as in the encryption phase and performs reverse operation on the processed pixel stream. This enables the hardware logic of the reversible obfuscation operation and the reversible diffusion operation to be reused in reverse order during the decryption phase.

6. The method as described in claim 1, characterized in that, The steps of constructing an internal state identical to that of the chaotic system based on the image digest during the decryption phase, and performing reverse operations on the processed pixel stream in reverse order using the same hardware logic to obtain the original pixel stream, include: Before entering the decryption process, the image digest is written into the digest register of the coprocessor, and the state register of the chaotic system is initialized or calibrated based on the image digest to generate initial state parameters consistent with the encryption phase. The coprocessor runs the same sponge structure squeezing process or equivalent state update process as the encryption phase under the initial state parameters, and restores the pseudo-random sequence generation state consistent with the encryption phase, so as to construct the same internal state as the chaotic system. The coprocessor reverses the scheduling order of the reversible obfuscation operation and the reversible diffusion operation based on the decryption control information, generates the control parameters required for decryption based on the internal state, and reuses the hardware computing module of the encryption stage to perform reverse reversible obfuscation operation and reverse reversible diffusion operation on the processed pixel stream to obtain the original pixel stream.

7. An image encryption / decryption device based on RISC-V, characterized in that, The device is applied to a RISC-V-based image encryption / decryption device, which integrates a RISC-V main core and a scalable coprocessor. The device includes: A state configuration module is used to write an initial key into the coprocessor based on a preset extended instruction, and to configure the internal state of the chaotic system based on the initial key. The sponge iteration module is used to perform sponge iteration within the coprocessor based on the internal state of the chaotic system, generate a random sequence associated with the plaintext image, and output an image summary. The direct read module is used to write the storage location information of the plaintext image into the coprocessor, so that the coprocessor can read the plaintext image pixel by pixel in the direct storage access mode to obtain a pixel stream; A reversible processing module is used in the coprocessor to perform reversible obfuscation and reversible diffusion operations on the order of the pixel stream based on the random sequence to obtain a processed pixel stream. The hardware logic of the reversible obfuscation and reversible diffusion operations is reused in reverse order during the decryption stage. The decryption reverse module is used to construct the same internal state as the chaotic system based on the image digest during the decryption stage, and to perform reverse operation on the processed pixel stream in reverse order using the same hardware logic to obtain the original pixel stream.

8. A computer device, characterized in that, The device includes: a memory, a processor, and a RISC-V-based image encryption / decryption program stored in the memory and executable on the processor, the RISC-V-based image encryption / decryption program being configured to implement the steps of the RISC-V-based image encryption / decryption method as described in any one of claims 1 to 6.

9. A storage medium, characterized in that, The storage medium stores a RISC-V-based image encryption and decryption program, which, when executed by a processor, implements the steps of the RISC-V-based image encryption and decryption method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the RISC-V-based image encryption and decryption method as described in any one of claims 1 to 6.

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